TWI817766B - Display driving circuit applied to cholesteric liquid crystal display apparatus - Google Patents

Display driving circuit applied to cholesteric liquid crystal display apparatus Download PDF

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TWI817766B
TWI817766B TW111138503A TW111138503A TWI817766B TW I817766 B TWI817766 B TW I817766B TW 111138503 A TW111138503 A TW 111138503A TW 111138503 A TW111138503 A TW 111138503A TW I817766 B TWI817766 B TW I817766B
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TW202341107A (en
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林文聰
羅友龍
梁彥雄
陳建銘
柯泰維
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瑞鼎科技股份有限公司
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Abstract

A display driving circuit applied to a cholesteric liquid crystal display apparatus including three positive buffer groups, three negative buffer groups and a level shifter and an output switch is disclosed. The three positive buffer groups receive a first reference voltage to a third reference voltage and output a first positive driving voltage to a third positive driving voltage respectively. The three negative buffer groups receive a fourth reference voltage to a sixth reference voltage and output a first negative driving voltage to a third negative driving voltage respectively. The level shifter and the output switch are coupled to the three positive buffer groups and the three negative buffer groups respectively for receiving the first positive driving voltage to the third positive driving voltage and the first negative driving voltage to the third negative driving voltage and generating an output signal accordingly.

Description

應用於膽固醇液晶顯示裝置的顯示驅動電路Display driving circuit applied to cholesteric liquid crystal display device

本發明係與顯示裝置有關，特別是關於一種應用於膽固醇液晶顯示裝置(Cholesteric Liquid Crystals Display，ChLCD)的顯示驅動電路。The present invention relates to display devices, and in particular to a display driving circuit applied to a cholesteric liquid crystal display (ChLCD).

目前的膽固醇液晶全彩顯示系統係採用以紅(R)/綠(G)/藍(B)畫素三層堆疊的方式，其優點包括：在技術發展上較為成熟、單一畫素的顯色區塊較大、色彩較為飽和。The current cholesterol liquid crystal full-color display system uses a three-layer stack of red (R)/green (G)/blue (B) pixels. Its advantages include: relatively mature technology development, single pixel color rendering The blocks are larger and the colors are more saturated.

然而，在目前的膽固醇液晶全彩顯示系統中，需在印刷電路板(Printed Circuit Board，PCB)上設置相當多的主動及被動元件作為驅動電壓源來提供驅動電壓給顯示驅動電路，再加上紅(R)/綠(G)/藍(B)畫素三層堆疊的方式更造成成本大增。However, in the current cholesteric liquid crystal full-color display system, a considerable number of active and passive components need to be installed on the printed circuit board (PCB) as the driving voltage source to provide the driving voltage to the display driving circuit. In addition, The three-layer stacking method of red (R)/green (G)/blue (B) pixels also greatly increases the cost.

舉例而言，如圖1所示，對單色(例如紅色)畫素面板而言，印刷電路板(PCB)上至少需設置有三個正緩衝器組PBF與三個負緩衝器組NBF來產生第一正驅動電壓VP1~第三正驅動電壓VP3及第一負驅動電壓VN1~第三負驅動電壓VN3至顯示驅動電路，並且如圖2A及圖2B所示，每個正緩衝器組PBF/負緩衝器組NBF均需包括2個回授電阻R1~R2及1個緩衝器BF。因此，單色(例如紅色)畫素面板即需包括12個回授電阻及6個緩衝器。也就是說，三色(亦即紅、綠及藍)畫素面板共需包括36個回授電阻及18個緩衝器，數量相當可觀。此外，正緩衝器組PBF及負緩衝器組NBF在印刷電路板(PCB)上的連接線及拉線亦需考量其本身的耐流與阻值大小，亦會造成整個系統的成本增加。For example, as shown in Figure 1, for a single-color (such as red) pixel panel, at least three positive buffer groups PBF and three negative buffer groups NBF need to be provided on the printed circuit board (PCB) to generate The first positive driving voltage VP1 ~ the third positive driving voltage VP3 and the first negative driving voltage VN1 ~ the third negative driving voltage VN3 are supplied to the display driving circuit, and as shown in Figure 2A and Figure 2B, each positive buffer group PBF/ The negative buffer group NBF needs to include 2 feedback resistors R1~R2 and 1 buffer BF. Therefore, a single-color (such as red) pixel panel needs to include 12 feedback resistors and 6 buffers. In other words, a three-color (i.e. red, green and blue) pixel panel needs to include a total of 36 feedback resistors and 18 buffers, which is a considerable number. In addition, the connection lines and pull lines of the positive buffer group PBF and negative buffer group NBF on the printed circuit board (PCB) also need to consider their own current resistance and resistance, which will also increase the cost of the entire system.

綜上所述，先前技術所遭遇到之上述問題仍亟待進一步解決。To sum up, the above problems encountered by previous technologies still need to be further solved.

因此，本發明提出一種應用於膽固醇液晶顯示裝置的顯示驅動電路，藉以有效解決先前技術所遭遇到之上述問題。Therefore, the present invention proposes a display driving circuit applied to a cholesteric liquid crystal display device, thereby effectively solving the above-mentioned problems encountered in the prior art.

根據本發明之一較佳具體實施例為一種應用於膽固醇液晶顯示裝置的顯示驅動電路。於此實施例中，顯示驅動電路包括三個正緩衝器組、三個負緩衝器組及電位轉換器及輸出開關。該三個正緩衝器組用以分別接收第一參考電壓、第二參考電壓及第三參考電壓並分別輸出第一正驅動電壓、第二正驅動電壓及第三正驅動電壓。該三個負緩衝器組用以分別接收第四參考電壓、第五參考電壓及第六參考電壓並分別輸出第一負驅動電壓、第二負驅動電壓及第三負驅動電壓。電位轉換器及輸出開關分別耦接該三個正緩衝器組及該三個負緩衝器組，用以接收第一正驅動電壓、第二正驅動電壓、第三正驅動電壓、第一負驅動電壓、第二負驅動電壓及第三負驅動電壓並據以產生輸出信號。其中，該三個正緩衝器組、該三個負緩衝器組與電位轉換器及輸出開關均接收正電源電壓及負電源電壓。A preferred embodiment according to the present invention is a display driving circuit applied to a cholesteric liquid crystal display device. In this embodiment, the display driving circuit includes three positive buffer groups, three negative buffer groups, a potential converter and an output switch. The three positive buffer groups are used to receive the first reference voltage, the second reference voltage and the third reference voltage respectively and to output the first positive driving voltage, the second positive driving voltage and the third positive driving voltage respectively. The three negative buffer groups are used to receive the fourth reference voltage, the fifth reference voltage and the sixth reference voltage respectively and to output the first negative driving voltage, the second negative driving voltage and the third negative driving voltage respectively. The potential converter and the output switch are respectively coupled to the three positive buffer groups and the three negative buffer groups for receiving the first positive driving voltage, the second positive driving voltage, the third positive driving voltage, and the first negative driving voltage. voltage, the second negative driving voltage and the third negative driving voltage and generate an output signal accordingly. Among them, the three positive buffer groups, the three negative buffer groups, the potential converter and the output switch all receive positive power supply voltage and negative power supply voltage.

於一實施例中，顯示驅動電路還包括接收電路、移位暫存器及控制邏輯電路與解碼器及資料鎖存電路。接收電路分別接收輸入資料信號及輸入時脈信號。移位暫存器及控制邏輯電路耦接於接收電路與解碼器及資料鎖存電路之間。解碼器及資料鎖存電路耦接於移位暫存器及控制邏輯電路與電位轉換器及輸出開關之間。In one embodiment, the display driving circuit further includes a receiving circuit, a shift register, a control logic circuit, a decoder and a data latch circuit. The receiving circuit receives the input data signal and the input clock signal respectively. The shift register and the control logic circuit are coupled between the receiving circuit, the decoder and the data latch circuit. The decoder and the data latch circuit are coupled between the shift register and the control logic circuit, the potential converter and the output switch.

於一實施例中，膽固醇液晶顯示裝置包括參考電壓產生電路，耦接顯示驅動電路，用以產生第一參考電壓、第二參考電壓、第三參考電壓、第四參考電壓、第五參考電壓及第六參考電壓至顯示驅動電路。In one embodiment, the cholesteric liquid crystal display device includes a reference voltage generating circuit coupled to the display driving circuit for generating a first reference voltage, a second reference voltage, a third reference voltage, a fourth reference voltage, a fifth reference voltage and The sixth reference voltage is supplied to the display driving circuit.

於一實施例中，參考電壓產生電路係設置於印刷電路板(PCB)上。In one embodiment, the reference voltage generating circuit is disposed on a printed circuit board (PCB).

於一實施例中，膽固醇液晶顯示裝置還包括與顯示驅動電路相同的至少一顯示驅動電路。該至少一顯示驅動電路耦接參考電壓產生電路並接收第一參考電壓、第二參考電壓、第三參考電壓、第四參考電壓、第五參考電壓及第六參考電壓。In one embodiment, the cholesteric liquid crystal display device further includes at least one display driving circuit that is the same as the display driving circuit. The at least one display driving circuit is coupled to the reference voltage generating circuit and receives the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, the fifth reference voltage and the sixth reference voltage.

於一實施例中，膽固醇液晶顯示裝置包括正電源電壓產生電路及負電源電壓產生電路，耦接顯示驅動電路，用以分別產生正電源電壓及負電源電壓至顯示驅動電路。In one embodiment, the cholesteric liquid crystal display device includes a positive power supply voltage generating circuit and a negative power supply voltage generating circuit coupled to the display driving circuit for respectively generating positive power supply voltage and negative power supply voltage to the display driving circuit.

於一實施例中，膽固醇液晶顯示裝置還包括與顯示驅動電路相同的至少一顯示驅動電路，該至少一顯示驅動電路耦接正電源電壓產生電路及負電源電壓產生電路並接收正電源電壓及負電源電壓。In one embodiment, the cholesteric liquid crystal display device further includes at least one display driving circuit that is the same as the display driving circuit. The at least one display driving circuit is coupled to the positive power supply voltage generating circuit and the negative power supply voltage generating circuit and receives the positive power supply voltage and the negative power supply voltage generating circuit. supply voltage.

於一實施例中，正電源電壓產生電路及負電源電壓產生電路係設置於印刷電路板(PCB)上。In one embodiment, the positive power supply voltage generating circuit and the negative power supply voltage generating circuit are disposed on a printed circuit board (PCB).

相較於先前技術，本發明提出的應用於膽固醇液晶顯示裝置的顯示驅動電路係將具有被動及主動元件的一個或多個驅動電壓源組整合至其內部，不僅可利用原本的顯示驅動電路的製程相容性來減少設計風險，還可有效簡化印刷電路板(PCB)的設計複雜度，故能大幅降低其生產成本。Compared with the prior art, the display driving circuit proposed by the present invention for use in a cholesteric liquid crystal display device integrates one or more driving voltage source groups with passive and active components into its interior, which not only utilizes the advantages of the original display driving circuit. Process compatibility can reduce design risks and effectively simplify the design complexity of printed circuit boards (PCBs), thus significantly reducing their production costs.

根據本發明之一較佳具體實施例為一種應用於膽固醇液晶顯示裝置的顯示驅動電路。請參照圖4及圖5，圖4繪示此實施例中之膽固醇液晶顯示裝置4的示意圖；圖5繪示應用於膽固醇液晶顯示裝置4的顯示驅動電路41的示意圖。A preferred embodiment according to the present invention is a display driving circuit applied to a cholesteric liquid crystal display device. Please refer to FIGS. 4 and 5 . FIG. 4 shows a schematic diagram of the cholesteric liquid crystal display device 4 in this embodiment. FIG. 5 shows a schematic diagram of the display driving circuit 41 applied to the cholesteric liquid crystal display device 4 .

如圖4所示，膽固醇液晶顯示裝置4包括正電源電壓產生電路BOOST、負電源電壓產生電路BUCK、參考電壓產生電路P-GAMMA、低壓差穩壓電路LDO及N個顯示驅動電路41~4N，其中N為正整數。正電源電壓產生電路BOOST、負電源電壓產生電路BUCK、參考電壓產生電路P-GAMMA及低壓差穩壓電路LDO均設置於印刷電路板PCB上且均耦接+12V的電源，但不以此為限。印刷電路板PCB透過軟性電路板FPC及陣列背板線路(Wring On Array)WOA耦接N個顯示驅動電路41~4N。As shown in Figure 4, the cholesterol liquid crystal display device 4 includes a positive power supply voltage generating circuit BOOST, a negative power supply voltage generating circuit BUCK, a reference voltage generating circuit P-GAMMA, a low voltage dropout voltage stabilizing circuit LDO and N display driving circuits 41~4N. Where N is a positive integer. The positive power supply voltage generating circuit BOOST, the negative power supply voltage generating circuit BUCK, the reference voltage generating circuit P-GAMMA and the low voltage dropout voltage stabilizing circuit LDO are all set on the printed circuit board PCB and are coupled to the +12V power supply, but they are not used as limit. The printed circuit board PCB is coupled to the N display driving circuits 41 to 4N through the flexible circuit board FPC and the array backplane circuit (Wring On Array) WOA.

正電源電壓產生電路BOOST分別耦接N個顯示驅動電路41~4N，用以產生正電源電壓VPP至N個顯示驅動電路41~4N。負電源電壓產生電路BUCK分別耦接N個顯示驅動電路41~4N，用以產生負電源電壓VNN至N個顯示驅動電路41~4N。低壓差穩壓電路LDO分別耦接N個顯示驅動電路41~4N，用以產生工作電壓VDD至N個顯示驅動電路41~4N。參考電壓產生電路P-GAMMA分別耦接N個顯示驅動電路41~4N，用以產生第一參考電壓REF1、第二參考電壓REF2、第三參考電壓REF3、第四參考電壓REF4、第五參考電壓REF5及第六參考電壓REF6至N個顯示驅動電路41~4N。The positive power supply voltage generating circuit BOOST is coupled to the N display driving circuits 41~4N respectively, and is used to generate the positive power supply voltage VPP to the N display driving circuits 41~4N. The negative power supply voltage generating circuit BUCK is coupled to the N display driving circuits 41~4N respectively, and is used to generate the negative power supply voltage VNN to the N display driving circuits 41~4N. The low dropout voltage stabilizing circuit LDO is coupled to the N display driving circuits 41~4N respectively, and is used to generate the operating voltage VDD to the N display driving circuits 41~4N. The reference voltage generating circuit P-GAMMA is coupled to the N display driving circuits 41~4N respectively to generate the first reference voltage REF1, the second reference voltage REF2, the third reference voltage REF3, the fourth reference voltage REF4, and the fifth reference voltage. REF5 and the sixth reference voltage REF6 to N display driving circuits 41~4N.

接下來，將以顯示驅動電路41為例進行說明。如圖5所示，顯示驅動電路41包括三個正緩衝器組PBF、三個負緩衝器組NBF、接收電路410、移位暫存器及控制邏輯電路411、解碼器及資料鎖存電路412與電位轉換器及輸出開關413。Next, the display driving circuit 41 will be described as an example. As shown in Figure 5, the display driving circuit 41 includes three positive buffer groups PBF, three negative buffer groups NBF, a receiving circuit 410, a shift register and a control logic circuit 411, a decoder and a data latch circuit 412 and potential converter and output switch 413.

接收電路410耦接至移位暫存器及控制邏輯電路411，用以接收輸入資料信號DAT_IN及輸入時脈信號CLK_IN。移位暫存器及控制邏輯電路411耦接至解碼器及資料鎖存電路412，用以傳送/接收資料輸出輸入指示信號DIO。解碼器及資料鎖存電路412耦接至電位轉換器及輸出開關413，用以接收關於解碼及資料鎖存之控制信號STB/SDOE/SDOZ並進行資料解碼及鎖存之動作。The receiving circuit 410 is coupled to the shift register and the control logic circuit 411 for receiving the input data signal DAT_IN and the input clock signal CLK_IN. The shift register and control logic circuit 411 are coupled to the decoder and data latch circuit 412 for transmitting/receiving the data output input indication signal DIO. The decoder and data latch circuit 412 is coupled to the potential converter and the output switch 413 for receiving the control signal STB/SDOE/SDOZ related to decoding and data latching and performing data decoding and latch operations.

該三個正緩衝器組PBF耦接電位轉換器及輸出開關413，用以分別接收來自參考電壓產生電路P-GAMMA的第一參考電壓REF1、第二參考電壓REF2及第三參考電壓REF3並分別輸出第一正驅動電壓VP1、第二正驅動電壓VP2及第三正驅動電壓VP3至電位轉換器及輸出開關413。The three positive buffer groups PBF are coupled to the potential converter and the output switch 413 to respectively receive the first reference voltage REF1, the second reference voltage REF2 and the third reference voltage REF3 from the reference voltage generating circuit P-GAMMA and respectively The first positive driving voltage VP1, the second positive driving voltage VP2 and the third positive driving voltage VP3 are output to the potential converter and the output switch 413.

該三個負緩衝器組NBF耦接電位轉換器及輸出開關413，用以分別接收來自參考電壓產生電路P-GAMMA的第四參考電壓REF4、第五參考電壓REF5及第六參考電壓REF6並分別輸出第一負驅動電壓VN1、第二負驅動電壓VN2及第三負驅動電壓VN3至電位轉換器及輸出開關413。The three negative buffer groups NBF are coupled to the potential converter and the output switch 413 to respectively receive the fourth reference voltage REF4, the fifth reference voltage REF5 and the sixth reference voltage REF6 from the reference voltage generating circuit P-GAMMA and respectively The first negative driving voltage VN1, the second negative driving voltage VN2 and the third negative driving voltage VN3 are output to the potential converter and the output switch 413.

此外，該三個正緩衝器組PBF、該三個負緩衝器組NBF及電位轉換器及輸出開關413還分別接收來自正電源電壓產生電路BOOST/負電源電壓產生電路BUCK的正電源電壓VPP/負電源電壓VNN。In addition, the three positive buffer groups PBF, the three negative buffer groups NBF, the potential converter and the output switch 413 also receive the positive power supply voltage VPP/from the positive power supply voltage generating circuit BOOST/negative power supply voltage generating circuit BUCK respectively. Negative supply voltage VNN.

電位轉換器及輸出開關413分別耦接該三個正緩衝器組PBF及該三個負緩衝器組NBF，用以接收第一正驅動電壓VP1、第二正驅動電壓VP2、第三正驅動電壓VP3、第一負驅動電壓VN1、第二負驅動電壓VN2及第三負驅動電壓VN3並據以產生輸出信號OUT。The potential converter and the output switch 413 are respectively coupled to the three positive buffer groups PBF and the three negative buffer groups NBF for receiving the first positive driving voltage VP1, the second positive driving voltage VP2, and the third positive driving voltage. VP3, the first negative driving voltage VN1, the second negative driving voltage VN2 and the third negative driving voltage VN3 and generate the output signal OUT accordingly.

根據圖4及圖5可知：此實施例中之膽固醇液晶顯示裝置4係利用正緩衝器組PBF及負緩衝器組NBF可與每個顯示驅動電路41~4N共用製程(均可使用LV/HV=3.3V/50V)的特性將三個正緩衝器組PBF及三個負緩衝器組NBF整合至顯示驅動電路41內而變成內嵌於顯示驅動電路41的三個正緩衝器組PBF及三個負緩衝器組NBF，藉以提供顯示驅動電路41本身所需的第一正驅動電壓VP1至第三正驅動電壓VP3及第一負驅動電壓VN1至第三負驅動電壓VN3。至於膽固醇液晶顯示裝置4的其他顯示驅動電路42~4N亦可依此類推，於此不另行贅述。According to FIG. 4 and FIG. 5 , it can be seen that the cholesteric liquid crystal display device 4 in this embodiment uses the positive buffer group PBF and the negative buffer group NBF to share the same process with each display driving circuit 41 ~ 4N (both can use LV/HV =3.3V/50V), three positive buffer groups PBF and three negative buffer groups NBF are integrated into the display driving circuit 41 to become three positive buffer groups PBF and three negative buffer groups embedded in the display driving circuit 41 A negative buffer group NBF is provided to provide the first to third positive driving voltages VP1 to VP3 and the first to third negative driving voltages VN1 to VN3 required by the display driving circuit 41 itself. As for the other display driving circuits 42 to 4N of the cholesterol liquid crystal display device 4 , the same can be said and will not be described again here.

由於此實施例中之印刷電路板PCB上不需如同先前技術設置大量的主動及被動元件來提供驅動電壓給各顯示驅動電路，而僅需透過參考電壓產生電路P-GAMMA提供第一參考電壓REF1至第六參考電壓REF6給內嵌於各顯示驅動電路的三個正緩衝器組PBF及三個負緩衝器組NBF即可，故可大幅簡化印刷電路板PCB上的電路設計並可有效節省生產成本。Since the printed circuit board PCB in this embodiment does not need to be equipped with a large number of active and passive components to provide driving voltage to each display driving circuit as in the prior art, it only needs to provide the first reference voltage REF1 through the reference voltage generating circuit P-GAMMA. The sixth reference voltage REF6 can be supplied to the three positive buffer groups PBF and three negative buffer groups NBF embedded in each display driving circuit. Therefore, the circuit design on the printed circuit board PCB can be greatly simplified and production can be effectively saved. cost.

根據本發明之另一較佳具體實施例亦為一種應用於膽固醇液晶顯示裝置的顯示驅動電路。請參照圖6及圖7A至圖7C，圖6繪示此實施例中之膽固醇液晶顯示裝置6的示意圖；圖7A至圖7C分別繪示應用於膽固醇液晶顯示裝置6的三個顯示驅動電路61~63的示意圖。Another preferred embodiment according to the present invention is also a display driving circuit applied to a cholesteric liquid crystal display device. Please refer to FIG. 6 and FIG. 7A to FIG. 7C. FIG. 6 illustrates a schematic diagram of the cholesteric liquid crystal display device 6 in this embodiment. FIGS. 7A to 7C respectively illustrate three display driving circuits 61 applied to the cholesteric liquid crystal display device 6. Schematic diagram of ~63.

如圖6所示，膽固醇液晶顯示裝置6包括正電源電壓產生電路BOOST、負電源電壓產生電路BUCK、參考電壓產生電路P-GAMMA、低壓差穩壓電路LDO、匯流排BUS及N個顯示驅動電路61~6N，其中N為正整數且為3的倍數(亦即以每三個顯示驅動電路為一組)。正電源電壓產生電路BOOST、負電源電壓產生電路BUCK、參考電壓產生電路P-GAMMA及低壓差穩壓電路LDO均設置於印刷電路板PCB上且均耦接+12V的電源，但不以此為限。印刷電路板PCB透過軟性電路板FPC及陣列背板線路WOA耦接該N個顯示驅動電路61~6N。匯流排BUS設置於軟性電路板FPC上。As shown in Figure 6, the cholesterol liquid crystal display device 6 includes a positive power supply voltage generating circuit BOOST, a negative power supply voltage generating circuit BUCK, a reference voltage generating circuit P-GAMMA, a low voltage dropout voltage stabilizing circuit LDO, a bus BUS and N display driving circuits 61~6N, where N is a positive integer and a multiple of 3 (that is, every three display driving circuits are a group). The positive power supply voltage generating circuit BOOST, the negative power supply voltage generating circuit BUCK, the reference voltage generating circuit P-GAMMA and the low voltage dropout voltage stabilizing circuit LDO are all set on the printed circuit board PCB and are coupled to the +12V power supply, but they are not used as limit. The printed circuit board PCB is coupled to the N display driving circuits 61 to 6N through the flexible circuit board FPC and the array backplane circuit WOA. The bus BUS is installed on the flexible circuit board FPC.

正電源電壓產生電路BOOST分別耦接該N個顯示驅動電路61~6N，用以產生正電源電壓VPP至該N個顯示驅動電路61~6N。負電源電壓產生電路BUCK分別耦接該N個顯示驅動電路61~6N，用以產生負電源電壓VNN至該N個顯示驅動電路61~6N。低壓差穩壓電路LDO分別耦接該N個顯示驅動電路61~6N，用以產生工作電壓VDD至該N個顯示驅動電路61~6N。參考電壓產生電路P-GAMMA分別耦接該N個顯示驅動電路61~6N。匯流排BUS分別耦接該N個顯示驅動電路61~6N。The positive power supply voltage generating circuit BOOST is coupled to the N display driving circuits 61 ~ 6N respectively, and is used to generate the positive power supply voltage VPP to the N display driving circuits 61 ~ 6N. The negative power supply voltage generating circuit BUCK is coupled to the N display driving circuits 61 ~ 6N respectively, and is used to generate the negative power supply voltage VNN to the N display driving circuits 61 ~ 6N. The low dropout voltage stabilizing circuit LDO is coupled to the N display driving circuits 61 ~ 6N respectively, and is used to generate the operating voltage VDD to the N display driving circuits 61 ~ 6N. The reference voltage generating circuit P-GAMMA is coupled to the N display driving circuits 61 to 6N respectively. The bus BUS is coupled to the N display driving circuits 61 to 6N respectively.

若以彼此相同的顯示驅動電路61~63為例進行說明，參考電壓產生電路P-GAMMA產生第一參考電壓REF1及第四參考電壓REF4至顯示驅動電路61、產生第二參考電壓REF2及第五參考電壓REF5至顯示驅動電路62、以及產生第三參考電壓REF3及第六參考電壓REF6至顯示驅動電路63；匯流排BUS分別接收來自顯示驅動電路61的第一正驅動電壓VP1及第一負驅動電壓VN1、來自顯示驅動電路62的第二正驅動電壓VP2及第二負驅動電壓VN2、以及來自顯示驅動電路63的第三正驅動電壓VP3及第三負驅動電壓VN3，並且匯流排BUS可將第一正驅動電壓VP1至第三正驅動電壓VP3及第一負驅動電壓VN1至第三負驅動電壓VN3分別提供給每個顯示驅動電路61~63。至於其他顯示驅動電路64~6N亦可依此類推，於此不另行贅述。Taking the same display driving circuits 61 to 63 as an example, the reference voltage generating circuit P-GAMMA generates the first reference voltage REF1 and the fourth reference voltage REF4 to the display driving circuit 61, and generates the second reference voltage REF2 and the fifth reference voltage REF2. The reference voltage REF5 is sent to the display driving circuit 62, and the third reference voltage REF3 and the sixth reference voltage REF6 are generated to the display driving circuit 63; the bus BUS receives the first positive driving voltage VP1 and the first negative driving voltage from the display driving circuit 61 respectively. voltage VN1, the second positive driving voltage VP2 and the second negative driving voltage VN2 from the display driving circuit 62, and the third positive driving voltage VP3 and the third negative driving voltage VN3 from the display driving circuit 63, and the bus BUS can The first to third positive driving voltages VP1 to VP3 and the first to third negative driving voltages VN1 to VN3 are provided to each of the display driving circuits 61 to 63 respectively. The same can be said for other display driving circuits 64 to 6N, which will not be described again here.

接著，請參照圖7A，圖7A繪示圖6中的顯示驅動電路61的示意圖。如圖7A所示，顯示驅動電路61包括一個正緩衝器組PBF、一個負緩衝器組NBF、接收電路610、移位暫存器及控制邏輯電路611、解碼器及資料鎖存電路612與電位轉換器及輸出開關613。Next, please refer to FIG. 7A , which is a schematic diagram of the display driving circuit 61 in FIG. 6 . As shown in FIG. 7A , the display driving circuit 61 includes a positive buffer group PBF, a negative buffer group NBF, a receiving circuit 610, a shift register and a control logic circuit 611, a decoder and a data latch circuit 612 and a potential Converter and output switch 613.

接收電路610耦接至移位暫存器及控制邏輯電路611，用以接收輸入資料信號DAT_IN及輸入時脈信號CLK_IN。移位暫存器及控制邏輯電路611耦接至解碼器及資料鎖存電路612，用以傳送/接收資料輸出輸入指示信號DIO。解碼器及資料鎖存電路612耦接至電位轉換器及輸出開關613，用以接收關於解碼及資料鎖存之控制信號STB/SDOE/SDOZ並進行資料解碼及鎖存之動作。The receiving circuit 610 is coupled to the shift register and the control logic circuit 611 for receiving the input data signal DAT_IN and the input clock signal CLK_IN. The shift register and control logic circuit 611 is coupled to the decoder and data latch circuit 612 for transmitting/receiving the data output input indication signal DIO. The decoder and data latch circuit 612 is coupled to the potential converter and the output switch 613 for receiving the control signal STB/SDOE/SDOZ related to decoding and data latching and performing data decoding and latch operations.

正緩衝器組PBF用以接收來自參考電壓產生電路P-GAMMA的第一參考電壓REF1並輸出第一正驅動電壓VP1至匯流排BUS。負緩衝器組NBF用以接收來自參考電壓產生電路P-GAMMA的第四參考電壓REF4並輸出第一負驅動電壓VN1至匯流排BUS。電位轉換器及輸出開關613耦接匯流排BUS，用以自匯流排BUS接收第一正驅動電壓VP1至第三正驅動電壓VP3及第一負驅動電壓VN1至第三負驅動電壓VN3並據以產生輸出信號OUT。The positive buffer group PBF is used to receive the first reference voltage REF1 from the reference voltage generating circuit P-GAMMA and output the first positive driving voltage VP1 to the bus BUS. The negative buffer group NBF is used to receive the fourth reference voltage REF4 from the reference voltage generating circuit P-GAMMA and output the first negative driving voltage VN1 to the bus BUS. The potential converter and the output switch 613 are coupled to the bus BUS for receiving the first positive driving voltage VP1 to the third positive driving voltage VP3 and the first negative driving voltage VN1 to the third negative driving voltage VN3 from the bus BUS and according to the Generates an output signal OUT.

至於圖7B及圖7C分別繪示圖6中的顯示驅動電路62~63的示意圖，其電路結構及運作情形可依圖7A及前面三段的文字說明類推，故於此不另行贅述。As for FIG. 7B and FIG. 7C , respectively, schematic diagrams of the display driving circuits 62 to 63 in FIG. 6 are shown. Their circuit structure and operation can be deduced from the text descriptions in FIG. 7A and the previous three paragraphs, so they will not be described again here.

根據圖6及圖7A至圖7C可知：若以彼此相同的顯示驅動電路61~63為例進行說明，此實施例中之膽固醇液晶顯示裝置6係利用正緩衝器組PBF及負緩衝器組NBF可與顯示驅動電路共用製程(均可使用LV/HV=3.3V/50V)的特性將三個正緩衝器組PBF及三個負緩衝器組NBF分別整合至三個顯示驅動電路61~63內而變成分別內嵌於顯示驅動電路61~63的三個正緩衝器組PBF及三個負緩衝器組NBF，再透過設置於軟性電路板FPC上的匯流排BUS及拉線將顯示驅動電路61提供的第一正驅動電壓VP1及第一負驅動電壓VN1、顯示驅動電路62提供的第二正驅動電壓VP2及第二負驅動電壓VN2、以及顯示驅動電路63提供的第三正驅動電壓VP3及第三負驅動電壓VN3同時共享給三個顯示驅動電路61~63使用，藉以有效減少每個顯示驅動電路61~63的面積。至於其他顯示驅動電路64~6N亦可依此類推，於此不另行贅述。According to FIG. 6 and FIG. 7A to FIG. 7C , it can be seen that if the same display driving circuits 61 to 63 are used as an example, the cholesteric liquid crystal display device 6 in this embodiment uses a positive buffer group PBF and a negative buffer group NBF. The three positive buffer groups PBF and three negative buffer groups NBF can be integrated into the three display driving circuits 61~63 due to the shared process with the display driving circuit (both can use LV/HV=3.3V/50V). It becomes three positive buffer groups PBF and three negative buffer groups NBF respectively embedded in the display driving circuits 61 to 63. The display driving circuit 61 is then connected to the display driving circuit 61 through the bus BUS and pull wires provided on the flexible circuit board FPC. The first positive driving voltage VP1 and the first negative driving voltage VN1 are provided, the second positive driving voltage VP2 and the second negative driving voltage VN2 provided by the display driving circuit 62, and the third positive driving voltage VP3 provided by the display driving circuit 63 and The third negative driving voltage VN3 is simultaneously shared by the three display driving circuits 61 to 63, thereby effectively reducing the area of each display driving circuit 61 to 63. The same can be said for other display driving circuits 64 to 6N, which will not be described again here.

由於此實施例中之印刷電路板PCB上不需如同先前技術設置大量的主動及被動元件來提供驅動電壓給各顯示驅動電路，而僅需透過參考電壓產生電路P-GAMMA提供不同組參考電壓給內嵌於各顯示驅動電路的不同正緩衝器組PBF及負緩衝器組NBF並搭配軟性電路板FPC上的匯流排BUS及拉線將驅動電壓共享給各顯示驅動電路，故可大幅簡化印刷電路板PCB上的電路設計並可有效節省生產成本。Since the printed circuit board PCB in this embodiment does not need to be equipped with a large number of active and passive components to provide driving voltages to each display driving circuit as in the prior art, it only needs to provide different sets of reference voltages through the reference voltage generating circuit P-GAMMA. Different positive buffer groups PBF and negative buffer groups NBF are embedded in each display driving circuit and are used with the bus BUS and pull wires on the flexible circuit board FPC to share the driving voltage to each display driving circuit, so the printed circuit can be greatly simplified. The circuit design on the board PCB can effectively save production costs.

相較於先前技術，本發明提出的應用於膽固醇液晶顯示裝置的顯示驅動電路係將具有被動及主動元件的一個或多個驅動電壓源組整合至其內部，不僅可利用原本的顯示驅動電路的製程相容性來減少設計風險，還可有效簡化印刷電路板(PCB)的設計複雜度，故能大幅降低其生產成本。Compared with the prior art, the display driving circuit proposed by the present invention for use in a cholesteric liquid crystal display device integrates one or more driving voltage source groups with passive and active components into its interior, which not only utilizes the advantages of the original display driving circuit. Process compatibility can reduce design risks and effectively simplify the design complexity of printed circuit boards (PCBs), thus significantly reducing their production costs.

1:膽固醇液晶顯示裝置 11~1N:顯示驅動電路 BOOST:正電源電壓產生電路 BUCK:負電源電壓產生電路 P-GAMMA:參考電壓產生電路 LDO:低壓差穩壓電路 PCB:印刷電路板 FPC:軟性電路板 WOA:陣列背板線路 PBF:正緩衝器組 NBF:負緩衝器組 BUS:匯流排 VPP:正電源電壓 VNN:負電源電壓 VDD:工作電壓 REF1~REF6:第一參考電壓~第六參考電壓 VP1~VP3:第一正驅動電壓~第三正驅動電壓 VN1~VN3:第一負驅動電壓~第三負驅動電壓 R1~R2:回授電阻 BF:緩衝器 110:接收電路 111:移位暫存器及控制邏輯電路 112:解碼器及資料鎖存電路 113:電位轉換器及輸出開關 OUT:輸出信號 VPP:正電源電壓 VNN:負電源電壓 DAT_IN:輸入資料信號 CLK_IN:輸入時脈信號 STB/SDOE/SDOZ:控制信號 DIO:資料輸出輸入指示信號 4:膽固醇液晶顯示裝置 41~4N:顯示驅動電路 410:接收電路 411:移位暫存器及控制邏輯電路 412:解碼器及資料鎖存電路 413:電位轉換器及輸出開關 6:膽固醇液晶顯示裝置 61~6N:顯示驅動電路 610:接收電路 611:移位暫存器及控制邏輯電路 612:解碼器及資料鎖存電路 613:電位轉換器及輸出開關 620:接收電路 621:移位暫存器及控制邏輯電路 622:解碼器及資料鎖存電路 623:電位轉換器及輸出開關 630:接收電路 631:移位暫存器及控制邏輯電路 632:解碼器及資料鎖存電路 633:電位轉換器及輸出開關1:Cholesterol LCD device 11~1N: Display drive circuit BOOST: Positive supply voltage generating circuit BUCK: Negative supply voltage generating circuit P-GAMMA: Reference voltage generation circuit LDO: low dropout voltage regulator circuit PCB: printed circuit board FPC: flexible circuit board WOA: array backplane circuit PBF: positive buffer group NBF: negative buffer group BUS: bus VPP: Positive supply voltage VNN: negative supply voltage VDD: working voltage REF1~REF6: first reference voltage~sixth reference voltage VP1~VP3: first positive driving voltage~third positive driving voltage VN1~VN3: first negative driving voltage~third negative driving voltage R1~R2: feedback resistor BF: buffer 110: Receiving circuit 111: Shift register and control logic circuit 112: Decoder and data latch circuit 113: Potential converter and output switch OUT: output signal VPP: Positive supply voltage VNN: negative supply voltage DAT_IN: input data signal CLK_IN: input clock signal STB/SDOE/SDOZ: control signal DIO: data output input indication signal 4:Cholesterol LCD device 41~4N: Display drive circuit 410: Receiving circuit 411: Shift register and control logic circuit 412: Decoder and data latch circuit 413: Potential converter and output switch 6:Cholesterol LCD device 61~6N: Display drive circuit 610: Receiving circuit 611: Shift register and control logic circuit 612: Decoder and data latch circuit 613: Potential converter and output switch 620: Receiving circuit 621: Shift register and control logic circuit 622: Decoder and data latch circuit 623: Potential converter and output switch 630: Receiving circuit 631: Shift register and control logic circuit 632: Decoder and data latch circuit 633: Potential converter and output switch

圖1繪示先前技術之膽固醇液晶顯示裝置的示意圖。FIG. 1 is a schematic diagram of a prior art cholesteric liquid crystal display device.

圖2A及圖2B分別繪示圖1中之正緩衝器組及負緩衝器組的示意圖。FIG. 2A and FIG. 2B are schematic diagrams of the positive buffer group and the negative buffer group in FIG. 1 respectively.

圖3繪示圖1中之顯示驅動電路的示意圖。FIG. 3 is a schematic diagram of the display driving circuit in FIG. 1 .

圖4繪示本發明之一具體實施例中之膽固醇液晶顯示裝置的示意圖。FIG. 4 is a schematic diagram of a cholesteric liquid crystal display device in an embodiment of the present invention.

圖5繪示應用於膽固醇液晶顯示裝置的顯示驅動電路的示意圖。FIG. 5 is a schematic diagram of a display driving circuit applied to a cholesteric liquid crystal display device.

圖6繪示本發明之另一具體實施例中之膽固醇液晶顯示裝置的示意圖。FIG. 6 is a schematic diagram of a cholesteric liquid crystal display device in another specific embodiment of the present invention.

圖7A至圖7C分別繪示應用於膽固醇液晶顯示裝置的三個顯示驅動電路的示意圖。7A to 7C respectively illustrate schematic diagrams of three display driving circuits applied to a cholesteric liquid crystal display device.

41:顯示驅動電路 41:Display drive circuit

410:接收電路 410: Receiving circuit

411:移位暫存器及控制邏輯電路 411: Shift register and control logic circuit

412:解碼器及資料鎖存電路 412: Decoder and data latch circuit

413:電位轉換器及輸出開關 413: Potential converter and output switch

PBF:正緩衝器組 PBF: positive buffer group

NBF:負緩衝器組 NBF: negative buffer group

REF1~REF6:第一參考電壓~第六參考電壓 REF1~REF6: first reference voltage~sixth reference voltage

VP1~VP3:第一正驅動電壓~第三正驅動電壓 VP1~VP3: first positive driving voltage~third positive driving voltage

VN1~VN3:第一負驅動電壓~第三負驅動電壓 VN1~VN3: first negative driving voltage~third negative driving voltage

OUT:輸出信號 OUT: output signal

VPP:正電源電壓 VPP: Positive supply voltage

VNN:負電源電壓 VNN: negative supply voltage

DAT_IN:輸入資料信號 DAT_IN: input data signal

CLK_IN:輸入時脈信號 CLK_IN: input clock signal

STB/SDOE/SDOZ:控制信號 STB/SDOE/SDOZ: control signal

DIO:資料輸出輸入指示信號 DIO: data output input indication signal

Claims (8)

一種顯示驅動電路，應用於膽固醇液晶顯示裝置，該顯示驅動電路包括： 三個正緩衝器組，用以分別接收第一參考電壓、第二參考電壓及第三參考電壓並分別輸出第一正驅動電壓、第二正驅動電壓及第三正驅動電壓； 三個負緩衝器組，用以分別接收第四參考電壓、第五參考電壓及第六參考電壓並分別輸出第一負驅動電壓、第二負驅動電壓及第三負驅動電壓；以及 電位轉換器及輸出開關，分別耦接該三個正緩衝器組及該三個負緩衝器組，用以接收該第一正驅動電壓、該第二正驅動電壓、該第三正驅動電壓、該第一負驅動電壓、該第二負驅動電壓及該第三負驅動電壓並據以產生輸出信號； 其中，該三個正緩衝器組、該三個負緩衝器組與該電位轉換器及輸出開關均接收正電源電壓及負電源電壓。 A display driving circuit applied to a cholesteric liquid crystal display device, the display driving circuit includes: Three positive buffer groups are used to receive the first reference voltage, the second reference voltage and the third reference voltage respectively and to output the first positive driving voltage, the second positive driving voltage and the third positive driving voltage respectively; Three negative buffer groups are used to receive the fourth reference voltage, the fifth reference voltage and the sixth reference voltage respectively and to output the first negative driving voltage, the second negative driving voltage and the third negative driving voltage respectively; and The potential converter and the output switch are respectively coupled to the three positive buffer groups and the three negative buffer groups for receiving the first positive driving voltage, the second positive driving voltage, the third positive driving voltage, the first negative driving voltage, the second negative driving voltage and the third negative driving voltage and generate an output signal accordingly; Among them, the three positive buffer groups, the three negative buffer groups, the potential converter and the output switch all receive positive power supply voltage and negative power supply voltage. 如請求項1所述的顯示驅動電路，還包括接收電路、移位暫存器及控制邏輯電路與解碼器及資料鎖存電路；該接收電路分別接收輸入資料信號及輸入時脈信號；該移位暫存器及控制邏輯電路耦接於該接收電路與該解碼器及資料鎖存電路之間；該解碼器及資料鎖存電路耦接於該移位暫存器及控制邏輯電路與該電位轉換器及輸出開關之間。The display driving circuit as described in claim 1 also includes a receiving circuit, a shift register, a control logic circuit, a decoder and a data latch circuit; the receiving circuit receives the input data signal and the input clock signal respectively; the shift circuit A bit register and a control logic circuit are coupled between the receiving circuit and the decoder and data latch circuit; the decoder and data latch circuit are coupled between the shift register and control logic circuit and the potential between converter and output switch. 如請求項1所述的顯示驅動電路，其中該膽固醇液晶顯示裝置包括參考電壓產生電路，耦接該顯示驅動電路，用以產生該第一參考電壓、該第二參考電壓、該第三參考電壓、該第四參考電壓、該第五參考電壓及該第六參考電壓至該顯示驅動電路。The display driving circuit of claim 1, wherein the cholesteric liquid crystal display device includes a reference voltage generating circuit coupled to the display driving circuit for generating the first reference voltage, the second reference voltage, and the third reference voltage. , the fourth reference voltage, the fifth reference voltage and the sixth reference voltage to the display driving circuit. 如請求項3所述的顯示驅動電路，其中該膽固醇液晶顯示裝置還包括與顯示驅動電路相同的至少一顯示驅動電路，該至少一顯示驅動電路耦接該參考電壓產生電路並接收該第一參考電壓、該第二參考電壓、該第三參考電壓、該第四參考電壓、該第五參考電壓及該第六參考電壓。The display driving circuit of claim 3, wherein the cholesteric liquid crystal display device further includes at least one display driving circuit that is the same as the display driving circuit, and the at least one display driving circuit is coupled to the reference voltage generating circuit and receives the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, the fifth reference voltage and the sixth reference voltage. 如請求項3所述的顯示驅動電路，其中該參考電壓產生電路係設置於印刷電路板上。The display driving circuit of claim 3, wherein the reference voltage generating circuit is disposed on a printed circuit board. 如請求項1所述的顯示驅動電路，其中該膽固醇液晶顯示裝置包括正電源電壓產生電路及負電源電壓產生電路，耦接該顯示驅動電路，用以分別產生正電源電壓及負電源電壓至該顯示驅動電路。The display driving circuit of claim 1, wherein the cholesteric liquid crystal display device includes a positive power supply voltage generating circuit and a negative power supply voltage generating circuit, coupled to the display driving circuit, for respectively generating positive power supply voltage and negative power supply voltage to the Display driver circuit. 如請求項6所述的顯示驅動電路，其中該膽固醇液晶顯示裝置還包括與顯示驅動電路相同的至少一顯示驅動電路，該至少一顯示驅動電路耦接該正電源電壓產生電路及該負電源電壓產生電路並接收該正電源電壓及該負電源電壓。The display driving circuit of claim 6, wherein the cholesteric liquid crystal display device further includes at least one display driving circuit that is the same as the display driving circuit, and the at least one display driving circuit is coupled to the positive power supply voltage generating circuit and the negative power supply voltage. A circuit is generated and receives the positive supply voltage and the negative supply voltage. 如請求項6所述的顯示驅動電路，其中該正電源電壓產生電路及該負電源電壓產生電路係設置於印刷電路板上。The display driving circuit of claim 6, wherein the positive power supply voltage generating circuit and the negative power supply voltage generating circuit are disposed on a printed circuit board.
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