TWI811245B - 用於顯示器應用之堆疊結構及製造其的方法與系統 - Google Patents
用於顯示器應用之堆疊結構及製造其的方法與系統 Download PDFInfo
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- TWI811245B TWI811245B TW107134605A TW107134605A TWI811245B TW I811245 B TWI811245 B TW I811245B TW 107134605 A TW107134605 A TW 107134605A TW 107134605 A TW107134605 A TW 107134605A TW I811245 B TWI811245 B TW I811245B
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- Prior art keywords
- dielectric layer
- layer
- metal electrode
- dielectric
- chamber
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- 238000000034 method Methods 0.000 title claims description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 63
- 238000012545 processing Methods 0.000 claims description 55
- 238000000151 deposition Methods 0.000 claims description 28
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 238000012546 transfer Methods 0.000 claims description 17
- 238000000231 atomic layer deposition Methods 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 11
- 239000004408 titanium dioxide Substances 0.000 claims description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 8
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 7
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract description 10
- 239000003989 dielectric material Substances 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 213
- 239000000758 substrate Substances 0.000 description 53
- 239000002243 precursor Substances 0.000 description 10
- 239000010409 thin film Substances 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 9
- 238000004140 cleaning Methods 0.000 description 8
- 239000007789 gas Substances 0.000 description 6
- 239000012636 effector Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 238000011282 treatment Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 3
- NFHFRUOZVGFOOS-UHFFFAOYSA-N palladium;triphenylphosphane Chemical compound [Pd].C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1 NFHFRUOZVGFOOS-UHFFFAOYSA-N 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- RKTYLMNFRDHKIL-UHFFFAOYSA-N copper;5,10,15,20-tetraphenylporphyrin-22,24-diide Chemical compound [Cu+2].C1=CC(C(=C2C=CC([N-]2)=C(C=2C=CC=CC=2)C=2C=CC(N=2)=C(C=2C=CC=CC=2)C2=CC=C3[N-]2)C=2C=CC=CC=2)=NC1=C3C1=CC=CC=C1 RKTYLMNFRDHKIL-UHFFFAOYSA-N 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- 210000000707 wrist Anatomy 0.000 description 2
- FWDQDBTTXSRLHJ-UHFFFAOYSA-N C(C)N(C)[Zr] Chemical compound C(C)N(C)[Zr] FWDQDBTTXSRLHJ-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000012809 cooling fluid Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005485 electric heating Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- LNKYFCABELSPAN-UHFFFAOYSA-N ethyl(methyl)azanide;titanium(4+) Chemical compound [Ti+4].CC[N-]C.CC[N-]C.CC[N-]C.CC[N-]C LNKYFCABELSPAN-UHFFFAOYSA-N 0.000 description 1
- -1 ethylmethylamino Chemical group 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000013532 laser treatment Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- VXPLXMJHHKHSOA-UHFFFAOYSA-N propham Chemical compound CC(C)OC(=O)NC1=CC=CC=C1 VXPLXMJHHKHSOA-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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- H—ELECTRICITY
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- C23C16/45525—Atomic layer deposition [ALD]
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
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- C—CHEMISTRY; METALLURGY
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/52—Controlling or regulating the coating process
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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- H—ELECTRICITY
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- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
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- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
- H01J37/32899—Multiple chambers, e.g. cluster tools
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
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- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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Abstract
本揭露之實施例大致有關於包含高介電常數介電層之層堆疊形成於第一介電層與金屬電極上方。高介電常數介電層具有20或更高的介電常數值且可形成為電子裝置中的電容器、閘極絕緣層或任意合適的絕緣層之一部分,電子裝置例如顯示器裝置。層堆疊包含第二介電層設置於第一介電層與金屬層上,且高介電常數介電層設置於第二介電層上。第二介電層提供均質表面,高介電常數介電層形成於均質表面上。均質表面使高介電常數介電材料得以均勻地沉積於其上,已產生均勻的厚度剖面。
Description
本揭露之實施例大致有關於用於顯示器裝置的包含介電層的層堆疊,介電層具有高介電常數(dielectric constant,K)值。本揭露之實施例尤其有關於沉積於具有金屬材料與介電材料之表面上方的包含介電層的層堆疊,介電層具有高介電常數(dielectric constant,K)值。
顯示器裝置已被廣泛使用於各種電子應用,例如電視、螢幕、手機、MP3撥放器、電子書閱讀器、個人數位助理(PDAs)等等。電容器,例如金屬-絕緣體-金屬(MIM)電容器,常使用於一些裝置中,且當操作顯示器裝置時電容器常形成以儲存電荷。電容器儲存電荷以維持驅動薄膜電晶體(TFT)的閘電壓,以定義出每幀中每像素之亮度。薄膜電晶體電路中的儲存電容器通常為MIM結構,MIM結構包含沉積於二金屬電極之間的介電層。所形成的電容器必須具有適於顯示器裝置的高電容。電容可能藉由改
變介電材料與/或介電層的維度來調整。例如,當介電層以具有高介電常數值的材料加以取代,電容同樣將會增加。二氧化鋯(Zirconium dioxide,ZrO2)具有介於約20至約50之間的介電常數值,且適合作為電容器中的介電層。然而,沉積於同時具有金屬部分與介電部分之表面上的二氧化鋯層,金屬部分例如金屬互連器,介電部分例如氮化矽(silicon nitride,SiN),由於高介電常數的介電層於金屬部分與介電部分的沉積速率不同,導致二氧化鋯層具有不均勻的厚度剖面。具有不均勻厚度剖面的高介電常數介電層可於後續的高介電常數介電層之圖案化製程期間引起過蝕刻與/或蝕刻不足。
因此,需要一種解決方案使具有均勻厚度剖面高介電常數層得以形成,高介電常數層係形成於具有不同材料的表面上方。
本揭露之實施例大致有關於包含介電層的層堆疊,介電層具有高介電常數值,介電層位於具有金屬材料與介電材料的表面上方。在一實施例中,堆疊結構包含第一介電層、設置於第一介電層上的金屬電極及設置於第一介電層與金屬電極上的層堆疊。層堆疊包含設置於第一介電層與金屬電極上的第二介電層,以及設置於第二介電層上的高介電常數介電層。在另一實施例中,堆疊結構包含金屬電極、設置於金屬電極下方的高介電
常數介電層、及層堆疊。層堆疊包含介電層和設置於該高介電常數介電層上的含矽層,其中高介電常數介電層設置於介電層上。
在另一實施例中,製造堆疊結構的方法包含沉積第一介電層於第二介電層與金屬電極上、沉積高介電常數介電層於第一介電層上、以及使高介電常數介電層退火(annealing)。
在另一實施例中,製造堆疊結構的系統包含傳送腔室、耦接於傳送腔室的電漿輔助原子層沉積(plasma enhanced atomic layer deposition)腔室、耦接於傳送腔室的熱處理腔室、以及用以進行數個步驟的控制器,該些步驟包含:在電漿輔助原子層沉積腔室中沉積第一介電層於第二介電層與金屬電極上、在電漿輔助原子層沉積腔室中沉積高介電常數介電層於第一介電層上、以及在熱處理腔室中使高介電常數介電層退火。
100、200、340:腔室
102:基板
103、201:腔室主體
104:蓋組件
106、205:基板支撐組件
108、202:狹縫閥開孔
110:射頻陰極
120:差動泵與清洗組件
122、128:風箱
124、211:軸
126:開孔
130:基座
134:孔
136:升舉銷
137:處理套組絕緣鈕
138:基板支撐表面
139:密封件
150:處理套組
186:第一密封件
188:第二密封件
203:底部
204、330:端效器
207:致動器
208:支撐指
210:加熱板結構
212:支撐棒
214:槽
300:多腔室基板處理系統
305、307:裝載鎖定腔室
310:控制器
312:中央處理器
314:記憶體
315:傳送腔室
316:支持電路
325:傳送機器人
335:腕部
342:指部
365、370:光學影像感測器
400:薄膜電晶體裝置結構
404:絕緣層
405:閘極絕緣層
408:通道區
409a:源極區
409b:汲極區
410a:源極金屬電極層
410b:汲極金屬電極層
411:層堆疊
414:閘極
416:金屬電極
418:介電層
420:高介電常數介電層
421:氮化矽層
422:第二金屬電極
424:層間介電質
D:深度
為了使本揭露的上述特徵可被詳細了解,參照實施例可更具體描述以上簡要概述之本揭露,一些實施例繪示於附圖中。然而,應注意的是,附圖僅為本揭露之典型實施例,因此不應被理解為對本揭露之保護範圍之侷限,因為本揭露可以允許其他等效實施例。
第1圖繪示根據本揭露之一實施例的可用於沉積介電層的處理腔室的剖面圖。
第2圖繪示根據本揭露之一實施例的可用於處理介電層的熱處理腔室的剖面圖。
第3圖繪示包含此處所述的處理腔室之多腔室基板處理系統的示意圖。
第4圖繪示根據本揭露之一實施例的利用層堆疊之薄膜電晶體裝置結構的剖面圖。
為了便於理解,在可能的情況下使用相同的元件符號來指示圖中共有的相同元件。可預期的是,在一實施例中揭露的元件可以有利地用於其他實施例而無需進一步描述。
本揭露之實施例大致有關於包含高介電常數介電層的層堆疊,高介電常數介電層形成於第一介電層與金屬電極上方。高介電常數介電層具有20或更高的介電常數值,且可形成為電容器、閘極絕緣層(gate insulating layer)或電子裝置中任何合適的絕緣層的一部分,電子裝置例如是顯示器裝置。層堆疊包含設置於第一介電層與金屬層上的第二介電層、以及設置於第二介電層上的高介電常數介電層。第二介電層提供均質表面,高介電常數介電層係形成於該均質表面上方。該均質表面使高介電常數介電材料得以均勻地沉積於其上方,形成均勻的厚度剖面。層堆疊可沉積於整合處理平台,包含至少一個用於沉積一或多層的沉積腔室與至少一個退火腔室以使沉積的一或多層退火。
如此處使用的詞「上方」、「其上方」、「下方」、「之間」、「上」與「其上」代表一層相對於其他層的相對位置。因此,舉例來說,設置於另一層的上方或下方之一層可能直接接
觸其他層或可能具有一或更多中介層。再者,設置於數層之間的一層可能直接接觸二層或可能具有一或更多中介層。相反地,在第二層「上」的第一層係為直接接觸第二層。此外,一層相對於其他層的相對位置係提供為假設操作是相對基板進行,不需要考慮基板的絕對方位。
第1圖繪示可用於實現此處討論之實施例的原子層沉積(atomic layer deposition,ALD)腔室100的剖面示意圖。原子層沉積腔室100可為電漿輔助原子層沉積腔室(PE-ALD)。在一實施例中,顯示器裝置中的介電層與明顯不同於介電層的高介電常數介電層皆形成於腔室100中。一般而言,腔室100包含以腔室主體103與蓋組件104定義出的外殼。基板支撐組件106與處理套組150設置於外殼內。蓋組件104設置於腔室主體103上,且基板支撐組件106至少部分設置於腔室主體103內。腔室主體103包含形成於其側壁中的狹縫閥開孔108以提供通道至處理腔室100內部。在一些實施例中,腔室主體103包含一或更多與真空系統(例如真空泵)流體連通的縫隙。縫隙為腔室100內的氣體提供出口。蓋組件104包含一或更多差動泵與清洗組件120。差動泵與清洗組件120和風箱122安裝至蓋組件104。風箱122使差動泵與清洗組件120得以相對於蓋組件104垂直移動,同時仍維持密封不使氣體外洩。當處理套組150升高至處理位置,處理套組150上的第一密封件186與第二密封件188和差動泵與清洗組件120接觸。差動泵與清洗組件120和真空系統(未繪示)連接,且維持於低壓。
如第1圖所示,蓋組件104包含射頻(RF)陰極110,可於腔室100內與/或處理套組150內產生活性物種電漿。射頻陰極110可藉由電加熱元件(未繪示)來加熱,且藉由冷卻流體循環來冷卻。可使用任何可使氣體活化為活性物種並維持活性物種電漿的電源。例如,可使用基於射頻或微波(MW)的放電技術。活化亦可藉由基於熱的技術、氣體擊穿(gas breakdown)技術、高密度光源(例如紫外光能量)或暴露於X射線源來產生。
基板支撐組件106可至少部分設置於腔室主體103內。基板支撐組件106包含基板支撐構件或基座130以支撐在腔室主體103內處理的基板102。基座130通過軸124耦接至基板升降機構(未繪示),軸124延伸通過一或更多個形成於腔室主體103之底表面中的開孔126。基板升降機構係藉由風箱128撓性密封至腔室主體103,避免真空自軸124周圍外洩。基板升降機構使基座130在腔室100內垂直移動於所示之較低的機械入口位置以及處理位置、處理套組傳送位置、與基板傳送位置之間。在一些實施例中,基板升降機構於少於此處所述的位置之間移動。
如第1圖所示,基座130包含一或更多通過基座130的孔134以容納一或更多升舉銷136。每個升舉銷136安裝以使升舉銷136可自由滑動於孔134內。基板支撐組件106係為可移動的,如此一來當基板支撐組件106位於較低的位置時,升舉銷136的上表面可定位於基座130之基板支撐表面138之上。反之,當基板支撐組件106位於升高的位置時,升舉銷136的上表面係定位於
基座130之基板支撐表面138之下或實質定位於基座130之基板支撐表面138的平面。當接觸腔室主體103時,升舉銷136推基板102之較低表面,使基板升舉離開基座130。反之,基座130可使基板102升高離開升舉銷136。
在一些實施例中,基座130包含處理套組絕緣鈕137,處理套組絕緣鈕137可包含一或更多密封件139。處理套組絕緣鈕137可用以在基座130上承載處理套組150。當基座使處理套組150升舉至處理位置時,處理套組絕緣鈕137中的一或更多密封件139係為壓縮的。
第2圖繪示可用以加熱多個基板102的熱處理腔室200的剖面圖,例如在退火製程中。熱處理腔室200包含以腔室主體201定義出的外殼,腔室主體201具有底部203與狹縫閥開孔202。狹縫閥開孔202形成為通過腔室主體201之側壁以使端效器204(以虛線繪示)得以進入與離開熱處理腔室200且從基板支撐組件205遞送或收回基板102(亦以虛線繪示)。基板支撐組件205耦接至軸211,軸211設置通過腔室主體201之底部203。軸211於Z方向相對於狹縫閥開孔202升高與降低基板支撐組件205。基板支撐組件205包含複數個加熱板結構210。這些加熱板結構210藉由一或更多支撐棒212相互耦接,一或更多支撐棒212使加熱板結構210相對於相鄰的加熱板結構210維持於固定位置。支撐棒212沿著加熱板結構210之邊緣設置於各種不同的位置。支撐棒212沿著加熱板結構210之邊緣排列使複數個支撐指208如以下更詳細描
述般通過。包含所有加熱板結構210與支撐棒212的基板支撐組件205如單一結構般移動於熱處理腔室200內。
支撐指208耦接至致動器207。致動器207使支撐指208移動於相對腔室主體201之縱軸的至少側向的方向(例如,於和Z方向夾角非零的橫向方向,例如於X與Y方向中至少一者),以控制支撐指208相對於腔室主體201之延伸距離。每一個加熱板結構210包含形成於其中的槽214,當基板支撐組件205垂直移動時,槽214使複數個支撐指208得以通過。每一個支撐指208從腔室主體201向內延伸的距離相當於每一個槽214之深度D,以在加熱板結構210移動經過該處時使支撐指208之遠端(即最深處)得以通過。
第3圖繪示適用於製造此處揭露之層堆疊中的一或更多層的整合式多腔室基板處理系統300的俯視圖。層堆疊可併入任何合適的顯示器裝置中,例如有機發光二極體(organic light emitting diodes,OLEDS)、薄膜電晶體或薄膜封裝(thin-film encapsulation,TFE)。系統300包含複數個處理腔室100、200、340與圍繞著中央的傳送腔室315定位之一或更多個裝載鎖定腔室305、307。處理腔室100、200、340提供以完成許多不同的處理步驟以達成對扁平介質之預定處理,例如大面積基板102(以虛線繪示)。在一實施例中,處理腔室100用以形成介電層與介電層上的高介電常數介電層,且處理腔室200用以使高介電常數介電層退火。在另一實施例中,介電層與高介電常數介電層形成於處理
腔室340中,處理腔室340係為電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)腔室,例如取自位於加利福尼亞州聖塔克拉拉(Santa Clara,California)的應用材料公司(Applied Materials,Inc.)的AKT® 55KS電漿輔助化學氣相沉積腔室。裝載鎖定腔室305、307裝配以使四邊形基板從多腔室基板處理系統300外部的周邊環境傳送至傳送腔室315內部的真空環境。
具有端效器330的傳送機器人325定位於傳送腔室315內。端效器330裝配以獨立於傳送機器人325被支撐與移動,以傳送基板102。端效器330包含適於支撐基板102的腕部335與複數個指部342。傳送機器人325視需求包含設置於傳送機器人325上的一或更多光學影像感測器365、370。
併入多腔室基板處理系統300的處理腔室340可為任何合適的腔室,例如高密度電漿化學氣相沉積(HDP-CVD)、有機金屬化學氣相沉積(MOCVD)、電漿輔助化學氣相沉積、原子層化學氣相沉積(ALD)、電漿輔助原子層化學氣相沉積(PE-ALD)、熱化學氣相沉積(thermal CVD)、熱退火(thermal annealing)、物理氣相沉積(PVD)、表面處理、電子束處理(electron beam(e-beam)treatment)、電漿處理(plasma treatment)、蝕刻腔室(etching chambers)、離子佈植腔室(ion implantation chambers)、表面清潔腔室(surface cleaning chamber)、計量腔室(metrology chambers)、旋轉塗佈腔室(spin-coating
chamber)、聚合物旋鍍腔室(polymer spinning deposition chamber)、遮蔽框架儲存腔室(shadow frame storage chamber)或任何根據需求之合適的腔室。在一繪示於多腔室基板處理系統300之示例中,系統300包含腔室100、腔室200與其他符合需要之合適的腔室340。藉由此類配置,介電層藉由電漿輔助原子層化學氣相沉積製程來形成,且高介電常數介電層之退火整合進行於單一系統,不需要破壞真空以便維持基板之清潔度,使基板不會有來自環境之不需要的汙染與殘留物。
控制器310可耦接至多腔室基板處理系統300之各種不同的零件以控制其操作。控制器310包含中央處理器(CPU)312、記憶體314與支持電路316。控制器310可直接控制多腔室基板處理系統300或藉由連接至特定處理腔室與/或支援系統元件之電腦(或控制器)來控制多腔室基板處理系統300。控制器310可為任意形式之通用電腦處理器中的一者,通用電腦處理器可用於工業設置中以控制各種不同的腔室與次處理器。控制器310之記憶體314或電腦可讀取媒體(computer readable medium)可為容易取得的記憶體,例如隨機存取記憶體(random access memory,RAM)、唯讀記憶體(read only memory,ROM)、磁片(floppy disk)、硬碟(hard disk)、光學儲存媒體(optical storage media)(例如光碟或數位影音光碟)、隨身碟(flash drive)或任意其他形式的遠端或本機之數位儲存中的一或更多者。支持電路316耦接至中央處理器312以用常規方式支持處理器。這些電路包含快
取、電源供應、時脈電路(clock circuits)、輸入/輸出電路、與次系統等等。如此處所述的方法可以軟體程序儲存於記憶體314中,可執行或呼叫此軟體程序以用此處描述之方式控制多腔室基板處理系統300之操作。軟體程序亦可藉由第二中央處理器(未繪示)來儲存與/或執行,第二中央處理器位於中央處理器312控制之硬體的遠端。
第4圖繪示根據一實施例的利用層堆疊411之薄膜電晶體裝置結構400的剖面圖。如第4圖所示,薄膜電晶體裝置結構400形成於基板102上。薄膜電晶體裝置結構400用於顯示器裝置,例如有機發光二極體裝置。薄膜電晶體裝置結構400包含形成於光學透明基板102上的源極區409a、通道區408與汲極區409b,光學透明基板102具有或不具有設置於其上的可選的絕緣層404。源極區409a、通道區408與汲極區409b一般形成自初始沉積非晶質矽(amorphous silicon,a-Si)層,初始沉積非晶質矽層典型地於之後經熱處理或雷射處理以形成多晶矽(polysilicon)層。源極區409a、汲極區409b與通道區408可藉由使初始沉積非晶質矽層圖案化與離子摻雜加以形成,接著熱處理或雷射處理以形成多晶矽層。閘極絕緣層405接著沉積於源極區409a、汲極區409b與通道區408上,且閘極414沉積於閘極絕緣層405上。閘極絕緣層405可以介電材料製造,例如氮化矽或二氧化矽(silicon dioxide,SiO2)。閘極414可以金屬製造,例如鉬(molybdenum,Mo)。閘極414可為包含二或更多金屬層的層堆疊。在一實施例
中,閘極414包含設置於二鈦(titanium,Ti)層之間的鋁(aluminum,Al)層。金屬電極416亦沉積於閘極絕緣層405上。金屬電極416可用和閘極414相同的材料製造。在一實施例中,金屬層沉積於閘極絕緣層405上,且使金屬層圖案化以形成閘極414與金屬電極416。
層堆疊411包含介電層418、高介電常數介電層420與可選的氮化矽層421。層堆疊411形成於閘極絕緣層405、閘極414與金屬電極416上。介電層418沉積於閘極絕緣層405、閘極414與金屬電極416上且與閘極絕緣層405、閘極414與金屬電極416接觸,高介電常數介電層420沉積於介電層418上且與介電層418接觸,而可選的氮化矽層421沉積於高介電常數介電層420上且與高介電常數介電層420接觸。相較於閘極絕緣層405、閘極414與金屬電極416之表面,介電層418具有均質表面。介電層418之均質表面提供理想表面使高介電常數介電層420均勻沉積,以產生均勻的厚度剖面。介電層418以不同於高介電常數介電層420之材料的材料加以製造。介電層418可為任何合適的介電層,例如氧化物,例如二氧化矽、氧化鋁(aluminum oxide,Al2O3)、二氧化鈦(titanium dioxide,TiO2)或氧化釔(yttrium(III)oxide,Y2O3)。在一示例中,介電層418與閘極絕緣層405為相同介電材料。在另一示例中,介電層418為不同於閘極絕緣層405之介電材料。介電層418具有介於約2埃(Angstroms)至約100埃之間的一厚度。
在一實施例中,介電層418係為二氧化鈦且具有介於約2埃至約50埃之間的一厚度。已發現當介電層418為二氧化鈦且具有介於約2埃至約50埃之間的一厚度時,沉積於其上的高介電常數介電層420具有立方(cubic)或正方晶相(tetragonal phase)晶體結構(crystalline structure),提供比傳統沉積於金屬與介電表面上方之介電層更高的介電常數值。當沉積於二氧化鈦介電層418上時,高介電常數介電層420具有介於約30至約50之間的介電常數值。此外,在相同製程條件下,沉積於二氧化鈦介電層418上的高介電常數介電層420之沉積速率比高介電常數介電層於二氧化鈦介電層以外的金屬上高約5%至約20%。二氧化鈦介電層418還改善了高介電常數介電層420與閘極絕緣層405、閘極414和金屬電極416的表面之間的附著力。
在另一實施例中,介電層418係為具有介於約2埃至約100埃之間的一厚度之非晶質氧化鋁(Al2O3)。高介電常數介電層420可為具有介於約20至約50之間的介電常數值之二氧化鋯(ZrO2)層或二氧化鉿(hafnium dioxide,HfO2)層,且高介電常數介電層420具有介於250埃至約900埃之間的一厚度。
介電層418可在電漿輔助原子層沉積腔室中沉積於閘極絕緣層405、閘極414和金屬電極416上,如第1圖繪示之腔室100,且高介電常數介電層420可在相同的電漿輔助原子層沉積腔室中沉積於介電層418上。沉積介電層418之製程條件可相似於沉積高介電常數介電層420之製程條件。例如,在沉積介電層418
與沉積高介電常數介電層420期間,基板之溫度維持於約150。℃和約300。℃之間。在沉積介電層418與沉積高介電常數介電層420期間,處理腔室之壓力維持於約0.1托(Torr)和1托之間。在一實施例中,含鈦前驅物(titanium containing precursor)與含氧前驅物(oxygen containing precursor)交替注入處理腔室以形成介電層418,含鈦前驅物例如四(乙基甲基胺基)鈦(tetrakis(ethylmethylamino)titanium),含氧前驅物例如氧氣。在另一實施例中,含鋁前驅物(aluminum containing precursor)與含氧前驅物交替注入處理腔室以形成介電層418,含鋁前驅物例如三甲基鋁(trimethylaluminum),含氧前驅物例如氧氣。高介電常數介電層420可藉由使含鋯前驅物(zirconium containing precursor)與含氧前驅物交替注入處理腔室來沉積,含鋯前驅物例如四(乙基甲基氨基)鋯(tetrakis(ethylmethylamino)zirconium),含氧前驅物例如氧氣。
在另一實施例中,介電層418與高介電常數介電層420可沉積於電漿輔助化學氣相沉積腔室中,例如取自位於加利福尼亞州聖塔克拉拉(Santa Clara,California)的應用材料公司(Applied Materials,Inc.)的AKT® 55KS電漿輔助化學氣相沉積腔室。
高介電常數介電層420退火以增加高介電常數介電層420之介電常數值。在一實施例中,高介電常數介電層420於
沉積高介電常數介電層420之處理腔室中退火。在另一實施例中,高介電常數介電層420於熱處理腔室中退火,例如第2圖所示之熱處理腔室200。高介電常數介電層420可於惰性環境或活性環境中以高於350℃之溫度退火,例如從約350℃至約650℃。退火溫度與高介電常數介電層420之厚度有關。較薄的層可導致較高的退火溫度。在一實施例中,高介電常數介電層420於惰性氣體存在下退火,例如氮氣(N2)、氬(Ar)或其組合。在另一實施例中,高介電常數介電層420於氧化氣體存在下退火,例如氧氣(O2)、臭氧(O3)或其組合。在又一實施例中,高介電常數介電層420於惰性氣體與活性氣體中至少一者存在下退火。退火製程可在高介電常數介電層420沉積後立即進行,或在一或更多層依序形成於高介電常數介電層420上之後進行。在一實施例中,退火製程進行於可選的氮化矽層421(或可稱為含矽層)沉積於高介電常數介電層420上之後。
第二金屬電極422設置於層堆疊411上,且第二金屬電極422可用和金屬電極416相同的材料製造,或可用和金屬電極416不同的材料製造。金屬電極416、層堆疊411與第二金屬電極422可形成金屬-絕緣體-金屬電容器。在金屬-絕緣體-金屬電容器形成後,層間介電質424形成於第二金屬電極422與層堆疊411上。層間介電質424可為任何合適的介電層,例如二氧化矽或氮化矽。源極金屬電極層410a與汲極金屬電極層410b形成為通過層間介電質424、層堆疊411與閘極絕緣層405,且源極金屬電極層
410a與汲極金屬電極層410b分別電連接至源極區409a與汲極區409b。
藉由沉積介電層於金屬表面與介電表面上並沉積高介電常數介電層於其上,高介電常數介電層之厚度剖面的均勻度提升,可增加介電常數值且可達成高介電常數介電層更佳的附著力。例如,若介電層係為二氧化鈦,可獲得額外的益處例如更高的介電常數值、更高的高介電常數介電層沉積速率與改善的附著力。
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以定義本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100:腔室
102:基板
103:腔室主體
104:蓋組件
106:基板支撐組件
108:狹縫閥開孔
110:射頻陰極
120:差動泵與清洗組件
122、128:風箱
124:軸
126:開孔
130:基座
134:孔
136:升舉銷
137:處理套組絕緣鈕
138:基板支撐表面
139:密封件
150:處理套組
186:第一密封件
188:第二密封件
Claims (20)
- 一種堆疊結構,包含:一第一介電層;一第一金屬電極,設置於該第一介電層上;一層堆疊,設置於該第一介電層與該第一金屬電極上,該層堆疊包含:一第二介電層,設置於該第一介電層與該第一金屬電極上且接觸該第一介電層與該第一金屬電極;一高介電常數介電層,設置於該第二介電層上且接觸該第二介電層,該高介電常數介電層不同於該第二介電層,該高介電常數介電層包含二氧化鋯(zirconium dioxide)或二氧化鉿(hafnium dioxide),該高介電常數介電層於該第一金屬電極的上方的一位置接觸該第二介電層;及一氮化矽層,設置於該高介電常數介電層上且接觸該高介電常數介電層;一第二金屬電極,共形地設置於該氮化矽層上且接觸該氮化矽層;以及一第三介電層,共形地設置於該第二金屬電極上。
- 如請求項1所述之結構,其中該第二介電層包含二氧化矽(silicon dioxide)、氧化鋁(aluminum oxide)、二氧化鈦(titanium dioxide)或氧化釔(yttrium(III)oxide)。
- 如請求項2所述之結構,其中該第二介電層具有介於約2埃(Angstroms)至約100埃之間的一厚度。
- 如請求項1所述之結構,其中該高介電常數介電層具有介於約250埃(Angstroms)至約900埃之間的一厚度。
- 如請求項1所述之結構,其中該第一介電層包含氮化矽(silicon nitride)或二氧化矽。
- 如請求項5所述之結構,其中該第一金屬電極包含一鋁(aluminum)層或一鉬(molybdenum)層。
- 如請求項6所述之結構,其中該第一金屬電極包含該鋁層,且其中該鋁層設置於二鈦(titanium)層之間。
- 一種製造堆疊結構之方法,包含:沉積一第一介電層於一第二介電層與一金屬電極上;沉積一高介電常數介電層於該第一介電層上;沉積一氮化矽層在該高介電常數介電層上;以及使該高介電常數介電層與該氮化矽層退火(annealing)。
- 如請求項8所述之方法,其中該第一介電層與該高介電常數介電層係為各自藉由一電漿輔助原子層沉積製程(plasma enhanced atomic layer deposition process)來沉積。
- 如請求項8所述之方法,其中該第一介電層與該高介電常數介電層係為各自藉由一電漿輔助化學氣相沉積製程(plasma enhanced chemical vapor deposition process)來沉積。
- 如請求項8所述之方法,其中該第一介電層與該高介電常數介電層係沉積於一處理腔室中。
- 如請求項11所述之方法,其中該處理腔室係為一電漿輔助原子層沉積腔室。
- 如請求項11所述之方法,其中該處理腔室係為一電漿輔助化學氣相沉積腔室。
- 一種製造堆疊結構之系統,包含:一傳送腔室;一電漿輔助原子層沉積腔室,耦接於該傳送腔室;一熱處理腔室,耦接於該傳送腔室;及一控制器,用以進行數個步驟,該些步驟包含:在該電漿輔助原子層沉積腔室中沉積一第一介電層於一第二介電層與一金屬電極上;在該電漿輔助原子層沉積腔室中沉積一高介電常數介電層於該第一介電層上;在該電漿輔助原子層沉積腔室中沉積一氮化矽層在該高介電常數介電層上;及在該熱處理腔室中使該高介電常數介電層與該氮化矽層退火。
- 如請求項14所述之系統,其中該第一介電層包含二氧化矽、氧化鋁、二氧化鈦或氧化釔。
- 如請求項15所述之系統,其中該第一介電層具有介於約2埃至約100埃之間的一厚度。
- 如請求項15所述之系統,其中該高介電常數介電層包含二氧化鋯或二氧化鉿。
- 如請求項17所述之系統,該高介電常數介電層具有介於約250埃至約900埃之間的一厚度。
- 如請求項14所述之系統,其中該第一介電層包含氮化矽或二氧化矽。
- 一種堆疊結構,包含:一金屬電極;一高介電常數介電層,設置於該金屬電極下方;及一層堆疊,該層堆疊包含:一介電層,其中該高介電常數介電層設置於該介電層上且介於該介電層與該金屬電極之間;以及一含矽層,設置於該高介電常數介電層上且介於該高介電常數介電層與該金屬電極之間。
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