TWI810380B - 包括橋接晶粒的系統級封裝件 - Google Patents

包括橋接晶粒的系統級封裝件 Download PDF

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TWI810380B
TWI810380B TW108136399A TW108136399A TWI810380B TW I810380 B TWI810380 B TW I810380B TW 108136399 A TW108136399 A TW 108136399A TW 108136399 A TW108136399 A TW 108136399A TW I810380 B TWI810380 B TW I810380B
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die
rdl
semiconductor wafer
semiconductor
pad
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TW108136399A
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TW202036832A (zh
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金鍾薰
成基俊
金基範
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南韓商愛思開海力士有限公司
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Abstract

一種系統級封裝件包括再分配線(RDL)結構、第一半導體晶片、第二半導體晶片和橋接晶粒。該RDL結構包括第一RDL圖案，第一半導體晶片的第一晶片焊墊電連接至第一RDL圖案。第二半導體晶片層疊在第一半導體晶片上，使得第二半導體晶片突出越過第一半導體晶片的側表面，其中，設置在突出部上的第二晶片焊墊透過橋接晶粒電連接到第一RDL圖案。

Description

包括橋接晶粒的系統級封裝件
本公開涉及半導體封裝技術，更具體地，涉及包括橋接晶粒的系統級封裝件。 相關申請的交叉引用
本申請主張2019年2月22日提交的韓國申請No. 10-2019-0021453的優先權，其整體透過引用併入本文。
近來，大量努力集中在將多個半導體晶片整合到單個半導體封裝件中。即，已嘗試增加封裝件整合密度以實現利用多功能操作高速處理大量資料的高性能半導體封裝件。例如，系統級封裝件（SiP）技術可被視為實現高性能半導體封裝件的有吸引力的候選。包括在各個SiP中的多個半導體晶片並排設置。然而，這可導致難以減小SiP的寬度。因此，已提出將多個半導體晶片設置在SiP封裝件中的各種技術以減小SiP的尺寸。
根據實施方式，一種系統級封裝件包括：再分配線（RDL）結構，其包括第一RDL圖案；以及第一半導體晶片，其設置在RDL結構上，使得第一半導體晶片的電連接到第一RDL圖案的第一晶片焊墊面向RDL結構。該系統級封裝件還包括第二半導體晶片，該第二半導體晶片層疊在第一半導體晶片上，使得第二半導體晶片突出越過第一半導體晶片的側表面，其中，設置在第二半導體晶片的突出部上的第二晶片焊墊面向RDL結構。該系統級封裝件還包括設置在RDL結構上以支撐第二半導體晶片的突出部的橋接晶粒，其中，該橋接晶粒包括被第一通孔所穿透的主體，其中，第一通孔將第二晶片焊墊電連接到第一RDL圖案。
根據另一實施方式，一種系統級封裝件包括第一子封裝件以及安裝在第一子封裝件上的第二子封裝件。第一子封裝件包括：再分配線（RDL）結構，其包括第一RDL圖案；以及第一半導體晶片，其設置在RDL結構上，使得第一半導體晶片的電連接到第一RDL圖案的第一晶片焊墊面向RDL結構。第一子封裝件還包括第二半導體晶片，該第二半導體晶片層疊在第一半導體晶片上，使得第二半導體晶片突出越過第一半導體晶片的側表面，其中，設置在第二半導體晶片的突出部上的第二晶片焊墊面向RDL結構。第一子封裝件還包括橋接晶粒，該橋接晶粒設置在RDL結構上以支撐第二半導體晶片的突出部，其中，橋接晶粒包括被第一通孔所穿透的主體，其中，第一通孔將第二晶片焊墊電連接到第一RDL圖案。第一子封裝件另外包括模製層，該模製層設置在RDL結構上以覆蓋第一半導體晶片和橋接晶粒並且圍繞第二半導體晶片。第一子封裝件還包括穿透模製層以電連接到RDL結構的模製通孔（TMV），其中，第二子封裝件設置在模製層上並且電連接到TMV。
本文所使用的術語可對應於考慮其在實施方式中的功能而選擇的文字，術語的含義可被解釋為根據實施方式所屬領域的通常知識者而不同。如果詳細定義，則可根據定義來解釋術語。除非另外定義，否則本文所使用的術語（包括技術術語和科學術語）具有實施方式所屬領域的通常知識者通常理解的相同含義。
將理解，儘管本文中可使用術語“第一”、“第二”、“第三”等來描述各種元件，但是這些元件不應受這些術語限制。這些術語僅用於將一個元件與另一元件相區分，而非用於僅限定元件本身或者意指特定順序。
還將理解，當元件或層被稱為在另一元件或層“上”、“上方”、“下麵”、“下方”或“外側”時，該元件或層可與另一元件或層直接接觸，或者可存在中間元件或層。用於描述元件或層之間的關係的其它詞語應該以類似的方式解釋（例如，“在...之間”與“直接在...之間”或者“相鄰”與“直接相鄰”）。
諸如“在...之下”、“在...下面”、“下”、“上面”、“上”、“頂部”、“底部”等的空間相對術語可用於描述元件和/或特徵與另一元件和/或特徵的關係（例如，如圖中所示）。將理解，除了附圖中所描繪的取向之外，空間相對術語旨在涵蓋裝置在使用和/或操作中的不同取向。例如，當附圖中的裝置翻轉時，被描述為在其它元件或特徵下面和/或之下的元件將被取向為在其它元件或特徵上面。裝置可按照其它方式取向（旋轉90度或處於其它取向）並且相應地解釋本文中所使用的空間相對描述符。
系統級封裝件（SiP）可對應於半導體封裝件，並且半導體封裝件可包括諸如半導體晶片或半導體晶粒的電子裝置。半導體晶片或半導體晶粒可透過使用切割製程而將諸如晶圓的半導體基板分離成多片來獲得。半導體晶片可對應於記憶體晶片、邏輯晶片、特殊應用積體電路（ASIC）晶片、應用處理器（AP）、圖形處理單元（GPU）、中央處理單元（CPU）或系統晶片（SoC）。記憶體晶片可包括整合在半導體基板上的動態隨機存取記憶體（DRAM）電路、靜態隨機存取記憶體（SRAM）電路、NAND型快閃記憶體電路、NOR型快閃記憶體電路、磁隨機存取記憶體（MRAM）電路、電阻式隨機存取記憶體（ReRAM）電路、鐵電隨機存取記憶體（FeRAM）電路或相變隨機存取記憶體（PcRAM）電路。邏輯晶片可包括整合在半導體基板上的邏輯電路。半導體封裝件可用在諸如行動電話的通信系統、與生物技術或保健關聯的電子系統或可穿戴式電子系統中。半導體封裝件可適用於物聯網（IoT）。
通篇說明書中，相同的標號表示相同的元件。即使標號未參照一幅圖提及或描述，該標號也可參照另一幅圖提及或描述。另外，即使標號未在一幅圖中示出，其也可參照另一幅圖提及或描述。
圖1是示出根據實施方式的系統級封裝件（SiP）10的橫截面圖。
參照圖1，SiP 10可被配置為包括再分配線（RDL）結構100、第一半導體晶片300、第二半導體晶片400和橋接晶粒500。
第一半導體晶片300可設置在RDL結構100上。第二半導體晶片400可層疊在第一半導體晶片300的與RDL結構100相對的表面上以與第一半導體晶片300交疊。第二半導體晶片400可層疊在第一半導體晶片300上以具有突出部435，突出部435對應於從與第一半導體晶片300的側表面對準的垂直線橫向突出的伸出物（overlang）。橋接晶粒500可設置在RDL結構100上以支撐第二半導體晶片400的突出部435。橋接晶粒500可設置在第二半導體晶片400的突出部435與RDL結構100之間，並且可被設置為在與突出部435相同的方向上與第一半導體晶片300橫向間隔開。
SiP 10還可包括形成在RDL結構100上的模製層700。模製層700可形成為覆蓋第一半導體晶片300和橋接晶粒500。模製層700可延伸以覆蓋第二半導體晶片400。模製層700可形成為圍繞並保護第二半導體晶片400並露出第二半導體晶片400的與第一半導體晶片300相對的第二表面402。在模製層700形成為露出第二半導體晶片400的第二表面402的情況下，來自第二半導體晶片400和第一半導體晶片300的由於SiP 10的操作而生成的熱可透過第二半導體晶片400的第二表面402更容易地消散到外部空間。模製層700可由各種模製材料或囊封材料中的任一種形成。例如，模製層700可由環氧樹脂模製料（EMC）材料形成。
圖2是示出圖1的一部分（包括橋接晶粒500）的放大橫截面圖。
參照圖1和圖2，RDL結構100可包括第一RDL圖案120。第一RDL圖案120可以是具有與第一半導體晶片300的一部分交疊的第一端以及與橋接晶粒500的一部分交疊的第二端的導電圖案。
第一半導體晶片300可包括第一組的晶片焊墊310。第一半導體晶片300可設置在RDL結構100上，使得第一半導體晶片300的第一晶片焊墊312電連接到第一RDL圖案120的第一端。第一晶片焊墊312可以是第一組的晶片焊墊310中的任一個。第一半導體晶片300可按照倒裝晶片形式安裝在RDL結構100上，使得第一半導體晶片300的第一組的晶片焊墊310面向RDL結構100。
第一組的內連接器610可設置在第一半導體晶片300與RDL結構100之間以將第一半導體晶片300電連接到RDL結構100。第一組的內連接器610可以是導電凸塊或焊料凸塊。第五內連接器612可接合到第一RDL圖案120的一部分以將第一晶片焊墊312電連接到第一RDL圖案120。第五內連接器612可以是第一組的內連接器610中的任一個。
第二半導體晶片400可包括設置在第二半導體晶片400的突出部435上的第二組的晶片焊墊410。第二半導體晶片400可按照倒裝晶片形式安裝在第一半導體晶片300上。因此，設置在突出部435上的第二晶片焊墊412可面向RDL結構100。由於第二晶片焊墊412設置在突出部435上，所以第二晶片焊墊412可能不與第一半導體晶片300垂直地交疊以在第一半導體晶片300的外側區域中露出。第二晶片焊墊412可以是第二組的晶片焊墊410中的任一個。
橋接晶粒500可設置在RDL結構100上以與第二半導體晶片400的突出部435交疊。橋接晶粒500可被配置為包括主體510以及穿透主體510的多個通孔520。儘管圖中未示出，絕緣層可另外設置在主體510與各個通孔520之間以將通孔520與主體510電絕緣。第一通孔522可被設置為與第二晶片焊墊412交疊，並且可電連接到第二半導體晶片400的第二晶片焊墊412。第一通孔522可以是通孔520中的任一個。第一通孔522可被設置為與第一RDL圖案120的第二端交疊，並且可電連接到與第一通孔522交疊的第一RDL圖案120。第一通孔522可被設置為在垂直方向上將第二晶片焊墊412電連接到第一RDL圖案120。
橋接晶粒500還可包括多個柱狀凸塊530。第一柱狀凸塊532可設置在主體510上以從主體510的頂表面突出。第一柱狀凸塊532可連接到第一通孔522的頂部。第一柱狀凸塊532可以是柱狀凸塊530中的任一個。
第三組的內連接器630可設置在橋接晶粒500與第二半導體晶片400之間以將橋接晶粒500電連接到第二半導體晶片400。橋接晶粒500可透過第三組的內連接器630接合到第二半導體晶片400，並且可透過第三組的內連接器630電連接到第二半導體晶片400。第二內連接器632可將第二晶片焊墊412電連接到第一柱狀凸塊532。第二內連接器632可以是第三組的內連接器630中的任一個。橋接晶粒500還可包括設置在主體510的底表面上的通孔焊墊540。第一通孔焊墊542可連接到第一通孔522的底部。第一通孔焊墊542可以是通孔焊墊540中的任一個。
第二組的內連接器620可設置在橋接晶粒500與RDL結構100之間以將橋接晶粒500電連接到RDL結構100。橋接晶粒500可透過第二組的內連接器620接合到RDL結構100，並且可透過第二組的內連接器620電連接到RDL結構100。第一內連接器622可接合並且電連接到第一通孔焊墊542。第一內連接器622可以是第二組的內連接器620中的任一個。第一內連接器622可接合到第一RDL圖案120的一部分以將第一通孔焊墊542電連接到第一RDL圖案120。
圖3是示出將圖2所示的第一半導體晶片300和第二半導體晶片400彼此電連接的第一電路徑P1的立體圖。
參照圖2和圖3，橋接晶粒500在結構上支撐第二半導體晶片400的突出部435並且還提供將第二半導體晶片400電連接到第一半導體晶片300的第一電路徑P1的一部分。第一電路徑P1可被配置為包括第二半導體晶片400的第二晶片焊墊412、第二內連接器632、第一柱狀凸塊532、第一通孔522、第一通孔焊墊542、第一內連接器622、第一RDL圖案120、第五內連接器612和第一半導體晶片300的第一晶片焊墊312。
第一半導體晶片300可以是執行資料的邏輯運算的處理器。例如，第一半導體晶片300可包括諸如執行邏輯運算的應用處理器的系統晶片（SoC）。第二半導體晶片400可以是儲存資料的記憶體半導體晶片。記憶體半導體晶片可用作快取記憶體晶片，其暫時儲存並提供在SoC的邏輯運算中使用的資料。第二半導體晶片400可被配置為包括DRAM裝置。
第一半導體晶片300的第一組的晶片焊墊310可均勻地設置在第一半導體晶片300的第一表面301的整個區域上，如圖3所示。第二半導體晶片400的第二組的晶片焊墊410可設置在第二半導體晶片400的突出部435上。第二半導體晶片400的第二組的晶片焊墊410可設置在第二半導體晶片400的相對於第一半導體晶片300外伸（不交疊）的部分（即，突出部435）上。第二半導體晶片400的第二組的晶片焊墊410可設置在第二半導體晶片400的週邊區域430上。設置有第二組的晶片焊墊410的週邊區域430可位於第二半導體晶片400的突出部435的第一表面401上。
第二半導體晶片400可與第一半導體晶片300部分地交疊。第二半導體晶片400的除了突出部435之外的其它區域可與第一半導體晶片300交疊。第二半導體晶片400的所述其它區域可由第一半導體晶片300共用。因此，第二半導體晶片400的第二組的晶片焊墊410可能不設置在第二半導體晶片400的所述其它區域上。
第一晶片焊墊312可透過第一電路徑P1電連接到第二半導體晶片400的第二晶片焊墊412。第一晶片焊墊312可以是第一組的晶片焊墊310中的一個。儘管圖3將第一電路徑P1示出為單個路徑，但SiP 10可包括多個第一電路徑P1。在這種情況下，第一組的晶片焊墊310可分別透過多個第一電路徑P1電連接到第二組的晶片焊墊410。在實施方式中，多個第一電路徑P1中的每一個可被配置為包括第二半導體晶片400的第二組的晶片焊墊410中的一個、第三組的內連接器630中的一個、柱狀凸塊530中的一個、通孔520中的一個、通孔焊墊540中的一個、第二組的內連接器620中的一個、第一RDL圖案120中的一個、第一組的內連接器610中的一個以及第一半導體晶片300的第一組的晶片焊墊310中的一個。由於第二半導體晶片400透過多個第一電路徑P1電連接到第一半導體晶片300，所以可在第一半導體晶片300和第二半導體晶片400之間提供多個輸入/輸出（I/O）路徑。即，由於兩個相鄰的半導體晶片透過與I/O路徑對應的多個短信號路徑彼此電連接，所以與透過單個路徑相比，可透過多個路徑在兩個相鄰的半導體晶片之間同時發送相對更多的資料。因此，在給定速度之下使用多個平行路徑，則從第一半導體晶片300向第二半導體晶片400可發送更大量的資料，或者反之亦然。如果第一半導體晶片300是邏輯晶片（例如，處理器晶片）並且第二半導體晶片400是記憶體晶片，則第一半導體晶片300可與充當高性能快取記憶體的第二半導體晶片400一起操作。因此，可改進包括第一半導體晶片300和第二半導體晶片400的SiP 10的操作速度和性能。
再參照圖2，第二半導體晶片400還可包括第三晶片焊墊411，第三晶片焊墊411設置在突出部435上以與第二晶片焊墊412間隔開。橋接晶粒500還可包括第二柱狀凸塊531，第二柱狀凸塊531被設置為基本上與第三晶片焊墊411交疊。橋接晶粒500還可包括第二通孔521，第二通孔521電連接到第二柱狀凸塊531並且被設置為與第一通孔522間隔開。橋接晶粒500還可包括電連接到第二通孔521的第二通孔焊墊541。
RDL結構100還可包括第二RDL圖案110，第二RDL圖案110被設置為與第一RDL圖案120間隔開。第二RDL圖案110可被設置為具有與第二通孔焊墊541交疊的部分。第二RDL圖案110可透過第五RDL圖案140電連接到第一外連接器210。第一外連接器210可以是連接到RDL結構100的多個外連接器200中的一個。外連接器200可充當將SiP 10電連接到外部裝置的連接端子或連接引腳。外連接器200可以是諸如焊球的連接構件。
RDL結構100還可包括設置在第五RDL圖案140與第二RDL圖案110之間的第一介電層191。第一RDL圖案120和第二RDL圖案110可設置在第一介電層191的頂表面上，並且第五RDL圖案140可設置在第一介電層191的底表面上。第五RDL圖案140可基本上穿透第一介電層191以連接到第二RDL圖案110。RDL結構100還可包括第二介電層193，第二介電層193設置在第一介電層191的與外連接器200相對的頂表面上以將第二RDL圖案110與第一RDL圖案120電隔離。RDL結構100還可包括第三介電層195，第三介電層195設置在第一介電層191的與第一半導體晶片300相對的底表面上以將第五RDL圖案140與SiP 10的外部空間電隔離。第一外連接器210可基本上穿透第三介電層195以連接到第五RDL圖案140。
第六內連接器621可接合到第二RDL圖案110以將第二通孔焊墊541電連接到第二RDL圖案110。第六內連接器621可以是將橋接晶粒500電連接到RDL結構100的第二組的內連接器620中的任一個。第七內連接器631可將第二柱狀凸塊531電連接到第三晶片焊墊411。第七內連接器631可以是將橋接晶粒500電連接到第二半導體晶片400的第三組的內連接器630中的任一個。
參照圖2和圖3，第二電路徑P2可被設置為包括第一外連接器210、第五RDL圖案140、第二RDL圖案110、第六內連接器621、第二通孔焊墊541、第二通孔521、第二柱狀凸塊531、第七內連接器631和第三晶片焊墊411。第二電路徑P2可以是將第二半導體晶片400電連接到第一外連接器210的路徑。與第一電路徑P1不同，第二電路徑P2可能不電連接到第一半導體晶片300。第一電路徑P1可將第一半導體晶片300和第二半導體晶片400彼此電連接，使得第一半導體晶片300和第二半導體晶片400彼此通信。相比之下，第二電路徑P2可用作將電源電壓或接地電壓供應給第二半導體晶片400的電路徑。
再參照圖2，RDL結構100還可包括第三RDL圖案130，第三RDL圖案130被設置為與第一RDL圖案120和第二RDL圖案110間隔開。第三RDL圖案130可被設置為與第一半導體晶片300交疊。第三RDL圖案130可透過第六RDL圖案150電連接到第二外連接器230。第一半導體晶片300還可包括第四晶片焊墊313，第四晶片焊墊313被設置為與第一晶片焊墊312間隔開。第三內連接器613可被設置為將第四晶片焊墊313電連接到第三RDL圖案130。第三內連接器613可以是將第一半導體晶片300電連接到RDL結構100的第一組的內連接器610中的任一個。
第三電路徑P3可被設置為包括第四晶片焊墊313、第三內連接器613、第三RDL圖案130、第六RDL圖案150和第二外連接器230。第三電路徑P3可以是將第一半導體晶片300電連接到第二外連接器230的電路徑。第一半導體晶片300可透過第三電路徑P3與外部裝置通信，或者可透過第三電路徑P3從外部裝置接收電力。
圖4是示出圖1的一部分（包括橋接晶粒500）的放大橫截面圖。圖5是示出圖4所示的橋接晶粒500的柱狀凸塊530的平面圖。
參照圖1和圖4，橋接晶粒500的主體510可對應於諸如矽基板的半導體基板。當橋接晶粒500的主體510由矽材料製成時，可使用應用於矽晶圓的光學微影製程來形成通孔520。橋接晶粒500的通孔520可對應於具有直徑D1的矽通孔（TSV）。直徑D1可小於穿透模製層的模製通孔（TMV）的直徑。因此，在具有有限尺寸的主體510中可增加形成的通孔520的數量。
如圖3所示，第二組的晶片焊墊410可密集地設置在第二半導體晶片400的突出部435上。橋接晶粒500的電連接到第二組的晶片焊墊410的柱狀凸塊530可包括至少兩個凸塊，如圖5所示。在這種情況下，橋接晶粒500的通孔520可對準以與第二組的晶片焊墊410交疊，使得柱狀凸塊530與第二半導體晶片400的第二組的晶片焊墊410交疊。由於使用TSV製程形成橋接晶粒500的通孔520，所以例如與TMV的直徑相比，通孔520可形成為具有值相對小的直徑D1。因此，可使橋接晶粒500的分別與多個I/O端子、電源端子和接地端子對應的通孔520的數量最大化。即，即使第二組的晶片焊墊410密集地設置，也可形成橋接晶粒500的通孔520，使得通孔520被設置為具有與第二組的晶片焊墊410相同的間距大小。因此，即使第二組的晶片焊墊410密集地設置，也可將第二組的晶片焊墊410垂直地連接到橋接晶粒500的相應通孔520，而不在第二半導體晶片400上形成任何再分配線。
如果通孔520的直徑D1減小，則通孔520的垂直長度也可減小。當通孔520形成為穿透具有厚度T3的主體510時，由於由通孔520填充的通孔洞的縱橫比的限制，在減小通孔520的直徑D1方面可存在限制。為了減小橋接晶粒500的通孔520的直徑D1，可能有必要減小主體510的厚度T3以滿足形成通孔520的通孔洞的縱橫比的限制。為了增加主體510中形成的通孔520的數量，可能有必要將主體510的厚度T3減小為小於第一半導體晶片300的厚度T1。在這種情況下，可減小橋接晶粒500的通孔520的直徑D1。
為了橋接晶粒500在結構上支撐第二半導體晶片400，橋接晶粒500的總厚度T2被設定為等於第一半導體晶片300的厚度T1可能是有效的。例如，小於第一半導體晶片300的厚度T1的主體510的厚度T3可由橋接晶粒500的柱狀凸塊530的厚度T4和橋接晶粒500的通孔焊墊540的厚度T5補償。即，透過適當地調節橋接晶粒500的柱狀凸塊530的厚度T4，橋接晶粒500的總厚度T2可被調節為等於第一半導體晶片300的厚度T1。橋接晶粒500的總厚度T2可包括橋接晶粒500的柱狀凸塊530的厚度T4、橋接晶粒500的通孔焊墊540的厚度T5和主體510的厚度T3。
柱狀凸塊530可分別直接接合到第三組的內連接器630。第一柱狀凸塊532的直徑D2可大於通孔520的直徑D1。因此，用作第三組的內連接器630的焊料凸塊可分別直接接合到橋接晶粒500的柱狀凸塊530。為了橋接晶粒500的通孔焊墊540直接接合到第二組的內連接器620，通孔焊墊540的直徑D3可大於通孔520的直徑D1。
圖6是示出圖1所示的第一半導體晶片300和第二半導體晶片400之間的連接部分的放大橫截面圖。
參照圖1和圖6，第二半導體晶片400可與第一半導體晶片300部分地交疊，並且第二半導體晶片400的突出部435可由橋接晶粒500支撐。第二半導體晶片400的突出部435透過第三組的內連接器630接合到橋接晶粒500，並且虛擬凸塊690可用於支撐第二半導體晶片400的與突出部435相對的邊緣436。由於虛擬凸塊690支撐第二半導體晶片400的邊緣436，所以可防止第二半導體晶片400傾斜。由於當第二半導體晶片400的突出部435接合到橋接晶粒500時虛擬凸塊690設置在第一半導體晶片300與第二半導體晶片400之間，所以第二半導體晶片400可維持水平高度。
虛擬凸塊690可以是焊料凸塊。虛擬凸塊690可附接到第二半導體晶片400的第一表面401。虛擬接合焊墊691可形成在第二半導體晶片400的第一表面401上。在這種情況下，虛擬凸塊690可接合到虛擬接合焊墊691。虛擬接合焊墊691可形成在設置在第二半導體晶片400的第一表面401上的鈍化層425上。虛擬接合焊墊691可使用金屬濺射製程形成在鈍化層425上。鈍化層425可形成為覆蓋第二半導體晶片400的主體420（由矽材料製成）並將其電絕緣。因此，虛擬凸塊690可與第二半導體晶片400的內部電路電絕緣。虛擬凸塊690可與第一半導體晶片300的與RDL結構100相對的第二表面302接觸。
圖7是示出根據另一實施方式的SiP 11的橫截面圖。
參照圖7，SiP 11可被配置為包括RDL結構100、第一半導體晶片300、第二半導體晶片400、橋接晶粒500和模製層700。第二半導體晶片400可與第一半導體晶片300部分地交疊，並且第二半導體晶片400的突出部435可由橋接晶粒500支撐。黏合層690L可設置在第一半導體晶片300與第二半導體晶片400之間。黏合層690L可支撐第二半導體晶片400。當第二半導體晶片400的突出部435接合到橋接晶粒500並由橋接晶粒500支撐時，黏合層690L可防止第二半導體晶片400傾斜。黏合層690L可幫助第二半導體晶片400維持水平高度。
黏合層690L可附接到第二半導體晶片400的第一表面401和第一半導體晶片300的第二表面302。黏合層690L可將第二半導體晶片400接合到第一半導體晶片300。
圖8是示出根據另一實施方式的SiP 12的橫截面圖。圖9是示出圖8的一部分（包括模製通孔（TMV）2800）的橫截面圖。
參照圖8，SiP 12可被實現為具有層疊封裝件（PoP）形狀。SiP 12可被配置為包括第一子封裝件SP1以及安裝在第一子封裝件SP1上的第二子封裝件SP2。第一子封裝件SP1可被配置為包括RDL結構2100、第一半導體晶片2300、第二半導體晶片2400、橋接晶粒2500、模製層2700和TMV 2800。
RDL結構2100可被配置為包括第一RDL圖案2120、第二RDL圖案2110、第三RDL圖案2130、第四RDL圖案2170、第五RDL圖案2140、第六RDL圖案2150、第七RDL圖案2180和第八RDL圖案2190。RDL結構2100還可包括第一介電層2191、第二介電層2193和第三介電層2195。第一RDL圖案2120、第二RDL圖案2110、第三RDL圖案2130、第四RDL圖案2170和第七RDL圖案2180可設置在第一介電層2191的頂表面上。第二介電層2193可設置在第一介電層2191的頂表面上以將第一RDL圖案2120、第二RDL圖案2110、第三RDL圖案2130、第四RDL圖案2170和第七RDL圖案2180彼此電絕緣。第五RDL圖案2140、第六RDL圖案2150和第八RDL圖案2190可設置在第一介電層2191的與第二介電層2193相對的底表面上。第三介電層2195可形成在第一介電層2191的底表面上以將第五RDL圖案2140、第六RDL圖案2150和第八RDL圖案2190彼此電絕緣。
RDL結構2100可對應於電連接到第一半導體晶片2300和第二半導體晶片2400的互連結構。在另一實施方式中，印刷電路板（PCB）可被使用作為互連結構。
外連接器2200可附接到RDL結構2100。外連接器2200可包括彼此間隔開並且彼此電絕緣的第一外連接器2210、第二外連接器2230和第三外連接器2270。
第一半導體晶片2300可包括系統晶片（SoC），並且第二半導體晶片2400可包括第一記憶體半導體晶片。第二子封裝件SP2可包括第二記憶體半導體晶片，第二記憶體半導體晶片連接到與第一半導體晶片2300對應的SoC。第二記憶體半導體晶片可包括NAND型快閃記憶體裝置或DRAM裝置。第一記憶體半導體晶片可充當臨時記憶體裝置或緩衝記憶體裝置，並且第二記憶體半導體晶片可充當主記憶體裝置。
第一半導體晶片2300可包括多個晶片焊墊2310。第一半導體晶片2300的晶片焊墊2310可包括第一晶片焊墊2312、第四晶片焊墊2313和第五晶片焊墊2317。
第一半導體晶片2300可透過多個內連接器2610電連接到RDL結構2100。內連接器2610可包括第三內連接器2613、第四內連接器2617和第五內連接器2612。
第二半導體晶片2400可包括突出部2435，突出部2435對應於從與第一半導體晶片2300的側表面對準的垂直線橫向突出的伸出物。第二半導體晶片2400包括設置在突出部2435上的多個晶片焊墊2410。
橋接晶粒2500可在結構上支撐第二半導體晶片2400的突出部2435。橋接晶粒2500可被配置為包括主體2510、通孔2520、柱狀凸塊2530和通孔焊墊2540。
橋接晶粒2500可透過內連接器2620電連接到RDL結構2100。橋接晶粒2500可透過其它內連接器2630電連接到第二半導體晶片2400。
多個虛擬凸塊2690可設置在第一半導體晶片300與第二半導體晶片400之間以維持第二半導體晶片400的水平高度。
TMV 2800可基本上穿透模製層2700以電連接到RDL結構2100。第二子封裝件SP2可設置在模製層2700上並且可透過互連器2250電連接到TMV 2800。互連器2250可以是諸如焊球的連接構件。儘管圖中未示出，第二子封裝件SP2可被設置為包括：半導體晶粒，其包括積體電路；內部互連線，其用於半導體晶粒中的元件之間的電連接；以及模製層，其保護半導體晶粒。
參照圖9，與TMV 2800中的任一個對應的第一TMV 2817可連接到第四RDL圖案2170的一端。第四RDL圖案2170的另一端可透過第四內連接器2617電連接到第一半導體晶片2300的第五晶片焊墊2317。第一TMV 2817可透過與互連器2250中的任一個對應的第一互連器2257電連接到第二子封裝件SP2。第一互連器2257、第一TMV 2817、第四RDL圖案2170、第四內連接器2617和第五晶片焊墊2317可構成第四電路徑P4。第四電路徑P4可以是將第二子封裝件SP2連接到第一半導體晶片2300的信號路徑。
與TMV 2800中的任一個對應的第二TMV 2818可將第七RDL圖案2180電連接到與互連器2250中的任一個對應的第二互連器2258。第七RDL圖案2180可連接到第八RDL圖案2190，並且第八RDL圖案2190可連接到第三外連接器2270。因此，第二互連器2258、第二TMV 2818、第七RDL圖案2180、第八RDL圖案2190和第三外連接器2270可構成第五電路徑P5。第五電路徑P5可以是將電源電壓或接地電壓供應給第二子封裝件SP2的電路徑。
如上所述，根據實施方式，第二半導體晶片400（或2400）可層疊在第一半導體晶片300（或2300）上以減小SiP 10、11或12的寬度或大小。根據SiP 10、11或12，由於第二半導體晶片400（或2400）使用橋接晶粒500（或2500）電連接到第一半導體晶片300（或2300），所以可在第一半導體晶片300（或2300）上層疊第二半導體晶片400（或2400）。
對半導體晶片施加熱的製程可使半導體晶片（具體地，記憶體晶片）的特性劣化。例如，當熱施加到DRAM裝置時，DRAM裝置的記憶體單元的資料保持時間減少，從而減小DRAM裝置的刷新迴圈時間。另外，如果熱施加到NAND型快閃記憶體裝置，則NAND型快閃記憶體裝置的記憶體單元的資料保持時間也可能被減少。
根據本教導的實施方式的SiP 10、11和12可被實現為包括內連接器，內連接器附接到RDL結構100以用於半導體晶片之間以及外部裝置與半導體晶片之間的互連。因此，可省略或減少使用於形成再分配線的聚合物層固化的熱製程（或退火製程）。結果，SiP 10、11和12的性能可改進。例如，如果在形成RDL結構100之後第一半導體晶片300和第二半導體晶片400層疊在RDL結構100上以形成SiP 10、11或12，則當執行熱製程（或退火製程）使得用於形成RDL圖案的聚合物層固化時，可防止熱施加到第一半導體晶片300和第二半導體晶片400。
圖10是示出包括採用根據實施方式的系統級封裝件（SiP）中的至少一個的記憶卡7800的電子系統的方塊圖。記憶卡7800包括諸如非揮發性記憶體裝置的記憶體7810以及記憶體控制器7820。記憶體7810和記憶體控制器7820可儲存資料以及讀出所儲存的資料。記憶體7810和記憶體控制器7820中的至少一個可包括根據實施方式的SiP中的至少一個。
記憶體7810可包括應用了本公開的實施方式的技術的非揮發性記憶體裝置。記憶體控制器7820可控制記憶體7810，使得回應於來自主機7830的讀/寫請求，讀出所儲存的資料或者儲存資料。
圖11是示出包括根據實施方式的SiP中的至少一個的電子系統8710的方塊圖。電子系統8710可包括控制器8711、輸入/輸出單元8712和記憶體8713。控制器8711、輸入/輸出單元8712和記憶體8713可透過提供資料移動的路徑的匯流排8715彼此連接。
在實施方式中，控制器8711可包括一個或更多個微處理器、數位訊號處理器、微控制器和/或能夠執行與這些元件相同的功能的邏輯裝置。控制器8711或記憶體8713可包括根據本公開的實施方式的SiP中的至少一個。輸入/輸出單元8712可包括選自鍵區、鍵盤、顯示裝置、觸控式螢幕等中的至少一個。記憶體8713是用於儲存資料的裝置。記憶體8713可儲存要由控制器8711執行的資料和/或命令等。
記憶體8713可包括諸如DRAM的揮發性記憶體裝置和/或諸如快閃記憶體的非揮發性記憶體裝置。例如，快閃記憶體可被安裝到諸如移動終端或桌上型電腦的資訊處理系統。快閃記憶體可構成固態硬碟（SSD）。在這種情況下，電子系統8710可在快閃記憶體系統中穩定地儲存大量資料。
電子系統8710還可包括被配置為向通信網路發送資料以及從通信網路接收資料的介面8714。介面8714可為有線或無線型。例如，介面8714可包括天線或者有線或無線收發器。
電子系統8710可被實現為移動系統、個人電腦、工業電腦或者執行各種功能的邏輯系統。例如，移動系統可以是個人數位助理（PDA）、可擕式電腦、平板電腦、行動電話、智慧型電話、無線電話、膝上型電腦、記憶卡、數位音樂系統和資訊發送/接收系統中的任一個。
如果電子系統8710是能夠執行無線通訊的設備，則電子系統8710可用在使用CDMA（碼分多址）、GSM（全球移動通信系統）、NADC（北美數位蜂窩）、E-TDMA（增強型分時多重存取）、WCDAM（頻寬多重分碼存取）、CDMA2000、LTE（長期演進）或Wibro（無線寬頻互聯網）的技術的通信系統中。
出於例示性目的公開了本公開的實施方式。所屬技術領域中具有通常知識者將理解，在不脫離本公開和所附請求項的範圍和精神的情況下，可進行各種修改、添加和替換。
10:系統級封裝件（SiP） 11:系統級封裝件（SiP） 12:系統級封裝件（SiP） 100:再分配線（RDL）結構 110:第二RDL圖案 120:第一RDL圖案 130:第三RDL圖案 140:第五RDL圖案 150:第六RDL圖案 191:第一介電層 193:第二介電層 195:第三介電層 200:外連接器 210:第一外連接器 230:第二外連接器 300:第一半導體晶片 301:第一表面 302:第二表面 310:第一組的晶片焊墊 312:第一晶片焊墊 313:第四晶片焊墊 400:第二半導體晶片 401:第一表面 402:第二表面 410:第二組的晶片焊墊 411:第三晶片焊墊 412:第二晶片焊墊 420:主體 425:鈍化層 430:週邊區域 435:突出部 436:邊緣 500:橋接晶粒 510:主體 520:通孔 521:第二通孔 522:第一通孔 530:柱狀凸塊 531:第二柱狀凸塊 532:第一柱狀凸塊 540:通孔焊墊 541:第二通孔焊墊 542:第一通孔焊墊 610:第一組的內連接器 612:第五內連接器 613:第三內連接器 620:第二組的內連接器 621:第六內連接器 622:第一內連接器 630:第三組的內連接器 631:第七內連接器 632:第二內連接器 690:虛擬凸塊 690L:黏合層 691:虛擬接合焊墊 700:模製層 2100:RDL結構 2110:第二RDL圖案 2120:第一RDL圖案 2130:第三RDL圖案 2140:第五RDL圖案 2150:第六RDL圖案 2170:第四RDL圖案 2180:第七RDL圖案 2190:第八RDL圖案 2191:第一介電層 2193:第二介電層 2195:第三介電層 2200:外連接器 2210:第一外連接器 2230:第二外連接器 2250:互連器 2257:第一互連器 2258:第二互連器 2270:三外連接器 2300:第一半導體晶片 2310:晶片焊墊 2312:第一晶片焊墊 2313:第四晶片焊墊 2317:第五晶片焊墊 2400:第二半導體晶片 2410:晶片焊墊 2435:突出部 2500:橋接晶粒 2510:主體 2520:通孔 2530:柱狀凸塊 2540:通孔焊墊 2610:內連接器 2612:第五內連接器 2613:第三內連接器 2617:第四內連接器 2620:內連接 2630:內連接器 2700:模製層 2800:模製通孔(TMV) 2817:第一TMV 2818:第二TMV 7800:記憶卡 7810:記憶體 7820:記憶體控制器 7830:主機 8710:電子系統 8711:控制器 8712:輸入/輸出單元 8713:記憶體 8714:介面 8715:匯流排 P1:第一電路徑 P2:第二電路徑 SP1:第一子封裝件 SP2:第二子封裝件
圖1是示出根據實施方式的系統級封裝件（SiP）的橫截面圖。
圖2是示出圖1的一部分（包括橋接晶粒）的放大橫截面圖。
圖3是示出將圖2所示的半導體晶片彼此連接的電路徑的立體圖。
圖4是聚焦於圖1的橋接晶粒的放大橫截面圖。
圖5是示出圖4的橋接晶粒中所包括的柱狀凸塊陣列的平面圖。
圖6是示出圖1所示的半導體晶片之間的連接部分的放大橫截面圖。
圖7是示出根據另一實施方式的SiP的橫截面圖。
圖8是示出根據另一實施方式的SiP的橫截面圖。
圖9是示出圖8的一部分（包括模製通孔）的橫截面圖。
圖10是示出採用包括根據實施方式的至少一個SiP的記憶卡的電子系統的方塊圖。
圖11是示出包括根據實施方式的至少一個SiP的另一電子系統的方塊圖。
10:系統級封裝件(SiP)
100:再分配線(RDL)結構
110:第二RDL圖案
120:第一RDL圖案
130:第三RDL圖案
140:第五RDL圖案
150:第六RDL圖案
191:第一介電層
193:第二介電層
195:第三介電層
200:外連接器
210:第一外連接器
230:第二外連接器
300:第一半導體晶片
301:第一表面
302:第二表面
310:第一組的晶片焊墊
312:第一晶片焊墊
313:第四晶片焊墊
400:第二半導體晶片
401:第一表面
402:第二表面
410:第二組的晶片焊墊
411:第三晶片焊墊
412:第二晶片焊墊
435:突出部
500:橋接晶粒
510:主體
520:通孔
521:第二通孔
522:第一通孔
530:柱狀凸塊
531:第二柱狀凸塊
532:第一柱狀凸塊
610:第一組的內連接器
612:第五內連接器
613:第三內連接器
620:第二組的內連接器
621:第六內連接器
622:第一內連接器
630:第三組的內連接器
631:第七內連接器
632:第二內連接器
690:虛擬凸塊
700:模製層

Claims (19)

  1. 一種系統級封裝件，該系統級封裝件包括：再分配線(RDL)結構，該RDL結構包括第一RDL圖案；第一半導體晶片，該第一半導體晶片設置在所述RDL結構上，使得所述第一半導體晶片的電連接到所述第一RDL圖案的第一晶片焊墊面向所述RDL結構；第二半導體晶片，該第二半導體晶片層疊在所述第一半導體晶片上，使得所述第二半導體晶片突出越過所述第一半導體晶片的側表面，其中，設置在所述第二半導體晶片的突出部上的第二晶片焊墊面向所述RDL結構；橋接晶粒，該橋接晶粒設置在所述RDL結構上以支撐所述第二半導體晶片的所述突出部，其中，所述橋接晶粒包括被第一通孔所穿透的主體，其中，所述第一通孔將所述第二晶片焊墊電連接到所述第一RDL圖案；以及虛擬凸塊，該虛擬凸塊設置在所述第一半導體晶片與所述第二半導體晶片之間以支撐所述第二半導體晶片，其中，所述第二半導體晶片還包括虛擬接合焊墊，該虛擬接合焊墊設置在所述第二半導體晶片的面向所述第一半導體晶片的表面上；並且其中，所述虛擬凸塊接合到所述虛擬接合焊墊。
  2. 根據請求項1所述的系統級封裝件，其中，所述第二半導體晶片包括被配置為儲存資料的記憶體半導體晶片；並且所述第一半導體晶片是系統晶片(SoC)，該SoC被配置為透過第一電路徑接收儲存在所述記憶體半導體晶片中的資料，該第一電路徑包括所述第二晶片焊墊、所述第一通孔、所述第一RDL圖案和所述第一晶片焊墊。
  3. 根據請求項1所述的系統級封裝件，其中，所述橋接晶粒還包括：第一柱狀凸塊，該第一柱狀凸塊設置在所述主體的頂表面上並且電連接到所述第一通孔，其中，所述第一柱狀凸塊的直徑大於所述第一通孔的直徑；以及 通孔焊墊，該通孔焊墊設置在所述主體的與所述第一柱狀凸塊背對的底表面上並且電連接到所述第一通孔，其中，所述通孔焊墊的直徑大於所述第一通孔的直徑。
  4. 根據請求項3所述的系統級封裝件，該系統級封裝件還包括：第一內連接器，該第一內連接器將所述通孔焊墊電連接到所述第一RDL圖案；以及第二內連接器，該第二內連接器將所述第一柱狀凸塊電連接到所述第二晶片焊墊。
  5. 根據請求項4所述的系統級封裝件，其中該虛擬凸塊與所述第二內連接器間隔開。
  6. 根據請求項4所述的系統級封裝件，該系統級封裝件還包括設置在所述第一半導體晶片與所述第二半導體晶片之間並且與所述第二內連接器間隔開的黏合層，其中，該黏合層被配置以支撐所述第二半導體晶片。
  7. 根據請求項3所述的系統級封裝件，其中，所述第二半導體晶片還包括第三晶片焊墊，該第三晶片焊墊設置在所述突出部上並且與所述第二晶片焊墊間隔開；所述RDL結構還包括第二RDL圖案，該第二RDL圖案與所述第一RDL圖案間隔開並且電連接到第一外連接器；並且所述橋接晶粒還包括第二通孔和第二柱狀凸塊，所述第二通孔與所述第一通孔間隔開並且透過所述第二RDL圖案將所述第三晶片焊墊電連接到所述第一外連接器，所述第二柱狀凸塊電連接到所述第二通孔。
  8. 根據請求項7所述的系統級封裝件，其中，所述第一外連接器、所述第二RDL圖案、所述第二通孔、所述第二柱狀凸塊和所述第三晶片焊墊構成將電力供應給所述第二半導體晶片或者將所述第二半導體晶片接地的第二電路 徑。
  9. 根據請求項3所述的系統級封裝件，其中，所述橋接晶粒的所述主體的厚度小於所述第一半導體晶片的厚度；並且所述第一柱狀凸塊、所述第一通孔和所述通孔焊墊的組合厚度基本上等於所述第一半導體晶片的厚度。
  10. 根據請求項1所述的系統級封裝件，其中，所述橋接晶粒的所述主體包括矽材料；並且所述橋接晶粒的所述第一通孔包括矽通孔(TSV)。
  11. 根據請求項1所述的系統級封裝件，其中，所述RDL結構還包括第三RDL圖案，該第三RDL圖案與所述第一RDL圖案間隔開並且電連接到第二外連接器；並且所述第一半導體晶片還包括第四晶片焊墊，該第四晶片焊墊透過第三內連接器電連接到所述第三RDL圖案。
  12. 根據請求項1所述的系統級封裝件，該系統級封裝件還包括模製層，該模製層設置在所述RDL結構上以覆蓋所述第一半導體晶片和所述橋接晶粒並且圍繞所述第二半導體晶片。
  13. 一種系統級封裝件，該系統級封裝件包括：第一子封裝件；以及安裝在所述第一子封裝件上的第二子封裝件，其中，所述第一子封裝件包括：再分配線(RDL)結構，該RDL結構包括第一RDL圖案；第一半導體晶片，該第一半導體晶片設置在所述RDL結構上，使得所述第一半導體晶片的電連接到所述第一RDL圖案的第一晶片焊墊面向所述RDL結構； 第二半導體晶片，該第二半導體晶片層疊在所述第一半導體晶片上，使得所述第二半導體晶片突出越過所述第一半導體晶片的側表面，其中，設置在所述第二半導體晶片的突出部上的第二晶片焊墊面向所述RDL結構；橋接晶粒，該橋接晶粒設置在所述RDL結構上以支撐所述第二半導體晶片的所述突出部，其中，所述橋接晶粒包括被第一通孔所穿透的主體，其中，所述第一通孔將所述第二晶片焊墊電連接到所述第一RDL圖案；模製層，該模製層設置在所述RDL結構上以覆蓋所述第一半導體晶片和所述橋接晶粒並且圍繞所述第二半導體晶片；模製通孔(TMV)，該TMV穿透所述模製層以電連接到所述RDL結構；以及虛擬凸塊，該虛擬凸塊設置在所述第一半導體晶片與所述第二半導體晶片之間以支撐所述第二半導體晶片，其中，所述第二半導體晶片還包括虛擬接合焊墊，該虛擬接合焊墊設置在所述第二半導體晶片的面向所述第一半導體晶片的表面上；其中，所述虛擬凸塊接合到所述虛擬接合焊墊；並且其中，所述第二子封裝件設置在所述模製層上並且電連接到所述TMV。
  14. 根據請求項13所述的系統級封裝件，其中，所述第二半導體晶片包括被配置為儲存資料的第一記憶體半導體晶片；所述第一半導體晶片是系統晶片(SoC)，該SoC被配置為透過第一電路徑接收儲存在所述第一記憶體半導體晶片中的資料，該第一電路徑包括所述第二晶片焊墊、所述第一通孔、所述第一RDL圖案和所述第一晶片焊墊；並且所述第二子封裝件包括電連接到所述SoC的第二記憶體半導體晶片。
  15. 根據請求項13所述的系統級封裝件，其中，所述RDL結構還包括第四RDL圖案，該第四RDL圖案與所述第一RDL圖案 間隔開；所述第一半導體晶片還包括第五晶片焊墊，該第五晶片焊墊透過第四內連接器電連接到所述第四RDL圖案；並且所述TMV電連接到所述第四RDL圖案。
  16. 根據請求項13所述的系統級封裝件，該系統級封裝件還包括將所述TMV電連接到所述第二子封裝件的互連器。
  17. 根據請求項13所述的系統級封裝件，其中，所述橋接晶粒還包括：第一柱狀凸塊，該第一柱狀凸塊設置在所述主體的頂表面上並且電連接到所述第一通孔，其中，所述第一柱狀凸塊的直徑大於所述第一通孔的直徑；以及通孔焊墊，該通孔焊墊設置在所述主體的與所述第一柱狀凸塊背對的底表面上並且電連接到所述第一通孔，其中，所述通孔焊墊的直徑大於所述第一通孔的直徑。
  18. 根據請求項17所述的系統級封裝件，該系統級封裝件還包括：第一內連接器，該第一內連接器將所述通孔焊墊電連接到所述第一RDL圖案；以及第二內連接器，該第二內連接器將所述第一柱狀凸塊電連接到所述第二晶片焊墊。
  19. 根據請求項18所述的系統級封裝件，其中，該虛擬凸塊與所述第二內連接器間隔開。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11742277B2 (en) * 2018-08-14 2023-08-29 Rambus Inc. Packaged integrated device having memory buffer integrated circuit asymmetrically positioned on substrate
KR102643424B1 (ko) 2019-12-13 2024-03-06 삼성전자주식회사 반도체 패키지
CN113066780B (zh) * 2021-03-23 2023-07-25 浙江集迈科微电子有限公司 转接板堆叠模组、多层模组和堆叠工艺
KR20220150075A (ko) * 2021-05-03 2022-11-10 삼성전자주식회사 반도체 패키지 및 그 제조 방법
TW202245212A (zh) * 2021-05-11 2022-11-16 群創光電股份有限公司 電子裝置
US20230019333A1 (en) * 2021-07-14 2023-01-19 Qualcomm Incorporated Package comprising stacked integrated devices with overhang
KR20230016485A (ko) * 2021-07-26 2023-02-02 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US11908838B2 (en) * 2021-08-26 2024-02-20 Taiwan Semiconductor Manufacturing Company Limited Three-dimensional device structure including embedded integrated passive device and methods of making the same
US20240113004A1 (en) * 2022-09-30 2024-04-04 Advanced Micro Devices, Inc. Connecting a chiplet to an interposer die and to a package interface using a spacer interconnect coupled to a portion of the chiplet

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200713552A (en) * 2005-09-13 2007-04-01 Taiwan Semiconductor Mfg Co Ltd Electronic package
TW201205699A (en) * 2010-07-30 2012-02-01 Taiwan Semiconductor Mfg Embedded wafer-level bonding approaches
US20130277831A1 (en) * 2012-04-19 2013-10-24 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
US20140264836A1 (en) * 2013-03-15 2014-09-18 Qualcomm Incorporated System-in-package with interposer pitch adapter
TW201533884A (zh) * 2014-02-25 2015-09-01 Powertech Technology Inc 內藏去耦合電容之半導體封裝構造
TW201620051A (zh) * 2014-11-26 2016-06-01 力成科技股份有限公司 防止中介導體橋接之半導體封裝件立體堆疊方法
TW201705311A (zh) * 2015-02-12 2017-02-01 碁鼎科技秦皇島有限公司 晶片封裝基板、晶片封裝結構及其製作方法
TW201712826A (zh) * 2015-07-10 2017-04-01 創研騰智權信託有限公司 通用表面黏著半導體封裝
TW201721822A (zh) * 2015-12-08 2017-06-16 愛思開海力士有限公司 包括側遮蔽部的半導體封裝
TW201802972A (zh) * 2016-07-13 2018-01-16 力成科技股份有限公司 避免中介銲球橋接之封裝堆疊方法與構造

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100876889B1 (ko) * 2007-06-26 2009-01-07 주식회사 하이닉스반도체 반도체 패키지 및 이를 이용한 멀티칩 반도체 패키지
US9236319B2 (en) * 2008-02-29 2016-01-12 Stats Chippac Ltd. Stacked integrated circuit package system
US9230898B2 (en) 2009-08-17 2016-01-05 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
KR102190382B1 (ko) * 2012-12-20 2020-12-11 삼성전자주식회사 반도체 패키지
TW201535652A (zh) * 2014-03-11 2015-09-16 United Microelectronics Corp 具有被動元件的晶片堆疊中介結構及其製造方法
US9941207B2 (en) * 2014-10-24 2018-04-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of fabricating 3D package with short cycle time and high yield
WO2016099463A1 (en) * 2014-12-16 2016-06-23 Intel Corporation Electronic assembly that includes stacked electronic devices
US9373605B1 (en) 2015-07-16 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. DIE packages and methods of manufacture thereof
US9786632B2 (en) * 2015-07-30 2017-10-10 Mediatek Inc. Semiconductor package structure and method for forming the same
JP2017092094A (ja) * 2015-11-04 2017-05-25 富士通株式会社 電子装置、電子装置の製造方法及び電子機器
US9773757B2 (en) 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
EP3288076B1 (en) * 2016-08-25 2021-06-23 IMEC vzw A semiconductor die package and method of producing the package

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200713552A (en) * 2005-09-13 2007-04-01 Taiwan Semiconductor Mfg Co Ltd Electronic package
TW201205699A (en) * 2010-07-30 2012-02-01 Taiwan Semiconductor Mfg Embedded wafer-level bonding approaches
US20130277831A1 (en) * 2012-04-19 2013-10-24 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
US20140264836A1 (en) * 2013-03-15 2014-09-18 Qualcomm Incorporated System-in-package with interposer pitch adapter
TW201533884A (zh) * 2014-02-25 2015-09-01 Powertech Technology Inc 內藏去耦合電容之半導體封裝構造
TW201620051A (zh) * 2014-11-26 2016-06-01 力成科技股份有限公司 防止中介導體橋接之半導體封裝件立體堆疊方法
TW201705311A (zh) * 2015-02-12 2017-02-01 碁鼎科技秦皇島有限公司 晶片封裝基板、晶片封裝結構及其製作方法
TW201712826A (zh) * 2015-07-10 2017-04-01 創研騰智權信託有限公司 通用表面黏著半導體封裝
TW201721822A (zh) * 2015-12-08 2017-06-16 愛思開海力士有限公司 包括側遮蔽部的半導體封裝
TW201802972A (zh) * 2016-07-13 2018-01-16 力成科技股份有限公司 避免中介銲球橋接之封裝堆疊方法與構造

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