TWI810261B - 半導體封裝的製造方法 - Google Patents

半導體封裝的製造方法 Download PDF

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Publication number
TWI810261B
TWI810261B TW108109212A TW108109212A TWI810261B TW I810261 B TWI810261 B TW I810261B TW 108109212 A TW108109212 A TW 108109212A TW 108109212 A TW108109212 A TW 108109212A TW I810261 B TWI810261 B TW I810261B
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Taiwan
Prior art keywords
semiconductor package
semiconductor
sealing substrate
sealant
manufacturing
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TW108109212A
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English (en)
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TW201941377A (zh
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金永奭
張秉得
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日商迪思科股份有限公司
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Publication of TW201941377A publication Critical patent/TW201941377A/zh
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Abstract

本發明的課題是使以密封劑密封的半導體封裝的放熱性提升。 其解決手段為一種半導體封裝的製造方法，作成以樹脂層來密封接合於配線基板上的半導體晶片之密封基板，而以保持膠帶來保持，以複合砥石來切入樹脂層而於樹脂層上面形成凹凸形狀來使表面積增加，沿著分割預定線來將密封基板個片化成各個的半導體封裝。

Description

半導體封裝的製造方法
本發明是有關以密封劑來密封半導體晶片的半導體封裝的製造方法。
製造以密封劑來密封半導體晶片者作為半導體封裝(例如參照專利文獻1)。專利文獻1記載的半導體封裝的製造方法是在配線基板搭載複數的半導體晶片，以模製樹脂等的密封劑來一併密封複數的半導體晶片而形成密封基板。然後，密封基板會沿著分割預定線來切割，藉此按各自封裝半導體晶片的每一封裝來分割而製造半導體封裝。 [先前技術文獻] [專利文獻]
[專利文獻1]日本特開2001-23936號公報
(發明所欲解決的課題)
可是，就半導體封裝而言，除了衝撃或異物等來自外部環境的半導體晶片的保護以外，也被要求將在半導體晶片產生的熱排放至外部的放熱性。然而，單以密封劑來密封半導體晶片的構成是在放熱性有限度，被要求半導體封裝的更進一步的放熱性的改善。
本發明是有鑑於如此的點而研發者，以提供一種可使以密封劑密封的半導體封裝的放熱性提升之半導體封裝的製造方法為目的之一。 (用以解決課題的手段)
本發明之一形態的半導體封裝的製造方法，係作成藉由密封劑來密封的半導體封裝之半導體封裝的製造方法，其特徵為具備： 保持步驟，其係在藉由交叉的分割預定線來區劃的配線基材表面上接合複數的半導體晶片，以保持治具或保持膠帶來保持對該配線基材的表面側供給該密封劑而被密封的密封基板的該配線基材背面側； 凹凸形成步驟，其係在實施該保持步驟之後，以具有凹凸形狀的加工面的複合砥石來以不到達該半導體晶片的深度切入該密封劑，在該密封劑表面形成凹凸而使表面積增加；及 個片化步驟，其係沿著該分割預定線來將該密封基板個片化成各個的半導體封裝。
若根據此構成，則藉由以複合砥石的凹凸形狀的加工面來以不到達半導體晶片的深度切入密封劑，可不傷到半導體晶片使密封劑的表面積增加。因此，在半導體晶片產生的熱會傳至密封劑表面，以密封劑表面的凹凸面來有效率地放散熱，而提升半導體封裝的放熱性。
本發明的其他形態的半導體封裝的製造方法，係作成藉由密封劑來密封的半導體封裝之半導體封裝的製造方法，其特徵為具備： 保持步驟，其係在藉由交叉的分割預定線來區劃的配線基材表面上接合複數的半導體晶片，以保持治具或保持膠帶來保持對該配線基材的表面側供給該密封劑而被密封的密封基板的該配線基材背面側；及 個片化步驟，其係在實施該保持步驟之後，以複合砥石來沿著該分割預定線而切入至該保持膠帶途中或該保持治具內，將該密封基板個片化成各個的半導體封裝， 該複合砥石，係對應於該分割預定線來至少形成2個的突起，該2個的突起間係具有凹凸形狀的加工面， 在該個片化步驟中，將該突起沿著該分割預定線而切入，分割成各個的半導體封裝，且在不到達被個片化的半導體封裝的該半導體晶片的深度，在該密封劑表面形成凹凸而使表面積增加。
若根據此構成，則由於在複合砥石形成有2個的突起，因此密封基板會以2個的突起來沿著分割預定線而切入，被個片化成各自的半導體封裝。並且，藉由以複合砥石的凹凸形狀的加工面來以不到達半導體晶片的深度切入密封劑，可不傷到被個片化的半導體晶片，在密封劑的表面形成凹凸來使表面積增加。因此，在半導體晶片產生的熱會傳至密封劑表面，以密封劑表面的凹凸面來有效率地放散熱。如此，密封基板被分割的同時在密封劑表面形成凹凸，因此可使作業工數減少，且半導體封裝的放熱性會提升。
本發明的其他形態的半導體封裝的製造方法，係作成藉由密封劑來密封的半導體封裝之半導體封裝的製造方法，其特徵為具備： 晶片接合步驟，其係在藉由交叉的分割預定線來區劃的配線基材表面上接合複數的半導體晶片； 密封基板作成步驟，其係以和該半導體晶片的表面之間形成有空間的方式，將在頂面形成有凹凸形狀的金屬模配置於配線基材表面側，在該金屬模與該半導體晶片的表面之間的該空間內供給密封劑而密封，作成在該密封劑表面形成有凹凸形狀的密封基板；及 個片化步驟，其係在實施該密封基板作成步驟之後，沿著該分割預定線來分割該配線基材，而沿著該分割預定線來個片化成各個的半導體封裝。
若根據此構成，則藉由使用在頂面形成有凹凸形狀的金屬模來以密封劑密封半導體晶片，形成密封劑表面成為凹凸面而表面積增加的密封基板。因此，在半導體晶片產生的熱會傳至密封劑表面，以密封劑表面的凹凸面來有效率地放散熱。又，由於不實施加工，密封劑表面的表面積會增加，因此在密封劑表面形成凹凸時不增加操作員的負擔。藉由如此使用金屬模來形成凹凸，可不增加作業工數，使半導體封裝的放熱性提升。
在本發明之一形態及其他形態的半導體封裝的製造方法中，在實施該個片化步驟之後，亦可包含在個片化後的半導體封裝的側面形成ID標記的ID標記形成步驟。 [發明的效果]
若根據本發明，則藉由使密封劑表面形成凹凸來增加表面積，在半導體晶片產生的熱會傳至密封劑表面，以密封劑表面的凹凸面來有效率地放散熱而提升半導體封裝的放熱性。
以下，參照附圖來說明有關本實施形態的半導體封裝的製造方法。圖1是本實施形態的半導體封裝的剖面模式圖。圖2是通常的半導體封裝的放熱性的說明圖。另外，以下的實施形態終究是其一例者，亦可在各步驟間具備其他的步驟，亦可適當更換步驟的順序。
如圖1所示般，半導體封裝10是以樹脂層(密封劑)13來封裝半導體晶片12的半導體裝置，藉由樹脂層13來從外部環境保護半導體晶片12。半導體封裝10是被安裝於配線基板(配線基材)11的表面的半導體晶片12會以樹脂層13來密封，在配線基板11的背面配設有凸塊14。在配線基板11是形成有包含被連接至半導體晶片12的電極或接地線17的各種配線。在半導體封裝10的側面是附有封裝識別用的ID標記(未圖示)。
就一般半導體封裝而言，有時因振動、衝撃、水分、塵埃、磁氣等而在半導體晶片12引起動作不良，必須從如此的外部環境適當地保護半導體晶片12。並且，一旦半導體晶片12動作則發熱，若晶片本身的溫度上昇，則不僅不正常動作，且恐有破損之虞，須將半導體晶片12維持於動作保障溫度以下。如此，在半導體封裝10是除了衝撃或異物等來自外部環境的半導體晶片12的保護以外，也被要求將在半導體晶片12產生的熱排放至外部的放熱性。
可是，如圖2的比較例所示般，通常的半導體封裝110是配線基板111上的半導體晶片112會藉由樹脂層113來密封，半導體封裝110的封裝上面114會被平坦地形成。一旦在半導體封裝110內的半導體晶片112發熱，則熱會傳至樹脂層113而從平坦的封裝上面114放散。然而，若半導體晶片112的發熱量變大，則難以從封裝上面114使熱充分地放散而適當地除去半導體晶片112的熱。因此，須更進一步改善半導體封裝110的放熱性。
此情況，雖亦可思考藉由薄化半導體晶片112上的樹脂層113來改善放熱性的構成，但半導體封裝110的機械性強度會降低，恐有無法自物理性的損傷等保護半導體晶片112之虞。於是，如圖1所示般，本實施形態是將半導體封裝10的封裝上面25形成凹凸狀使表面積增加。半導體晶片12的發熱傳至封裝上面25，以封裝上面25的凹凸來有效率地放散熱而提升半導體封裝10的放熱性。可一面抑制機械性強度的降低，一面使放熱性提升。
以下，參照圖3及圖4來說明有關第1實施形態的半導體封裝的製造方法。圖3及圖4是第1實施形態的半導體封裝的製造方法的說明圖。另外，圖3A是表示晶片接合步驟，圖3B是表示密封基板作成步驟，圖3C是表示保持步驟的各一例的圖。圖4A表示凹凸形成步驟，圖4B是表示個片化步驟，圖4C是表示ID標記形成步驟的各一例的圖。
如圖3A所示般，首先實施晶片接合步驟。在晶片接合步驟中，配線基板11的表面會以交叉的分割預定線來區劃成格子狀，在被區劃的各裝置領域，在配線基板11的表面接合有複數的半導體晶片12。此情況，在半導體晶片12的上面的電極連接接線(wire)19的一端，在配線基板11的表面的電極18連接接線19的另一端。並且，在配線基板11內形成有接地線17等的各種配線，在配線基板11的背面配設有將來自外部的訊號等傳至半導體晶片12的凸塊14。
如圖3B所示般，在實施晶片接合步驟之後實施密封基板作成步驟。在密封基板作成步驟中，在接合有複數的半導體晶片12的配線基板11的上面側供給密封劑34，各半導體晶片12會以密封劑34來一併密封而作成密封基板15(參照圖3C)。此情況，安裝有半導體晶片12的配線基板11的背面會被保持於保持治具(未圖示)，以覆蓋配線基板11的上面(表面)之方式配置金屬模31。在金屬模31的頂面是開口有注入口32，在注入口32的上方定位有用以供給密封劑34的供給噴嘴33。
然後，從供給噴嘴33經由注入口32來供給密封劑34至配線基板11的上面而密封半導體晶片12。在此狀態下，藉由密封劑34被加熱或乾燥而硬化，作成在配線基板11的上面形成有樹脂層13(參照圖3C)的密封基板15。另外，密封劑34是可使用具有硬化性者，可從環氧樹脂、矽樹脂、聚氨酯樹脂、不飽和聚酯樹脂、丙烯酸聚氨酯樹脂或聚醯亞胺樹脂等選擇。又，密封劑34是不限於液狀，亦可使用薄片狀、粉末狀的樹脂。另外，當密封基板15被預先準備時，是亦可省略晶片接合步驟、密封基板作成步驟。
如圖3C所示般，在實施密封基板作成步驟之後實施保持步驟。在保持步驟中，以堵塞環狀框(未圖示)的中央之方式貼附有保持膠帶36，密封基板15的配線基板背面側會被保持於此保持膠帶36。此情況，密封基板15的凸塊14會進入至保持膠帶36的黏著層，密封基板15會經由保持膠帶36來良好地被環狀框支撐。另外，保持步驟是亦可以貼片機等的專用裝置來機械性地實施，或亦可以操作員的人工作業來實施。又，環狀框是亦可被形成上面視環狀，或亦可被形成上面視矩形框狀。
如圖4A所示般，在實施保持步驟之後實施凹凸形成步驟。在凹凸形成步驟中，使用具有凹凸形狀的加工面42的大致圓筒狀的複合砥石41。複合砥石41的外周面是形成側面視在軸方向交替重複山形狀及谷形狀的凹凸形狀，在凹凸形狀的外周面附著有鑽石等的砥粒而形成加工面42。加工面42的山形狀的高度與谷形狀的深度的差量是比從晶片上面21到樹脂層上面(密封劑表面)22的高度更小，被形成為即使切入至加工面42的谷形狀，山形狀也不會到達半導體晶片12。
一旦密封基板15的配線基板11側經由保持膠帶36來保持於吸盤(未圖示)，則在密封基板15的外側，複合砥石41會被降至不到達半導體晶片12的深度。相對於複合砥石41，密封基板15會被加工進給於水平方向，藉此複合砥石41的加工面42的山形狀及谷形狀會被轉印至樹脂層上面22。藉此，在樹脂層上面22形成由山形狀及谷形狀所成的凹凸形狀，樹脂層上面22的表面積會增加。又，由於複合砥石41不會碰到半導體晶片12，因此在凹凸形成時也不會有半導體晶片12受傷的情形。
藉由重複此複合砥石41的切入動作，在樹脂層上面22的全域交替形成複數列的山形狀及谷形狀。以使吸盤旋轉90度，橫穿過山形狀及谷形狀的方式，藉複合砥石41重複同樣的加工動作。藉此，在密封基板15的樹脂層上面22形成四角錐形狀的多數的凹凸，接觸於外氣的樹脂層13的表面積會增加，放熱性提升。另外，複合砥石41的切入量是被調整成在分割後的半導體封裝10(參照圖4B)可取得充分的放熱性，且此半導體封裝10的機械性強度會被充分地確保的深度。
如圖4B所示般，在實施凹凸形成步驟之後實施個片化步驟。在個片化步驟中，使用以結合劑來將鑽石砥粒等凝固成圓板狀的直線刀刃44。密封基板15的配線基板11側會經由保持膠帶36來保持於吸盤(未圖示)，直線刀刃44會被對位於密封基板15的分割預定線。然後，在密封基板15的外側，直線刀刃44會被降至保持膠帶36的厚度方向途中的深度，相對於直線刀刃44，密封基板15會被加工進給於水平方向。
藉此，以直線刀刃44來從樹脂層13側切入至保持膠帶36的途中而密封基板15被全切。一旦密封基板15沿著一條的分割預定線而被全切，則直線刀刃44會對於旁邊的分割預定線對位而全切密封基板15。藉由此切斷動作對於密封基板15重複進行，密封基板15會沿著分割預定線來個片化成各個的半導體封裝10。如此，製造一種在樹脂層上面22形成凹凸形狀，使放熱性提升的半導體封裝10。
如圖4C所示般，在實施個片化步驟之後實施ID標記形成步驟。在ID標記形成步驟中，在個片化後的半導體封裝10的封裝側面26形成ID標記。此情況，在將封裝側面26朝向上方的狀態下，半導體封裝10會被定位於加工頭46的下方，藉由雷射打印在封裝側面26形成ID標記。藉此，即使在半導體封裝10的封裝上面25形成有凹凸形狀，也可在各個的半導體封裝10形成ID標記。
如以上般，若根據本實施形態的半導體封裝10的製造方法，則藉由以複合砥石41的凹凸形狀的加工面42來以不到達半導體晶片12的深度切入樹脂層13，可不傷到半導體晶片12使樹脂層上面22的表面積增加。因此，在半導體晶片12產生的熱會傳至樹脂層上面22，以樹脂層上面22的凹凸面來有效率地放散熱，而提升半導體封裝10的放熱性。
參照圖5來說明有關第2實施形態的半導體封裝的製造方法。第2實施形態是在個片化步驟，邊在密封基板形成凹凸形狀，邊將密封基板個片化的點，與第1實施形態不同。因此，有關個片化步驟以外的各步驟是省略說明。圖5是第2實施形態的半導體封裝的製造方法的說明圖。
如圖5所示般，在實施晶片接合步驟、密封基板作成步驟、保持步驟之後實施個片化步驟。在個片化步驟中，使用具有凹凸形狀的加工面54及個片化用的一對的突起53之複合砥石51。複合砥石51的基台52是被形成圓筒狀，一對的突起53會從基台52的外周面突出成圓環狀。一對的突起53之間是形成側面視在軸方向交替重複山形狀及谷形狀的凹凸形狀，加上一對的突起53，在一對的突起53之間的凹凸形狀也附著有鑽石等的砥粒而形成加工面54。加工面54的高度與谷形狀的深度的差量是被形成比從半導體晶片12的晶片上面21到樹脂層上面(密封劑表面)22的高度更小。
一旦密封基板15的配線基板11側經由保持膠帶36來保持於吸盤(未圖示)，則在密封基板15的外側，複合砥石51的一對的突起53會分別被對位至分割預定線。亦即，一對的突起53的間隔是對應於分割預定線的間隔。並且，在密封基板15的外側，可以一對的突起53來切入至保持膠帶36的途中，凹凸形狀的加工面54可切入樹脂層上面22且複合砥石51會被降至不到達半導體晶片12的深度。然後，相對於複合砥石51，密封基板15會被加工進給於水平方向，藉此密封基板15會沿著分割預定線來加工。
密封基板15會藉由複合砥石51來切入而被分割，且複合砥石51的凹凸形狀會被轉印至所被分割的密封基板15的樹脂層上面22。藉由使吸盤旋轉90度，以複合砥石51來實施同樣的加工動作，密封基板15會被分割成各個的半導體封裝10，且在被個片化的半導體封裝10的樹脂層上面22形成有四角錐形狀的凹凸形狀。樹脂層上面22的表面積會藉由凹凸形狀而增加，放熱性會提升。又，由於複合砥石51不會碰到半導體晶片12，因此在凹凸形成時也不會有半導體晶片12受傷的情形。在個片化步驟後，在ID標記形成步驟，在個片化後的封裝側面26形成ID標記(參照圖4C)。
如以上般，本實施形態的半導體封裝10的製造方法是在複合砥石51形成有2個的突起53，因此密封基板15會以此2個的突起53沿著分割預定線來切入而個片化成各個的半導體封裝10。藉由以複合砥石51的凹凸形狀的加工面54來以不到達半導體晶片12的深度切入樹脂層13，可不傷及半導體晶片12，在樹脂層上面22形成凹凸而表面積增加。因此，在半導體晶片12產生的熱會傳至樹脂層上面22，以樹脂層上面22的凹凸面來有效率地放散熱。如此，密封基板15被分割的同時在樹脂層上面22形成凹凸，因此可使作業工數減少，且半導體封裝10的放熱性會提升。
參照圖6來說明有關第3實施形態的半導體封裝的製造方法。第3實施形態是在密封基板作成步驟，以金屬模在密封基板的上面形成凹凸形狀的點，與第1實施形態不同。因此，有關密封基板作成步驟以外的各步驟是省略說明。圖6是第3實施形態的半導體封裝的製造方法的說明圖。
如圖6A所示般，在實施晶片接合步驟之後實施密封基板作成步驟。在密封基板作成步驟中，密封劑34會被供給至接合有複數的半導體晶片12的配線基板11的上面側，各半導體晶片12會以密封劑34來一併密封而作成密封基板15(參照圖6B)。此情況，安裝有半導體晶片12的配線基板11的背面會被保持於保持治具(未圖示)，以和半導體晶片12的晶片上面21持有空間來覆蓋配線基板11的方式載置金屬模61。亦即，金屬模61是以在半導體晶片12的晶片上面21與金屬模61之間形成有空間的方式配置於配線基材11的表面側。在金屬模61的頂面62是藉由四角錐形狀的多數的凹部來形成凹凸形狀。
並且，在金屬模61的頂面62是開口有注入口63，在注入口63的上方是定位有密封劑34的供給噴嘴33。由於注入口63是被定位於分割預定線的上方，因此在密封劑34的硬化後不會有注入口63的樹脂柱65(參照圖6B)被形成於半導體晶片12的上方的情形。又，注入口63是比在後段的個片化步驟被使用的直線刀刃44(參照圖6B)的刀刃寬度更小徑。然後，從供給噴嘴33經由注入口63來供給密封劑34至金屬模61的頂面62與半導體晶片12的上面之間的空間內而密封複數的半導體晶片12。
如圖6B所示般，一旦複數的半導體晶片12以密封劑34密封，則密封劑34會藉由加熱或乾燥而硬化。藉由從配線基板11卸下金屬模61，作成在配線基板11的上面形成樹脂層13(參照圖3C)的密封基板15。在樹脂層上面22是被轉印頂面62(參照圖6A)的凹凸形狀，而在樹脂層上面22形成四角錐形狀的凹凸形狀，樹脂層上面22的表面積會增加而放熱性提升。在分割預定線上雖形成有樹脂柱65，但在後段的個片化步驟藉由直線刀刃44來分割密封基板15時，樹脂柱65會被除去。
另外，密封劑34可使用具有硬化性者，可由環氧樹脂、矽、聚氨酯樹脂、不飽和聚酯樹脂、丙烯酸聚氨酯樹脂或聚醯亞胺樹脂等來選擇。並且，密封劑34是不限於液狀，亦可使用薄片狀、粉末狀的樹脂。在密封基板作成步驟後，在保持步驟，密封基板15的配線基板背面側會被保持於保持膠帶36，在個片化步驟，密封基板15會被個片化成各個的半導體封裝10。然後，在ID標記形成步驟，在個片化後的封裝側面26形成ID標記。
如以上般，若根據本實施形態的半導體封裝10的製造方法，則藉由使用在頂面62形成有凹凸形狀的金屬模61來以密封劑34密封半導體晶片12，形成樹脂層上面22會成為凹凸面而表面積增加的密封基板15。因此，在半導體晶片12產生的熱會傳至樹脂層上面22，以樹脂層上面22的凹凸面來有效率地放散熱。由於不實施加工，樹脂層上面22的表面積會增加，因此在樹脂層13形成凹凸時不增加操作員的負擔。藉由如此使用金屬模61來形成凹凸，可不增加作業工數，使半導體封裝10的放熱性提升。
另外，上述的第1-第3實施形態的半導體封裝的製造方法是在需要防止所謂的EMI(Electro-Magnetic Interference)的半導體封裝的製造方法也可適用。在第1-第3實施形態，藉由在個片化步驟前實施V溝形成步驟，在個片化步驟後實施屏蔽層形成步驟，可在半導體封裝的外面形成EMI屏蔽來防止電磁雜訊的洩漏。
以下，參照圖7來說明有關附屏蔽層的半導體封裝的製造方法。圖7是第4實施形態的半導體封裝的製造方法的說明圖。在此，說明有關在第1實施形態的半導體封裝的製造方法追加V溝形成步驟、屏蔽層形成步驟的一例。因此，有關V溝形成步驟、個片化步驟、屏蔽層形成步驟以外的各步驟是省略說明。另外，圖7A是表示V溝形成步驟，圖7B是表示個片化步驟，圖7C及圖7D是表示屏蔽層形成步驟的各一例的圖。
如圖7A所示般，在實施晶片接合步驟、密封基板作成步驟、保持步驟、凹凸形成步驟之後實施V溝形成步驟。在V溝形成步驟中，使用以結合劑來將鑽石砥粒等凝固成圓板狀，且將前端(前端的剖面)形成V字狀的V刀刃66。密封基板15的配線基板11側會經由保持膠帶36來保持於吸盤(未圖示)，V刀刃66會被對位於密封基板15的分割預定線。在密封基板15的外側，V刀刃66會被降至密封基板15的厚度方向途中的深度，相對於V刀刃66，密封基板15會被加工進給於水平方向。藉此，樹脂層上面22會沿著分割預定線來被半切而形成V溝68。
另外，在本實施形態中，V刀刃66的前端會被形成尖的V字形狀，但不限於此構成。V刀刃66的前端是只要為對於密封基板15可形成V溝68的形狀即可。例如，如圖15所示般，V刀刃99的前端亦可為形成平坦的V字形狀。因此，所謂切削刀刃的前端為V字形狀是不限於尖至切削刀刃的前端的完全的V字形狀，包含切削刀刃的前端為平坦的大致V字形狀的形狀。又，V刀刃的前端的V字面是不須直線性地傾斜，亦可稍微到圓弧。
如圖7B所示般，在實施V溝形成步驟之後實施個片化步驟。在個片化步驟中，密封基板15的配線基板11側會經由保持膠帶36來保持於吸盤(未圖示)，直線刀刃67會被對位於密封基板15的V溝68。在密封基板15的外側，直線刀刃67會被降至保持膠帶36的厚度方向途中的深度，相對於直線刀刃67，密封基板15會被加工進給於水平方向。藉此，密封基板15會沿著分割預定線來全切，而被個片化成各個的半導體封裝10。
如圖7C所示般，在實施個片化步驟之後實施屏蔽層形成步驟。在屏蔽層形成步驟中，在複數的半導體封裝10的封裝外面，以導電性材料來形成屏蔽層69。此情況，各半導體封裝10會經由保持膠帶36來搬入至電漿裝置(未圖示)內，在預定的形成條件下，對於各半導體封裝10，從上方藉由濺射等的電漿處理來成膜以導電性材料所成的屏蔽層16。藉此，在各半導體封裝10的封裝上面25及封裝側面26以所望的厚度來形成屏蔽層69。
此時，如圖7D所示般，封裝側面26的傾斜面27會從封裝上面25朝向下方而擴展至外側，傾斜面27會對於屏蔽層69的形成方向(鉛直方向)傾斜地交叉。因此。在半導體封裝10形成屏蔽層69時，不僅封裝上面25，連在封裝側面26的傾斜面27也以發揮充分的屏蔽效果的厚度來形成屏蔽層69。雖在封裝上面25是形成有凹凸形狀，但由於凹凸形狀會以斜面形成，因此在凹凸形狀的斜面也以適度的厚度來形成屏蔽層69。
又，由於在封裝側面26的鉛直面28或封裝間的溝底29也形成有屏蔽層69，因此在從保持膠帶36拾取半導體封裝10時，有時在半導體封裝10的下部產生屏蔽層69的毛邊。此情況，除了屏蔽層69的成膜條件，還藉由調整封裝間的縱橫比(aspect ratio)，可抑制半導體封裝10的毛邊的發生。封裝間的縱橫比是依據直線刀刃67(參照圖7B)的寬度尺寸及切入量來調整。
封裝間的縱橫比是在將從封裝側面26的傾斜面27的下端到切入至保持膠帶36的溝底29的深度設為Ymm，將封裝側面26的鉛直面28的對向間隔設為Xmm時，以Y/X來表示。封裝側面26的鉛直面28的下側或封裝間的溝底29是容易受縱橫比的影響，隨著封裝間的縱橫比變高而屏蔽層69形成薄。因此，藉由提高縱橫比，在縱橫比不易影響的傾斜面27以適度的厚度形成屏蔽層69，在縱橫比容易影響的鉛直面28的下側或溝底29形成薄的屏蔽層69，而可抑制毛邊的發生。
配線基板11的接地線17是在封裝側面26的傾斜面27的下側露出至外部。在傾斜面27的下側，接地線17會被連接至適度的厚度的屏蔽層69，因此在半導體封裝10產生的電磁雜訊會經由接地線17來放掉至半導體封裝10外。另外，在封裝側面26的鉛直面28的下側雖屏蔽層69會變薄，但電磁雜訊會藉由配線基板11的多數的配線(未圖示)來去掉。因此，往半導體封裝10的周圍的電子零件之電磁雜訊的洩漏會全體被防止。
配線基板11的接地線17是只要被連接至屏蔽層69即可，亦可在封裝側面26的鉛直面28被連接至屏蔽層69。屏蔽層69是以銅、鈦、鎳、金等之中一個以上的導電性材料所成的厚度數μm以上的金屬層，亦可藉由濺射法、離子鍍(ion plating)法、電漿CVD(chemical Vapor Deposition)法等的電漿處理來形成。如此，製造一種封裝上面25及封裝側面26會以屏蔽層69所覆蓋的半導體封裝10。
另外，在本實施形態中，使用以對於屏蔽層形成步驟的電漿處理具有耐性的材料所形成者作為保持膠帶36。所謂對於電漿處理的耐性是表示包含耐電漿性、耐熱性、耐真空性的電漿耐性。保持膠帶36的膠帶基材是以150度-170度的耐熱溫度的材料所形成為理想，例如，可由聚對苯二甲酸乙二酯樹脂、聚醯亞胺樹脂來選擇。
接著，說明有關半導體封裝的側面的傾斜角度與屏蔽層的關係。圖8是表示設於試驗體的屏蔽層的厚度的圖。圖9是表示試驗體的側面的傾斜角與屏蔽層的厚度的關係的圖。
如圖8所示般，準備改變了側面72的傾斜角度θ的複數的試驗體70，在180℃，8×10-4 Pa的條件下，藉由離子鍍法來形成屏蔽層。側面72的傾斜角度θ是設為90°，82°，68°，60°，45°的任一個。並且，根據掃描型電子顯微鏡的觀察畫像來測定被形成於上面71的上部屏蔽層73的厚度t1及被形成於側面72的側部屏蔽層74的厚度t2。上部屏蔽層73及側部屏蔽層74的厚度t1，t2是作為次式(1)所示的階梯覆蓋(step coverage)的值算出，且將此值與傾斜角度θ的關係彙整於圖9。 (1) step coverage=(t2/t1)×100
此結果，隨著傾斜角度θ從90°變小，階梯覆蓋(step coverage)的值慢慢地變大，若傾斜角度θ形成45°，則階梯覆蓋的值形成100%。具體而言，設定為傾斜角度θ形成45°時，上部屏蔽層73的厚度t1與側部屏蔽層74的厚度t2為一致，在試驗體70的上面71及側面72被確認均一的厚度的屏蔽層。又，根據發明者的實驗，若階梯覆蓋的值低於50%，則側部屏蔽層74的成膜需要時間，製程成本增大，因此階梯覆蓋的值成為50%以上的範圍為理想。因此，半導體封裝的側面的傾斜角度θ是45°以上且82°以下為理想。
如以上般，若根據本實施形態的半導體封裝10的製造方法，則能以可一面提升半導體封裝10的放熱性，一面在封裝外面發揮充分的屏蔽效果之預定的厚度來形成屏蔽層69。
另外，以第1實施形態的半導體封裝的製造方法，說明有關在半導體封裝形成屏蔽層的一例，但不限於此構成。即使在第2、第3實施形態的半導體封裝的製造方法追加V溝形成步驟、屏蔽層形成步驟，也可在半導體封裝形成屏蔽層。又，亦可藉由使用專用的複合砥石，同時實施凹凸形成步驟、V溝形成步驟、個片化步驟。
具體而言，如圖10所示般，一對的突起83會從複合砥石81的圓筒狀的基台82的外周面突出成圓環狀。一對的突起83的各者是從基端朝向突出方向而寬度變窄，從突出方向的途中到前端是被形成一定寬度。亦即，突起83的側面的基端側是形成傾斜面84，突起83的側面的前端側是形成鉛直面85。在一對的突起83之間是形成有側面視將山形狀及谷形狀交替地重複於軸方向的凹凸形狀。除了複合砥石81的突起83的兩側面及前端面，在一對的突起83之間也附著有鑽石等的砥粒而形成加工面86。
若使用如此的專用的複合砥石81來實施個片化步驟，則密封基板15會藉由複合砥石81來切入而分割，且複合砥石81的凹凸形狀會被轉印至所被分割的密封基板15的樹脂層上面22。因此，密封基板15會被個片化成各個的半導體封裝10，且各半導體封裝10的樹脂層上面22的表面積會增加。由於突起83側面的基端側形成傾斜面84，因此半導體封裝10會以在下面側比上面側變更大的方式在封裝側面26附上傾斜。如此，可一邊在封裝側面26附上傾斜，一邊將密封基板15個片化成各個的半導體封裝10，使各半導體封裝10的放熱性提升。
另外，本實施形態是舉例說明在配線基板安裝1個半導體晶片的半導體封裝，但不限於此構成。亦可製造一種在配線基板安裝複數的半導體晶片之半導體封裝。例如圖11A所示般，亦可製造一種在配線基板93安裝複數(例如3個)的半導體晶片92a-92c，將半導體晶片92a-92c歸納在一起的半導體封裝91。另外，半導體晶片92a-92c是亦可具有同一機能，或亦可具有不同的機能。
又，如圖11B所示般，亦可在配線基板97安裝複數(例如2個)的半導體晶片96a、96b，製造一種個別地屏蔽半導體晶片96a、96b的半導體封裝95。此情況，以晶片單位在密封基板形成溝，以封裝單位分割密封基板。另外，半導體晶片96a、96b是亦可具有同一機能，或亦可具有不同的機能。
又，本實施形態是在V溝形成步驟使用V刀刃作為V溝形成手段的構成，但不限於此構成。例如圖12A所示般，亦可使用通常的直線刀刃101作為V溝形成手段，在密封基板15形成V溝。此情況，對於密封基板15的分割預定線上的鉛直面P，僅預定角度將直線刀刃101傾斜至一方側而切削之後，對於鉛直面P，僅預定角度將直線刀刃101傾斜至另一方側而切削。藉此，密封基板15的上面會藉由直線刀刃101來切成V狀，而沿著分割預定線來形成V溝。
又，如圖12B所示般，亦可使用雷射切除用的加工頭102作為V溝形成手段，在密封基板15形成V溝。此情況，對於密封基板15的分割預定線上的鉛直面P，僅預定角度將加工頭102傾斜於一方側而實施切除加工之後，對於鉛直面P，僅預定角度將加工頭102傾斜至另一方側而實施切除加工。密封基板15的上面會藉由對於密封基板15具有吸收性的雷射光線來切成V字狀，而沿著分割預定線來形成V溝。
又，如圖12C所示般，亦可使用靠模工具機(profiler)103作為V溝形成手段，在密封基板15形成V溝。靠模工具機103是在鋁基台104的大致V字狀的加工面附著由鑽石砥粒所成的砥粒層而構成。靠模工具機103是與V刀刃作比較，不易消耗，可長期持續維持V字形狀。
又，本實施形態是在個片化步驟使用直線刀刃作為分割手段的構成，但不限於此構成。例如圖13所示般，亦可使用雷射切除用的加工頭106作為分割手段來分割密封基板15。又，第2實施形態是使用具有一對的突起的複合砥石作為分割手段的構成，但亦可使用多刀刃，取代此複合砥石。
又，本實施形態是說明有關在樹脂層上面形成四角錐形狀的凹凸形狀的構成，但樹脂層上面的凹凸形狀是只要為表面積增加的形狀即可。例如圖14所示般，半導體封裝108的樹脂層上面109的凹凸形狀亦可被形成角柱狀。另外，在半導體封裝108形成屏蔽層時，角柱狀的凹凸形狀考慮縱橫比來形成為理想。藉由降低相鄰的角柱的間隔與角柱的高度的縱橫比，在角柱的側面也可形成屏蔽層。
又，本實施形態是說明有關製造一種半導體晶片會經由接線來接線接合至配線基板的電極之半導體封裝的構成，但不限於此構成。半導體封裝是亦可半導體晶片被直接連接至配線基板的電極而被覆晶接合。
又，本實施形態是加工設有凸塊作為電極的密封基板的構成，但不限於此構成。密封基板的電極是未特別加以限定，例如，亦可加工設有觸點(land)作為電極的密封基板。
又，本實施形態是在保持步驟，與密封基板的樹脂層相反的面會被貼附於保持膠帶的構成，但不限於此構成。例如，亦可取代在與密封基板的樹脂層相反的面貼附有保持膠帶，而是以保持治具來吸引保持與密封基板的樹脂層相反的面，在被保持於保持治具的狀態下實施後段的步驟。保持治具是只要可保持基板即可，例如，亦可以吸盤(Chuck table)或襯底(substrate)所構成。
又，第1實施形態是在實施凹凸形成步驟之後實施個片化步驟的構成，但不限於此構成。亦可在實施個片化步驟之後實施凹凸形成步驟。
又，第4實施形態是不重貼被貼附於密封基板的保持膠帶來實施各步驟的構成，但不限於此構成。亦可在V溝形成步驟及個片化步驟是使用切削用的保持膠帶，在屏蔽層形成步驟是使用電漿處理用的保持膠帶。
又，第4實施形態是對於密封基板的V溝的形成及密封基板的個片化可以同一的裝置實施，或亦可以個別的裝置實施。
又，半導體封裝是不限於用在行動電話等的攜帶型通訊機器的構成，亦可用在照相機等的其他的電子機器。
又，密封基板是未特別加以限定，只要是可形成屏蔽層的工件即可。例如，亦可使用CSP(Chip Size Package)、WLCSP(Wafer Level Chip Size Package)、SIP(System In Package)、FOWLP(Fan Out Wafer Level Package)用的各種基板。FOWLP基板時，亦可形成在再配線層上安裝半導體晶片的構成。因此，配線基材是不限於PCB基板等的配線基板，包含FOWLP基板的再配線層的概念。
又，雖說明了本實施形態及變形例，但亦可全體或部分地組合上述各實施形態及變形例，作為本發明的其他的實施形態。
又，本發明的實施形態是不限於上述的實施形態及變形例，亦可在不脫離本發明的技術思想的主旨範圍實施各種變更、置換、變形。又，藉由技術的進步或衍生的別的技術，若能以別的方式來實現本發明的技術思想，則亦可使用該方法來實施。因此，申請專利範圍是覆蓋在本發明的技術思想的範圍內所能包含的全部的實施形態。
又，本實施形態是說明有關將本發明適用於半導體封裝的製造方法的構成，但亦可適用於其他的封裝的製造方法。 [產業上的利用可能性]
如以上說明般，本發明是具有可使以密封劑所密封的半導體封裝的放熱性提升的效果，特別是在被使用於攜帶型通訊機器的半導體封裝的製造方法有用。
10、108‧‧‧半導體封裝 11‧‧‧配線基板(配線基材) 12‧‧‧半導體晶片 13‧‧‧樹脂層 15‧‧‧密封基板 22、109‧‧‧樹脂層上面(密封劑表面) 34‧‧‧密封劑 36‧‧‧保持膠帶 41、51、81‧‧‧複合砥石 42、54、86‧‧‧加工面 53、83‧‧‧突起 61‧‧‧金屬模 62‧‧‧頂面
圖1是本實施形態的半導體封裝的剖面模式圖。 圖2是通常的半導體封裝的放熱性的說明圖。 圖3A是表示第1實施形態的晶片接合步驟的一例的圖，圖3B是表示第1實施形態的密封基板作成步驟的一例的圖，圖3C是表示第1實施形態的保持步驟的一例的圖。 圖4A是表示第1實施形態的凹凸形成步驟的一例的圖，圖4B是表示第1實施形態的個片化步驟的一例的圖，圖4C是表示第1實施形態的ID標記形成步驟的一例的圖。 圖5是第2實施形態的半導體封裝的製造方法的說明圖。 圖6A是表示第3實施形態的密封基板作成步驟的一例的圖，圖6B是表示在第3實施形態作成的密封基板的一例的圖。 圖7A是表示第4實施形態的V溝形成步驟的一例的圖，圖7B是表示第4實施形態的個片化步驟的一例的圖，圖7C及圖7D是表示第4實施形態的屏蔽層形成步驟的一例的圖。 圖8是表示設在試驗體的屏蔽層的厚度的圖。 圖9是表示試驗體的側面的傾斜角與屏蔽層的厚度的關係的圖。 圖10是表示個片化步驟的變形例的圖。 圖11A及圖11B是表示半導體封裝的變形例的圖。 圖12A、圖12B及圖12C是表示V溝形成步驟的變形例的圖。 圖13是表示個片化步驟的變形例的圖。 圖14是表示半導體封裝的凹凸形狀的變形例的圖。 圖15是表示V刀刃的變形例的圖。
10‧‧‧半導體封裝
11‧‧‧配線基板(配線基材)
12‧‧‧半導體晶片
13‧‧‧樹脂層
14‧‧‧凸塊
15‧‧‧密封基板
21‧‧‧晶片上面
22‧‧‧樹脂層上面(密封劑表面)
26‧‧‧封裝側面
36‧‧‧保持膠帶
41‧‧‧複合砥石
42‧‧‧加工面
44‧‧‧直線刀刃
46‧‧‧加工頭

Claims (4)

  1. 一種半導體封裝的製造方法，係作成藉由密封劑來密封的半導體封裝之半導體封裝的製造方法，其特徵為具備：保持步驟，其係在藉由交叉的分割預定線來區劃的配線基材表面上接合複數的半導體晶片，以保持治具或保持膠帶來保持對該配線基材的表面側供給該密封劑而被密封的密封基板的該配線基材背面側；凹凸形成步驟，其係在實施該保持步驟之後，以具有凹凸形狀的加工面的複合砥石來以不到達該半導體晶片的深度切入該密封劑，在該密封劑表面形成四角錐形狀的多數的凹凸而使表面積增加；個片化步驟，其係沿著該分割預定線來將該密封基板個片化成各個的半導體封裝；及屏蔽層形成步驟，其係在個片化後的該半導體封裝的外面以導電性材料來形成屏蔽層。
  2. 一種半導體封裝的製造方法，係作成藉由密封劑來密封的半導體封裝之半導體封裝的製造方法，其特徵為具備：保持步驟，其係在藉由交叉的分割預定線來區劃的配線基材表面上接合複數的半導體晶片，以保持治具或保持膠帶來保持對該配線基材的表面側供給該密封劑而被密封 的密封基板；及個片化步驟，其係在實施該保持步驟之後，以複合砥石來沿著該分割預定線而切入至該保持膠帶途中或該保持治具內，將該密封基板個片化成各個的半導體封裝，該複合砥石，係對應於該分割預定線來至少形成2個的突起，該2個的突起間係具有凹凸形狀的加工面，在該個片化步驟中，將該突起沿著該分割預定線而切入，個片化成各個的半導體封裝，且在不到達被個片化的半導體封裝的該半導體晶片的深度，在該密封劑表面形成凹凸而使表面積增加。
  3. 一種半導體封裝的製造方法，係作成藉由密封劑來密封的半導體封裝之半導體封裝的製造方法，其特徵為具備：晶片接合步驟，其係在藉由交叉的分割預定線來區劃的配線基材表面上接合複數的半導體晶片；密封基板作成步驟，其係以和該半導體晶片的表面之間形成有空間的方式，將在頂面形成有凹凸形狀的金屬模配置於配線基材表面側，在該金屬模與該半導體晶片的表面之間的該空間內供給密封劑而密封，作成在該密封劑表面形成有四角錐形狀的多數的凹凸形狀的密封基板；個片化步驟，其係在實施該密封基板作成步驟之後，沿著該分割預定線來分割該配線基材，而沿著該分割預定線來個片化成各個的半導體封裝；及 屏蔽層形成步驟，其係在個片化後的該半導體封裝的外面以導電性材料來形成屏蔽層。
  4. 如申請專利範圍第1~3項中的任一項所記載之半導體封裝的製造方法，其中，包含：在實施該個片化步驟之後，在個片化後的半導體封裝的側面形成ID標記之ID標記形成步驟。
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