TWI804384B - 記憶體裝置之製造方法 - Google Patents

記憶體裝置之製造方法 Download PDF

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TWI804384B
TWI804384B TW111126507A TW111126507A TWI804384B TW I804384 B TWI804384 B TW I804384B TW 111126507 A TW111126507 A TW 111126507A TW 111126507 A TW111126507 A TW 111126507A TW I804384 B TWI804384 B TW I804384B
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semiconductor
memory device
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transistor
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細田達矢
成田容久
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日商鎧俠股份有限公司
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Abstract

實施方式提供一種能使特性穩定提高之半導體裝置、記憶體裝置及電晶體之製造方法。  實施方式之半導體裝置具備基板、基板上之閘極絕緣膜、積層半導體層、及積層半導體層上或積層半導體層之上方之金屬層。積層半導體層具有：第1層，其形成於閘極絕緣層上，並且包含摻雜有磷之多晶半導體；第2層，其形成於第1層上，並且包含摻雜有碳之多晶半導體；及第3層，其形成於第2層上，並且包含摻雜有磷或未摻雜磷之多晶半導體。第3層之磷含量少於第1層之磷含量，或第3層不含磷。

Description

記憶體裝置之製造方法
本發明係關於一種半導體裝置、記憶體裝置及電晶體之製造方法。
為了將半導體記憶體裝置高積體化，已提出一種將記憶單元三維堆疊之三維積層型非揮發性記憶體裝置。三維積層型非揮發性記憶體裝置例如具有記憶單元陣列與成為記憶單元之控制電路之周邊電路積層之構造。周邊電路使用CMOS(Complementary Metal Oxide Semiconductor，互補金氧半導體)等。CMOS中使用之電晶體會因其製造步驟等而發生特性之劣化。
本發明之實施方式提供一種能使特性穩定提高之半導體裝置、記憶體裝置及電晶體之製造方法。
實施方式之半導體裝置具備基板、基板上之閘極絕緣膜、積層半導體層、及積層半導體層上或積層半導體層之上方之金屬層。積層半導體層具有：第1層，其形成於閘極絕緣層上，並且包含摻雜有磷之多晶半導體；第2層，其形成於第1層上，並且包含摻雜有碳之多晶半導體；及第3層，其形成於第2層上，並且包含摻雜有磷或未摻雜磷之多晶半導體。第3層之磷含量少於第1層之磷含量，或第3層不含磷。
以下，參照圖式，對實施方式之半導體裝置及半導體記憶裝置進行說明。再者，於各實施方式中，存在對實質上相同之構成部位標註相同之符號並將相關說明部分省略之情形。圖式係模式化之圖，厚度與平面尺寸之關係、各部分之厚度比例等有時會與實物不同。
(第1實施方式/閘極電極)  圖1係表示實施方式之半導體裝置中之閘極電極之構造之剖視圖。圖1所示之閘極電極100設置於閘極絕緣層120上，該閘極絕緣層120形成於半導體基板110之一面上。作為半導體基板110，例如可使用矽基板。閘極絕緣層120例如可使用氧化矽(SiO)。閘極電極100具備3層構造之積層半導體層130、及金屬層150，且視需要而具備TSI(Through Silicon oxide Insertion，穿通氧化矽***)層140。
於閘極絕緣層120之上形成有3層構造之積層半導體層130。積層半導體層130自靠近閘極絕緣層120之一側起依序具有：第1層131，其包含摻雜有磷(P)之多晶半導體；第2層132，其包含摻雜有碳(C)之多晶半導體；及第3層133，其包含摻雜有P或未摻雜P之多晶半導體。作為積層半導體層130之第1層131、第2層132、第3層133中之多晶半導體，例如可使用多晶矽。
第2層132中所摻雜之C具有捕捉P以抑制彼此擴散之作用。然而，如下述製造步驟(圖2)所示，為了抑制蝕刻殘留會形成氧化膜160，於第2層132之正上方形成氧化膜160後，氧化膜160將變得難以剝離。因此，要於第2層132之上插置第3層133，以促進氧化膜160之剝離。
第3層133具有抑制積層半導體層130與下述金屬層150之界面電阻上升之作用。然而，若第3層133中之P摻雜量過多，則將促進作為下述氧化層之TSI層140加速氧化。因此，第3層133之P摻雜量要設定為較第1層131之P摻雜量少。即，第3層133之磷含量要少於第1層131之磷含量。
於積層半導體層130之第3層133之上，視需要而形成有TSI層140。TSI層140具有防止雜質向下述金屬層150擴散之作用。TSI層140例如可使用氧化矽(SiO)。但根據金屬層150之構成材料，如圖2所示，亦可省略TSI層140，而於積層半導體層130上直接設置金屬層150。
於TSI層140上形成有金屬層150。作為金屬層150，例如可使用自靠近TSI層140之一側起依序積層有矽化鎢(WSi)/氮化鈦(TiN)、或鈦(Ti)/氮化鈦(TiN)/鎢(W)之積層體。
若金屬層150為WSi/TiN，則有雜質向界面之WSi中擴散之虞。因此，傾向於插置TSI層140。但於金屬層150為Ti/TiN/W之情形時，界面並不存在W，因此便無需TSI層140。圖2所示之閘極電極100例如具有Ti/TiN/W之積層膜作為金屬層150，於是便省略了TSI層140之形成。
上述閘極電極100例如係按以下所述而製造。按照圖3說明閘極電極100之製造步驟。如圖3(a)所示，準備半導體基板110。如圖3(b)所示，於半導體基板110之一面上成膜出閘極絕緣層120。
繼而，如圖3(c)所示，於閘極絕緣層120之上依序成膜出第1層131、第2層132、第3層133，從而形成積層半導體層130。如圖3(d)所示，於第3層133之上成膜出氧化膜160。氧化膜160例如可使用氧化矽(SiO)。
其次，成膜出氧化膜160後，如圖3(e)所示，將第3層133之上層部分133a連同氧化膜160一併去除。作為去除方法，可使用機械蝕刻(CMP)或化學蝕刻。化學蝕刻例如可使用CDE(Chemical Dry Etching，化學乾式蝕刻)、RIE(Reactive Ion Etching，反應性離子蝕刻)或濕式蝕刻。又，亦可將該等去除方法中之複數種去除方法組合使用。
其次，如圖3(f)所示，於第3層133之上成膜出TSI層140，再於TSI層140之上成膜出金屬層150，從而獲得圖1所示之閘極電極100。圖2所示之閘極電極100係藉由在第3層133上直接成膜出金屬層150而獲得。
(第2實施方式/半導體裝置)  作為第2實施方式之半導體裝置例如為CMOSFET。圖4係表示第2實施方式之一例之剖視圖。圖4所示之CMOSFET具有N通道MOSFET(以下有時簡稱「NMOS電晶體(TrN)」)與P通道MOSFET(以下有時簡稱「PMOS電晶體(TrP)」)。再者，將圖4中之X方向設為閘極寬度方向，將Y方向設為閘極長度方向，將Z方向設為與X方向及Y方向交叉之方向而進行說明。
於半導體基板110之表面附近，形成有P型井區域PW、N型井區域NW、及用以將N型井區域NW與P型井區域PW電性分離之元件分離區域STI。元件分離區域STI例如可使用氧化矽(SiO)。
於P型井區域PW設置有NMOS(N-Channel Metal Oxide Semiconductor，N通道金氧半導體)電晶體TrN，於N型井區域NW設置有PMOS(P-Channel Metal Oxide Semiconductor，P通道金氧半導體)電晶體TrP。
作為NMOS電晶體TrN之閘極電極GCn，可使用上述閘極電極100。金屬層150之上表面被絕緣層55覆蓋。金屬層150之側面被絕緣層56n覆蓋。絕緣層56n作為NMOS電晶體TrN之閘極電極100之側壁發揮功能。絕緣層55一部分開口，閘極電極100經由絕緣層55之開口連接於接觸插塞C0。
又，於P型井區域PW設置有n +雜質擴散區域NP1及NP2，其等例如摻雜有磷(P)。n +雜質擴散區域NP1與n +雜質擴散區域NP2沿Y方向隔開配置。n +雜質擴散區域NP1及NP2作為NMOS電晶體TrN之源極(源極擴散層)及汲極(汲極擴散層)發揮功能。n +雜質擴散區域NP1及NP2分別連接於接觸插塞CS。
接觸插塞CS、C0具有形成於接觸孔之底面及側面之導電層58、及與導電層58相接地埋入接觸孔內之導電層59。導電層58作為障壁金屬發揮功能，可使用鈦(Ti)與氮化鈦(TiN)之積層構造。導電層59例如可使用鎢(W)。
而PMOS電晶體TrP並不特別限定，可採用一般構造。例如，於N型井區域NW之表面附近，沿Y方向隔開設置有p +雜質擴散區域PP1及PP2，於其等間之區域設置有閘極電極GCp之閘極絕緣層120p。p +雜質擴散區域PP1及PP2例如摻雜有硼(B)。p +雜質擴散區域PP1及PP2作為PMOS電晶體TrP之源極(源極擴散層)及汲極(汲極擴散層)發揮功能。
又，於閘極絕緣層120p與金屬層150p之間設置有摻硼(B)多晶矽層180。進而，金屬層150p之上表面被絕緣層55覆蓋。金屬層150p之側面被絕緣層56p覆蓋。絕緣層56p作為PMOS電晶體(TrP)之閘極電極GCp之側壁發揮功能。絕緣層55一部分開口，閘極電極GCp經由絕緣層55之開口連接於接觸插塞C0。p +雜質擴散區域PP1及PP2分別連接於接觸插塞CS。
於接觸插塞CS及C0之上表面，連接導電體層(圖4中未圖示；圖10中之符號D0)。該導電體層作為圖4所示之PMOS電晶體TrP及NMOS電晶體TrN與其他電晶體或外部連接端子之間之配線發揮功能。
接觸插塞CS係設置於NMOS電晶體TrN及PMOS電晶體TrP之源極或汲極與導電體層之間之導電體層。接觸插塞C0係設置於NMOS電晶體TrN及PMOS電晶體TrP之閘極電極與導電體層之間之導電體層。n +雜質擴散區域NP1及NP2與p +雜質擴散區域PP1及PP2各自經由接觸插塞CS電性連接於導電體層。又，NMOS電晶體TrN及PMOS電晶體TrP被絕緣層31覆蓋。
上述CMOSFET例如按以下方式製造。參照圖5、圖6及圖7說明CMOSFET之製造步驟。首先，如圖5(a)所示，準備半導體基板110，如圖5(b)所示，於其一面上成膜出閘極絕緣層120。再者，將圖4所示之P型井區域PW、N型井區域NW、n +雜質擴散區域NP1及NP2、p +雜質擴散區域PP1及PP2之圖示省略。
如圖5(c)所示，於閘極絕緣層120之上，依序成膜第1層131、第2層132、第3層133而形成積層半導體層130。如圖5(d)所示，於第3層133之上成膜氧化膜160。氧化膜160例如藉由熱氧化而形成。
繼而，如圖5(e)所示，成膜終止層170。終止層170例如可使用氮化矽(SiN)。如圖5(f)所示，將後續要形成PMOS電晶體TrP之側去除。作為去除方法，例如可使用RIE。
如圖6(g)所示，成膜PMOS電晶體TrP之閘極絕緣層120p，於閘極絕緣層120p之上成膜摻硼(B)多晶矽層180。摻B多晶矽層180不僅成膜於後續要形成PMOS電晶體TrP之側(PMOS電晶體TrP側)之閘極絕緣層120p上，而且成膜於後續要設置NMOS電晶體TrN之側(NMOS電晶體TrN側)之終止層170上。如圖6(h)所示，於摻B多晶矽層180上成膜終止層190。例如，終止層190中可使用SiN。
如圖6(i)所示，藉由RIE將NMOS電晶體TrN側之摻B多晶矽層180去除。如圖6(j)所示，形成將NMOS電晶體TrN與PMOS電晶體TrP分離之STI槽200。
如圖7(k)所示，向STI槽200內填充填充物201。填充物201例如可使用SiO。向STI槽200中填充填充物201後，將終止層170之一部分、終止層190之一部分、及填充物201之一部分去除。作為去除方法，可使用CMP。如圖7(l)所示，將NMOS電晶體TrN側之終止層170、及PMOS電晶體TrP側之終止層190去除。作為去除方法，可使用濕式蝕刻。
如圖7(m)所示，將NMOS電晶體TrN之氧化膜160、及3層多晶半導體層130之第3層133之上層部分去除。作為去除方法，可使用濕式蝕刻。如圖7(n)所示，於NMOS電晶體TrN側之第3層133上、及PMOS電晶體TrP側之摻B多晶矽層180上，成膜出TSI層140。如圖7(o)所示，於TSI層140上成膜出金屬層150。
追加NMOS電晶體TrN側與PMOS電晶體TrP側之形成所需之步驟，諸如將金屬層150分於NMOS電晶體TrN側與PMOS電晶體TrP側，從而製作CMOSFET，但相關圖示被省略了。
於上述製造步驟之步驟(e)中，若不成膜出第3層133，而於第2層132上直接成膜出終止(SiN)層170，則在後續步驟中受熱時，有可能會於第2層132與終止層170之界面發生異常氧化。該異常氧化被認為是第2層132中所包含之C捕獲了第1層131中所摻雜之磷(P)而導致，會於形成STI(填充物201)後進行蝕刻(步驟(l))時產生蝕刻殘渣等。該蝕刻殘渣有可能會導致電晶體之漏電流增大。又，蝕刻殘渣會導致閘極電極100(GCn)間發生短路等，從而成為了使製造良率下降之主要因素。
因此，實施方式之閘極電極100中，於第2層132上設置有P濃度較第1層131低之第3層133。第3層133使用摻雜有低濃度之P或未摻雜P之多晶矽等，因此能抑制P於熱步驟中發生偏析等。藉此，能防止蝕刻殘渣之產生。其結果，能抑制蝕刻殘渣導致之缺陷產生，從而能提高電晶體之性能。進而，藉由減少蝕刻殘渣，亦能提高電晶體之良率。
(第3實施方式/半導體記憶裝置)  作為第2實施方式之半導體裝置之CMOSFET例如可用於將記憶單元電晶體三維積層於半導體基板上之三維積層型非揮發性記憶體裝置之控制電路等。但第2實施方式之半導體裝置之用途並不限於此，而可用於各種半導體裝置。作為第3實施方式之半導體記憶裝置，參照圖8、圖9及圖10說明三維積層型NAND型快閃記憶體。
圖8係表示第3實施方式之三維積層型NAND型快閃記憶體之整體構成之方塊圖。如圖8所示，半導體記憶裝置1例如由外部之記憶體控制器2加以控制。半導體記憶裝置1包含記憶單元陣列10、指令暫存器11、位址暫存器12、定序器13、驅動器模組14、列解碼器模組15及感測放大器模組16。
記憶單元陣列10包含複數個塊BLK0～BLK(L－1)(L為2以上之整數)。塊BLK係非揮發地記憶資料之複數個記憶單元電晶體(以下有時簡稱「記憶單元」)之集合體，例如用作資料之抹除單位。於記憶單元陣列10設置有複數個位元線及複數個字元線。各記憶單元電晶體例如與1個位元線及1個字元線相關聯。關於記憶單元陣列10之詳細構成，將於下文加以說明。
指令暫存器11保持半導體記憶裝置1自記憶體控制器2接收到之指令CMD。指令CMD例如包含使定序器13執行讀出動作、寫入動作及抹除動作等之命令。位址暫存器12保持半導體記憶裝置1自記憶體控制器2接收到之位址資訊ADD。位址資訊ADD例如包含塊位址BA、頁位址PA及行位址CA。例如，塊位址BA、頁位址PA及行位址CA分別用於塊BLK、字元線及位元線之選擇。
定序器13控制半導體記憶裝置1整體之動作。例如，定序器13基於指令暫存器11中所保持之指令CMD控制驅動器模組14、列解碼器模組15及感測放大器模組16等，從而執行讀出動作、寫入動作及抹除動作等。
驅動器模組14產生讀出動作、寫入動作及抹除動作等中所要使用之電壓。然後，驅動器模組14例如基於位址暫存器12中所保持之頁位址PA，將所產生之電壓施加給與選擇字元線對應之信號線。
列解碼器模組15基於位址暫存器12中所保持之塊位址BA，選擇對應記憶單元陣列10內之1個塊BLK。然後，列解碼器模組15例如向選擇塊BLK內之選擇字元線傳輸施加給與選擇字元線對應之信號線之電壓。
感測放大器模組16於寫入動作中，根據自記憶體控制器2接收到之寫入資料DAT，對各位元線施加所期望之電壓。又，感測放大器模組16於讀出動作中，基於位元線之電壓對記憶單元中所記憶之資料進行判定，並將判定結果作為讀出資料DAT傳輸給記憶體控制器2。
半導體記憶裝置1與記憶體控制器2之間之通信例如支持NAND介面。例如，於半導體記憶裝置1與記憶體控制器2之間之通信中，會使用指令鎖存賦能信號CLE、位址鎖存賦能信號ALE、寫賦能信號WEn、讀賦能信號REn、就緒忙碌信號RBn及輸入輸出信號I/O。
指令鎖存賦能信號CLE係表示半導體記憶裝置1所接收到之輸入輸出信號I/O為指令CMD之信號。位址鎖存賦能信號ALE係表示半導體記憶裝置1所接收到之信號I/O為位址資訊ADD之信號。寫賦能信號WEn係命令半導體記憶裝置1將輸入輸出信號I/O輸入之信號。讀賦能信號REn係命令半導體記憶裝置1將輸入輸出信號I/O輸出之信號。
就緒忙碌信號RBn係通知記憶體控制器2半導體記憶裝置1究竟是處於可受理來自記憶體控制器2之命令之就緒狀態還是處於不可受理命令之忙碌狀態之信號。
輸入輸出信號I/O例如為8位元寬度之信號，可包含指令CMD、位址資訊ADD、資料DAT等。
上文所說明之半導體記憶裝置1及記憶體控制器2亦可藉由組合而構成1個半導體裝置。作為此種半導體裝置，例如可例舉SD卡等記憶卡或SSD(Solid State Drive，固態驅動器)等。
其次，使用圖9，對記憶單元陣列10之電路構成進行說明。圖9之例表示塊BLK0，其他塊BLK之電路構成亦相同。如圖9所示，塊BLK例如包含4個串單元SU0～SU3。各串單元SU包含複數個NAND串NS。
複數個NAND串NS分別與位元線BL0～BL(N－1)(N為2以上之整數)相關聯。各NAND串NS例如包含記憶單元電晶體MC0～MC7、以及選擇電晶體ST1及ST2。
記憶單元電晶體MC包含控制閘極及電荷儲存層，非揮發地保持資料。以下，於不限定是記憶單元電晶體MC0～MC7中之何者之情形時，記作記憶單元電晶體MC。再者，記憶單元電晶體MC既可為對電荷儲存層使用絕緣膜之MONOS型，亦可為對電荷儲存層使用導電體層之FG型。以下，於實施方式中，以MONOS型為例進行說明。
選擇電晶體ST1用以於各種動作時選擇串單元SU。於各NAND串NS中，選擇電晶體ST1之汲極連接於相關聯之位元線BL。選擇電晶體ST1之源極連接於串聯連接之記憶單元電晶體MC0～MC7之一端。串聯連接之記憶單元電晶體MC0～MC7之另一端連接於選擇電晶體ST2之汲極。
於同一個塊BLK中，選擇電晶體ST2之源極共通連接於源極線SL。串單元SU0～SU3內之選擇電晶體ST1之閘極分別共通連接於選擇閘極線SGD0～SGD3。記憶單元電晶體MC0～MC7之控制閘極分別共通連接於字元線WL0～WL7。選擇電晶體ST2之閘極共通連接於選擇閘極線SGS。
上文所說明之記憶單元陣列10之電路構成中，被分配相同行位址CA之複數個NAND串NS乃於複數個塊BLK間共通連接於相同之位元線BL。源極線SL於複數個塊BLK間共通連接。
再者，實施方式之半導體記憶裝置1所具備之記憶單元陣列10之電路構成並不限定於上文所說明之構成。例如，各NAND串NS所包含之記憶單元電晶體MC、以及選擇電晶體ST1及ST2之個數可分別設計為任意個數。各塊BLK所包含之串單元SU之個數可設計為任意個數。
其次，使用圖10，對記憶單元陣列10之剖面構成進行說明。如圖10所示，於半導體基板100上形成絕緣層31。絕緣層31例如可使用氧化矽(SiO)。於絕緣層31內設置有電路區域UA，於絕緣層31上設置有記憶單元陣列10。於電路區域UA例如形成供感測放大器模組16等使用之電路。
首先，對記憶單元陣列10之構成進行說明。於絕緣層31上設置有作為源極線SL發揮功能之導電體層32。例如，導電體層32形成為沿著與半導體基板100大致平行之XY平面擴展之板狀。導電體層32係使用導電材料形成，導電材料例如包括金屬材料或半導體材料等。
於導電體層32上，交替地積層11層絕緣層33與10層導電體層34。絕緣層33例如可使用SiO。10層導電體層34例如自下方起依序作為選擇閘極線SGS、字元線WL0～WL7及選擇閘極線SGD發揮功能。例如，導電體層34形成為沿著X方向延伸之板狀。導電體層34係使用導電材料形成，導電材料例如包括金屬材料。
設置有貫通(通過)10層導電體層34、且底面到達導電體層32之複數個記憶柱MP。記憶柱MP沿著與半導體基板100大致垂直且與X及Y方向交叉之Z方向延伸。1個記憶柱MP對應於1個NAND串NS。記憶柱MP包含阻擋絕緣膜35、電荷儲存層36、隧道絕緣膜37、半導體層38、核心層39及上覆層40。
更具體而言，以貫通10層導電體層34從而底面到達導電體層32之方式，形成有與記憶柱MP對應之孔洞。於孔洞之側面依序積層有阻擋絕緣膜35、電荷儲存層36及隧道絕緣膜37。而且，以側面與隧道絕緣膜37相接且底面與導電體層32相接之方式，形成有半導體層38。半導體層38係形成記憶單元電晶體MC、以及選擇電晶體ST1及ST2之通道之區域。藉此，半導體層38作為將選擇電晶體ST2、記憶單元電晶體MC0～MC7及選擇電晶體ST1之電流路徑連接之信號線發揮功能。於半導體層38內設置有核心層39。而且，於半導體層38及核心層39上形成有側面與隧道絕緣膜37相接之上覆層40。
阻擋絕緣膜35、隧道絕緣膜37及核心層39例如可使用SiO。電荷儲存層36例如可使用氮化矽(SiN)。半導體層38及上覆層40例如可使用多晶矽。
記憶柱MP與分別作為字元線WL0～WL7發揮功能之8層導電體層34組合，而作為記憶單元電晶體MC0～MC7發揮功能。同樣地，記憶柱MP與分別作為選擇閘極線SGD及SGS發揮功能之2層導電體層34組合，而作為選擇電晶體ST1及ST2發揮功能。
於上覆層40上形成有接觸插塞CP。於接觸插塞CP上形成有作為位元線BL發揮功能之導電體層(未圖示)。接觸插塞CP係使用導電材料而形成，導電材料例如可使用金屬材料。
再者，於圖10之例中，3個記憶柱MP沿著Y方向而配置，但其實記憶柱MP可任意配置。
電路區域UA包含具有上述PMOS電晶體TrP與NMOS電晶體TrN之半導體裝置。如上所述，能抑制蝕刻殘渣導致之缺陷產生。
再者，PMOS電晶體TrP及NMOS電晶體TrN例如亦可用於指令暫存器11、位址暫存器12、定序器13、驅動器模組14、列解碼器模組15及感測放大器模組16等。
對本發明之若干個實施方式進行了說明，但該等實施方式係作為示例而提出，並非意欲限定發明之範圍。該等新穎之實施方式可採用其他各種方式加以實施，於不脫離發明主旨之範圍內，可進行各種省略、替換、變更。該等實施方式及其變形包含於發明之範圍及主旨中，並且包含於申請專利範圍所記載之發明及其等同之範圍內。  [相關申請]
本申請享有以日本專利申請2020-157386號(申請日期：2020年9月18日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。
1:半導體記憶裝置 2:記憶體控制器 10:記憶單元陣列 11:指令暫存器 12:位址暫存器 13:定序器 14:驅動器模組 15:列解碼器模組 16:感測放大器模組 31:絕緣層 32:導電體層 33:絕緣層 34:導電體層 35:阻擋絕緣膜 36:電荷儲存層 37:隧道絕緣膜 38:半導體層 39:核心層 40:上覆層 55:絕緣層 56n:絕緣層 56p:絕緣層 58:導電體層 59:導電體層 100:閘極電極 110:半導體基板 120:閘極絕緣層 120p:閘極絕緣層 130:3層多晶半導體層 131:第1層 132:第2層 133:第3層 133a:第3層之上層部分 140:TSI層 150:金屬層 150p:金屬層 160:氧化膜 170:終止層 180:摻硼多晶矽層 190:終止層 200:STI槽 201:填充物 BL0～BL(N－1):位元線 BLK0～BLK(L－1):塊 C0:接觸插塞 CP:接觸插塞 CS:接觸插塞 D0:導電體層 GCn:閘極電極 GCp:閘極電極 MC0～MC7:記憶單元電晶體 MP:記憶柱 NP1:n +雜質擴散區域 NP2:n +雜質擴散區域 NS:NAND串 NW:N型井區域 PP1:p +雜質擴散區域 PP2:p +雜質擴散區域 PW:P型井區域 SGD0～SGD3:選擇閘極線 SGS:選擇閘極線 SL:源極線 ST1:選擇電晶體 ST2:選擇電晶體 STI:元件分離區域 SU0～SU3:串單元 TrN:電晶體 TrP:電晶體 UA:電路區域 WL0～WL7:字元線
圖1係表示實施方式之半導體裝置中之閘極電極之剖視圖。  圖2係表示圖1所示之閘極電極之變化例之剖視圖。  圖3(a)～(f)係表示圖1所示之閘極電極之製造步驟之圖。  圖4係表示作為實施方式之半導體裝置之CMOSFET(Complementary Metal Oxide Semiconductor Field Effect Transistor，互補金氧半導體場效電晶體)之剖視圖。  圖5(a)～圖7(o)係表示圖4所示之CMOSFET之製造步驟之圖。  圖8係表示實施方式之半導體記憶裝置之構成之方塊圖。  圖9係表示圖8所示之半導體記憶裝置之記憶單元陣列之電路構成之電路圖。  圖10係表示實施方式之半導體記憶裝置之剖視圖。
100:閘極電極
110:半導體基板
120:閘極絕緣層
130:3層多晶半導體層
131:第1層
132:第2層
133:第3層
140:TSI層
150:金屬層

Claims (5)

  1. 一種記憶體裝置之製造方法，其係：  於基板上設置電晶體，且   設置與上述電晶體電性連接之記憶單元陣列，其中  上述電晶體係設置於上述基板與上述記憶單元陣列之間，  於設置上述電晶體時，  於上述基板上形成閘極絕緣層，  形成包含第1層、第2層及第3層之積層半導體層，該第1層於上述閘極絕緣層上包含摻雜有磷之多晶半導體，該第2層於上述第1層上包含摻雜有碳之多晶半導體，該第3層於上述第2層上包含摻雜有較上述第1層之磷含量少的磷或未摻雜磷之多晶半導體，  於上述第3層上或上述第3層之上方形成金屬層。
  2. 如請求項1之記憶體裝置之製造方法，其中形成上述積層半導體層後且形成上述金屬層前，於上述第3層上設置氧化膜，  形成貫通上述閘極絕緣層、上述積層半導體層及上述氧化膜之槽，  將上述氧化膜去除。
  3. 如請求項2之記憶體裝置之製造方法，其中上述基板包含P型井部與N型井部，  設置上述氧化膜後，將形成於上述N型井部上或上方之所有層去除，且  形成上述金屬層前，於上述N型井部上設置其他閘極絕緣層與多晶半導體層。
  4. 如請求項1之記憶體裝置之製造方法，其中上述金屬層形成於上述第3層之正上方，且  上述金屬層係具有自上述積層半導體層側起依序配置之鈦層、氮化鈦層及鎢層之積層體。
  5. 如請求項1之記憶體裝置之製造方法，其中形成上述金屬層前，於上述第3層上形成氧化層，且  上述金屬層包含具有自上述積層半導體層側起依序配置之鈦層、氮化鈦層及鎢層之積層體。
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