TWI803180B - Semiconductor memory structure and method for forming the same - Google Patents

Semiconductor memory structure and method for forming the same Download PDF

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TWI803180B
TWI803180B TW111104464A TW111104464A TWI803180B TW I803180 B TWI803180 B TW I803180B TW 111104464 A TW111104464 A TW 111104464A TW 111104464 A TW111104464 A TW 111104464A TW I803180 B TWI803180 B TW I803180B
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bit line
layer
semiconductor memory
memory structure
forming
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TW111104464A
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TW202333347A (en
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顏英竹
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華邦電子股份有限公司
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Abstract

Embodiments of the invention provide a method of forming a semiconductor memory structure. An isolation structure surrounding an active area is disposed over a substrate. Two word lines are disposed in the active area. A bit line contact is disposed between two word lines. A first bit line is disposed over the bit line contact. The bit line contact includes polysilicon and has a concave top surface.

Description

半導體記憶體結構及其形成方法 Semiconductor memory structure and method of forming the same

本發明實施例係有關於一種半導體記憶體裝置，且特別有關於一種位元線及其形成方法。 Embodiments of the present invention relate to a semiconductor memory device, and in particular to a bit line and a method for forming the same.

隨著積體電路尺寸縮小，動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)密度增加，縫隙填充製程越來越困難。可能在形成位元線接點時產生接縫，進而造成高阻值的位元線接點。 As the size of integrated circuits shrinks and the density of Dynamic Random Access Memory (DRAM) increases, the gap filling process becomes more and more difficult. Seams may be created when bit line contacts are formed, resulting in high resistance bit line contacts.

本發明一些實施例提供一種半導體記憶體結構，包括：隔離區，包圍主動區，位於基板中；兩字元線，位於主動區之中；位元線接點，位於兩字元線之間；第一位元線，位於位元線接點之上，位元線接點包括多晶矽，並具有下凹的頂表面。 Some embodiments of the present invention provide a semiconductor memory structure, including: an isolation region, surrounding the active region, located in the substrate; two word lines, located in the active area; a bit line contact, located between the two word lines; The first bit line is located on the bit line contact. The bit line contact includes polysilicon and has a concave top surface.

本發明實施例亦提供一種半導體記憶體結構，包括：位元線接點，位於兩字元線之間的主動區上；第一位元線，包括第 一阻障層及第一導電層，位於位元線接點之上，第二位元線，包括第二阻障層及第二導電層，位於隔離區上，第一阻障層比第二阻障層厚。 The embodiment of the present invention also provides a semiconductor memory structure, comprising: a bit line contact located on the active area between two word lines; a first bit line including a second bit line A barrier layer and the first conductive layer are located on the bit line contact, the second bit line, including the second barrier layer and the second conductive layer, are located on the isolation region, the first barrier layer is larger than the second The barrier layer is thick.

本發明實施例又提供一種半導體記憶體結構的形成方法，包括：形成隔離結構包圍主動區於基板之中；形成兩字元線於主動區之中；形成開口於兩字元線之間；沉積多晶矽層具有接縫於開口之中；蝕刻多晶矽層以擴大接縫；以及沉積位元線材料於接縫之中。 The embodiment of the present invention also provides a method for forming a semiconductor memory structure, including: forming an isolation structure to surround the active area in the substrate; forming two word lines in the active area; forming an opening between the two word lines; depositing The polysilicon layer has seams in the openings; the polysilicon layer is etched to enlarge the seams; and the bit line material is deposited in the seams.

100,200:半導體記憶體結構 100,200: Semiconductor memory structure

102:基板 102: Substrate

104:隔離區 104: Quarantine

105:蓋層 105: cover layer

106:主動區 106: active zone

107:襯層 107: lining

108:字元線 108: character line

108a:閘極介電層 108a: gate dielectric layer

108b:阻障層 108b: barrier layer

108c:導電層 108c: conductive layer

114:頂層 114: top floor

116:半導體材料層 116: semiconductor material layer

118:硬罩幕層 118: hard mask layer

120:開口 120: opening

122:位元線接點 122: bit line contact

122a:多晶矽層 122a: polysilicon layer

124:接縫 124: seam

126:位元線材料 126: bit line material

126a:第一位元線 126a: first bit line

126b:第二位元線 126b: second bit line

128:阻障層 128: barrier layer

128e:延伸部分 128e: extension

130:導電層 130: conductive layer

132:硬罩幕層 132: hard mask layer

134:凹槽 134: Groove

136:隔離層 136: isolation layer

140:電容接點 140: capacitor contact

142:矽化物 142: Silicide

144:電容 144: capacitance

1-1,2-2:線 1-1,2-2: line

H:高度差 H: height difference

以下將配合所附圖式詳述本發明實施例。應注意的是，各種特徵部件並未按照比例繪製且僅用以說明例示。事實上，元件的尺寸可能經放大或縮小，以清楚地表現出本發明實施例的技術特徵。 Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of elements may be enlarged or reduced to clearly show the technical characteristics of the embodiments of the present invention.

第1圖係根據一些實施例繪示出半導體記憶體結構之上視圖。 FIG. 1 is a top view of a semiconductor memory structure according to some embodiments.

第2A-2E、2F-1、2F-2、2G圖係根據一些實施例繪示出形成半導體記憶體結構之各階段剖面圖。 Figures 2A-2E, 2F-1, 2F-2, and 2G are cross-sectional views of various stages of forming a semiconductor memory structure according to some embodiments.

第3A-3C、3D-1、3D-2圖係根據另一些實施例繪示出形成半導體記憶體結構之各階段剖面圖。 Figures 3A-3C, 3D-1, and 3D-2 are cross-sectional views of various stages of forming a semiconductor memory structure according to other embodiments.

第1圖係根據一些實施例繪示出半導體記憶體結構 100之上視圖。第2A-2E、2F-1、2F-2、2G圖係根據一些實施例繪示出形成半導體記憶體結構100之各階段剖面圖。第2A-2E、2F-1圖繪示出第1圖中沿線1-1而得的半導體記憶體結構100的剖面圖。第2F-2、2G圖繪示出第1圖中沿線2-2而得的半導體記憶體結構100的剖面圖。 Figure 1 depicts a semiconductor memory structure according to some embodiments 100 above view. 2A-2E, 2F-1, 2F-2, and 2G are cross-sectional views of various stages of forming the semiconductor memory structure 100 according to some embodiments. FIGS. 2A-2E and 2F-1 illustrate cross-sectional views of the semiconductor memory structure 100 taken along line 1 - 1 in FIG. 1 . 2F-2 and 2G are cross-sectional views of the semiconductor memory structure 100 taken along line 2-2 in FIG. 1 .

如第1圖所繪示，半導體記憶體結構100包括隔離區104包圍主動區106。位元線接點122形成於兩字元線108之間，位元線126形成於位元線接點122之上，並在上視圖中與字元線108垂直。如第2A圖所繪示，提供基板102。基板102可為半導體基板，其可包括元素半導體或合金半導體。此外，基板102也可以是絕緣層上覆半導體(semiconductor on insulator，SOI)。基板102可為N型或P型的導電類型。接著，形成一頂層114於基板102之上，並形成墊層於頂層114之上(未繪示)。頂層114可作為基板102及墊層之間的緩衝層，墊層可為隔離層，且可做為後續蝕刻的停止層。頂層114為氧化物例如氧化矽。墊層可為SiN、SiCN、SiOC、SiOCN、其他可用的材料，或上述之組合。 As shown in FIG. 1 , the semiconductor memory structure 100 includes an isolation region 104 surrounding an active region 106 . A bit line contact 122 is formed between two word lines 108 , and a bit line 126 is formed above the bit line contact 122 and perpendicular to the word line 108 in a top view. As shown in FIG. 2A , a substrate 102 is provided. The substrate 102 may be a semiconductor substrate, which may include elemental semiconductors or alloy semiconductors. In addition, the substrate 102 may also be a semiconductor on insulator (SOI). The substrate 102 can be of N-type or P-type conductivity. Next, a top layer 114 is formed on the substrate 102 , and a pad layer (not shown) is formed on the top layer 114 . The top layer 114 can serve as a buffer layer between the substrate 102 and the pad layer, which can be an isolation layer and can be used as a stop layer for subsequent etching. The top layer 114 is an oxide such as silicon oxide. The underlayer can be SiN, SiCN, SiOC, SiOCN, other available materials, or combinations thereof.

接著，以圖案化製程例如微影及蝕刻製程形成溝槽以定義主動區106(未繪示)。在一些實施例中，溝槽包圍主動區106。 Next, trenches are formed by patterning processes such as lithography and etching processes to define the active region 106 (not shown). In some embodiments, the trench surrounds the active region 106 .

接著，在溝槽的側壁及底表面順應性地形成襯層107。襯層107可用以保護主動區106，使其在後續製程中(例如退火或蝕刻製程中)不受損害。在一些實施例中，襯層107以氧化物例如氧化矽製成。 Next, a liner 107 is conformally formed on the sidewall and bottom surface of the trench. The liner 107 can be used to protect the active region 106 from being damaged in subsequent processes such as annealing or etching. In some embodiments, the liner 107 is made of oxide such as silicon oxide.

接著，在溝槽中形成隔離結構104。隔離結構104可以氮化矽、氧化矽、其他介電材料、或上述之組合製成。之後，平坦化隔離結構104以露出墊層的頂表面(未繪示)。接著，移除墊層露出頂層114的上表面(未繪示)。在一些實施例中，以濕蝕刻製程或乾蝕刻製程移除墊層，濕蝕刻製程可包括使用磷酸(H3PO4)溶液。 Next, an isolation structure 104 is formed in the trench. The isolation structure 104 can be made of silicon nitride, silicon oxide, other dielectric materials, or a combination thereof. Afterwards, the isolation structure 104 is planarized to expose the top surface (not shown) of the pad layer. Next, the pad layer is removed to expose the upper surface (not shown) of the top layer 114 . In some embodiments, the pad layer is removed by a wet etching process or a dry etching process, and the wet etching process may include using a phosphoric acid (H 3 PO 4 ) solution.

接著，進行圖案化製程例如微影及蝕刻製程在主動區106中以及隔離結構104中形成溝槽(未繪示)。由於蝕刻製程在主動區106以及隔離結構104中的蝕刻速率不同，因此在主動區106中以及隔離結構104所形成的溝槽深度不同。在一些實施例中，隔離結構104中的溝槽比主動區106中的溝槽深。 Next, a patterning process such as lithography and etching is performed to form trenches (not shown) in the active region 106 and the isolation structure 104 . Due to the different etching rates of the etching process in the active region 106 and the isolation structure 104 , the trenches formed in the active region 106 and the isolation structure 104 have different depths. In some embodiments, the trenches in isolation structures 104 are deeper than the trenches in active region 106 .

接著，在主動區106中以及隔離結構104的溝槽中形成字元線108。字元線108包括閘極介電層108a、阻障層108b、及導電層108c。其中，閘極介電層108a形成於主動區106中溝槽的側壁及底表面上。可於主動區106中溝槽以及隔離結構104中溝槽的側壁及底表面形成阻障層108b，以防止後續形成的導電材料擴散。接著，以導電層108c填充主動區106以及隔離結構104中溝槽內阻障層108b之間的空間。 Next, word lines 108 are formed in the active region 106 and in the trenches of the isolation structure 104 . The word line 108 includes a gate dielectric layer 108a, a barrier layer 108b, and a conductive layer 108c. Wherein, the gate dielectric layer 108 a is formed on the sidewall and bottom surface of the trench in the active region 106 . The barrier layer 108b can be formed on the trench in the active region 106 and the sidewall and bottom surface of the trench in the isolation structure 104 to prevent the diffusion of the subsequently formed conductive material. Next, the space between the active region 106 and the barrier layer 108b in the trench in the isolation structure 104 is filled with the conductive layer 108c.

在一些實施例中，閘極介電層108a可包括氧化矽、氮化矽、或氮氧化矽、高介電常數(high-k)(亦即介電常數大於3.9)之介電材料例如HfO2、LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3、BaTiO3、BaZrO、HfZrO、HfLaO、HfTaO、HfSiO、HfSiON、HfTiO、LaSiO、AlSiO、(Ba、Sr)TiO3、Al2O3、或 上述之組合。在一些實施例中，閘極介電層108a以熱氧化製程例如快速熱製程(rapid thermal processing，RTP)原位蒸氣產生(in-situ steam generation，ISSG)形成於主動區106內的溝槽中。 In some embodiments, the gate dielectric layer 108a may include silicon oxide, silicon nitride, or silicon oxynitride, a dielectric material with a high dielectric constant (high-k) (that is, a dielectric constant greater than 3.9) such as HfO. 2. LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaTiO 3 , BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, (Ba, Sr)TiO 3. Al 2 O 3 , or a combination of the above. In some embodiments, the gate dielectric layer 108a is formed in the trench in the active region 106 by a thermal oxidation process such as rapid thermal processing (rapid thermal processing, RTP) in-situ steam generation (ISSG). .

在一些實施例中，阻障層108b以金屬材料製成。阻障層108b的材料可為鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)、鎢(W)、氮化鎢(WN)、或上述之組合。導電層108c包括金屬材料(例如鎢、鋁、或銅)、金屬合金、或上述之組合。 In some embodiments, the barrier layer 108b is made of metal material. The material of the barrier layer 108b can be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), or a combination thereof. The conductive layer 108c includes a metal material (such as tungsten, aluminum, or copper), a metal alloy, or a combination thereof.

接著，進行蝕刻製程回蝕主動區106中以及隔離結構104中的導電層108c及阻障層108b至想要的高度以形成字元線108。 Next, an etching process is performed to etch back the conductive layer 108 c and the barrier layer 108 b in the active region 106 and the isolation structure 104 to a desired height to form the word line 108 .

接著，以蓋層105填充字元線108上方的溝槽，並覆蓋基板102。在一些實施例中，蓋層105及隔離結構104包括氮化物例如SiN、SiCN、SiOC、SiOCN。 Next, the trench above the word line 108 is filled with a capping layer 105 and covers the substrate 102 . In some embodiments, the capping layer 105 and the isolation structure 104 include nitrides such as SiN, SiCN, SiOC, SiOCN.

接著，在蓋層105上方沉積半導體材料層116，並在半導體材料層116上方沉積硬罩幕層118。半導體材料層116可包括多晶矽(polysilicon)。硬罩幕層118可包括氧化物例如氧化矽。接著，以圖案化製程例如微影及蝕刻製程形成開口120於字元線108之間的主動區106上。在一些實施例中，開口120穿過硬罩幕層118、半導體材料層116、蓋層105及主動區106。接著，如第2B圖中所繪示，順應性地沉積多晶矽層122a於開口120的側壁及底表面上，且覆蓋硬罩幕層118的上表面。接縫124形成於開口120中的多晶矽層122a之中。 Next, a semiconductor material layer 116 is deposited over the capping layer 105 , and a hard mask layer 118 is deposited over the semiconductor material layer 116 . The semiconductor material layer 116 may include polysilicon. The hard mask layer 118 may include an oxide such as silicon oxide. Next, openings 120 are formed on the active region 106 between the word lines 108 by a patterning process such as lithography and etching. In some embodiments, the opening 120 passes through the hard mask layer 118 , the semiconductor material layer 116 , the cap layer 105 and the active region 106 . Next, as shown in FIG. 2B , a polysilicon layer 122 a is conformally deposited on the sidewalls and bottom surface of the opening 120 and covers the upper surface of the hard mask layer 118 . The seam 124 is formed in the polysilicon layer 122 a in the opening 120 .

接著，如第2C圖中所繪示，蝕刻多晶矽層122a以擴大接縫124。在一些實施例中，蝕刻製程去除了硬罩幕層118上表面及側壁上的多晶矽層122a，並露出硬罩幕層118上表面及側壁。餘留在開口120中的多晶矽層122a在字元線108之間的主動區106上形成位元線接點122。在一些實施例中，在蝕刻多晶矽層122a後，多晶矽層122a的最高點與半導體材料層116的上表面大抵上齊平。此外，在蝕刻多晶矽層122a後，多晶矽層122a具有彎曲且下凹的頂表面。在一些實施例中，蝕刻多晶矽層122a的製程可包括乾蝕刻製程(例如反應離子蝕刻、非等向性電漿蝕刻、或上述之組合)。在一些實施例中，乾蝕刻的蝕刻流量為10sccm至20sccm。 Next, as shown in FIG. 2C, the polysilicon layer 122a is etched to enlarge the seam 124. Referring to FIG. In some embodiments, the etching process removes the polysilicon layer 122 a on the upper surface and sidewalls of the hard mask layer 118 , and exposes the upper surface and sidewalls of the hard mask layer 118 . The polysilicon layer 122 a remaining in the opening 120 forms a bitline contact 122 on the active region 106 between the wordlines 108 . In some embodiments, after the polysilicon layer 122a is etched, the highest point of the polysilicon layer 122a is substantially flush with the upper surface of the semiconductor material layer 116 . In addition, after the polysilicon layer 122a is etched, the polysilicon layer 122a has a curved and concave top surface. In some embodiments, the process of etching the polysilicon layer 122a may include a dry etching process (such as reactive ion etching, anisotropic plasma etching, or a combination thereof). In some embodiments, the etching flow rate of the dry etching is 10 sccm to 20 sccm.

接著，如第2D圖中所繪示，以蝕刻製程移除硬罩幕層118以露出半導體材料層116的上表面。蝕刻製程可包括乾蝕刻製程(例如反應離子蝕刻、非等向性電漿蝕刻)、濕蝕刻製程、或上述之組合。 Next, as shown in FIG. 2D , the hard mask layer 118 is removed by an etching process to expose the upper surface of the semiconductor material layer 116 . The etching process may include a dry etching process (such as reactive ion etching, anisotropic plasma etching), a wet etching process, or a combination thereof.

接著，如第2E圖中所繪示，形成位元線材料126於擴大的接縫124及開口120之中，並覆蓋位元線接點122的上方。位元線材料126包括阻障層128及導電層130。在形成導電層130之前，可於接縫124的側壁及底部形成阻障層128。阻障層128的材料可為鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)、氮化鎢(WN)、其他合適的材料、或上述之組合。導電層130包括金屬材料(例如鎢、鋁、或銅)、金屬合金、或上述之組合。根據一些實施例，可以原子層沉積製程沉積位元線材料126的阻障層128及導電層130。 Next, as shown in FIG. 2E , bitline material 126 is formed within enlarged seam 124 and opening 120 and overlies bitline contact 122 . The bit line material 126 includes a barrier layer 128 and a conductive layer 130 . Before forming the conductive layer 130 , a barrier layer 128 may be formed on the sidewall and bottom of the seam 124 . The material of the barrier layer 128 can be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), other suitable materials, or combinations thereof. The conductive layer 130 includes a metal material (such as tungsten, aluminum, or copper), a metal alloy, or a combination thereof. According to some embodiments, the barrier layer 128 and the conductive layer 130 of the bitline material 126 may be deposited by an atomic layer deposition process.

在一些實施例中，阻障層128具有延伸部分128e形成於擴大的接縫124之中。在一些實施例中，延伸部分128e延伸於位元線接點122之中。在一些實施例中，由於擴大了接縫124，阻障層128的延伸部分128e的上表面比下表面寬。並且，阻障層128的延伸部分128e比位元線接點122窄。 In some embodiments, the barrier layer 128 has an extension 128 e formed in the enlarged seam 124 . In some embodiments, the extension portion 128e extends into the bit line contact 122 . In some embodiments, the upper surface of the extended portion 128e of the barrier layer 128 is wider than the lower surface due to the enlarged seam 124 . Also, the extension portion 128 e of the barrier layer 128 is narrower than the bit line contact 122 .

在一些實施例中，由於位元線126材料的阻障層128及導電層130係順應性地形成於位元線接點122之上，位元線126材料的導電層130在位元線接點122上方具有下凹的上表面。 In some embodiments, since the barrier layer 128 and the conductive layer 130 of the material of the bit line 126 are conformably formed on the contact 122 of the bit line, the conductive layer 130 of the material of the bit line 126 is formed on the bit line contact. Above point 122 there is a concave upper surface.

接著，如第2F-1中所繪示，形成硬罩幕層132於位元線材料126之上。硬罩幕層132可包括氮化物例如SiN、SiCN、SiOC、SiOCN。硬罩幕層132可為多層結構，每一層硬罩幕層132的材料可相同或不同。接著，如第2F-2圖中所繪示，以圖案化製程例如微影及蝕刻製程形成第一位元線126a及第二位元線126b。第一位元線126a位於位元線接點122之上，且第二位元線126b位於第一位元線126a旁的隔離結構104之上。 Next, as shown in Section 2F-1, a hard mask layer 132 is formed on the bit line material 126 . The hard mask layer 132 may include nitrides such as SiN, SiCN, SiOC, SiOCN. The hard mask layer 132 can be a multi-layer structure, and the materials of each hard mask layer 132 can be the same or different. Next, as shown in FIG. 2F-2, the first bit line 126a and the second bit line 126b are formed by a patterning process such as lithography and etching process. The first bit line 126a is located above the bit line contact 122, and the second bit line 126b is located above the isolation structure 104 next to the first bit line 126a.

根據一些實施例，在形成第一位元線126a的過程中，移除了第一位元線126a兩側的位元線接點材料122，而在第一位元線126a兩側的基板102中形成凹槽134。在一些實施例中，為了將位元線接點材料122徹底移除，凹槽134的底表面低於位元線接點122的底表面。 According to some embodiments, in the process of forming the first bit line 126a, the bit line contact material 122 on both sides of the first bit line 126a is removed, and the substrate 102 on both sides of the first bit line 126a A groove 134 is formed in the middle. In some embodiments, the bottom surface of the groove 134 is lower than the bottom surface of the bitline contact 122 in order to completely remove the bitline contact material 122 .

由於在位元線接點122上方的第一位元線126a的阻障層128具有延伸部分128e，第一位元線126a的阻障層128比第二位 元線126b的阻障層128厚。此外，由於位元線126材料的導電層130在位元線接點122上方具有下凹的上表面，第一位元線126a的頂表面低於第二位元線126b的頂表面，第一位元線126a與第二位元線126b的高度差為H。在一些實施例中，第一位元線126a的導電層130與第二位元線126b的導電層130的厚度大抵相同。 Since the barrier layer 128 of the first bit line 126a above the bit line contact 122 has an extension 128e, the barrier layer 128 of the first bit line 126a is larger than the barrier layer 128 of the second bit line 126a. The barrier layer 128 of the element line 126b is thick. In addition, since the conductive layer 130 of bitline 126 material has a concave upper surface above the bitline contact 122, the top surface of the first bitline 126a is lower than the top surface of the second bitline 126b, the first The height difference between the bit line 126a and the second bit line 126b is H. In some embodiments, the thickness of the conductive layer 130 of the first bit line 126a is substantially the same as that of the conductive layer 130 of the second bit line 126b.

接著，如第2G圖中所繪示，在位元線126a及126b之間及之上順應性地沉積間隔物結構136。間隔物結構136可提供位元線126側壁的隔離。間隔物結構136可為多層結構。間隔物結構136可包括氧化物、氮化物、其他可用的材料、或上述之組合。在一些實施例中，間隔物結構136填充凹槽134以形成隔離結構136。在一些實施例中，隔離結構136的底表面低於位元線接點122的底表面。 Next, spacer structures 136 are conformally deposited between and over bitlines 126a and 126b, as depicted in FIG. 2G. Spacer structures 136 may provide isolation of sidewalls of bitlines 126 . The spacer structure 136 may be a multilayer structure. The spacer structure 136 may include oxide, nitride, other available materials, or combinations thereof. In some embodiments, the spacer structure 136 fills the groove 134 to form the isolation structure 136 . In some embodiments, the bottom surface of the isolation structure 136 is lower than the bottom surface of the bit line contact 122 .

接著，以圖案化製程例如微影及蝕刻製程在位元線126a及126b之間形成溝槽(未繪示)。先在溝槽中形成電容接點140。電容接點140可包括多晶矽材料。接著，在電容接點140上形成矽化物142。矽化物142可降低電容接點140與後續形成的電容之間的阻值。接著，在矽化物142上形成電容144。 Next, trenches (not shown) are formed between the bit lines 126a and 126b by patterning processes such as lithography and etching processes. Capacitive contact 140 is first formed in the trench. Capacitor contact 140 may include polysilicon material. Next, a silicide 142 is formed on the capacitor contact 140 . The silicide 142 can reduce the resistance between the capacitor contact 140 and the subsequently formed capacitor. Next, a capacitor 144 is formed on the silicide 142 .

電容144可包括底電極、頂電極、及夾於其中的介電質(未繪示)。底電極及頂電極可包括TiN、TaN、TiAlN、TiW、WN、Ti、Au、Ta、Ag、Cu、AlCu、Pt、W、Ru、Al、Ni、金屬氮化物、或上述之組合。介電質可包括高介電常數介電材料例如HfO2、LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3、BaTiO3、BaZrO、HffZrO、HfLaO、HfTaO、HfSiO、HfSiON、HfTiO、LaSiO、 AlSiO、(Ba、Sr)TiO3、Al2O3、或上述之組合。 The capacitor 144 may include a bottom electrode, a top electrode, and a dielectric (not shown) interposed therebetween. The bottom and top electrodes may include TiN, TaN, TiAlN, TiW, WN, Ti, Au, Ta, Ag, Cu, AlCu, Pt, W, Ru, Al, Ni, metal nitrides, or combinations thereof. The dielectric may include high-k dielectric materials such as HfO 2 , LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaTiO 3 , BaZrO, Hf f ZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, (Ba, Sr)TiO 3 , Al 2 O 3 , or a combination thereof.

如上所述，藉由擴大位元線接點材料122的接縫124，並將位元線126的阻障層128填入擴大的接縫124之中，可降低位元線接點122電阻。此外，位元線接點122上的位元線126的位置較低，位元線接點122亦較短，可降低位元線126至電容接點140之間的寄生電容。 As described above, by enlarging the seam 124 of the bit line contact material 122 and filling the barrier layer 128 of the bit line 126 into the enlarged seam 124, the resistance of the bit line contact 122 can be reduced. In addition, the position of the bit line 126 on the bit line contact 122 is lower, and the bit line contact 122 is also shorter, which can reduce the parasitic capacitance between the bit line 126 and the capacitor contact 140 .

第3A-3C、3D-1、3D-2圖係根據一些實施例繪示出形成半導體記憶體結構200之各階段剖面圖。其中與前述實施例相同或相似的製程或元件將沿用相同的元件符號，其詳細內容將不再贅述。與前述實施例的差別在於，如第3A圖所示，在蝕刻位元線接點材料122，擴大接縫124之後，接縫124兩側的位元線接點122具有平坦的上表面。 3A-3C, 3D-1, and 3D-2 are cross-sectional views illustrating various stages of forming the semiconductor memory structure 200 according to some embodiments. Wherein, the same or similar manufacturing processes or elements as those of the foregoing embodiments will use the same reference numerals, and details thereof will not be described again. The difference from the previous embodiments is that, as shown in FIG. 3A , after the bit line contact material 122 is etched to enlarge the seam 124 , the bit line contacts 122 on both sides of the seam 124 have flat upper surfaces.

如第3A圖中所繪示，蝕刻位元線接點122以擴大接縫124且露出硬罩幕層118的上表面及側壁。在一些實施例中，在蝕刻位元線接點122後，位元線接點122的上表面與半導體材料層116的上表面大抵上齊平。與第2C圖所示的實施例相較之下，第3A圖所示的實施例的蝕刻量較少，因此在接縫124兩側的位元線接點122產生平坦的頂表面。在一些實施例中，乾蝕刻的蝕刻流量為20sccm至30sccm。 As shown in FIG. 3A , the bitline contacts 122 are etched to enlarge the seams 124 and expose the top surface and sidewalls of the hard mask layer 118 . In some embodiments, the upper surface of the bitline contact 122 is substantially flush with the upper surface of the semiconductor material layer 116 after the bitline contact 122 is etched. Compared to the embodiment shown in FIG. 2C , the embodiment shown in FIG. 3A has less etch, so that the bit line contacts 122 on both sides of the seam 124 create flat top surfaces. In some embodiments, the etching flow rate of the dry etching is 20 sccm to 30 sccm.

接著，如第3B圖中所繪示，以蝕刻製程移除硬罩幕層118以露出半導體材料層116的上表面。 Next, as shown in FIG. 3B , the hard mask layer 118 is removed by an etching process to expose the upper surface of the semiconductor material layer 116 .

接著，如第3C圖中所繪示，形成位元線材料126於接 縫124及開口120之中，並覆蓋基板102的上方。位元線材料126包括阻障層128及導電層130。在形成導電層130之前，可於接縫124的中形成阻障層128。形成第3C圖中位元線材料126的製程及材料可與形成第2E圖中位元線材料126的製程及材料相同或相似，於此不重述。 Next, as shown in FIG. 3C, bit line material 126 is formed at the junction The slot 124 and the opening 120 cover the top of the substrate 102 . The bit line material 126 includes a barrier layer 128 and a conductive layer 130 . Before forming the conductive layer 130 , a barrier layer 128 may be formed in the seam 124 . The process and materials for forming the bit line material 126 in FIG. 3C may be the same or similar to the process and materials for forming the bit line material 126 in FIG. 2E , and will not be repeated here.

在一些實施例中，由於接縫124兩側的位元線接點122具有平坦的頂表面，而位元線126材料的阻障層128及導電層130係順應性地形成於位元線接點122之上，位元線126材料的導電層130在位元線接點122上方亦具有平坦的上表面。 In some embodiments, since the bit line contacts 122 on both sides of the seam 124 have flat top surfaces, the barrier layer 128 and the conductive layer 130 of the bit line 126 material are conformably formed on the bit line contacts. Above point 122 , conductive layer 130 of bitline 126 material also has a planar upper surface above bitline contact 122 .

接著，如第3D-1圖中所繪示，形成硬罩幕層132於位元線材料126之上。形成第3D-1圖中硬罩幕層132的製程及材料可與形成第2F-1圖中硬罩幕層132的製程及材料相同或相似，於此不重述。 Next, as shown in FIG. 3D-1 , a hard mask layer 132 is formed on the bit line material 126 . The process and materials for forming the hard mask layer 132 in FIG. 3D-1 may be the same or similar to those for forming the hard mask layer 132 in FIG. 2F-1 , and will not be repeated here.

接著，如第3D-2圖中所繪示，以圖案化製程例如微影及蝕刻製程形成第一位元線126a及第二位元線126b。第一位元線126a位於位元線接點122之上，且第二位元線126b位於第一位元線126a旁的隔離結構104之上。形成第3D-2圖中第一位元線126a及第二位元線126b的製程及材料可與形成第2F-2圖中第一位元線126a及第二位元線126b的製程及材料相同或相似，於此不重述。 Next, as shown in FIG. 3D-2 , the first bit line 126 a and the second bit line 126 b are formed by a patterning process such as lithography and etching process. The first bit line 126a is located above the bit line contact 122, and the second bit line 126b is located above the isolation structure 104 next to the first bit line 126a. The process and materials for forming the first bit line 126a and the second bit line 126b in FIG. 3D-2 can be compared with the process and materials for forming the first bit line 126a and the second bit line 126b in FIG. 2F-2. The same or similar, not repeated here.

在一些實施例中，第一位元線126a的導電層130的底表面與第二位元線126b的導電層130的底表面大抵齊平。第一位元線126a的阻障層128比第二位元線126b的阻障層128厚。因此，可 藉以降低電阻。 In some embodiments, the bottom surface of the conductive layer 130 of the first bitline 126a is substantially flush with the bottom surface of the conductive layer 130 of the second bitline 126b. The barrier layer 128 of the first bit line 126a is thicker than the barrier layer 128 of the second bit line 126b. Therefore, can to reduce resistance.

如上所述，藉由擴大位元線接點材料122的接縫124，並將位元線126的阻障層128填入擴大的接縫124之中，可降低電阻。藉由控制蝕刻位元線接點材料122的製程參數，位元線接點材料122上位元線126的導電層130可與隔離區104上位元線126的導電層130大抵齊平。 As mentioned above, by enlarging the seam 124 of the bit line contact material 122 and filling the barrier layer 128 of the bit line 126 into the enlarged seam 124, the resistance can be reduced. By controlling the process parameters for etching the bit line contact material 122 , the conductive layer 130 of the bit line 126 on the bit line contact material 122 can be substantially flush with the conductive layer 130 of the bit line 126 on the isolation region 104 .

綜上所述，藉由蝕刻製程擴大位元線接點的接縫，再於接縫中填入位元線的阻障層，可降低位元線接點電阻。此外，較短的位元線接點以及較低的位元線位置均可降低寄生電容。 To sum up, by enlarging the seam of the bit line contact through the etching process, and then filling the bit line barrier layer in the seam, the resistance of the bit line contact can be reduced. In addition, shorter bit line contacts and lower bit line locations reduce parasitic capacitance.

102:基板 102: Substrate

104:隔離區 104: Quarantine

105:蓋層 105: cover layer

106:主動區 106: active area

107:襯層 107: lining

108:字元線 108: character line

114:頂層 114: top floor

116:半導體材料層 116: semiconductor material layer

118:硬罩幕層 118: hard mask layer

122:位元線接點 122: bit line contact

126:位元線材料 126: bit line material

128:阻障層 128: barrier layer

128e:延伸部分 128e: extension

130:導電層 130: conductive layer

1-1:線 1-1: line

Claims (12)

一種半導體記憶體結構，包括：一隔離區，包圍一主動區，位於一基板中；兩字元線，位於該主動區之中；一位元線接點，位於兩字元線之間；一第一位元線，位於該位元線接點之上；其中該位元線接點包括多晶矽，並具有一下凹的頂表面。 A semiconductor memory structure, comprising: an isolation area, surrounding an active area, located in a substrate; two word lines, located in the active area; a bit line contact, located between the two word lines; The first bit line is located on the bit line contact; wherein the bit line contact includes polysilicon and has a concave top surface. 如請求項1之半導體記憶體結構，更包括：一第二位元線，位於該第一位元線旁的該隔離區上；其中該第一位元線的一頂表面低於該第二位元線的一頂表面。 The semiconductor memory structure according to claim 1, further comprising: a second bit line located on the isolation region next to the first bit line; wherein a top surface of the first bit line is lower than the second bit line A top surface of the bit line. 如請求項2之半導體記憶體結構，其中該第一位元線及該第二位元線分別包括一阻障層及一導電層，其中該第一位元線的該阻障層比該第二位元線的該阻障層厚。 The semiconductor memory structure according to claim 2, wherein the first bit line and the second bit line respectively include a barrier layer and a conductive layer, wherein the barrier layer of the first bit line is smaller than the second bit line The barrier layer of the bit line is thick. 如請求項3之半導體記憶體結構，其中該第二位元線的該導電層的一底表面與該第一位元線的該導電層的一底表面大抵齊平。 The semiconductor memory structure according to claim 3, wherein a bottom surface of the conductive layer of the second bit line is substantially flush with a bottom surface of the conductive layer of the first bit line. 如請求項1之半導體記憶體結構，其中該第一位元線包括一第一阻障層，其中該第一阻障層具有一延伸部分延伸於該位元線接點之中，其中該延伸部分比該位元線接點窄。 The semiconductor memory structure according to claim 1, wherein the first bit line comprises a first barrier layer, wherein the first barrier layer has an extension extending in the bit line contact, wherein the extension Partially narrower than the bit line junction. 如請求項5之半導體記憶體結構，其中該延伸部分的一上表面比該延伸部分的一下表面寬。 The semiconductor memory structure according to claim 5, wherein an upper surface of the extension portion is wider than a lower surface of the extension portion. 如請求項2之半導體記憶體結構，更包括： 一電容接點，位於該第一位元線及該第二位元線之間；一電容，位於該電容接點之上；以及一隔離結構，位於該位元線接點及該電容接點之間；其中該隔離結構的一底表面低於該位元線接點的一底表面。 Such as the semiconductor memory structure of claim 2, further including: a capacitor contact located between the first bit line and the second bit line; a capacitor located above the capacitor contact; and an isolation structure located between the bit line contact and the capacitor contact between; wherein a bottom surface of the isolation structure is lower than a bottom surface of the bit line contact. 一種半導體記憶體結構的形成方法，包括：形成一隔離結構包圍一主動區於一基板之中；形成兩字元線於該主動區之中；形成一開口於兩字元線之間；沉積一多晶矽層具有一接縫於該開口之中；蝕刻該多晶矽層以擴大該接縫；以及沉積一位元線材料於該接縫之中。 A method for forming a semiconductor memory structure, comprising: forming an isolation structure to surround an active area in a substrate; forming two word lines in the active area; forming an opening between the two word lines; depositing a The polysilicon layer has a seam in the opening; etching the polysilicon layer to enlarge the seam; and depositing a bit line material in the seam. 如請求項8之半導體記憶體結構的形成方法，其中在蝕刻該多晶矽層之後，該多晶矽層具有一彎曲且下凹的頂表面。 The method for forming a semiconductor memory structure according to claim 8, wherein after etching the polysilicon layer, the polysilicon layer has a curved and concave top surface. 如請求項8之半導體記憶體結構的形成方法，更包括：沉積一第一硬罩幕層於該基板之上；形成該開口於該第一硬罩幕層之中；順應性地沉積該多晶矽層於該開口之中及該第一硬罩幕層之上；以及在擴大該接縫之後，移除該第一硬罩幕層；其中在蝕刻該多晶矽層之後，露出該第一硬罩幕層的一上表面 及一側壁。 The method for forming a semiconductor memory structure according to claim 8, further comprising: depositing a first hard mask layer on the substrate; forming the opening in the first hard mask layer; conformally depositing the polysilicon layer within the opening and over the first hard mask layer; and after enlarging the seam, removing the first hard mask layer; wherein after etching the polysilicon layer, exposing the first hard mask layer upper surface of layer and one side wall. 如請求項8之半導體記憶體結構的形成方法，更包括：沉積一隔離層於該主動區上；沉積一半導體材料層於該隔離層上；在擴大該接縫之後，該多晶矽層的一最高點與該半導體材料層的一頂表面大抵上齊平。 The method for forming a semiconductor memory structure as claimed in claim 8 further includes: depositing an isolation layer on the active region; depositing a semiconductor material layer on the isolation layer; after expanding the joint, a highest layer of the polysilicon layer The dots are substantially flush with a top surface of the layer of semiconductor material. 如請求項8之半導體記憶體結構的形成方法，其中在蝕刻該多晶矽層之後，該接縫兩側的該多晶矽層具有平坦的一上表面。 The method for forming a semiconductor memory structure according to claim 8, wherein after etching the polysilicon layer, the polysilicon layer on both sides of the seam has a flat upper surface.
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