TWI795855B - Gate drive interposer with integrated passives for wide band gap semiconductor devices - Google Patents

Gate drive interposer with integrated passives for wide band gap semiconductor devices Download PDF

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TWI795855B
TWI795855B TW110127397A TW110127397A TWI795855B TW I795855 B TWI795855 B TW I795855B TW 110127397 A TW110127397 A TW 110127397A TW 110127397 A TW110127397 A TW 110127397A TW I795855 B TWI795855 B TW I795855B
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wide bandgap
gate drive
interposer
semiconductor devices
integrated passive
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TW202145580A (en
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愛倫 坦伯頓
強 包樂特圖德
朗尼G. 強斯
菲力普M. 雷思納
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美商凱門特電子股份有限公司
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本發明提供一種改良的電子組件。該電子組件包括具有多層的陶瓷中介器。該多層的主動層形成一嵌入式電容器，該嵌入式電容器包括數個並聯電極且在相鄰電極之間具有一電介質，其中該相鄰電極具有相反的極性。一寬帶隙裝置也在該多層陶瓷中介器上。The present invention provides an improved electronic assembly. The electronic assembly includes a ceramic interposer having multiple layers. The multi-layer active layer forms an embedded capacitor comprising parallel electrodes with a dielectric between adjacent electrodes, wherein the adjacent electrodes have opposite polarities. A wide bandgap device is also on the multilayer ceramic interposer.

Description

用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器Gate drive interposer with integrated passive components for wide bandgap semiconductor devices

[0001]   本發明是2019年8月5日提交的美國專利申請案第16/531,255號的部分繼續申請案，而該美國專利申請案係請求於2019年2月21日提交的美國臨時申請案第第62/808,493號的優先權。 [0002]   本發明涉及一種改良的柵極驅動中介器。更具體地，本發明涉及一種具有積體式被動組件的改良的柵極驅動中介器，該積體被動組件特別適合與寬帶隙半導體裝置一起使用。[0001] The present invention is a continuation-in-part of U.S. Patent Application No. 16/531,255 filed on August 5, 2019, which is a U.S. provisional application filed on February 21, 2019 Priority of No. 62/808,493. [0002] The present invention relates to an improved gate drive intermediary. More specifically, the present invention relates to an improved gate drive interposer having an integrated passive component particularly suited for use with wide bandgap semiconductor devices.

[0003]   縮小電子元件的尺寸是一項持續的需求。在本領域中被稱為小型化的努力係以兩種主要方式體現。其中，一主要重點是組件的階層，藉由不斷地詳細檢視每個組件在結構或功能上的不足，以期能在更小的體積內實現更高階的功能。另一個主要重點是模組或電子設備的階層，如何將電子組件組裝在一起以形成功能模組或功能裝置。本發明具體地涉及模組的小型化，特別是功率模組，並且更具體地涉及特別適合用於優選地具有約2至約4eV帶隙的寬帶隙半導體裝置中的功率模組。 [0004]   寬帶隙(WBG)半導體裝置為功率電子元件的設計人員提供了更高的開關頻率和更高的功率密度。隔離的柵極驅動器係位於控制電路和WBG器件之間，並提供必要的電壓和電流，以實現最佳性能。由於受限於本領域中通常被稱為等效串聯電感或ESL以及等效串聯電阻或ESR的寄生電感和電阻，因此在某種程度上限制了改良。 [0005]   WBG裝置廣泛用於諸如發光二極體、雷射、例如雷達的某些射頻應用、大型工業電動機、大型高效數據中心等設備，適用於例如風能和太陽能系統、運輸系統、衛星通訊和其他應用所使用的直流能量產生系統中的逆變器。WBG裝置可以在更高的開關頻率、更高的電壓和更高的溫度下工作，從而有助於在更小的裝置中進行更高效的能量轉換。將低損耗電容器整合在這些裝置和系統的操作條件下，具有持續的需求。 [0006]   諸如基於SiC和GaN的寬帶隙半導體可在更高的開關頻率和更高的電壓下工作。在較高的開關頻率下，所需的電容較小，因此減小了電容器佔用的空間。例如，在一給定頻率下以Hz為單位的DC鏈路電容器為例所需的電容量可以使用公式1計算：

Figure 02_image001
Figure 02_image002
公式1 其中: C =電容量(F); Pload =功率(W); Uripple =漣波電壓(V); Umax =最大電壓(V);和 f =開關頻率(Hz) [0007]   使用公式1，可以估計給定功率負載所需的電容量，如圖1和2所示。圖1和2顯示，增加電壓進一步減小了所需的電容量，但是隨著功率負載的增加，需要更高的電容量。增大開關頻率也會減小緩衝電容器所需的電容量。為了減小尺寸，需要較低的電容值，但是在較高的頻率下，電磁干擾(EMI)成為一個問題。 [0008]   如圖1和2所示，在低頻下，高功率和較低電壓須要很大的DC鏈路電容器。在20kHz的開關頻率下，例如典型的Si基半導體，所需的大電容量係由薄膜和電解電容器供給。然而，採用基於SiC和GaN的寬帶隙半導體裝置，因為它們支持高轉換效率和更小的尺寸，故可以在更高的頻率和電壓切換。 [0009]   低溫共燒陶瓷(LTCC)已用於將半導體與其他被動組件一起封裝。但是，所用的玻璃陶瓷材料的介電常數小於10，並且主要用於高頻和低壓能量轉換以及控制電子裝置。低介電常數的結果是只能得到原有的低電容，並且必須通過表面黏著將低壓獨立電容器的更高電容值併入這些封裝中。 [0010]   本文提供一種功率模組，該功率模組適用於高電壓和高開關頻率。此外，本文提供了用於高壓和高開關頻率的功率模組，其允許功率模組的進一步小型化，並且特別適合與寬帶隙器件一起使用。[0003] There is an ongoing need to reduce the size of electronic components. The effort known in the art as miniaturization manifests itself in two main ways. Among them, one of the main points is the hierarchy of components. By continuously examining the structural or functional deficiencies of each component in detail, it is expected to achieve higher-level functions in a smaller volume. Another major focus is the hierarchy of modules or electronics, how electronic components are assembled together to form functional modules or functional devices. The present invention relates in particular to the miniaturization of modules, especially power modules, and more particularly to power modules which are particularly suitable for use in wide bandgap semiconductor devices preferably having a bandgap of about 2 to about 4 eV. [0004] Wide bandgap (WBG) semiconductor devices provide designers of power electronics with higher switching frequencies and higher power densities. An isolated gate driver sits between the control circuitry and the WBG device and provides the necessary voltage and current for optimum performance. Improvements are somewhat limited by parasitic inductance and resistance, commonly referred to in the art as equivalent series inductance or ESL and equivalent series resistance or ESR. [0005] WBG devices are widely used in equipment such as light-emitting diodes, lasers, certain radio frequency applications such as radar, large industrial electric motors, large high-efficiency data centers, etc., suitable for applications such as wind and solar systems, transportation systems, satellite communications Inverters in DC energy generation systems used in DC and other applications. WBG devices can operate at higher switching frequencies, higher voltages, and higher temperatures, facilitating more efficient energy conversion in smaller devices. There is a continuing need to integrate low loss capacitors under the operating conditions of these devices and systems. [0006] Wide bandgap semiconductors such as those based on SiC and GaN can operate at higher switching frequencies and higher voltages. At higher switching frequencies, less capacitance is required, thus reducing the space occupied by the capacitors. For example, the required capacitance of a DC link capacitor in Hz at a given frequency can be calculated using Equation 1:
Figure 02_image001
Figure 02_image002
Equation 1 where: C = capacitance (F); P load = power (W); U ripple = ripple voltage (V); U max = maximum voltage (V); and f = switching frequency (Hz) [0007] Using Equation 1, the capacitance required for a given power load can be estimated, as shown in Figures 1 and 2. Figures 1 and 2 show that increasing the voltage further reduces the required capacitance, but as the power load increases, higher capacitance is required. Increasing the switching frequency also reduces the capacitance required for the snubber capacitor. To reduce size, lower capacitance values are required, but at higher frequencies, electromagnetic interference (EMI) becomes an issue. [0008] As shown in Figures 1 and 2, at low frequencies, high power and lower voltages require large DC link capacitors. At a switching frequency of 20kHz, such as typical Si-based semiconductors, the required large capacitance is supplied by film and electrolytic capacitors. However, wide bandgap semiconductor devices based on SiC and GaN are used, which can switch at higher frequencies and voltages because they support high conversion efficiency and smaller size. [0009] Low temperature co-fired ceramics (LTCCs) have been used to package semiconductors with other passive components. However, the glass-ceramic material used has a dielectric constant of less than 10 and is mainly used for high-frequency and low-voltage energy conversion and control electronics. A consequence of the low dielectric constant is that only inherently low capacitance is available, and the higher capacitance values of low-voltage stand-alone capacitors must be incorporated into these packages by surface mount. [0010] This paper provides a power module, which is suitable for high voltage and high switching frequency. Furthermore, this paper provides a power module for high voltage and high switching frequency, which allows further miniaturization of the power module and is particularly suitable for use with wide bandgap devices.

[0011]   本發明涉及一種改良的陶瓷中介器，其特別適合用作寬帶隙半導體裝置的柵極驅動中介器。 [0012]   本發明的特定特徵是減小了總體積，其滿足了電路設計中的持續需求。 [0013]   更具體地，本發明涉及層狀陶瓷中介器，該層狀陶瓷中介器的主動層包括極***替的平行電極與相鄰電極之間的電介質。 [0014]   除了併入DC鏈路電容器之外，本發明還允許將其他類型的電容器併入中介器中，以進行去耦、濾波、計時和緩衝。本發明還允許將其他功能結合在中介器的一部分中，並允許散熱。這些優點將在下面的說明中予以描述。 [0015]   如將瞭解的，這些和其他實施例被提供在包括陶瓷中介器的電子組件中，該陶瓷中介器包括多層。多層的主動層形成嵌入式電容器，該嵌入式電容器包括具有在相鄰電極之間具有電介質的平行電極，其中，相鄰電極具有相反的極性。寬帶隙裝置也在多層陶瓷中介器上。 [0016]   在電子組件中所提供的又一個實施例包括具有多層的陶瓷中介器。多層的主動層形成一嵌入式電容器，該電容器包括具有在相鄰電極之間具有電介質的平行電極，其中，相鄰電極具有相反的極性，並且其中該電介質是相對介電常數在10以上且在300以下的順電陶瓷電介質。寬帶隙裝置也在多層陶瓷中介器上。[0011] The present invention relates to an improved ceramic interposer, which is particularly suitable for use as a gate drive interposer for wide bandgap semiconductor devices. [0012] A particular feature of the present invention is the reduced overall volume, which meets a continuing need in circuit design. [0013] More specifically, the present invention relates to layered ceramic interposers whose active layers include parallel electrodes of alternating polarity and a dielectric between adjacent electrodes. [0014] In addition to incorporating DC link capacitors, the present invention also allows other types of capacitors to be incorporated into the interposer for decoupling, filtering, timing and buffering. The invention also allows for the incorporation of other functions in a part of the interposer and allows for heat dissipation. These advantages will be described in the description below. [0015] As will be appreciated, these and other embodiments are provided in an electronic assembly including a ceramic interposer comprising multiple layers. The multilayer active layer forms an embedded capacitor comprising parallel electrodes with a dielectric between adjacent electrodes, wherein the adjacent electrodes have opposite polarities. Wide bandgap devices are also on multilayer ceramic interposers. [0016] Yet another embodiment provided in an electronic assembly includes a ceramic interposer having multiple layers. The multilayer active layer forms an embedded capacitor comprising parallel electrodes with a dielectric between adjacent electrodes, wherein the adjacent electrodes have opposite polarities, and wherein the dielectric has a relative permittivity above 10 and in Paraelectric ceramic dielectric below 300. Wide bandgap devices are also on multilayer ceramic interposers.

[0018]   本發明涉及一種改良的功率模組，更具體地係涉及一種特別適用於寬帶隙裝置的功率模組，其中該功率模組包括具有嵌入式或積體式電容的中介器。更具體地，本發明涉及使用嵌入式多層陶瓷電容器結構的高功率電子設備的改良封裝，以有效地將嵌入在模組或微處理器的中介器內或積體在其內的電容積體在一起，而不是作為分開安裝的組件。 [0019]   在本發明的實施例中，特別是隨著開關頻率的增加，提供了低寄生ESR和ESL去耦合電容器，以減輕瞬態電流並改善柵極驅動器的性能。在特定實施例中，諸如零電壓開關(ZVS)、高壓緩衝電容器之類的軟式開關跨接在WBG開關裝置之間，使WBG開關到緩衝電容器的感應環路面積最小化，從而隨著開關頻率的增加而改善了緩衝性能。 [0020]   如本文所述，具有積體的去耦合電容器和緩衝電容器的WBG開關中介器的柵極驅動器使電路佈局的有害寄生效應最小化，並且通過將裝置封裝在一起而增加了功率密度。封裝還縮小了互相連接的體積。 [0021]   本發明的中介器提供了能夠將柵極驅動器輸入與柵極驅動器輸出隔離的高壓陶瓷層。積體的輸入濾波器可提高抗電雜訊性能，並最大程度地減少輸入控制信號品質引起的驅動器振鈴。一計時電容器較佳地整合以控制WBG切換之間的截止時間。 [0022]   典型驅動器去耦合電容器(D-Caps)、開關緩衝電容器電感迴路面積和功率封裝體積所形成的寄生電感ESL和電阻ESR相關的問題，通常是使用一包括積體電容器的中介器將柵極驅動器連接至一WBG開關裝置來緩解。 [0023]   現有技術中的一個特殊問題是當超過臨限電壓的振鈴時會有意外開啟的風險。本發明的中介器減小了柵極驅動器和開關的輸入柵極之間的距離。距離的減小可降低振鈴的趨勢。中介器的積體輸入濾波電容器可減少由於輸入信號質量而引起的振鈴，從而提高了抗雜訊能力。最好提供一個可控制WBG切換之間的截止時間的積體計時電容器。 [0024]   本發明的中介器的另一個優點是減輕了驅動器的控制輸入與WBG裝置的輸出之間以及柵極驅動器的輸出通道之間的電隔離問題。中介器在中介器內提供高壓電絕緣區域。 [0025]   本發明的中介層的積體電容器可以結合屏蔽電極和間隙以提供進一步的電隔離。可以將緩衝整合到中介器中，以利用寬帶隙裝置減少電感環路，從而幫助實現零電壓開關(ZVS)。另一個優點是可以將熱緩衝整合至中介層內。 [0026]   以下將參照本文所揭露的積體組件的附圖對本發明作一說明，但不限於此。在各個附圖中，相似的元件將以相應的編號予以標示。 [0027]   以下將參閱圖3對本發明的一實施例予以描述，其係以方塊圖的型式顯示一陶瓷中介器的輸入、絕緣體、輸出和緩衝器。在圖3中，中介器300與一柵極驅動器302電連通。柵極驅動器在輸入和輸出之間需要電隔離。在至少一個積體緩衝電容器306之間具有一電隔離區304。該電隔離區304還可以包括熱緩衝區316。一輸入濾波電阻器308電連通於至少一個積體功能區310，優選地包括積體的輸入濾波和至少一個去耦合電容器。一積體輸出區域312電連通於一柵極驅動電流控制電阻器314，其中該積體輸出區域包括至少一個輸出去耦合電容器。 [0028]   以下將參閱圖4對本發明的一實施例予以描述，其係以電路示意圖型式顯示一中介器和WBG開關。大部分電性功能是使用分立的表面黏著電容器的市售隔離式雙通道柵極驅動器，例如可使用德州儀器公司的的商用驅動器UCC21530-Q1作為示例，但不限於此。圖4表示的電路圖對於本領域技術人員而言是已知的，因此，除了本文所提到的電路設計的變化之外，沒有必要進一步闡述。 [0029]   圖4中示意地顯示了一中介器輸入電路320。中介器輸入電路包括多個濾波電容器322，其可以相同或不同，用以提供濾除本領域中已知不想要的頻率。在一個特別優選的實施例中，至少一個濾波電容器，並且更優選地所有濾波電容器，係被內嵌到中介器中且係使用如同以下說明中進一步描述的順電介質電容器(PDC)。特別優選的是，去耦合電容器被嵌入在中介器中。在一個特別優選的實施例中，中介器輸入電路中的任何去耦合電容器都是使用PDC。中介器輸入電路中至少有一個去耦合電容器324。如本領域中已知的，通常與一電阻器並聯的一計時電容器336共同控制WBG切換間的截止時間。在優選實施例中，計時電容器是PDC，其優選地嵌入在中介器中。 [0030]   在圖4中，示意性地顯示一中介器輸出電路338。該中介器輸出電路包括至少一個去耦合電容器324。在特別優選的實施例中，中介器輸出電路中的任何去耦合電容器是使用PDC，並且優選地，去耦合電容器被嵌入在中介器中。優選地，在中介器輸出電路中提供至少一個去耦合電容器324、至少一個DC鏈路電容器325，以使電路的一部分與另一部分去耦合，如同本領域中已知者。 [0031]   在圖4中，WBG開關340具有與WBG開關電並聯的緩衝電容器342。緩衝電容器優選地係嵌入在中介器中，該中介器為電路提供了顯著減小的電流路徑長度，從而減小了電路的體積，因此減小了電感。緩衝電容器優選是PDC電容器。 [0032]   以下將參閱圖1和2描述本發明的優點。參照圖5和6，其中圖5示意地顯示電子組件佈設在電路板上的傳統市售柵極驅動印刷電路板(PCB)。圖6示意地顯示本發明實施例中作為柵極驅動器的陶瓷中介器的電子組件的佈局。為了清楚起見，並未顯示其佈線。在圖5中，驅動器400係以本領域常見技術被表面黏著到電路板401的陶瓷中介器。電阻器404、二極體406、寬帶隙裝置408和緩衝電容器410通常被表面黏著在公同側，以使電流路徑長度最小化。解耦合電容器和濾波電容器係共同地以標號412予以表示，且安裝在與驅動器400相對的表面上，並通過通孔414進行電連接。 [0033]   在圖6中，優選地將驅動器400、電阻器404、二極體406和寬帶隙裝置408安裝在電路板403上的陶瓷中介器420的公同面上，並將去耦合電容器、濾波電容器和緩衝電容器嵌入到陶瓷中介器中作為主動層，因此在佈局中看不到這些組件。 [0034]   相對於可商購的柵極驅動器，本發明的中介器的優點是可減少寄生電感，該寄生電感是由現有技術中不理想的電路板佈局和較長的封裝引線的組件所引入的。電流路徑長度的減小使得電容器得以進行更好的優化，最好包括使用PDC電容器，這可以降低在高dI/dt和dv/dt切換期間功率電晶體的柵極-源極驅動電壓的電子振鈴。通過減少電子振鈴，可以減少超過臨限電壓的振鈴狀況，以及減少意外接通甚至擊穿的風險。在現有技術的裝置中，通常通過在柵極驅動器上施加負偏壓來減輕振鈴，但本發明的中介器是不必要的，如此消除了負偏壓或反向偏壓的電源，從而有助於進一步的小型化。 [0035]   本發明陶瓷中介器的一個特別優點是將用於橫向散熱的熱緩衝器316予以積體化。雖然適用於現有技術的設備，但是受到空間限制，通常不希望採用熱緩衝技術。本發明的中介器，可以將由於具有較小封裝尺寸而騰出的區域重新作為散熱或其他組件的空間，而不會增加整體尺寸，也不會超出現有技術裝置所佔據的尺寸。 [0036]   在一特別優選的實施例中，提供一包括嵌入式電容器的改良功率模組封裝，其中該嵌入式電容器優選地包括在本文中稱為順電介質電容器(PDC)的順電介質。PDC的使用可以使電源模組進一步小型化，並可以操作於更高的電壓和更高的頻率。將PDC嵌入到基板中可以使該基板的體積在不犧牲電路面積和不需要安裝組件的情況下提供嵌入式電容。此外，組成功率模組的電路傳導路徑被顯著最小化，這改善了ESR和ESL，從而改善了模組的電性功能。為便於小型化，電容器須可以在更高的電壓和頻率下工作，儘管電容器的界面溫度可能高達250℃，但它們仍可以封裝在靠近寬帶隙(WBG)半導體的位置。 [0037]   以下將參閱圖7對本發明的實施例予以說明。在圖7中以隔離視圖顯示了模組的一部分。順電介質電容器(PDC)係以標號10予以表示。PDC包括平行的平面內部電極14，相鄰電極之間具有相反的極性。在相鄰電極之間是順電介質12。內部電極形成電容耦合，而平行的平面內部電極和順電介質共同形成主動層。電容耦合外部端子16與交替的內部電極14電接觸，從而提供電容耦合的電性連接至PDC界面焊墊18或等效的電連接，如此使其得以電連接到以下將進一步說明的模組的至少一個組件24。連接到界面焊墊的方式並不受特別限制，優選地可以通過焊球、焊柱或引線焊接來連接。 [0038]   以下將參閱圖8對本發明的實施例予以說明。在圖8中以局部示意圖顯示模組20。該模組包括至少一個電容性耦合，並且優選地將PDC10嵌入到陶瓷中介器的結構基板22，可選地並且優選地，至少一PDC10的內部電極被封裝在順電介質12中。安裝到結構基板、結構基板上或結構基板中的數個組件24係彼此電連接及/或連接到PDC，以提供模組所須的電功能，該模組在本文中也稱為中介器。一電源28可提供電源至模組，而控制器26可調節供應至一受電設備30的電源。圖8中未示出PDC與多個組件之間的電路佈線，因為各組件之間的連接對於如何組成一模組在本領域中是已知的，並且不限於此。 [0039]   PDC10、結構基板22和組件24可以組合在一起形成一微處理器，微處理器可選地位於模組20內。嵌入在微處理器中的PDC特別適合使用在例如低於200伏特的較低電壓。 [0040]   以下將參閱圖9-12對PDC作一說明，其示意性地顯示包括順電介質的多層式陶瓷電容器。在圖9中，為了便於討論，一對內部電極100係以標號A和B予以標示。實際上，內部電極優選是相同的。每個內部電極具有一個電容區域102和數個接線凸耳104。內部電極與相鄰電極之間的順電介質堆疊在一起，而內部電極A和B交替排列，以使電容區域對準並交替接線凸耳，例如各個內部電極A係對準而形成堆疊內部電極。在圖10的俯視示意圖中顯示該堆疊，其中相鄰的接線凸耳具有交替的極性。整個組件優選地封裝在陶瓷中，優選地在順電介質中。在圖11所示的實施例中，外部端子106係與共同極性的對準接線凸耳電接觸。在使用時，外部端子是作為電容耦合端子，隨後與PDC界面焊墊電接觸。外部端子優選地包括選自銅、鎳、鎢、銀、鈀、鉑、金或其組合的至少一種材料。 [0041]   在圖12所示的實施例中，具有共同極性的對準接線凸耳堆疊後，形成穿過該堆疊的通孔108。通孔用作電容耦合端子，其隨後優選地通過優選在PDC表面上的外部端子與PDC界面焊墊電接觸。通孔提供了一低熱阻路徑，以去除模組中多餘的熱量。在使用具有鎳內部電極的鋯酸鈣基的電介質的優選情況下，以銅填充通孔為佳。在接線凸耳和通孔上露出的銅表面可以鍍鎳，銀、錫、金、鈀或其組合。通孔可以藉由使用於結構中的介電帶的孔隙來形成，或在生坯或燒結體中機加工而形成。本領域技術人員還將瞭解，當不接觸內部電極時，它們可以用於純機構附件。此外，可以通過具有可選過鍍層的網版印刷銅來形成組件表面上的佈線，以提供焊墊和電觸區，以將其他組件封裝在模組內以及與半導體接觸。 [0042]   以下將參閱圖13說明本發明的實施例，為便於討論目的和描述清楚，在示意圖中顯示三相功率模組。在圖13中，第一組件由交流電源200表示。第二組件由電磁干擾或射頻干擾濾波器EMI/RFI 202表示，其可以表面黏著整合至交流電源或該EMI/RFI可以內嵌於陶瓷中介器的結構基板22中，如圖所示，電容耦合端子161 -163 終止於PDC界面焊墊181 -183 。代表性的EMI/RFI濾波器在圖14中被示意性地標示為A。在一實施例中，該EMI/RFI濾波器的至少電容器是如本文所述的嵌入式PDC。以AC諧波濾波器204標示的第三組件優選地通過內部電極2011 -2013 接收EMI/RFI濾波過的電能。在圖14中以標號B示意性地表示代表性的AC諧波濾波器。在一個實施例中，AC諧波濾波器的電容器和電感器是如本文所述的嵌入式PDC。以AC/DC轉換器206標示的第四組件可以用於將AC信號轉換為DC信號。AC/DC轉換器可以通過電容耦合端子164 -166 電連接到AC諧波濾波器，該端子耦合於PDC界面焊墊184 -186 ，從而使導電路徑長度最小。在AC/DC轉換器和標示為DC/AC逆變器214的第五組件之間，設有緩衝器208、212以及一DC鏈路電容器210的嵌入式組件。在圖14中示意性地顯示以標號C標示的代表性緩衝器，以及在圖14中以標號D標示的代表性DC鏈路電容器。緩衝器的電容器優選地係通過電容耦合端子167 -1610 與PDC界面焊墊187 -1810 電連通的嵌入式PDC。DC鏈路電容器優選地是嵌入式PDC，並且優選地通過內部電極2013 -2016 與每個緩衝器電連接。內部電極的使用改善了法拉第屏蔽，從而將模組發出的EMI雜訊降至最低。 [0043]   在某些電路設計中，具有最低等效串聯電感(ESL)和/或最低等效串聯電阻(ESR)以獲得最佳性能是有利的。結構中包含多個極性相反的電容器，可將ESL降至最低。如從圖15中將瞭解到，如同以上對於圖9至圖10的說明，交替地將層A和層B堆疊，以可將兩個電容性耦合在一共同結構中，其中相鄰的外部端子具有相反的極性，如此可將ESL降至最低。 [0044]   為了防止電路振鈴，有時期望增加電容器的ESR。通過增加PDC內部電極中的路徑長度，可以增加PDC中ESR。從圖16中可以瞭解到，使用如同由交替的層A-1和B-1之間設有電介質的PDC內的矩形內部電極，可達到更大的重疊面積。如圖16中從左到右所示，隨著路徑長度而寬度變小，可使ESR增大。通過組合電容器的數量和電極形狀，可以優化ESL和/或ESR。 [0045]   使用這些技術，可以優化包含PDC的模組或中介器的性能。 [0046]   低電感是有益的，因為在WBG半導體應用中，較高的切換電流波沿速率dI/dt和較高的切換頻率會產生較大的電壓振鈴驅動電感性負載。緩衝電容器鄰近位於開關封裝有助於減少這種振鈴。將緩衝器積體化在基板中可以進一步減小從緩衝器到開關裝置的總環路電感，從而最大程度地發揮了緩衝器的優勢。 [0047]   嵌入式PDC與其他組件一起可以使模組或電子封裝適用於許多應用。圖17示意性地顯示一飛馳電容器電路。圖18示意性地顯示零電壓開關(ZVS)金屬氧化物半導體場效應電晶體(MOSFET)電路。圖19示意性地顯示MOSFET的H橋式電路。圖20示意性地顯示積體式整流電容器。 [0048]   在圖17中所示具有2個開關單元的示例中，多階飛馳電容器反相器整流環路電感是一個限制因素。在開關附近增加一個額外的積體式整流電容器可改善整流性能。如圖18所示的軟式開關中，當負載電流改變方向而使零電壓開關(ZVS)致動時，緩衝器可以用來提供充電和放電電流。 [0049]   在圖19及圖20所示的4個開關電路中，在開關鄰近處增加電容可改善例如直流鏈路或位在稍離開該開關裝置位置的飛馳電容器的高平滑電容器的性能。 [0050]   以下將參閱圖24對本發明的實施例予以描述。在圖24中，一模組218可以是陶瓷中介器的組件，其上具有至少一個散熱層20接觸於至少一半導體19。該散熱層有助於從模組橫向散熱。至少一個優選為PDC10的電容器與半導體電接觸，優選地，與半導體和PDC之間的散熱層電接觸。PDC可以通過散熱層通過絕緣的通孔222電連接到半導體，其中絕緣通孔具有導電芯226和絕緣體224，該絕緣體224將導電芯與延伸穿過散熱層的通孔中的散熱層予以電隔離。 [0051]   採用具有通孔的PDC(尤其是貫通孔)可以提供分開封裝的替代方法。使用現有技術中眾所周知的技術，例如焊球黏著，將得到的數個電容器PDC封裝到微處理器中，以形成積體式微處理器-電容器組件。可以考慮將其他類型的組件包裝為PDC的一部分，這些組件包括ESD抑制器、電感器和其他組件。 [0052]   由諸如Al2 O3 、BeO、AlN、Si3 N4 的氧化物形成的具有各種金屬化的典型高功率基底可以用作散熱層。例如，AlN和BeO因其高導熱性而受到重視。例如，AlN具有140-200W/m-K的導熱率。但是，BeO有毒，而AlN的銅金屬化可靠性存在問題。由於這些原因，具有35-60 W/m-K的熱導率且具有硬焊Al的Si3 N4 適合作為本發明的示範例。為了改善z方向上的PDC熱傳導性，優選較高熱導率的材料。PDC可以在主動內部電極的最後一層上併入覆蓋層，該覆蓋層包括比PDC電介質更高的導熱率材料。本領域技術人員將瞭解到，這可以通過使用絕緣黏結層或更實際地在製造過程中與PDC一起焙燒包含高導熱率電介質的覆蓋層來實現。在基於CaZrO3 的電介質中，由於對氧氣的親和力高，因此可以與空氣敏感材料(如AlN，Si3 N4 )結合使用。在燒結貧金屬電極和非氧化物陶瓷所需的還原氣氛中，在燒製過程中氧不會損失。其他氧化物陶瓷會失去氧氣，因此產生的空位隨後會在電場下遷移，從而損害了可靠性。鋯酸鈣的這種行為使得與非氧化物基底材料的組合成為可行。當考慮熱膨脹係數(CTE)時，有效地將CaZrO3 與這些非氧化物基底材料結合的能力也很重要。這是由於最小化CTE與可靠性的提高不匹配很重要。鋯酸鈣的CTE為8.4 PPM/℃，接近商業化的以Al2 O3 和BeO為基礎的基底的8-10 PPM/℃。但是，諸如AlN和Si3 N4 等非氧化物基底材料的CTE較低，為3.3-5.6 PPM/℃，因此將這些材料與CaZrO3 有效結合可以解決這種不匹配問題。 [0053]   用於散熱層的特別優選材料是介電常數比PDC的介電常數低的電介質。包括介電常數比PDC的陶瓷低的介電常數的散熱層在高頻性能方面具有特別的優勢。 [0054]   在另一實施例中，與PDC的內部自熱有關的問題，可以藉由加入至少一個穿過PDC主體的散熱通道(優選地是連續的)來予以緩解，如此可使PDC的核心溫度通過熱傳導介質來降低。儘管在高功率應用中，PDC的內部電極可以更有效地將熱量通過電極表面散發到端子，但仍需要更有效地散熱。導熱介質可以是流量有限的靜態，也可以是流入並通過散熱通道以促使熱能可以由MLCC內部傳送出。 [0055]   以下將參閱圖25、26描述本發明的實施例，其中在圖25的側視斷面圖和在圖26的端視斷面圖中所顯示的一PDC係以標號110予以標示。在圖25和26中，PDC包括交錯的平行內部電極112和114以及電介質116，該電介質116位於內部電極和相反極性的外部端子118、120之間。平行於內部電極的散熱通道122優選地穿過電容器本體的至少一個表面，並且更優選地提供具有穿過電容器本體的連續通道。散熱通道或散熱口的端部優選地位於電容器本體表面上沒有外部端子的位置，從而允許進出該通道的散熱口124以使導熱介質進入散熱通道的一散熱口並優選地由另一散熱口離開散熱通道。可以提供橫跨散熱通道高度的可選支柱126，以改善結構整體性或提供亂流以減少層流，從而增加電容器主體與導熱介質之間的導熱速率。支柱優選地不延伸電容器的整個寬度，例如從散熱口到散熱口。在圖25和圖26的實施例中，散熱通道在所有側面上都由陶瓷予以限定，散熱通道與內部電極112和114之間沒有接觸點。陶瓷不是有效的熱導體，因此，散熱通道在所有側面上都由陶瓷限定。陶瓷缺乏導熱效率。然而，陶瓷是不導電的，這允許更大範圍的導熱介質，因此該實施例在某些應用中是有利的。 [0056]   在替代實施例中，散熱通道在三個側面上由陶瓷限定，並且在至少一側上的一部分由內部電極限定。在另一個替代實施例中，散熱通道在兩側由陶瓷限定，並且在兩側的至少一部分上由內部電極限定，如在本文結合參照的美國專利第10，147，544號中所述。由至少一個內部電極限定的散熱通道的一特別優點是內部電極所提供的增強導熱，其在導熱方面通常比陶瓷更有效。如果導熱介質與內部電極接觸，則優選地，導熱介質是不導電且無腐蝕性的。 [0057]   以下將參照圖27描述本發明的實施例，其中以側視斷面圖顯示本發明的PDC係以標號110予以表示。在圖27中，PDC包括具有電絕緣屏障127的多個散熱通道122，其中散熱通道係佈置在多個公共散熱通道平面中，其中每個公共散熱通道平面係平行於內部電極。本領域技術人員將瞭解到，所描述的熱緩衝可以應用於中介器內的多個獨立電容器。 [0058]   以下將參閱圖28描述本發明的實施例，其係以斷面示意圖示出一PDC。在圖28中，外部端子118和120以及電介質116如上所述。顯示的屏蔽電極128和129係被定義為位於PDC中最外面具有相反極性的內部電極的共平面電極。屏蔽電極可防止從外部端子到極性相反的內部電極產生電弧。舉例來說，電極128和129'防止外部端子和最接近的相反極性的內部電極130和131之間的電弧。散熱通道122與相對的極性相反的共平面內部電極132和134呈共平面。在圖28所示的實施例中，如上所述，散熱通道在所有側面上都由陶瓷限定。 [0059]   以下將參閱圖29描述本發明的實施例，其係以斷面示意圖示出一PDC。圖29的PDC包括極性相反的共平面主動內部電極136和138與平行於該共平面主動內部電極的浮置電極140，並且優選地每個浮置電極的每一側相鄰處都有共平面主動內部電極。主動電極在本文中定義為與外部端子電接觸的內部電極。浮置電極是不與外部端子電接觸的內部電極。至少一個散熱通道122係共平面於該具有相反極性的共平面主動電極。 [0060]   以下將參閱圖30描述本發明的實施例，其係以斷面示意圖示出一PDC。圖30的PDC包括極性相反的共平面主動內部電極136和138與平行於該共平面主動內部電極的浮置電極140，並且優選地每個浮置電極的每一側相鄰處都有共平面主動內部電極。至少一個散熱通道122係共平面於該具有相反極性的共平面主動電極，並且可選地可流體接觸於該內部電極。 [0061]   以下將參閱圖31描述本發明的實施例，其係以斷面示意圖示出一PDC。圖31中，散熱通道122的內部塗覆一可選的塗層130，該塗層優選地是導熱塗層，從而增加了陶瓷與導熱介質128之間的熱傳導。該塗覆的材料並不特別受限於可塗覆在電介質並可提供電介質到導熱介質的足夠導熱功能的偏好材料。以下將參閱圖32描述本發明的實施例。圖32中，一PDC110具有散熱通道122，其並不平行於電極112、114且較佳地重直於該電極。藉由穿過電極的散熱通道，可以在傳熱介質和內部電極之間形成更高的接觸。在一實施例中，導熱介質是不導電的。在另一個實施例中，可以將導熱但電絕緣的塗層施加到散熱通道的內部。 [0062]   以下將參閱圖33描述本發明的實施例。圖33中，一模組218具有安裝在至少一個半導體19的PDC110，其中PDC包括至少一個貫通的散熱通道，其中散熱通道係平行於電極、垂直於電極或在電極之間呈一中間角度。冷卻裝置228可將通過散熱通道所收集的熱量予以散發。冷卻裝置可以是被動裝置，其藉由與諸如散熱器之類的介質(優選地是空氣)相互作用來散發熱量。替代地，冷卻裝置可以是主動裝置，其通過電、機械或化學方法例如通過絕熱膨脹、流動介質或通過帕爾帖(Peltier)技術來散熱。 [0063]   包含金屬、導熱陶瓷、聚合物及其組合的導熱無機或有機材料特別適用於本發明。有機矽導熱油脂由於其高導熱性、低耐熱性、成本、可加工性和可重複利用性而特別優選。作為本發明的非限制性實例，例如可使用Dow Corning®TC-5026，Dow Corning®TC-5022，Dow Corning®TC-5600，Dow Corning®TC-5121，Dow Corning® SE4490CV，Dow Corning®SC 102; Dow Corning®340散熱器；Shin-Etsu MicroSI®X23-7853W1，Shin-Etsu MicroSI®X23-7783 D，Shin-Etsu MicroSI®G751和Shin-Etsu MicroSI®X23-7762D特別適合用作散熱通道中的塗層。 [0064]   傳熱介質可以是靜態或流動的氣體或液體，以改善熱傳導。非導電的材料是特別優選的。全氟化烴，納米流體，礦物油和醚由於具有高效的導熱能力和最小的電導率而特別適合。作為非限制性實例，例如可使用Galden®HT55，Galden®HT70，Galden®HT80，Galden®HT110，Galden®HT135，Galden®HT170，Galden®HT200，Galden®HT230和Galden®HT270特別適合作為本發明的導熱介質。諸如空氣，至少部分乾燥的空氣或惰性氣體之類的氣體特別適合作為傳熱介質。 [0065]   可以在PDC的製造過程中，通過多種技術來形成散熱通道。陶瓷前體層可以用犧牲有機材料或碳以對應於散熱通道的預定圖案印刷。在PDC的烘烤和共燒期間，優選地通過蒸發除去犧牲有機材料或碳。可以在PDC的層壓之前去除陶瓷帶的區域，或者可以在烘烤和燒結之前或之後加工出散熱通道。 [0066]   如本領域中已知的，PDC是通過以適當的對準順序層疊陶瓷前體和導體前體而製備的。建立足夠數量的層後，將組件加熱以形成內部導體和燒結陶瓷的交替層，並在陶瓷層中形成散熱通道前驅體。 [0067]   在預備形成散熱通道的每一層中，印刷上與散熱通道相對應的預通道材料的圖案。燒結後，預通道材料汽化，留下印刷的預通道材料形狀的間隙。可以將非揮發性材料(優選為陶瓷)添加到預通道材料中，以在間隙中形成支撐體。 [0068]   該預通道材料可以以預定圖案施加、並且在對該層進行燒結時將散熱通道留為間隙的任何材料。特別優選的材料是不包括金屬的電極油墨。這種材料是優選的，因為它們容易獲得且對製造環境具有固有的適應性。另一種特別合適的材料是與陶瓷前體一起使用的黏合劑，不包括陶瓷前體。 [0069]   大面積的結構基底通常不具有電功能。重新分配這些區域以形成嵌入式電容可為電容耦合增加重疊面積，而不會增加模組的總體積。這些優點，再加上電介質的高介電常數，可在功率模組區域內提供高電容值，否則該區域將無法實現電功能。此外，通過在結構中結合高壓電容，基本上消除了相反極性的組件之間的表面電弧，這相對於表面黏著的獨立組件是一個主要優點。 [0070]   在PDC的構造中使用的陶瓷材料對於功能可靠和更高的電壓(例如200V以上的電壓)至關重要。這是因為多層陶瓷結構可以與導致陶瓷致動器形成機械位移的高電壓牢固地耦合。在鐵電材料和反鐵電類型的材料中，這種電致耦合很高，這會對高壓電容器引起故障。因此，優選的陶瓷材料是具有低電致耦合係數的順電材料。特別優選的是相對介電常數在10以上至不超過300，更優選地在至少25至不超過175的順電介質。特別優選的順電介質包括鋯酸鈣，非化學計量的鋇鈦氧化物，例如Ba2 Ti9 O20 ; BaTi4 O9 ; 含釹或鐠的鋇稀土氧化物，摻雜有各種添加劑的二氧化鈦，鈦酸鈣，鈦酸鍶，鋯酸鍶，鈦酸鋅鎂，鈦酸鋯錫，鈮酸鉍鋅，鉭酸鉍鋅及其組合。特別地，第1類EIA的電介質是特別優選的，特別是那些包含至少50重量％的鋯酸鈣。此外，可符合C0G規範的溫度穩定電介質是最優選的。C0G表示具有溫度係數為+ 30o C的電介質。使用鋯酸鈣的PDC可以在至少260o C的工作溫度下達到1V到10,000V的額定電壓，更優選地達到20,000V的額定電壓。使用具有相對介電常數為32的鋯酸鈣作為電介質，可以得到額定電壓為500V至10,000V的PDC，其在500V時的單位體積電容量為1.0µF/cc，在10,000V時的單位體積電容量至少為0.003µF/cc，且其適用於-65至300oC 的額定工作溫度範圍和150至300o C的最高額定溫度。 [0071]        適用於本發明的結構基板在此不受特別限制，條件是它可以承受高壓、高開關頻率應用中預期的電壓和溫度範圍。本領域技術人員將理解，結構基板不干擾PDC的功能，並且如果結構基板是導電的，則PDC與結構基板是電隔離的。非導電基底是優選的。特別優選的結構基底包括諸如氧化鋁之類的陶瓷，例如96％的Al2 O3 或99.6％的Al2 O3 ;氮化鋁氮化矽或氧化鈹；G10；FR(阻燃)材料，例如FR 1-6，FR 4(環氧樹脂和玻璃的複合材料)，使用酚醛紙或酚醛棉和紙的FR2；複合環氧材料(CEM)，例如CEM 1，2，3，4，5;絕緣金屬基板，例如可從Bergquist Mfg獲得的鋁基板，以及包括諸如聚酰亞胺材料的可撓性電路。層壓板，纖維增強樹脂，陶瓷填充樹脂，特種材料和可撓性基材特別適合。阻燃（FR）層壓板特別適合用作中介層材料，尤其是FR-1，FR-2，FR-3，FR-4，FR-5或FR-6。FR-2是酚醛紙，酚醛棉紙或酚醛樹脂浸漬紙。特別優選FR-4，其為浸漬有環氧樹脂的玻璃纖維編織布。複合環氧材料(CEM)是合適的，尤其是CEM-1，CEM-2，CEM-3，CEM-4或CEM-5，每種材料都包含增強材料，例如棉紙，無紡玻璃或環氧的編織玻璃。玻璃基板(G)被廣泛使用，例如G-5，G-7，G-9，G-10，G-11等，其中最優選的是G-10和G-11，每種玻璃基板都是玻璃環氧。聚四氟乙烯(PTFE)可以是陶瓷填充的，也可以是玻璃纖維增強的，例如RF-35，是特別合適的基材。聚醚醚酮(PEEK)也是一種合適的聚合物，特別是由於其耐高溫性。電子級陶瓷材料，例如可取得的氧化鋁或氧化釔穩定的氧化鋯，其中96％的Al2 O3 和99.6％的Al2 O3 易於商購。雙馬來酰亞胺-三嗪(BT)環氧樹脂是一種特別合適的基材。撓性基材通常是聚酰亞胺，例如可商購到的Kapton或UPILEX聚酰亞胺箔或可商購的Pyralux聚酰亞胺-含氟聚合物複合物。這些基板可以包含由鐵合金(例如合金42，因鋼，科伐合金)或非鐵材料(例如銅，磷青銅或鈹銅)製成的引線。 [0072]        組件係可選自於電晶體，電容器，二極體，電阻器，壓敏電阻，電感器，保險絲，積體電路，過電壓放電裝置，感測器，開關，靜電放電抑制器，逆變器，整流器和濾波器。特別優選的電晶體是基於GaN和SiC的寬帶隙元件。這些組件優選地積體到例如交流/直流轉換器，直流/交流逆變器，EMI/RFI濾波器，緩衝器，諧波濾波器，尤其是交流諧波濾波器等功能裝置中。 [0073]   內部電極優選包含例如鎳，銅等卑金屬或例如銀，鈀，鎢，鉑或金等貴金屬/半貴金屬或它們的組合，其中鎳或鎳合金是優選的。優選的鎳合金包括選自錳，鉻，鈷和鋁中的至少一種，並且這種鎳合金較佳地包含至少95重量％的鎳。要注意的是，鎳和鎳合金可包含至多約0.1重量％的磷和其他微量成分。 實施例 [0074]   製備包括一順電介質和如圖16所示第1組的鎳電極的PDC。電極被鋯酸鈣作為電介質隔開，並且PDC的尺寸為3.1cm x 5cm x 0.3cm(公分)。電介質的厚度是基於650 VDC額定的BME C0G MLCC的示例可靠性而選定。典型的MLCC製造工藝用於製作包含110個主動層的PDC。圖23是CSAM掃描圖像，顯示沒有裂紋、離層或與結構相關缺陷的跡象。PDC的最終電容量為2.7µF，得到的電容量(µF)/體積(CC)為0.58µF/cc。 [0075]   在圖21和22中呈現的數據說明了對於500V至10,000V的電介質K值為32時的電容量(µF)/體積(cc)可以達到1.0至0.003。以相同的結果用於K值為300及10的電介質時，可以預期其電容量(µF)/體積(cc)分別為9.8至0.020和0.33至0.001。 [0076]   本發明已經參閱優選實施例予以描述，但不限於此。本領域技術人員將瞭解到本文未具體描述但在所附申請專利範圍中更具體闡述的本發明專利範圍內的其他實施例和改良。[0018] The present invention relates to an improved power module, and more particularly to a power module especially suitable for wide bandgap devices, wherein the power module includes an interposer with embedded or integrated capacitors. More specifically, the present invention relates to improved packaging of high power electronic devices using embedded multilayer ceramic capacitor structures to effectively integrate capacitors embedded in or integrated within interposers of modules or microprocessors. together, rather than as separately installed components. [0019] In embodiments of the present invention, low parasitic ESR and ESL decoupling capacitors are provided to mitigate transient currents and improve gate driver performance, especially as switching frequency increases. In certain embodiments, soft switches such as zero voltage switching (ZVS), high voltage snubber capacitors are connected across the WBG switching devices to minimize the inductive loop area from the WBG switches to the snubber capacitors, thereby increasing the The increase improves the cushioning performance. [0020] As described herein, gate drivers for WBG switch interposers with integrated decoupling capacitors and snubber capacitors minimize unwanted parasitic effects of circuit layout and increase power density by packaging devices together. Packaging also reduces the volume of interconnects. [0021] The interposer of the present invention provides a high voltage ceramic layer capable of isolating the gate driver input from the gate driver output. An integrated input filter improves immunity to electrical noise and minimizes driver ringing caused by input control signal quality. A timing capacitor is preferably integrated to control the off-time between WBG switching. [0022] Typical driver decoupling capacitors (D-Caps), switching snubber capacitor inductance loop area and power package volume form the parasitic inductance ESL and resistance ESR related issues, usually using an interposer that includes an integrated capacitor to connect the gate pole driver connected to a WBG switching device to ease. [0023] A particular problem in the prior art is the risk of accidental switch-on when ringing exceeds a threshold voltage. The inventive interposer reduces the distance between the gate driver and the input gate of the switch. The reduction in distance reduces the tendency to ring. The interposer's integrated input filter capacitor reduces ringing due to input signal quality, improving noise immunity. It is preferable to provide an integral timing capacitor that controls the off-time between WBG switching. [0024] Another advantage of the interposer of the present invention is to alleviate the problem of galvanic isolation between the control input of the driver and the output of the WBG device and between the output channels of the gate driver. The interposer provides a high voltage electrically isolated area within the interposer. [0025] The interposer integrated capacitors of the present invention may incorporate shield electrodes and gaps to provide further electrical isolation. Snubbering can be integrated into the interposer to reduce inductive loops with wide bandgap devices, helping to achieve zero-voltage switching (ZVS). Another advantage is that thermal buffering can be integrated into the interposer. [0026] The present invention will be described below with reference to the drawings of the integrated components disclosed herein, but not limited thereto. In the various drawings, similar elements will be labeled with corresponding numerals. [0027] An embodiment of the present invention will be described below with reference to FIG. 3, which shows the input, insulator, output and buffer of a ceramic interposer in a block diagram form. In FIG. 3 , the interposer 300 is in electrical communication with a gate driver 302 . Gate drivers require galvanic isolation between input and output. There is an electrical isolation region 304 between at least one integrated snubber capacitor 306 . The electrical isolation region 304 may also include a thermal buffer zone 316 . An input filter resistor 308 is in electrical communication with at least one integrated functional area 310, preferably including the integrated input filter and at least one decoupling capacitor. An integrated output region 312 is in electrical communication with a gate drive current control resistor 314, wherein the integrated output region includes at least one output decoupling capacitor. [0028] An embodiment of the present invention will be described below with reference to FIG. 4 , which shows an interposer and a WBG switch in a schematic circuit diagram. Most of the electrical functions are commercially available isolated dual-channel gate drivers using discrete surface mount capacitors, such as, but not limited to, the commercial driver UCC21530-Q1 from Texas Instruments. The circuit diagram shown in FIG. 4 is known to those skilled in the art, so no further elaboration is necessary except for the circuit design variations mentioned herein. [0029] An intermediary input circuit 320 is schematically shown in FIG. 4 . The interposer input circuit includes a plurality of filter capacitors 322, which may be the same or different, to provide filtering of unwanted frequencies known in the art. In a particularly preferred embodiment, at least one filter capacitor, and more preferably all filter capacitors, are embedded in the interposer and use paradielectric capacitors (PDC) as further described in the description below. Particularly preferably, the decoupling capacitor is embedded in the interposer. In a particularly preferred embodiment, any decoupling capacitors in the interposer input circuit use PDCs. There is at least one decoupling capacitor 324 in the interposer input circuit. A timing capacitor 336, typically in parallel with a resistor, controls the off-time between WBG switches, as is known in the art. In a preferred embodiment, the timing capacitor is a PDC, which is preferably embedded in the interposer. [0030] In FIG. 4, an intermediary output circuit 338 is schematically shown. The intermediary output circuit includes at least one decoupling capacitor 324 . In a particularly preferred embodiment, any decoupling capacitors in the interposer output circuit are PDCs, and preferably the decoupling capacitors are embedded in the interposer. Preferably, at least one decoupling capacitor 324, at least one DC link capacitor 325 is provided in the interposer output circuit to decouple one part of the circuit from another, as is known in the art. [0031] In FIG. 4, the WBG switch 340 has a snubber capacitor 342 electrically connected in parallel with the WBG switch. The snubber capacitor is preferably embedded in the interposer, which provides the circuit with a significantly reduced current path length, thereby reducing the size of the circuit and thus reducing the inductance. The snubber capacitor is preferably a PDC capacitor. [0032] The advantages of the present invention will be described below with reference to FIGS. 1 and 2 . Referring to FIGS. 5 and 6 , wherein FIG. 5 schematically shows a conventional commercially available gate drive printed circuit board (PCB) on which electronic components are laid out. FIG. 6 schematically shows the layout of electronic components of a ceramic interposer as a gate driver in an embodiment of the present invention. Its wiring is not shown for clarity. In FIG. 5, driver 400 is a ceramic interposer surface-mounted to circuit board 401 using techniques common in the art. Resistor 404, diode 406, wide bandgap device 408, and snubber capacitor 410 are typically surface mounted on the same side to minimize current path length. Decoupling capacitors and filter capacitors are collectively indicated at 412 and are mounted on the surface opposite the driver 400 and are electrically connected through vias 414 . In Fig. 6, driver 400, resistor 404, diode 406 and wide bandgap device 408 are preferably mounted on the common face of ceramic interposer 420 on circuit board 403, and decoupling capacitor, Filter capacitors and snubber capacitors are embedded into the ceramic interposer as active layers, so these components are not visible in the layout. [0034] Compared with commercially available gate drivers, the interposer of the present invention has the advantage of reducing the parasitic inductance introduced by the suboptimal circuit board layout and long package lead assembly of the prior art of. The reduced current path length allows for better capacitor optimization, preferably including the use of PDC capacitors, which reduces electronic ringing of the gate-source drive voltage of the power transistor during high dI/dt and dv/dt switching . By reducing electronic ringing, it is possible to reduce ringing conditions that exceed the threshold voltage, as well as reduce the risk of accidental turn-on or even breakdown. In prior art devices, ringing is usually mitigated by applying a negative bias on the gate driver, but the interposer of the present invention is unnecessary, thus eliminating negative or reverse biased power supplies, thereby facilitating for further miniaturization. [0035] A special advantage of the ceramic interposer of the present invention is that the heat buffer 316 for lateral heat dissipation is integrated. While suitable for prior art devices, thermal buffering techniques are generally undesirable due to space constraints. The interposer of the present invention can repurpose the area vacated by the smaller package size as space for heat dissipation or other components without increasing the overall size or exceeding the size occupied by prior art devices. [0036] In a particularly preferred embodiment, an improved power module package is provided that includes an embedded capacitor, wherein the embedded capacitor preferably includes a paradielectric, referred to herein as a paradielectric capacitor (PDC). The use of PDC can further miniaturize the power module, and can operate at higher voltage and higher frequency. Embedding the PDC into the substrate allows the bulk of that substrate to provide embedded capacitance without sacrificing circuit area and requiring no mounted components. In addition, the conductive paths of the circuits making up the power module are significantly minimized, which improves ESR and ESL, thereby improving the electrical function of the module. To facilitate miniaturization, capacitors must be able to operate at higher voltages and frequencies, and although capacitor interface temperatures can be as high as 250°C, they can still be packaged close to wide-bandgap (WBG) semiconductors. [0037] An embodiment of the present invention will be described below with reference to FIG. 7 . A portion of the module is shown in isolated view in FIG. 7 . A paradielectric capacitor (PDC) is indicated at 10 . The PDC comprises parallel planar internal electrodes 14 with opposite polarity between adjacent electrodes. Between adjacent electrodes is a paradielectric 12 . The internal electrodes form a capacitive coupling, while the parallel planar internal electrodes and the para-dielectric together form the active layer. Capacitively coupled external terminals 16 are in electrical contact with alternating internal electrodes 14, thereby providing capacitively coupled electrical connections to PDC interface pads 18 or equivalent electrical connections, thus enabling electrical connection to the modules as further described below. At least one component 24. The way of connecting to the interface pad is not particularly limited, and it can preferably be connected by soldering balls, soldering columns or wire bonding. [0038] An embodiment of the present invention will be described below with reference to FIG. 8 . Module 20 is shown in partial schematic view in FIG. 8 . The module includes at least one capacitive coupling and preferably embeds the PDC 10 in the structural substrate 22 of the ceramic interposer, optionally and preferably the internal electrodes of at least one PDC 10 are encapsulated in the para-dielectric 12 . Several components 24 mounted to, on or in the structural substrate are electrically connected to each other and/or to the PDC to provide the required electrical functions of the module, also referred to herein as an interposer. A power supply 28 can provide power to the modules, and the controller 26 can regulate the power supplied to a powered device 30 . The circuit wiring between the PDC and the various components is not shown in FIG. 8 because the connections between the various components are known in the art as to how to make up a module, and are not limited thereto. [0039] The PDC 10, the structural substrate 22, and the assembly 24 may be combined to form a microprocessor, optionally within the module 20. PDCs embedded in microprocessors are particularly suitable for use at lower voltages, eg, below 200 volts. [0040] The PDC will be described below with reference to FIGS. 9-12, which schematically show a multilayer ceramic capacitor including a para-dielectric. In FIG. 9, a pair of internal electrodes 100 are labeled A and B for ease of discussion. In fact, the internal electrodes are preferably identical. Each internal electrode has a capacitive region 102 and several connection lugs 104 . Internal electrodes are stacked together with the parallel dielectric between adjacent electrodes, and internal electrodes A and B are alternately arranged to align the capacitive areas and alternate wiring lugs, for example, each internal electrode A is aligned to form a stacked internal electrode. The stack is shown in the schematic top view of Figure 10, where adjacent terminal lugs have alternating polarity. The entire assembly is preferably encapsulated in ceramic, preferably in a para-dielectric. In the embodiment shown in FIG. 11, the external terminals 106 are in electrical contact with aligned terminal lugs of common polarity. In use, the external terminals are used as capacitive coupling terminals and subsequently make electrical contact with the PDC interface pads. The external terminal preferably includes at least one material selected from copper, nickel, tungsten, silver, palladium, platinum, gold, or combinations thereof. [0041] In the embodiment shown in FIG. 12, after the aligned terminal lugs having a common polarity are stacked, a via 108 is formed through the stack. The vias serve as capacitive coupling terminals, which are then preferably in electrical contact with the PDC interface pads through external terminals, preferably on the PDC surface. The vias provide a low thermal resistance path to remove excess heat from the module. In the preferred case of using a calcium zirconate based dielectric with nickel internal electrodes, the vias are preferably filled with copper. Exposed copper surfaces on terminal lugs and vias may be plated with nickel, silver, tin, gold, palladium or combinations thereof. Vias may be formed by porosity of the dielectric tape used in the structure, or machined in a green or sintered body. Those skilled in the art will also appreciate that they can be used for purely mechanical attachments when the internal electrodes are not contacted. In addition, wiring on the surface of the component can be formed by screen printing copper with optional overplating to provide solder pads and electrical contacts for encapsulating other components within the module and contacting the semiconductor. [0042] An embodiment of the present invention will be described below with reference to FIG. 13 . For ease of discussion and clear description, a three-phase power module is shown in the schematic diagram. In FIG. 13 , the first component is represented by an AC power supply 200 . The second component is represented by the electromagnetic interference or radio frequency interference filter EMI/RFI 202, which can be surface mount integrated to the AC power supply or the EMI/RFI can be embedded in the structural substrate 22 of the ceramic interposer, as shown, capacitively coupled Terminals 16 1 -16 3 terminate at PDC interface pads 18 1 -18 3 . A representative EMI/RFI filter is schematically labeled A in FIG. 14 . In an embodiment, at least the capacitor of the EMI/RFI filter is an embedded PDC as described herein. A third component, denoted AC harmonic filter 204, preferably receives EMI/RFI filtered power through internal electrodes 201 1 -201 3 . A representative AC harmonic filter is schematically indicated at B in FIG. 14 . In one embodiment, the capacitors and inductors of the AC harmonic filter are embedded PDCs as described herein. A fourth component, designated AC/DC converter 206, may be used to convert an AC signal to a DC signal. The AC/DC converter may be electrically connected to the AC harmonic filter through capacitively coupled terminals 16 4 - 16 6 coupled to PDC interface pads 18 4 - 18 6 to minimize the conductive path length. Between the AC/DC converter and a fifth component denoted DC/AC inverter 214 there are embedded components of buffers 208 , 212 and a DC link capacitor 210 . A representative buffer, labeled C in FIG. 14 , is schematically shown, and a representative DC link capacitor, labeled D in FIG. 14 . The capacitors of the buffer are preferably embedded PDCs in electrical communication with the PDC interface pads 18 7 - 18 10 through capacitive coupling terminals 16 7 - 16 10 . The DC link capacitors are preferably embedded PDCs and are preferably electrically connected to each buffer via internal electrodes 201 3 - 201 6 . The use of internal electrodes improves Faraday shielding to minimize EMI noise emitted by the module. [0043] In certain circuit designs, it is advantageous to have the lowest equivalent series inductance (ESL) and/or the lowest equivalent series resistance (ESR) for best performance. The structure includes multiple capacitors of opposite polarity to minimize ESL. As will be appreciated from Figure 15, as described above for Figures 9-10, layers A and B are alternately stacked so that the two can be capacitively coupled in a common structure where adjacent external terminals With opposite polarity, this minimizes ESL. [0044] In order to prevent circuit ringing, it is sometimes desirable to increase the ESR of a capacitor. The ESR in a PDC can be increased by increasing the path length in the electrodes inside the PDC. From Fig. 16 it can be seen that using rectangular internal electrodes as in a PDC with a dielectric between alternating layers A-1 and B-1, a larger overlap area can be achieved. As shown from left to right in Figure 16, decreasing width as path length increases ESR. By combining the number of capacitors and electrode shapes, ESL and/or ESR can be optimized. [0045] Using these techniques, the performance of a module or mediator that includes a PDC can be optimized. [0046] Low inductance is beneficial because in WBG semiconductor applications, higher switching current edge rate dI/dt and higher switching frequency will generate larger voltage ringing to drive inductive loads. Snubber capacitors located adjacent to the switch package help reduce this ringing. Integrating the snubber into the substrate further reduces the total loop inductance from the snubber to the switching device, maximizing the snubber's benefits. [0047] An embedded PDC, along with other components, can make a module or electronic package suitable for many applications. Figure 17 schematically shows a flying capacitor circuit. Figure 18 schematically shows a Zero Voltage Switching (ZVS) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) circuit. Fig. 19 schematically shows an H-bridge circuit of MOSFETs. Figure 20 schematically shows an integrated rectifier capacitor. [0048] In the example shown in FIG. 17 with 2 switching cells, the multi-stage flying capacitor inverter rectification loop inductance is a limiting factor. Adding an additional bulk rectification capacitor near the switch improves rectification performance. In soft switching as shown in Figure 18, a snubber can be used to provide charge and discharge current when the load current changes direction to actuate the zero voltage switch (ZVS). [0049] In the 4 switch circuits shown in Figures 19 and 20, adding capacitance near the switches can improve the performance of high smoothing capacitors such as DC links or flying capacitors located slightly away from the switching device. [0050] An embodiment of the present invention will be described below with reference to FIG. 24 . In FIG. 24 , a module 218 may be a component of a ceramic interposer with at least one heat dissipation layer 20 contacting at least one semiconductor 19 thereon. This thermal layer helps dissipate heat laterally from the module. At least one capacitor, preferably a PDC 10 , is in electrical contact with the semiconductor, preferably with a heat sink layer between the semiconductor and the PDC. The PDC may be electrically connected to the semiconductor through the heat sink layer through an insulated via 222 having a conductive core 226 and an insulator 224 electrically isolating the conductive core from the heat sink layer in the via extending through the heat sink layer . [0051] Utilizing a PDC with vias, especially vias, may provide an alternative to separate packaging. The resulting plurality of capacitors PDC are packaged into a microprocessor using techniques well known in the art, such as solder ball attach, to form an integrated microprocessor-capacitor assembly. Other types of components that can be considered packaged as part of the PDC include ESD suppressors, inductors, and others. [0052] Typical high power substrates with various metallizations formed from oxides such as Al 2 O 3 , BeO, AlN, Si 3 N 4 can be used as heat sink layers. For example, AlN and BeO are valued for their high thermal conductivity. For example, AlN has a thermal conductivity of 140-200 W/mK. However, BeO is toxic and copper metallization reliability of AlN is problematic. For these reasons, Si3N4 with a thermal conductivity of 35-60 W/mK and with brazed Al is suitable as an example for the present invention. To improve the PDC thermal conductivity in the z direction, higher thermal conductivity materials are preferred. A PDC may incorporate a capping layer on the last layer of active internal electrodes that includes a higher thermal conductivity material than the PDC dielectric. Those skilled in the art will appreciate that this can be achieved by using an insulating tie layer or, more practically, firing a capping layer comprising a high thermal conductivity dielectric along with the PDC during the manufacturing process. In CaZrO 3 -based dielectrics, due to the high affinity for oxygen, it can be used in combination with air-sensitive materials (such as AlN, Si 3 N 4 ). In the reducing atmosphere required for sintering metal-poor electrodes and non-oxide ceramics, oxygen is not lost during firing. Other oxide ceramics lose oxygen, so the resulting vacancies can then migrate under an electric field, compromising reliability. This behavior of calcium zirconate enables combinations with non-oxide base materials. The ability to efficiently bond CaZrO3 to these non-oxide base materials is also important when considering the coefficient of thermal expansion (CTE). This is due to the importance of minimizing the CTE mismatch with increased reliability. Calcium zirconate has a CTE of 8.4 PPM/°C, which is close to the 8-10 PPM/°C of commercial Al2O3 and BeO-based substrates . However, non-oxide base materials such as AlN and Si3N4 have low CTEs of 3.3–5.6 PPM/°C, so effectively combining these materials with CaZrO3 can resolve this mismatch. [0053] A particularly preferred material for the heat dissipation layer is a dielectric having a dielectric constant lower than that of the PDC. A heat sink layer comprising a lower dielectric constant than the ceramic of the PDC has particular advantages in terms of high frequency performance. [0054] In another embodiment, the problems associated with the internal self-heating of the PDC can be alleviated by adding at least one heat dissipation channel (preferably continuous) through the body of the PDC so that the core of the PDC The temperature is lowered by the heat transfer medium. Although in high power applications, the internal electrodes of the PDC can dissipate heat more efficiently through the electrode surface to the terminals, there is still a need to dissipate heat more efficiently. The heat conduction medium can be static with limited flow, or it can flow into and pass through the heat dissipation channel to facilitate the transfer of heat energy from the inside of the MLCC. Embodiments of the present invention will now be described with reference to FIGS. 25 and 26, wherein a PDC shown in the side sectional view of FIG. 25 and in the end sectional view of FIG. 26 is designated by reference numeral 110. In FIGS. 25 and 26 , the PDC includes alternating parallel internal electrodes 112 and 114 and a dielectric 116 between the internal electrodes and external terminals 118 , 120 of opposite polarity. The heat dissipation channels 122 parallel to the internal electrodes preferably pass through at least one surface of the capacitor body, and are more preferably provided with a continuous passage through the capacitor body. The ends of the heat dissipation channels or vents are preferably located on the face of the capacitor body where there are no external terminals to allow access to the thermal vents 124 of the channel so that the heat transfer medium enters one vent of the thermal channel and preferably exits through the other vent. cooling channels. Optional struts 126 may be provided across the height of the thermal channel to improve structural integrity or to provide turbulent flow to reduce laminar flow, thereby increasing the rate of heat transfer between the capacitor body and the thermally conductive medium. The struts preferably do not extend the entire width of the capacitor, for example from thermal vent to thermal vent. In the embodiment of FIGS. 25 and 26 , the heat dissipation channels are defined on all sides by ceramic, and there are no contact points between the heat dissipation channels and the internal electrodes 112 and 114 . Ceramics are not effective thermal conductors, therefore, the heat dissipation channels are defined on all sides by the ceramics. Ceramics lack thermal efficiency. However, ceramics are non-conductive, which allows for a greater range of thermally conductive media, so this embodiment can be advantageous in certain applications. [0056] In an alternative embodiment, the heat dissipation channel is defined on three sides by ceramic and on at least one side is partially defined by the internal electrode. In another alternative embodiment, the heat dissipation channel is defined on both sides by ceramic and on at least a portion of both sides by internal electrodes, as described in US Patent No. 10,147,544, incorporated herein by reference. A particular advantage of a heat dissipation channel defined by at least one internal electrode is the enhanced heat conduction provided by the internal electrodes, which are generally more efficient at conducting heat than ceramics. If the heat transfer medium is in contact with the internal electrodes, it is preferably non-conductive and non-corrosive. [0057] An embodiment of the present invention will be described below with reference to FIG. 27, in which a PDC of the present invention is shown at 110 in a side view in cross-section. In FIG. 27 , the PDC includes a plurality of heat dissipation channels 122 with electrically insulating barriers 127 , wherein the heat dissipation channels are arranged in a plurality of common heat dissipation channel planes, wherein each common heat dissipation channel plane is parallel to the inner electrodes. Those skilled in the art will appreciate that the described thermal buffering can be applied to multiple individual capacitors within an interposer. [0058] An embodiment of the present invention will be described below with reference to FIG. 28 , which shows a schematic cross-sectional view of a PDC. In FIG. 28, the external terminals 118 and 120 and the dielectric 116 are as described above. Shield electrodes 128 and 129 are shown as being defined as coplanar electrodes with opposite polarity inner electrodes positioned outermost in the PDC. The shield electrode prevents arcing from the outer terminal to the inner electrode of opposite polarity. For example, electrodes 128 and 129' prevent arcing between the outer terminals and the closest inner electrodes 130 and 131 of opposite polarity. The heat dissipation channel 122 is coplanar with opposing coplanar inner electrodes 132 and 134 of opposite polarity. In the embodiment shown in Figure 28, the heat dissipation channels are defined on all sides by ceramic, as described above. [0059] An embodiment of the present invention will be described below with reference to FIG. 29 , which shows a schematic cross-sectional view of a PDC. The PDC of FIG. 29 includes coplanar active internal electrodes 136 and 138 of opposite polarity and floating electrodes 140 parallel to the coplanar active internal electrodes, and preferably coplanar adjacent to each side of each floating electrode. Active internal electrodes. An active electrode is defined herein as an internal electrode in electrical contact with an external terminal. A floating electrode is an internal electrode that is not in electrical contact with an external terminal. At least one heat dissipation channel 122 is coplanar with the coplanar active electrodes of opposite polarity. [0060] An embodiment of the present invention will be described below with reference to FIG. 30 , which shows a schematic cross-sectional view of a PDC. The PDC of FIG. 30 includes coplanar active internal electrodes 136 and 138 of opposite polarity and floating electrodes 140 parallel to the coplanar active internal electrodes, and preferably coplanar adjacent to each side of each floating electrode. Active internal electrodes. At least one heat dissipation channel 122 is coplanar with the coplanar active electrode of opposite polarity, and optionally in fluid contact with the inner electrode. [0061] An embodiment of the present invention will be described below with reference to FIG. 31 , which shows a schematic cross-sectional view of a PDC. In FIG. 31 , the interior of the heat dissipation channel 122 is coated with an optional coating 130 , which is preferably a thermally conductive coating, so as to increase the heat conduction between the ceramic and the thermally conductive medium 128 . The coating material is not particularly limited to a preferred material that can coat the dielectric and provide sufficient thermal conductivity from the dielectric to the thermally conductive medium. An embodiment of the present invention will be described below with reference to FIG. 32 . In Figure 32, a PDC 110 has heat dissipation channels 122 that are not parallel to the electrodes 112, 114 and are preferably perpendicular to the electrodes. A higher contact between the heat transfer medium and the inner electrodes can be made by means of heat dissipation channels through the electrodes. In one embodiment, the thermally conductive medium is non-conductive. In another embodiment, a thermally conductive but electrically insulating coating can be applied to the interior of the heat dissipation channel. [0062] An embodiment of the present invention will be described below with reference to FIG. 33 . In FIG. 33, a module 218 has a PDC 110 mounted on at least one semiconductor 19, wherein the PDC includes at least one through heat dissipation channel, wherein the heat dissipation channel is parallel to the electrodes, perpendicular to the electrodes or at an intermediate angle between the electrodes. The cooling device 228 can dissipate the heat collected through the cooling channels. The cooling device may be a passive device that dissipates heat by interacting with a medium, preferably air, such as a heat sink. Alternatively, the cooling device may be an active device which dissipates heat by electrical, mechanical or chemical means, for example by adiabatic expansion, flow media or by Peltier techniques. [0063] Thermally conductive inorganic or organic materials comprising metals, thermally conductive ceramics, polymers, and combinations thereof are particularly suitable for use in the present invention. Silicone thermal grease is particularly preferred due to its high thermal conductivity, low thermal resistance, cost, processability and reusability. As non-limiting examples of the invention, for example Dow Corning® TC-5026, Dow Corning® TC-5022, Dow Corning® TC-5600, Dow Corning® TC-5121, Dow Corning® SE4490CV, Dow Corning® SC 102 may be used ; Dow Corning® 340 heatsinks; Shin-Etsu MicroSI® X23-7853W1, Shin-Etsu MicroSI® X23-7783 D, Shin-Etsu MicroSI® G751, and Shin-Etsu MicroSI® X23-7762D are particularly suitable for use as cooling channels coating. [0064] The heat transfer medium can be a static or flowing gas or liquid to improve heat transfer. Non-conductive materials are particularly preferred. Perfluorinated hydrocarbons, nanofluids, mineral oils and ethers are particularly suitable due to their high thermal conductivity and minimal electrical conductivity. As non-limiting examples, for example Galden® HT55, Galden® HT70, Galden® HT80, Galden® HT110, Galden® HT135, Galden® HT170, Galden® HT200, Galden® HT230 and Galden® HT270 are particularly suitable as heat transfer medium. Gases such as air, at least partially dry air or inert gases are particularly suitable as heat transfer medium. [0065] The heat dissipating channels can be formed by various techniques during the manufacturing process of the PDC. The ceramic precursor layer may be printed with a sacrificial organic material or carbon in a predetermined pattern corresponding to the heat dissipation channels. During baking and co-firing of the PDC, the sacrificial organic material or carbon is preferably removed by evaporation. Areas of the ceramic tape can be removed prior to lamination of the PDC, or heat dissipation channels can be machined before or after baking and sintering. [0066] As known in the art, a PDC is prepared by layering ceramic precursors and conductor precursors in a proper alignment sequence. After a sufficient number of layers have been built, the assembly is heated to form alternating layers of internal conductors and sintered ceramic, with heat dissipation channel precursors formed in the ceramic layers. [0067] In each layer where the heat dissipation channel is to be formed, the pattern of the pre-channel material corresponding to the heat dissipation channel is printed. After sintering, the pre-channel material vaporizes, leaving gaps in the shape of the printed pre-channel material. A non-volatile material, preferably ceramic, may be added to the pre-channel material to form a support in the gap. [0068] The pre-channel material may be any material that is applied in a predetermined pattern and leaves heat dissipation channels as gaps when the layer is sintered. Particularly preferred materials are electrode inks which do not include metals. Such materials are preferred because of their ready availability and inherent adaptability to manufacturing environments. Another particularly suitable material is a binder for use with ceramic precursors, excluding ceramic precursors. [0069] Large-area structural substrates generally do not have electrical functionality. Redistribution of these areas to form embedded capacitors increases the overlap area for capacitive coupling without increasing the overall volume of the module. These advantages, combined with the high dielectric constant of the dielectric, provide high capacitance values in areas of the power module that would otherwise be electrically incapable of functioning. Furthermore, by incorporating high-voltage capacitors in the structure, surface arcing between components of opposite polarity is essentially eliminated, a major advantage over surface-mounted stand-alone components. [0070] Ceramic materials used in the construction of PDCs are critical for functional reliability and higher voltages (eg, voltages above 200V). This is because the multilayer ceramic structure can be robustly coupled to the high voltages that cause the mechanical displacement of the ceramic actuator. In ferroelectric and antiferroelectric types of materials, this electrocoupling is high, which can cause malfunctions in high voltage capacitors. Therefore, a preferred ceramic material is a paraelectric material with a low electrocoupling coefficient. Particularly preferred are paradielectrics having a relative permittivity of above 10 and not exceeding 300, more preferably at least 25 and not exceeding 175. Particularly preferred paradielectrics include calcium zirconate, non-stoichiometric barium titanium oxides such as Ba 2 Ti 9 O 20 ; BaTi 4 O 9 ; barium rare earth oxides containing neodymium or helium, titanium dioxide doped with various additives, Calcium titanate, strontium titanate, strontium zirconate, zinc magnesium titanate, zirconium tin titanate, bismuth zinc niobate, bismuth zinc tantalate, and combinations thereof. In particular, Class 1 EIA dielectrics are particularly preferred, especially those comprising at least 50% by weight calcium zirconate. Furthermore, temperature stable dielectrics that can meet COG specifications are most preferred. C0G denotes a dielectric with a temperature coefficient of +30 o C. A PDC using calcium zirconate can achieve a rated voltage of 1 V to 10,000 V, more preferably a rated voltage of 20,000 V, at an operating temperature of at least 260 ° C. Using calcium zirconate with a relative permittivity of 32 as the dielectric, a PDC with a rated voltage of 500V to 10,000V can be obtained, and its capacitance per unit volume at 500V is 1.0µF/cc, and its capacitance per unit volume at Capacitance is at least 0.003µF/cc, and it is suitable for a rated operating temperature range of -65 to 300 oC and a maximum temperature rating of 150 to 300 oC . [0071] A structural substrate suitable for use in the present invention is not particularly limited herein, provided that it can withstand the voltage and temperature ranges expected in high voltage, high switching frequency applications. Those skilled in the art will understand that the structural substrate does not interfere with the function of the PDC, and if the structural substrate is conductive, the PDC is electrically isolated from the structural substrate. Non-conductive substrates are preferred. Particularly preferred structural substrates include ceramics such as alumina, for example 96% Al 2 O 3 or 99.6% Al 2 O 3 ; aluminum nitride silicon nitride or beryllium oxide; G10; FR (flame retardant) materials, Such as FR 1-6, FR 4 (composite materials of epoxy resin and glass), FR2 using phenolic paper or phenolic cotton and paper; composite epoxy materials (CEM), such as CEM 1, 2, 3, 4, 5; insulation Metal substrates, such as aluminum substrates available from Bergquist Mfg, and flexible circuits including materials such as polyimide. Laminates, fiber reinforced resins, ceramic filled resins, specialty materials and flexible substrates are especially suitable. Flame Retardant (FR) laminates are particularly suitable as interposer materials, especially FR-1, FR-2, FR-3, FR-4, FR-5 or FR-6. FR-2 is phenolic paper, phenolic tissue paper or phenolic resin impregnated paper. Particularly preferred is FR-4, which is a woven glass fiber cloth impregnated with epoxy resin. Composite epoxy materials (CEM) are suitable, especially CEM-1, CEM-2, CEM-3, CEM-4 or CEM-5, each containing reinforcements such as tissue paper, non-woven glass or rings Oxygen woven glass. Glass substrates (G) are widely used, such as G-5, G-7, G-9, G-10, G-11, etc., among which G-10 and G-11 are the most preferred, and each glass substrate is Glass epoxy. Polytetrafluoroethylene (PTFE), which can be ceramic filled or glass fiber reinforced, such as RF-35, is a particularly suitable substrate. Polyetheretherketone (PEEK) is also a suitable polymer, especially due to its high temperature resistance. Electronic grade ceramic materials such as available alumina or yttria stabilized zirconia with 96% Al2O3 and 99.6% Al2O3 are readily available commercially. Bismaleimide-triazine (BT) epoxy resin is a particularly suitable substrate. The flexible substrate is typically a polyimide, such as the commercially available Kapton or UPILEX polyimide foils or the commercially available Pyralux polyimide-fluoropolymer composites. These substrates may contain leads made of ferrous alloys (eg Alloy 42, Invar, Kovar) or non-ferrous materials (eg copper, phosphor bronze or beryllium copper). Components may be selected from transistors, capacitors, diodes, resistors, varistors, inductors, fuses, integrated circuits, overvoltage discharge devices, sensors, switches, electrostatic discharge suppressors, inverters, rectifiers and filters. Particularly preferred transistors are wide bandgap elements based on GaN and SiC. These components are preferably integrated into functional devices such as AC/DC converters, DC/AC inverters, EMI/RFI filters, snubbers, harmonic filters, especially AC harmonic filters. [0073] The internal electrodes preferably comprise base metals such as nickel, copper or noble/semi-precious metals such as silver, palladium, tungsten, platinum or gold or combinations thereof, wherein nickel or nickel alloys are preferred. Preferred nickel alloys include at least one selected from manganese, chromium, cobalt and aluminum, and such nickel alloys preferably contain at least 95% by weight nickel. It is to be noted that nickel and nickel alloys may contain phosphorus and other minor constituents up to about 0.1% by weight. Embodiment [0074] A PDC comprising a cis dielectric and a nickel electrode of the first group as shown in FIG. 16 was prepared. The electrodes are separated by calcium zirconate as the dielectric, and the PDC measures 3.1 cm x 5 cm x 0.3 cm (centimeter). The thickness of the dielectric was selected based on the example reliability of a 650 VDC rated BME C0G MLCC. A typical MLCC fabrication process is used to make a PDC with 110 active layers. Figure 23 is a CSAM scan image showing no evidence of cracks, delamination or structural related defects. The final capacitance of the PDC is 2.7µF, resulting in a capacitance (µF)/volume (CC) of 0.58µF/cc. [0075] The data presented in FIGS. 21 and 22 illustrate that capacitance (µF)/volume (cc) can reach 1.0 to 0.003 for a dielectric K value of 32 for 500V to 10,000V. With the same results for dielectrics with K values of 300 and 10, capacitance (µF)/volume (cc) can be expected to be 9.8 to 0.020 and 0.33 to 0.001, respectively. [0076] The present invention has been described with reference to preferred embodiments, but is not limited thereto. Those skilled in the art will recognize other embodiments and modifications within the scope of the invention not specifically described herein but more particularly set forth in the appended claims.

[0077] 10:順電介質電容器 12:順電介質 14:內部電極 16:電容耦合端子 18:界面焊墊 19:半導體 20:模組 22:結構基板 24:組件 26:控制器 28:電源 30:受電設備 100:內部電極 102:電容區域 104:接線凸耳 106:外部端子 110:順電介質電容器 112、114:內部電極 116:電介質 118、120:外部端子 122:散熱通道 124:散熱口 127:電絕緣屏障 128、129:屏蔽電極 130、131:內部電極 132、134:內部電極 136、138:內部電極 140:浮動電極 200:交流電源 201:內部電極 202:濾波器 204:AC諧波濾波器 206:AC/DC轉換器 208:緩衝器 210:DC鏈路電容器 212:緩衝器 214:DC/AC逆變器 218:模組 222:通孔 224:絕緣體 226:導電芯 228:冷卻裝置 300:中介器 302:柵極驅動器 304:電隔離區 306:緩衝電容器 308:輸入濾波電阻器 310:積體功能區 312:積體輸出區域 314:柵極驅動電流控制電阻器 316:熱緩衝區 320:中介器輸入電路 322:濾波電容器 324:去耦合電容器 325:DC鏈路電容器 336:計時電容器 338:中介器輸出電路 340:WBG開關 342:緩衝電容器 400:驅動器 401:電路板 403:電路板 404:電阻器 406:二極體 408:寬帶隙裝置 410:緩衝電容器 412:解耦合電容器和濾波電容器 414:通孔 420:陶瓷中介器[0077] 10: Shun Dielectric Capacitor 12: Shun Dielectric 14: Internal electrode 16: Capacitive coupling terminal 18: Interface pad 19: Semiconductor 20:Module 22: Structural substrate 24: Components 26: Controller 28: Power 30: Power receiving equipment 100: Internal electrode 102:Capacitance area 104: Wiring Lug 106: External terminal 110: Shun Dielectric Capacitor 112, 114: internal electrodes 116: Dielectric 118, 120: external terminals 122: cooling channel 124: cooling port 127: Electrical insulation barrier 128, 129: shielding electrode 130, 131: internal electrodes 132, 134: internal electrodes 136, 138: internal electrodes 140: Floating electrode 200: AC power 201: Internal electrode 202: filter 204: AC harmonic filter 206:AC/DC Converter 208: buffer 210:DC link capacitor 212: buffer 214:DC/AC Inverter 218:Module 222: through hole 224: insulator 226: conductive core 228: cooling device 300: Mediator 302: Gate driver 304: electrical isolation area 306: snubber capacitor 308: Input filter resistor 310: Integrated functional area 312: Integrated output area 314: Gate drive current control resistor 316: Thermal buffer 320: Mediator input circuit 322: filter capacitor 324: decoupling capacitor 325:DC link capacitor 336: timing capacitor 338: Mediator output circuit 340: WBG switch 342: snubber capacitor 400: drive 401: circuit board 403: circuit board 404: Resistor 406: Diode 408: Wide Bandgap Device 410: snubber capacitor 412: Decoupling Capacitors and Filter Capacitors 414: through hole 420: ceramic intermediary

[0017] 圖1顯示在400V和10％鏈波電壓下各種功率準位的電容量與頻率關係的圖形。 圖2顯示在1200V和10％鏈波電壓下各種功率準位的電容量與頻率關係的圖形。 圖3係本發明的方塊圖。 圖4係本發明的電路圖。 圖5係現有技術裝置的示意圖。 圖6係本發明裝置的示意圖 圖7係本發明實施例的示意圖。 圖8係本發明實施例的示意圖。 圖9-12係本發明中的一PDC的實施例示意圖。 圖13係本發明實施例的示意圖。 圖14係本發明代表性組件的實施例示意圖。 圖15-16顯示適用於本發明的內部電極圖型的示意圖。 圖17-20係本發明實施例的示意圖。 圖21-22係本發明實施例的圖形。 圖23係本發明實施例的圖像。 圖24係本發明一實施例的示意圖。 圖25係本發明一實施例的示意圖。 圖26係本發明一實施例的示意圖。 圖27係本發明一實施例的示意圖。 圖28係本發明一實施例的示意圖。 圖29係本發明一實施例的示意圖。 圖30係本發明一實施例的示意圖。 圖31係本發明一實施例的示意圖。 圖32係本發明一實施例的示意圖。 圖33係本發明一實施例的示意圖。[0017] Figure 1 shows a graph of capacitance versus frequency for various power levels at 400V and 10% chain wave voltage. Figure 2 shows a graph of capacitance versus frequency for various power levels at 1200V and 10% chain wave voltage. Fig. 3 is a block diagram of the present invention. Fig. 4 is the circuit diagram of the present invention. Figure 5 is a schematic diagram of a prior art device. Fig. 6 is the schematic diagram of device of the present invention Fig. 7 is a schematic diagram of an embodiment of the present invention. Fig. 8 is a schematic diagram of an embodiment of the present invention. 9-12 are schematic diagrams of an embodiment of a PDC in the present invention. Fig. 13 is a schematic diagram of an embodiment of the present invention. Figure 14 is a schematic diagram of an embodiment of a representative assembly of the present invention. 15-16 show schematic diagrams of internal electrode patterns suitable for use in the present invention. 17-20 are schematic diagrams of embodiments of the present invention. 21-22 are diagrams of embodiments of the present invention. Figure 23 is an image of an embodiment of the present invention. Fig. 24 is a schematic diagram of an embodiment of the present invention. Fig. 25 is a schematic diagram of an embodiment of the present invention. Fig. 26 is a schematic diagram of an embodiment of the present invention. Fig. 27 is a schematic diagram of an embodiment of the present invention. Fig. 28 is a schematic diagram of an embodiment of the present invention. Fig. 29 is a schematic diagram of an embodiment of the present invention. Fig. 30 is a schematic diagram of an embodiment of the present invention. Fig. 31 is a schematic diagram of an embodiment of the present invention. Fig. 32 is a schematic diagram of an embodiment of the present invention. Fig. 33 is a schematic diagram of an embodiment of the present invention.

300:中介器 300: Mediator

302:柵極驅動器 302: Gate driver

304:電隔離區 304: electrical isolation area

306:緩衝電容器 306: snubber capacitor

308:輸入濾波電阻器 308: Input filter resistor

310:積體功能區 310: Integrated functional area

312:積體輸出區域 312: Integrated output area

314:柵極驅動電流控制電阻器 314: Gate drive current control resistor

316:熱緩衝區 316: Thermal buffer

Claims (32)

一種用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，包括：一陶瓷中介器，包括多層；其中該多層中的主動層形成嵌入式電容器，該嵌入式電容器包括複數個並聯電極且在相鄰電極之間具有一電介質，其中該相鄰電極具有相反的極性，且其中所述電介質是具有相對介電常數在10以上且在300以下的順電陶瓷電介質，所述順電陶瓷電介質包括至少50重量%的鋯酸鈣；和一寬帶隙裝置，位在多層的該陶瓷中介器上。 A gate drive interposer with integrated passive components for a wide bandgap semiconductor device, comprising: a ceramic interposer comprising multiple layers; wherein the active layer in the multiple layers forms an embedded capacitor comprising a plurality of parallel electrodes and have a dielectric between adjacent electrodes, wherein the adjacent electrodes have opposite polarities, and wherein the dielectric is a paraelectric ceramic dielectric having a relative permittivity of 10 or more and 300 or less, the paraelectric A ceramic dielectric comprising at least 50% by weight calcium zirconate; and a wide bandgap device on the multilayered ceramic interposer. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述嵌入式電容器中的至少一個電容器係選自去耦合電容器、緩衝電容器、計時電容器、濾波電容器和直流鏈路電容器之一。 The gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 1, wherein at least one of the embedded capacitors is selected from decoupling capacitors, snubber capacitors, timing capacitors , filter capacitor and one of the DC link capacitors. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，包括至少一個間隙區域，以電隔離所述嵌入式電容器。 The gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 1 includes at least one gap region to electrically isolate the embedded capacitor. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述介電常數為至少25至不大於175。 The gate drive interposer with integrated passive devices for wide bandgap semiconductor devices according to claim 1, wherein the dielectric constant is at least 25 and not greater than 175. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述順電介質是COG電介質。 The gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 1, wherein the paradielectric is a COG dielectric. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，還包括至少一個PDC界面焊墊。 According to claim 1, the gate drive interposer with integrated passive components for wide bandgap semiconductor devices further includes at least one PDC interface pad. 依據請求項6所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述寬帶隙裝置係電接觸於所述至少一個PDC界面焊墊。 The gate drive interposer with integrated passive devices for wide bandgap semiconductor devices according to claim 6, wherein the wide bandgap device is in electrical contact with the at least one PDC interface pad. 依據請求項7所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述至少一個PDC界面焊墊通過焊球、焊柱、引線焊接、厚膜漿料或其他冶金結合而連接至所述半導體裝置。 According to the gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 7, wherein the at least one PDC interface pad is soldered by solder balls, solder columns, wire bonding, thick film paste or other metallurgical bonding to the semiconductor device. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述電極包括銅、鎳、鎢、銀、鈀、鉑、或金。 According to claim 1, the gate drive interposer with integrated passive devices for wide bandgap semiconductor devices, wherein the electrodes include copper, nickel, tungsten, silver, palladium, platinum, or gold. 依據請求項9所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述電極包括鎳。 The gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 9, wherein the electrodes comprise nickel. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，還包括外部端子。 According to claim 1, the gate drive interposer with integrated passive components for wide bandgap semiconductor devices further includes external terminals. 依據請求項11所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述外部端子係電接觸於所述電極，其中所述外部端子包括銅、鎳、鎢、銀、鈀、鉑、或金。 According to the gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 11, wherein the external terminals are in electrical contact with the electrodes, wherein the external terminals include copper, nickel, Tungsten, silver, palladium, platinum, or gold. 依據請求項12所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述外部端子通過所述陶瓷中介器中的通孔與所述電極電接觸。 The gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 12, wherein the external terminals are in electrical contact with the electrodes through via holes in the ceramic interposer. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，所述陶瓷中介器上還包括一柵極驅動器。 According to the gate drive interposer with integrated passive components for wide bandgap semiconductor devices described in Claim 1, the ceramic interposer further includes a gate driver. 依據請求項14所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，所述陶瓷中介器上包括至少一選自於包括電晶體，電容器，二極體，電阻器，壓敏電阻，電感器，保險絲，積體電路，過電壓放電裝置，感測器，開關，靜電放電抑制器，逆變器，整流器，濾波器和電隔離電源的組群之一的組件。 According to the gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 14, the ceramic interposer includes at least one selected from transistors, capacitors, diodes, and resistors , varistors, inductors, fuses, integrated circuits, overvoltage discharge devices, sensors, switches, electrostatic discharge suppressors, inverters, rectifiers, filters and components of one of the groups of electrically isolated power supplies. 依據請求項15所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述電隔離電源是反向偏壓電源。 The gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 15, wherein the electrically isolated power supply is a reverse bias power supply. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述嵌入式電容器的至少一嵌入式電容器的額定電壓為500V至10,000V，在500V下的單位體積的電容量至少為1.0μF/cc，在10,000V下的單位體積的電容量為至少0.003μF/cc。 According to the gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 1, wherein at least one of the embedded capacitors has a rated voltage of 500V to 10,000V, at 500V The capacitance per unit volume at 10,000 V is at least 0.003 μF/cc at least 1.0 μF/cc. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述嵌入式電容器中的至少一個嵌入式電容器包括至少一個散熱通道。 The gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 1, wherein at least one of the embedded capacitors includes at least one heat dissipation channel. 依據請求項18所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，至少一個所述散熱通道係選自於與所述電極平行和所述電極垂直之一。 The gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 18, wherein at least one of said heat dissipation channels is selected from one of parallel to said electrodes and perpendicular to said electrodes . 依據請求項18所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述嵌入式電容器係位在所述半導體與一冷卻裝置之間。 The gate drive interposer with integrated passive devices for wide bandgap semiconductor devices according to claim 18, wherein the embedded capacitor is located between the semiconductor and a cooling device. 依據請求項20所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述冷卻裝置選自一被動裝置和一主動裝置。 The gate drive interposer with integrated passive devices for wide bandgap semiconductor devices according to claim 20, wherein the cooling device is selected from a passive device and an active device. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，還包括與所述電容器中的至少一個電容器電接觸的至少一個組件。 The gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 1, further comprising at least one component in electrical contact with at least one of said capacitors. 依據請求項22所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述組件係選自於包括電晶體，電容器，二極體，電阻器，壓敏電阻，電感器，保險絲，積體電路，過電壓放電裝置，感測器，開關，靜電放電抑制器，逆變器，整流器，濾波器和電隔離電源的組群之一的組件。 A gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 22, wherein said components are selected from the group consisting of transistors, capacitors, diodes, resistors, voltage sensitive Components of one of the group of resistors, inductors, fuses, integrated circuits, surge discharge devices, sensors, switches, electrostatic discharge suppressors, inverters, rectifiers, filters and galvanically isolated power supplies. 依據請求項22所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述電隔離電源是反向偏壓電源。 The gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 22, wherein the electrically isolated power supply is a reverse bias power supply. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，至少一個所述電容器包括一通孔。 The gate drive interposer with integrated passive devices for wide bandgap semiconductor devices according to claim 1, wherein at least one of said capacitors comprises a via. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述內部電極中的至少一個內部電極係通過通孔與一外部端子電接觸。 According to the gate drive interposer with integrated passive devices for wide bandgap semiconductor devices according to claim 1, at least one of the internal electrodes is in electrical contact with an external terminal through a via hole. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中該寬帶隙裝置還包括一散熱層，其中所述散熱層係位在所述嵌入式電容器和所述半導體裝置之間。 According to claim 1, the gate drive interposer with integrated passive components for a wide bandgap semiconductor device, wherein the wide bandgap device further includes a heat dissipation layer, wherein the heat dissipation layer is located on the embedded capacitor and between the semiconductor device. 依據請求項27所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，還包括穿過所述散熱層的至少一個通孔。 The gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 27, further comprising at least one via hole passing through the heat dissipation layer. 依據請求項28所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述通孔是一絕緣通孔。 The gate drive interposer with integrated passive devices for wide bandgap semiconductor devices according to claim 28, wherein the via is an insulating via. 依據請求項1所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，還包括至少一個開關。 The gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to Claim 1 further comprises at least one switch. 依據請求項30所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，包括與所述至少一個開關電並聯的一緩衝電容器。 A gate drive interposer with integrated passive components for a wide bandgap semiconductor device according to claim 30, comprising a snubber capacitor electrically connected in parallel with the at least one switch. 依據請求項31所述的用於寬帶隙半導體裝置的具有積體被動組件的柵極驅動中介器，其中，所述緩衝電容器是PDC。 The gate drive interposer with integrated passive components for wide bandgap semiconductor devices according to claim 31, wherein the snubber capacitor is a PDC.
TW110127397A 2019-08-05 2020-06-18 Gate drive interposer with integrated passives for wide band gap semiconductor devices TWI795855B (en)

Applications Claiming Priority (4)

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