TWI788100B - Semiconductor structure and method of forming the same - Google Patents

Semiconductor structure and method of forming the same Download PDF

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TWI788100B
TWI788100B TW110142506A TW110142506A TWI788100B TW I788100 B TWI788100 B TW I788100B TW 110142506 A TW110142506 A TW 110142506A TW 110142506 A TW110142506 A TW 110142506A TW I788100 B TWI788100 B TW I788100B
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dielectric layer
conductive layer
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TW202322219A (en
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溫文瑩
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新唐科技股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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Abstract

A method of forming a semiconductor structure includes sequentially forming an epitaxial layer and a semiconductor layer on the substrate. A trench is formed in the epitaxial layer and the semiconductor layer. A first dielectric layer is conformally formed in the trench. A first conductive layer is formed on the first dielectric layer. A first portion of the first dielectric layer is removed to expose a side surface of the first conductive layer so that a second portion of the first dielectric layer covers a side surface of the semiconductor layer. The second portion of the first dielectric layer is removed to expose the side surface of the semiconductor layer so that the first dielectric layer has a step portion. A second dielectric layer is formed on the exposed side surface of the semiconductor layer, the step portion of the first dielectric layer and the first conductive layer. A second conductive layer is formed on the second dielectric layer.

Description

半導體結構及其形成方法Semiconductor structures and methods of forming them

本揭露係關於半導體結構及其形成方法，特別是關於具有階梯部分的介電層的半導體結構及其形成方法。The present disclosure relates to semiconductor structures and methods of forming the same, and more particularly to semiconductor structures having a dielectric layer with stepped portions and methods of forming the same.

一般而言，金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor，MOSFET)具有各種形式，諸如包括溝槽結構的溝槽式MOSFET。而溝槽式MOSFET即因為具有溝槽結構，而能降低元件間距(device pitch)及閘極-汲極間電容(C gd)，可以有效降低導通電阻(R on)與開關損耗(switching loss)。 In general, a metal oxide semiconductor field effect transistor (MOSFET) has various forms, such as a trench MOSFET including a trench structure. The trench MOSFET has a trench structure, which can reduce the device pitch and gate-drain capacitance (C gd ), which can effectively reduce the on-resistance (R on ) and switching loss (switching loss) .

溝槽式MOSFET更發展出遮蔽閘極溝槽式(shielded gate trench，SGT)MOSFET，以在SGT-MOSFET中設置稱為遮蔽電極(shield electrode)的源極電極於閘極電極的下方，而前述遮蔽電極能夠作為場板(field plate)來調整電場的分布。然而，不同的遮蔽電極的設置形式會導致不同的電場分布的態樣，但是仍然無法顯著降低電場的最大值，故而難以顯著提升半導體結構的崩潰電壓。The trench MOSFET has developed a shielded gate trench (SGT) MOSFET, in order to set the source electrode called the shield electrode (shield electrode) below the gate electrode in the SGT-MOSFET, and the aforementioned The shielding electrode can act as a field plate to adjust the distribution of the electric field. However, different configurations of the shielding electrodes will result in different electric field distributions, but the maximum value of the electric field cannot be significantly reduced, so it is difficult to significantly increase the breakdown voltage of the semiconductor structure.

是以，雖然現存的半導體結構及其形成方法已逐步滿足它們既定的用途，但它們仍未在各方面皆徹底的符合要求。因此，關於進一步加工後可作為SGT-MOSFET的半導體結構及其形成方法仍有一些問題需要克服。Therefore, although existing semiconductor structures and methods of forming them have gradually met their intended uses, they have not yet fully met the requirements in all aspects. Therefore, there are still some problems to be overcome regarding the semiconductor structure and its formation method that can be further processed as SGT-MOSFET.

鑒於前述問題，本揭露藉由設置具有不同厚度的介電層，舉例而言：在剖面圖觀察時具有階梯部分的介電層，調整從基板下方的汲極區至漂移區之間的電場分布，使得電場分布均勻，進而提升後續形成的SGT-MOSFET的崩潰電壓。此外，本揭露藉由設置包括階梯部分及突出部分的第二導電層作為閘極電極，來調整閘極電極與閘極電極下方的遮蔽電極之間的相對位置，進而降低電場最大值，使得電場分布更為均勻。據此，能更提升後續形成的SGT-MOSFET的崩潰電壓。In view of the aforementioned problems, the present disclosure adjusts the electric field distribution from the drain region to the drift region under the substrate by arranging dielectric layers with different thicknesses, for example, a dielectric layer having a stepped portion when observed in a cross-sectional view. , so that the electric field distribution is uniform, and then the breakdown voltage of the subsequently formed SGT-MOSFET is increased. In addition, the present disclosure adjusts the relative position between the gate electrode and the shielding electrode below the gate electrode by setting the second conductive layer including the stepped portion and the protruding portion as the gate electrode, thereby reducing the maximum value of the electric field, so that the electric field more evenly distributed. Accordingly, the breakdown voltage of the subsequently formed SGT-MOSFET can be further increased.

根據一些實施例，提供半導體結構的形成方法。半導體結構的形成方法包括：依序形成磊晶層及半導體層在基板上。形成溝槽在磊晶層及半導體層中。順應性地形成第一介電層在溝槽中。形成第一導電層在第一介電層上。移除第一介電層的第一部分，以暴露第一導電層的側表面且使第一介電層的第二部分覆蓋半導體層的側表面。移除第一介電層的第二部分，以暴露半導體層的側表面，使得第一介電層具有階梯部分。形成第二介電層在經暴露的半導體層的側表面、第一介電層的階梯部分及第一導電層上。形成第二導電層於第二介電層上。According to some embodiments, methods of forming semiconductor structures are provided. The method for forming the semiconductor structure includes: sequentially forming an epitaxial layer and a semiconductor layer on the substrate. Grooves are formed in the epitaxial layer and the semiconductor layer. A first dielectric layer is conformally formed in the trench. A first conductive layer is formed on the first dielectric layer. The first portion of the first dielectric layer is removed to expose the side surface of the first conductive layer and the second portion of the first dielectric layer covers the side surface of the semiconductor layer. A second portion of the first dielectric layer is removed to expose a side surface of the semiconductor layer such that the first dielectric layer has a stepped portion. A second dielectric layer is formed on the exposed side surface of the semiconductor layer, the stepped portion of the first dielectric layer, and the first conductive layer. A second conductive layer is formed on the second dielectric layer.

根據一些實施例，提供半導體結構。半導體結構包括：基板、磊晶層、第一介電層、第一導電層、第二介電層及第二導電層。基板具有第一導電型態。磊晶層具有第一導電型態。磊晶層設置在基板上。半導體層具有不同於第一導電型態的第二導電型態。半導體層設置在磊晶層上。磊晶層與半導體層包括溝槽。第一介電層設置在溝槽中。第一介電層具有與溝槽的側表面接觸的階梯部分。第一導電層設置在第一介電層上。第二介電層設置在第一導電層的階梯部分的頂表面與側表面及第一導電層的頂表面與側表面上。第二導電層設置在第二介電層上。According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a substrate, an epitaxial layer, a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer. The substrate has a first conductivity type. The epitaxial layer has a first conductivity type. The epitaxial layer is disposed on the substrate. The semiconductor layer has a second conductivity type different from the first conductivity type. The semiconductor layer is disposed on the epitaxial layer. The epitaxial layer and the semiconductor layer include grooves. The first dielectric layer is disposed in the trench. The first dielectric layer has a stepped portion in contact with a side surface of the trench. The first conductive layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the top and side surfaces of the stepped portion of the first conductive layer and the top and side surfaces of the first conductive layer. The second conductive layer is disposed on the second dielectric layer.

本揭露的半導體結構可應用於多種類型的半導體裝置，為讓本揭露的部件及優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下。The semiconductor structure of the present disclosure can be applied to various types of semiconductor devices. In order to make the components and advantages of the present disclosure more comprehensible, preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings.

以下揭露提供了很多不同的實施例或範例，用於實施所提供的半導體結構的不同部件。各部件及其配置的具體範例描述如下，以簡化本揭露實施例。當然，這些僅僅是範例，並非用以限定本揭露。舉例而言，敘述中若提及第一部件形成在第二部件之上，可能包括第一部件及第二部件直接接觸的實施例，也可能包括額外的部件形成在第一部件及第二部件之間，使得它們不直接接觸的實施例。此外，本揭露實施例可能在不同的範例中重複元件符號及/或字符。如此重複是為了簡明及清楚，而非用以表示所討論的不同實施例及/或態樣之間的關係。The following disclosure provides many different embodiments or examples for implementing different components of the provided semiconductor structures. Specific examples of each component and its configuration are described below to simplify the embodiments of the present disclosure. Of course, these are just examples, not intended to limit the present disclosure. For example, if it is mentioned in the description that the first component is formed on the second component, it may include an embodiment in which the first component and the second component are in direct contact, and may also include an additional component formed on the first component and the second component between them so that they are not in direct contact with each other. In addition, the embodiments of the present disclosure may repeat element symbols and/or characters in different examples. This repetition is for brevity and clarity and is not intended to represent a relationship between the different embodiments and/or aspects discussed.

以下描述實施例的一些變化。在不同圖式及說明的實施例中，相似的元件符號被用來標明相似的元件。可以理解的是，在方法的之前、期間中、之後可以提供額外的操作，且一些敘述的操作可為了前述方法的其他實施例被取代或刪除。Some variations of the embodiment are described below. In the different drawings and described embodiments, similar reference numerals are used to designate similar components. It can be understood that additional operations may be provided before, during, and after the method, and some described operations may be replaced or deleted for other embodiments of the foregoing method.

再者，空間上的相關用語，例如「在…上」、「在…下」、「在…上方」、「在…下方」及類似的用詞，除了包括圖式繪示的方位外，也包括使用或操作中的裝置的不同方位。當裝置被轉向至其他方位時(旋轉90度或其他方位)，則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。在此，「大約」、「實質上」或其類似用語通常表示在一給定值或範圍的20%之內，較佳是10%之內，且更佳是5%之內，或3%之內，或2%之內，或1%之內，或0.5%之內。應注意的是，說明書中所提供的數量為大約的數量，亦即在沒有特定說明「大約」、「實質上」或其類似用語的情況下，仍可隱含「大約」、「實質上」或其類似用語的含義。Furthermore, terms related to space, such as "on", "under", "above", "below" and similar expressions, in addition to including the orientation shown in the diagram, also include Including different orientations of the device in use or operation. When the device is turned to another orientation (rotated 90 degrees or otherwise), the spatially relative descriptions used herein can also be read in the rotated orientation. Here, "about", "substantially" or similar terms generally mean within 20%, preferably within 10%, and more preferably within 5%, or 3% of a given value or range Within, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, "approximately" and "substantially" can still be implied without specifying "approximately", "substantially" or similar terms or the meaning of similar terms.

第1至11圖是根據本揭露的一些實施例，說明形成半導體結構1在各個階段的剖面示意圖。1 to 11 are schematic cross-sectional views illustrating various stages of forming the semiconductor structure 1 according to some embodiments of the present disclosure.

參照第1圖，在基板100上依序形成磊晶層200及半導體層300。在一些實施例中，基板100可以為或包括塊材半導體(bulk semiconductor)基板、絕緣體上覆半導體(semiconductor-on-insulator，SOI)基板或其類似基板。一般而言，絕緣體上覆半導體基板包括形成於絕緣體上的半導體膜層。舉例而言，前述絕緣層可包括或可為氧化矽(silicon oxide)層、氮化矽(silicon nitride)層、多晶矽(poly-silicon)層或其組合，且提供前述絕緣層於矽(silicon)基板或氮化鋁(AlN)基板上。基板100可為經摻雜的基板或未摻雜的基板。舉例而言，使用P型或N型摻質(dopant)來摻雜。Referring to FIG. 1 , an epitaxial layer 200 and a semiconductor layer 300 are sequentially formed on a substrate 100 . In some embodiments, the substrate 100 may be or include a bulk semiconductor (bulk semiconductor) substrate, a semiconductor-on-insulator (SOI) substrate, or the like. Generally, a semiconductor-on-insulator substrate includes a semiconductor film layer formed on an insulator. For example, the aforementioned insulating layer may include or may be a silicon oxide (silicon oxide) layer, a silicon nitride (silicon nitride) layer, a polysilicon (poly-silicon) layer or a combination thereof, and the aforementioned insulating layer is provided on silicon (silicon) substrate or aluminum nitride (AlN) substrate. The substrate 100 may be a doped substrate or an undoped substrate. For example, P-type or N-type dopants are used for doping.

基板100亦可為其他種類的基板，例如多層(multi-layered)基板或漸變(gradient)基板。在一些實施例中，基板100可為元素半導體，且前述元素半導體可包括：矽(silicon)、鍺(germanium)；基板100亦可為化合物半導體，且前述化合物半導體可包括：舉例而言，碳化矽(silicon carbide)、砷化鎵(gallium arsenide)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide)，但不限於此；基板100亦可為合金半導體，且前述合金半導體可包括：舉例而言，SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP或其任意組合，但不限於此。在一些實施例中，基板100為矽基板。The substrate 100 can also be other types of substrates, such as multi-layered substrates or gradient substrates. In some embodiments, the substrate 100 can be an elemental semiconductor, and the aforementioned elemental semiconductor can include: silicon (silicon), germanium (germanium); the substrate 100 can also be a compound semiconductor, and the aforementioned compound semiconductor can include: for example, carbonized Silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide, but not Limited to this; the substrate 100 can also be an alloy semiconductor, and the aforementioned alloy semiconductor can include: for example, SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP and/or GaInAsP or any combination thereof, but not limited thereto. In some embodiments, the substrate 100 is a silicon substrate.

在一些實施例中，磊晶層200及/或半導體層300可包括矽、鍺、矽鍺、III-V族化合物或其組合。前述磊晶層200及/或半導體層300可藉由諸如有機金屬化學氣相沉積(Metal Organic Chemical Vapor Deposition，MOCVD)、原子層沉積(Atomic Layer Deposition，ALD)、分子束磊晶(Molecular Beam Epitaxy，MBE)、液相磊晶(Liquid Phase Epitaxy，LPE)、其組合、或其類似製程的沉積製程或磊晶製程來形成。In some embodiments, the epitaxial layer 200 and/or the semiconductor layer 300 may include silicon, germanium, silicon germanium, III-V compounds or combinations thereof. The aforementioned epitaxial layer 200 and/or semiconductor layer 300 can be deposited by metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD), atomic layer deposition (Atomic Layer Deposition, ALD), molecular beam epitaxy (Molecular Beam Epitaxy) , MBE), liquid phase epitaxy (Liquid Phase Epitaxy, LPE), a combination thereof, or a deposition process or an epitaxy process of a similar process.

在一些實施例，基板100及磊晶層200具有第一導電型態，且半導體層300具有不同於第一導電型態的第二導電型態。在一些實施例中，基板100及磊晶層200具有的第一導電型態為N型，則半導體層300具有的第二導電型態為P型。在一些實施例中，基板100及磊晶層200具有的第一導電型態為P型，則半導體層300具有的第二導電型態為N型。第一導電型態與第二導電型態可依據需求調整，同時，摻雜濃度、摻雜深度及摻雜區域的大小亦可依據需求調整。在一些實施例中，亦可於後續形成作為閘極電極的第二導電層之後，再形成半導體層300於磊晶層200上。In some embodiments, the substrate 100 and the epitaxial layer 200 have a first conductivity type, and the semiconductor layer 300 has a second conductivity type different from the first conductivity type. In some embodiments, the first conductivity type of the substrate 100 and the epitaxial layer 200 is N-type, and the second conductivity type of the semiconductor layer 300 is P-type. In some embodiments, the first conductivity type of the substrate 100 and the epitaxial layer 200 is P-type, and the second conductivity type of the semiconductor layer 300 is N-type. The first conductive type and the second conductive type can be adjusted according to requirements, and meanwhile, the doping concentration, doping depth and size of the doped region can also be adjusted according to requirements. In some embodiments, the semiconductor layer 300 may be formed on the epitaxial layer 200 after the second conductive layer serving as the gate electrode is subsequently formed.

為了便於說明，在後續實施例中，以基板100及磊晶層200具有N型導電型態，且半導體層300具有P型導電型態來描述。For ease of description, in the subsequent embodiments, the substrate 100 and the epitaxial layer 200 have an N-type conductivity, and the semiconductor layer 300 has a P-type conductivity for description.

繼續參照第1圖，在一些實施例中，依序形成第一硬遮罩310及第二硬遮罩320在半導體層300上。具體而言，形成第一硬遮罩310在半導體層300上，再形成第二硬遮罩320在第一硬遮罩310上。第一硬遮罩310及第二硬遮罩320可為具有開口的圖案化硬遮罩，以使第一硬遮罩310及第二硬遮罩320下方的半導體層300及磊晶層200圖案化。因此，藉由蝕刻製程來移除半導體層300的一部分及磊晶層200的一部分，來形成溝槽201在半導體層300及磊晶層200中。在一些實施例中，半導體層300及磊晶層200包括溝槽201，且溝槽201貫穿半導體層300而不貫穿磊晶層200。Continuing to refer to FIG. 1 , in some embodiments, a first hard mask 310 and a second hard mask 320 are sequentially formed on the semiconductor layer 300 . Specifically, a first hard mask 310 is formed on the semiconductor layer 300 , and a second hard mask 320 is formed on the first hard mask 310 . The first hard mask 310 and the second hard mask 320 may be patterned hard masks with openings to pattern the semiconductor layer 300 and the epitaxial layer 200 under the first hard mask 310 and the second hard mask 320 change. Therefore, a portion of the semiconductor layer 300 and a portion of the epitaxial layer 200 are removed by an etching process to form the trench 201 in the semiconductor layer 300 and the epitaxial layer 200 . In some embodiments, the semiconductor layer 300 and the epitaxial layer 200 include a trench 201 , and the trench 201 penetrates the semiconductor layer 300 but does not penetrate the epitaxial layer 200 .

在一些實施例中，蝕刻製程可包括乾式蝕刻、濕式蝕刻或其他蝕刻製程。乾式蝕刻可包含但不限於電漿蝕刻、無電漿氣體蝕刻、濺射蝕刻(sputter etching)、離子研磨(ion milling)、反應離子蝕刻(reactive ion etching，RIE)。濕式蝕刻可包含但不限於使用酸性溶液、鹼性溶液或是溶劑來移除待移除結構的至少一部分。In some embodiments, the etching process may include dry etching, wet etching, or other etching processes. Dry etching may include, but is not limited to, plasma etching, plasma-free gas etching, sputter etching, ion milling, and reactive ion etching (RIE). Wet etching may include, but is not limited to, using an acidic solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed.

在一些實施例中，第一硬遮罩310及第二硬遮罩320可包括或可為諸如氧化矽的氧化物、諸如氮化矽的氮化物、諸如氮氧化矽的氮氧化物、其類似物或其組合。在一些實施例中，第一硬遮罩310可為氧化矽，且第二硬遮罩320可為氮化矽。在一些實施例中，可在此先移除或省略第一硬遮罩310及第二硬遮罩320。In some embodiments, the first hard mask 310 and the second hard mask 320 may include or may be an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, the like. substances or combinations thereof. In some embodiments, the first hard mask 310 may be silicon oxide, and the second hard mask 320 may be silicon nitride. In some embodiments, first hard mask 310 and second hard mask 320 may be removed or omitted here.

參照第2圖，順應性地(conformally)形成第一介電層330在溝槽201中。在一些實施例中，第一介電層330具有對應於溝槽201的形狀，亦即第一介電層330可形成溝槽。在一些實施例中，第一介電層330覆蓋半導體層300的頂表面及溝槽201的側表面及底表面。具體而言，第一介電層330可覆蓋第二硬遮罩320的頂表面及側表面、第一硬遮罩310的側表面及半導體層300的側表面及磊晶層200的側表面。Referring to FIG. 2 , the first dielectric layer 330 is conformally formed in the trench 201 . In some embodiments, the first dielectric layer 330 has a shape corresponding to the trench 201 , that is, the first dielectric layer 330 can form a trench. In some embodiments, the first dielectric layer 330 covers the top surface of the semiconductor layer 300 and the side surfaces and the bottom surface of the trench 201 . Specifically, the first dielectric layer 330 may cover the top and side surfaces of the second hard mask 320 , the side surfaces of the first hard mask 310 , the side surfaces of the semiconductor layer 300 , and the side surfaces of the epitaxial layer 200 .

在一些實施例中，第一介電層330可藉由沉積製程或熱氧化製程來形成。沉積製程可為低壓化學氣相沉積法(low pressure chemical vapor deposition，LPCVD)、低溫化學氣相沉積法(low temperature chemical vapor deposition，LTCVD)、快速升溫化學氣相沉積法(rapid thermal chemical vapor deposition，RTCVD)、PECVD、原子層沉積法(atomic layer deposition，ALD)或其它合適的沉積製程。In some embodiments, the first dielectric layer 330 may be formed by a deposition process or a thermal oxidation process. The deposition process can be low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid temperature chemical vapor deposition (rapid thermal chemical vapor deposition, RTCVD), PECVD, atomic layer deposition (atomic layer deposition, ALD) or other suitable deposition processes.

在一些實施例中，第一介電層330可包括或可為氧化矽、氮化矽、氮氧化矽、介電材料、其它任何合適的介電材料或其組合。前述介電材料可包括金屬氧化物、金屬氮化物、金屬矽化物、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽化物、金屬的氮氧化物、金屬鋁酸鹽、其類似物或其組合。在一些實施例中，第一介電層330可為氧化物。在一些實施例中，第一介電層330可為氧化矽。在一些實施例中，第一介電層330可具有均勻的第一厚度t1。可根據電性需求調整第一介電層330的第一厚度t1。In some embodiments, the first dielectric layer 330 may include or may be silicon oxide, silicon nitride, silicon oxynitride, a dielectric material, any other suitable dielectric material, or a combination thereof. The foregoing dielectric materials may include metal oxides, metal nitrides, metal silicides, transition metal oxides, transition metal nitrides, transition metal silicides, metal oxynitrides, metal aluminates, the like, or combinations thereof . In some embodiments, the first dielectric layer 330 may be an oxide. In some embodiments, the first dielectric layer 330 can be silicon oxide. In some embodiments, the first dielectric layer 330 may have a uniform first thickness t1. The first thickness t1 of the first dielectric layer 330 can be adjusted according to electrical requirements.

參照第3圖，形成第一導電層400在第一介電層330上。在一些實施例中，第一導電層400直接形成於第一介電層330上。第一導電層400可藉由化學氣相沉積、濺鍍法、電阻加熱蒸鍍法、電子束蒸鍍法、或其它任何適合的沉積製程來形成。在一些實施例中，第一導電層400的頂表面低於磊晶層200的頂表面。Referring to FIG. 3 , a first conductive layer 400 is formed on the first dielectric layer 330 . In some embodiments, the first conductive layer 400 is directly formed on the first dielectric layer 330 . The first conductive layer 400 can be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process. In some embodiments, the top surface of the first conductive layer 400 is lower than the top surface of the epitaxial layer 200 .

在一些實施例中，可先毯覆式地(blanketly)形成第一導電材料在第一介電層330形成的溝槽中，接著執行回蝕(etch back)製程，來形成第一導電層400。在一些實施例中，第一導電層400可具有第一高度h1。在一些實施例中，第一導電層400的回蝕程度可影響第一導電層400的第一高度h1，且第一導電層400的回蝕程度可根據後續電性需求而調整。In some embodiments, the first conductive layer 400 can be formed by blanketly forming the first conductive material in the trench formed by the first dielectric layer 330 and then performing an etch back process. . In some embodiments, the first conductive layer 400 may have a first height h1. In some embodiments, the etch back degree of the first conductive layer 400 can affect the first height h1 of the first conductive layer 400 , and the etch back degree of the first conductive layer 400 can be adjusted according to subsequent electrical requirements.

在一些實施例中，第一導電材料可包括多晶矽、非晶矽、金屬、金屬氮化物、導電金屬氧化物、其他合適的材料或其組合。在一些實施例中，第一導電層400的第一導電材料可為多晶矽。在一些實施例中，第一介電層330完全覆蓋第一導電層400的側表面，且暴露第一導電層400的頂表面。In some embodiments, the first conductive material may include polysilicon, amorphous silicon, metal, metal nitride, conductive metal oxide, other suitable materials, or combinations thereof. In some embodiments, the first conductive material of the first conductive layer 400 may be polysilicon. In some embodiments, the first dielectric layer 330 completely covers the side surfaces of the first conductive layer 400 and exposes the top surface of the first conductive layer 400 .

參照第4圖，在一些實施例中，執行第一移除製程，來移除第一介電層330的第一部分，以暴露第一導電層400的側表面及頂表面，且保留第一介電層的一部分以覆蓋半導體層300的側表面。在一些實施例中，移除位於第二硬遮罩320上的第一介電層330，且移除位於第二硬遮罩320的側表面、第一硬遮罩310的側表面、半導體層300的側表面及磊晶層200的側表面上的部分第一介電層330。因此，來減薄位於溝槽201的側壁上的第一介電層330的厚度。如第4圖所示，經減薄的第一介電層330可包括覆蓋第二硬遮罩320的側表面、第一硬遮罩310的側表面及半導體層300的側表面的第二部分。Referring to FIG. 4, in some embodiments, a first removal process is performed to remove the first portion of the first dielectric layer 330 to expose the side surface and the top surface of the first conductive layer 400, and to retain the first dielectric layer. part of the electrical layer to cover the side surface of the semiconductor layer 300 . In some embodiments, the first dielectric layer 330 on the second hard mask 320 is removed, and the side surfaces of the second hard mask 320, the side surfaces of the first hard mask 310, and the semiconductor layer are removed. 300 and a portion of the first dielectric layer 330 on the side surface of the epitaxial layer 200 . Therefore, the thickness of the first dielectric layer 330 on the sidewall of the trench 201 is reduced. As shown in FIG. 4, the thinned first dielectric layer 330 may include a second portion covering the side surfaces of the second hard mask 320, the side surfaces of the first hard mask 310, and the side surfaces of the semiconductor layer 300. .

在一些實施例中，在執行第一移除製程之後，第一介電層330可具有沿著遠離基板100的方向向上減少的厚度。在一些實施例中，在溝槽201的下部的第一介電層330具有第一厚度t1，在溝槽201的上部的第一介電層330具有第二厚度t2，且第一厚度t1大於第二厚度t2。據此，第一介電層300的厚度從第一厚度t1減薄至第二厚度t2。In some embodiments, after performing the first removal process, the first dielectric layer 330 may have a thickness that decreases upward along a direction away from the substrate 100 . In some embodiments, the first dielectric layer 330 on the lower portion of the trench 201 has a first thickness t1, the first dielectric layer 330 on the upper portion of the trench 201 has a second thickness t2, and the first thickness t1 is greater than The second thickness t2. Accordingly, the thickness of the first dielectric layer 300 is reduced from the first thickness t1 to the second thickness t2.

在一些實施例中，第一移除製程可為乾式蝕刻製程。因此，在執行第一移除製程之後，第一介電層330具有凹狀頂表面。第一介電層330的凹狀頂表面的輪廓可根據蝕刻參數來調整。在一些實施例中，第一介電層330具有凹狀頂表面可為凹形、U形、V形、弧形、半球形、半橢圓形或任何合適的形狀。In some embodiments, the first removal process may be a dry etching process. Therefore, after performing the first removal process, the first dielectric layer 330 has a concave top surface. The profile of the concave top surface of the first dielectric layer 330 can be adjusted according to etching parameters. In some embodiments, the concave top surface of the first dielectric layer 330 may be concave, U-shaped, V-shaped, curved, hemispherical, semi-elliptical, or any suitable shape.

在一些實施例中，第一導電層400可更包括突出部分401。在一些實施例中，在執行第一移除製程之後，暴露第一導電層400的突出部分401的側表面及頂表面。在一些實施例中，第一導電層400的突出部分401從第一介電層330的凹狀頂表面向上突出。In some embodiments, the first conductive layer 400 may further include a protruding portion 401 . In some embodiments, after performing the first removal process, the side surface and the top surface of the protruding portion 401 of the first conductive layer 400 are exposed. In some embodiments, the protruding portion 401 of the first conductive layer 400 protrudes upward from the concave top surface of the first dielectric layer 330 .

如第4圖所示，第一導電層400的突出部分401具有第二高度h2。在一些實施例中，第二高度h2大於0，因此後續形成的第二導電層能夠覆蓋第一導電層400的突出部分401的側表面。在一些實施例中，第二高度h2可占第一高度h1的15%~60%。舉例而言，第二高度h2可占第一高度h1的15%、20%、25%、30%、35%、40%、45%、50%、55%、60%或前述數值所組成的任意範圍，但本揭露不限於此。在一些實施例中，第二高度h2可影響後續形成的第二導電層覆蓋第一導電層的側表面的面積大小。在一些實施例中，當第二高度h2越大，後續形成的第二導電層可覆蓋第一導電層的側表面的面積更大。在一些實施例中，第一導電層400的突出部分401可具有弧狀側表面。在另一些實施例中，藉由調整第一移除製程的參數，第一導電層400的突出部分401可具有實質上垂直的側表面。As shown in FIG. 4, the protruding portion 401 of the first conductive layer 400 has a second height h2. In some embodiments, the second height h2 is greater than 0, so that the subsequently formed second conductive layer can cover the side surface of the protruding portion 401 of the first conductive layer 400 . In some embodiments, the second height h2 may account for 15%˜60% of the first height h1. For example, the second height h2 may account for 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60% of the first height h1 or a combination of the aforementioned values Arbitrary scope, but the present disclosure is not limited thereto. In some embodiments, the second height h2 may affect the area of the side surface of the first conductive layer covered by the subsequently formed second conductive layer. In some embodiments, when the second height h2 is larger, the subsequently formed second conductive layer can cover a larger area of the side surface of the first conductive layer. In some embodiments, the protruding portion 401 of the first conductive layer 400 may have an arc-shaped side surface. In other embodiments, by adjusting the parameters of the first removal process, the protruding portion 401 of the first conductive layer 400 may have a substantially vertical side surface.

在另一些實施例中，執行第一移除製程，以移除位於第二硬遮罩320的頂表面及側表面、第一硬遮罩310的側表面及半導體層300的側表面上的第一介電層330，而暴露第二硬遮罩320的頂表面及側表面、第一硬遮罩310的側表面及半導體層300的側表面。接著，執行熱氧化製程，以在第一硬遮罩310的側表面及半導體層300的側表面上形成為氧化矽的側壁。在一些實施例中，由於第一介電層330為氧化矽，且在第一硬遮罩310的側表面及半導體層300的側表面上形成的側壁亦為氧化矽，所以第一介電層330與前述側壁可實質上不具有界面。因此，前述側壁可視為第一介電層330的一部分。In other embodiments, the first removal process is performed to remove the first hard mask 320 on the top surface and side surface, the first hard mask 310 side surface and the side surface of the semiconductor layer 300 on the first surface. A dielectric layer 330 exposes the top and side surfaces of the second hard mask 320 , the side surfaces of the first hard mask 310 and the side surfaces of the semiconductor layer 300 . Next, a thermal oxidation process is performed to form silicon oxide sidewalls on the side surfaces of the first hard mask 310 and the side surfaces of the semiconductor layer 300 . In some embodiments, since the first dielectric layer 330 is silicon oxide, and the sidewalls formed on the side surfaces of the first hard mask 310 and the side surfaces of the semiconductor layer 300 are also silicon oxide, the first dielectric layer 330 may have substantially no interface with the aforementioned sidewall. Therefore, the aforementioned sidewall can be regarded as a part of the first dielectric layer 330 .

參照第5圖，在一些實施例中，形成犧牲層500於第一導電層400及第一介電層330上，以使犧牲層500覆蓋第一導電層400的側表面及第一介電層330的頂表面。具體而言，犧牲層500可覆蓋第一介電層330的的凹狀頂表面。在一些實施例中，犧牲層500可藉由化學氣相沉積、濺鍍法、電阻加熱蒸鍍法、電子束蒸鍍法、或其它任何適合的沉積製程來形成。在一些實施例中，可先毯覆式地填充犧牲材料在第一介電層330及第一導電層400共同形成的溝槽中，接著執行回蝕製程，來形成犧牲層500。在一些實施例中，犧牲層500的頂表面低於磊晶層200的頂表面，且犧牲層500的頂表面高於第一導電層400的頂表面。在一些實施例中，犧牲層500的回蝕程度影響第一介電層330的高度，且犧牲層500的回蝕程度可根據後續電性需求而調整。5, in some embodiments, a sacrificial layer 500 is formed on the first conductive layer 400 and the first dielectric layer 330, so that the sacrificial layer 500 covers the side surface of the first conductive layer 400 and the first dielectric layer 330 top surface. Specifically, the sacrificial layer 500 may cover the concave top surface of the first dielectric layer 330 . In some embodiments, the sacrificial layer 500 can be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process. In some embodiments, the sacrificial layer 500 can be formed by blanket filling the trench formed by the first dielectric layer 330 and the first conductive layer 400 with a sacrificial material first, and then performing an etch-back process. In some embodiments, the top surface of the sacrificial layer 500 is lower than the top surface of the epitaxial layer 200 , and the top surface of the sacrificial layer 500 is higher than the top surface of the first conductive layer 400 . In some embodiments, the etch-back degree of the sacrificial layer 500 affects the height of the first dielectric layer 330 , and the etch-back degree of the sacrificial layer 500 can be adjusted according to subsequent electrical requirements.

在一些實施例中，犧牲材料可包括光阻材料或任何可選擇性移除的犧牲材料。在一些實施例中，犧牲層500的犧牲材料可為光阻材料，因此可藉由簡易的光微影製程來形成犧牲層500。在一些實施例中，犧牲層500完全覆蓋第一導電層400的突出部分401的頂表面及側表面。在一些實施例中，犧牲層500覆蓋第一介電層330的側表面的一部分，且暴露第一介電層330的側表面的另一部分。In some embodiments, the sacrificial material may include photoresist material or any selectively removable sacrificial material. In some embodiments, the sacrificial material of the sacrificial layer 500 can be a photoresist material, so the sacrificial layer 500 can be formed by a simple photolithography process. In some embodiments, the sacrificial layer 500 completely covers the top surface and the side surface of the protruding portion 401 of the first conductive layer 400 . In some embodiments, the sacrificial layer 500 covers a part of the side surface of the first dielectric layer 330 and exposes another part of the side surface of the first dielectric layer 330 .

參照第6圖，在一些實施例中，藉由犧牲層500作為蝕刻遮罩來執行第二移除製程，以移除第一介電層330的第二部分，使得第一介電層330具有階梯部分331。換句話說，移除位於溝槽201的上部的第一介電層330，以暴露第二硬遮罩320的側表面、第一硬遮罩310的側表面、半導體層300的側表面及磊晶層200的側表面。在一些實施例中，第二移除製程可為濕式蝕刻製程。Referring to FIG. 6, in some embodiments, the second removal process is performed by using the sacrificial layer 500 as an etching mask to remove the second portion of the first dielectric layer 330, so that the first dielectric layer 330 has The stepped portion 331 . In other words, the first dielectric layer 330 located on the upper portion of the trench 201 is removed to expose the side surfaces of the second hard mask 320, the side surfaces of the first hard mask 310, the side surfaces of the semiconductor layer 300 and the epitaxial surface. The side surface of the crystal layer 200. In some embodiments, the second removal process may be a wet etching process.

在一些實施例中，第一介電層330的階梯部分331頂表面低於磊晶層200的頂表面。在一些實施例中，第一介電層330的階梯部分331的頂表面介於犧牲層500的頂表面及第一導電層400的頂表面之間。亦即，第一介電層330的階梯部分331的頂表面可低於犧牲層500的頂表面，且第一介電層330的階梯部分331的頂表面可高於第一導電層400的頂表面。在一些實施例中，犧牲層500與溝槽201的側表面間隔一距離。In some embodiments, the top surface of the stepped portion 331 of the first dielectric layer 330 is lower than the top surface of the epitaxial layer 200 . In some embodiments, the top surface of the stepped portion 331 of the first dielectric layer 330 is between the top surface of the sacrificial layer 500 and the top surface of the first conductive layer 400 . That is, the top surface of the stepped portion 331 of the first dielectric layer 330 may be lower than the top surface of the sacrificial layer 500 , and the top surface of the stepped portion 331 of the first dielectric layer 330 may be higher than the top surface of the first conductive layer 400 . surface. In some embodiments, the sacrificial layer 500 is separated from the side surface of the trench 201 by a distance.

在一些實施例中，第一介電層330的階梯部分331與溝槽201的側表面接觸。在一些實施例中，第一介電層330的階梯部分331介於溝槽201與犧牲層500之間。在一些實施例中，第一介電層330具有分別接觸溝槽201的相對側表面的一對階梯部分331，且第一介電層330的前述的一對階梯部分331之間具有凹狀頂表面。In some embodiments, the stepped portion 331 of the first dielectric layer 330 contacts the side surface of the trench 201 . In some embodiments, the stepped portion 331 of the first dielectric layer 330 is between the trench 201 and the sacrificial layer 500 . In some embodiments, the first dielectric layer 330 has a pair of stepped portions 331 respectively contacting the opposite side surfaces of the trench 201, and a concave top is formed between the aforementioned pair of stepped portions 331 of the first dielectric layer 330. surface.

需要特別說明的是，由於本揭露設置犧牲層500於第一介電層330及第一導電層400上，因此可藉由犧牲層500來保護第一介電層330及第一導電層400的頂部輪廓。也就是說，藉由設置犧牲層500來保留如第4圖所示的第一介電層330的凹狀頂表面的輪廓。此外，藉由保留如第4圖所示的第一介電層330的一部分在溝槽201的側表面上，在執行第二移除製程時，可形成如第6圖所示的具有階梯部分331的第一介電層330。在一些實施例中，第一介電層330的階梯部分331可具有實質上為平坦的頂表面。是以，第一介電層330在鄰接溝槽201的側表面處可具有平坦頂表面，且第一介電層330在相鄰的平坦頂表面之間可具有凹狀頂表面。It should be noted that since the present disclosure sets the sacrificial layer 500 on the first dielectric layer 330 and the first conductive layer 400, the sacrificial layer 500 can be used to protect the first dielectric layer 330 and the first conductive layer 400. top profile. That is, the profile of the concave top surface of the first dielectric layer 330 as shown in FIG. 4 is preserved by disposing the sacrificial layer 500 . In addition, by keeping a portion of the first dielectric layer 330 on the side surface of the trench 201 as shown in FIG. 4, the portion with a step as shown in FIG. 331 of the first dielectric layer 330 . In some embodiments, the stepped portion 331 of the first dielectric layer 330 may have a substantially flat top surface. Accordingly, the first dielectric layer 330 may have flat top surfaces adjacent to side surfaces of the trenches 201 , and the first dielectric layer 330 may have concave top surfaces between adjacent flat top surfaces.

參照第7圖，在一些實施例中，移除犧牲層500，以暴露第一導電層400的側表面與頂表面及第一介電層330。具體而言，暴露第一導電層400的突出部分401的側表面及頂表面及第一介電層330的階梯部分331及介於階梯部分331之間的凹狀頂表面。在一些實施例中，可藉由任何合適的製程來移除犧牲層500。舉例而言，當犧牲層500為光阻層時，可藉由灰化製程來移除犧牲層500。Referring to FIG. 7 , in some embodiments, the sacrificial layer 500 is removed to expose the side and top surfaces of the first conductive layer 400 and the first dielectric layer 330 . Specifically, the side surface and the top surface of the protruding portion 401 of the first conductive layer 400 and the stepped portion 331 of the first dielectric layer 330 and the concave top surface between the stepped portion 331 are exposed. In some embodiments, the sacrificial layer 500 may be removed by any suitable process. For example, when the sacrificial layer 500 is a photoresist layer, the sacrificial layer 500 can be removed by an ashing process.

參照第8圖，在一些實施例中，形成第二介電層600在第一介電層330及第一導電層400上。具體而言，順應性地形成第二介電層600在第一介電層330的階梯部分331的頂表面與側表面及第一導電層400的突出部分401的頂表面及側表面上。在一些實施例中，形成第二介電層600的材料與製程可與形成第一介電層330的材料與製程相同或不同。在一些實施例中，第二介電層600可為氧化矽。Referring to FIG. 8 , in some embodiments, a second dielectric layer 600 is formed on the first dielectric layer 330 and the first conductive layer 400 . Specifically, the second dielectric layer 600 is conformally formed on the top and side surfaces of the stepped portion 331 of the first dielectric layer 330 and the top and side surfaces of the protruding portion 401 of the first conductive layer 400 . In some embodiments, the material and process for forming the second dielectric layer 600 may be the same as or different from the material and process for forming the first dielectric layer 330 . In some embodiments, the second dielectric layer 600 can be silicon oxide.

在一些實施例中，可藉由熱氧化製程來形成第二介電層600。因此，在包括不同材料的不同層上所形成的第二介電層600的厚度不同。舉例而言，當第二硬遮罩320為氮化矽，第二介電層600可不形成或幾乎不形成於第二硬遮罩320上。在此實施例中，第二介電層600可形成於第一硬遮罩310的側表面、半導體層300的側表面、第一介電層330的階梯部分331的頂表面與側表面及第一導電層400的突出部分401的頂表面及側表面上。In some embodiments, the second dielectric layer 600 may be formed by a thermal oxidation process. Accordingly, the thickness of the second dielectric layer 600 formed on different layers including different materials is different. For example, when the second hard mask 320 is silicon nitride, the second dielectric layer 600 may not be formed or hardly be formed on the second hard mask 320 . In this embodiment, the second dielectric layer 600 may be formed on the side surface of the first hard mask 310, the side surface of the semiconductor layer 300, the top surface and the side surface of the stepped portion 331 of the first dielectric layer 330, and the second On the top surface and the side surface of the protruding portion 401 of a conductive layer 400 .

在另一些實施例中，可藉由沉積製程來形成第二介電層600。因此，第二介電層600的厚度不受到形成第二介電層600於其上的層的材料的影響。在此實施例中，第二介電層600可進一步形成於第二硬遮罩320的頂表面及側表面上。In other embodiments, the second dielectric layer 600 may be formed by a deposition process. Therefore, the thickness of the second dielectric layer 600 is not affected by the material of the layer on which the second dielectric layer 600 is formed. In this embodiment, the second dielectric layer 600 may be further formed on the top surface and side surfaces of the second hard mask 320 .

在一些實施例中，第一介電層330覆蓋且接觸溝槽201的側表面的一部分，且第二介電層600覆蓋且接觸溝槽201的側表面的一剩餘部分。在一些實施例中，第一介電層330覆蓋且接觸第一導電層400除了突出部分401以外的部分，且第二介電層600覆蓋且接觸第一導電層400的突出部分401。在一些實施例中，第一介電層330覆蓋第一導電層400的側表面的一部分，且第二介電層600覆蓋第一導電層400的側表面的剩餘部分。In some embodiments, the first dielectric layer 330 covers and contacts a portion of the side surface of the trench 201 , and the second dielectric layer 600 covers and contacts a remaining portion of the side surface of the trench 201 . In some embodiments, the first dielectric layer 330 covers and contacts the first conductive layer 400 except the protruding portion 401 , and the second dielectric layer 600 covers and contacts the protruding portion 401 of the first conductive layer 400 . In some embodiments, the first dielectric layer 330 covers a portion of the side surface of the first conductive layer 400 , and the second dielectric layer 600 covers the remaining portion of the side surface of the first conductive layer 400 .

如第8圖所示，在一些實施例中，第二介電層600具有第三厚度t3。在一些實施例中，第二介電層600的第三厚度t3小於如第4圖所示的第一介電層330的第二厚度t2。具體而言，第二介電層600的第三厚度t3小於第一介電層330的階梯部分331的寬度。As shown in FIG. 8, in some embodiments, the second dielectric layer 600 has a third thickness t3. In some embodiments, the third thickness t3 of the second dielectric layer 600 is smaller than the second thickness t2 of the first dielectric layer 330 as shown in FIG. 4 . Specifically, the third thickness t3 of the second dielectric layer 600 is smaller than the width of the stepped portion 331 of the first dielectric layer 330 .

需特別說明的是，由於第一介電層330及第二介電層600皆可為氧化矽，因此第一介電層330及第二介電層600可實質上不具有界面。換句話說，第一介電層330及第二介電層600可整體化為一介電層。是以，在本揭露的半導體結構中，前述介電層在沿著遠離基板100的方向上的厚度可逐漸減少。更甚者，前述介電層在沿著遠離基板100的方向上的可具有階梯狀的側表面。It should be noted that, since both the first dielectric layer 330 and the second dielectric layer 600 can be made of silicon oxide, the first dielectric layer 330 and the second dielectric layer 600 can substantially have no interface. In other words, the first dielectric layer 330 and the second dielectric layer 600 can be integrated into one dielectric layer. Therefore, in the semiconductor structure of the present disclosure, the thickness of the aforementioned dielectric layer can gradually decrease along the direction away from the substrate 100 . What's more, the aforementioned dielectric layer may have a stepped side surface along the direction away from the substrate 100 .

還須說明的是，藉由調整第一介電層330、第一導電層400及第二介電層600的相對位置及形狀等參數，可調整後續形成的第二導電層的形狀。在一些實施例中，當第二介電層600的第三厚度t3較大時，後續形成的第二導電層可具有寬度均勻的突出部分。換句話說，第二介電層600的第三厚度t3能夠影響後續形成的第二導電層的共形程度。舉例而言，當第二介電層600的第三厚度t3較大時，第二介電層600的頂表面的輪廓與第一介電層330及第一導電層400的頂表面的輪廓可能不同。因此，後續形成的第二導電層的突出部分的寬度可為一致，且突出部分的底表面可為水平表面。It should also be noted that by adjusting parameters such as the relative positions and shapes of the first dielectric layer 330 , the first conductive layer 400 , and the second dielectric layer 600 , the shape of the subsequent second conductive layer can be adjusted. In some embodiments, when the third thickness t3 of the second dielectric layer 600 is larger, the subsequently formed second conductive layer may have a protruding portion with a uniform width. In other words, the third thickness t3 of the second dielectric layer 600 can affect the degree of conformality of the subsequently formed second conductive layer. For example, when the third thickness t3 of the second dielectric layer 600 is large, the profile of the top surface of the second dielectric layer 600 and the profiles of the top surfaces of the first dielectric layer 330 and the first conductive layer 400 may be different. Therefore, the width of the protruding portion of the subsequently formed second conductive layer may be uniform, and the bottom surface of the protruding portion may be a horizontal surface.

參照第9圖，在一些實施例中，形成第二導電層700在第二介電層600上。在一些實施例中，用於形成第二導電層700的製程可與用於形成第一導電層400的製程相同或不同。在一些實施例中，毯覆式地形成第二導電材料於第二介電層600上，接著執行回蝕(etch back)製程，來形成第二導電層700。在一些實施例中，用於形成第二導電層700的第一導電材料可與用於形成第一導電層400的第二導電材料相同或不同。在一些實施例中，第二導電層700可為多晶矽。在一些實施例中，可進一步執行平坦化製程，以移除第二硬遮罩320及第一硬遮罩310。在一些實施例中，第二導電層700的頂表面與半導體層300的頂表面齊平。Referring to FIG. 9 , in some embodiments, a second conductive layer 700 is formed on the second dielectric layer 600 . In some embodiments, the process used to form the second conductive layer 700 may be the same as or different from the process used to form the first conductive layer 400 . In some embodiments, the second conductive material is blanket formed on the second dielectric layer 600 , and then an etch back process is performed to form the second conductive layer 700 . In some embodiments, the first conductive material used to form the second conductive layer 700 may be the same as or different from the second conductive material used to form the first conductive layer 400 . In some embodiments, the second conductive layer 700 can be polysilicon. In some embodiments, a planarization process may be further performed to remove the second hard mask 320 and the first hard mask 310 . In some embodiments, the top surface of the second conductive layer 700 is flush with the top surface of the semiconductor layer 300 .

如第9圖所示，在一些實施例中，第二導電層700的側表面具有階梯部分701。在一些實施例中，由於第二介電層600是順應性地形成，因此第二導電層700的階梯部分701對應於第一介電層330的階梯部分331，且第二介電層600設置於第二導電層700的階梯部分701及第一介電層330的階梯部分331之間。在一些實施例中，第二導電層700的階梯部分701在橫向方向上向朝向磊晶層200的方向突出。換句話說，第二導電層700的階梯部分701在橫向方向上向外突出。As shown in FIG. 9 , in some embodiments, the side surface of the second conductive layer 700 has a stepped portion 701 . In some embodiments, since the second dielectric layer 600 is conformally formed, the stepped portion 701 of the second conductive layer 700 corresponds to the stepped portion 331 of the first dielectric layer 330, and the second dielectric layer 600 is set between the stepped portion 701 of the second conductive layer 700 and the stepped portion 331 of the first dielectric layer 330 . In some embodiments, the stepped portion 701 of the second conductive layer 700 protrudes toward the epitaxial layer 200 in the lateral direction. In other words, the stepped portion 701 of the second conductive layer 700 protrudes outward in the lateral direction.

如第9圖所示，在一些實施例中，第二導電層700具有突出部分702。在一些實施例中，第二導電層700的突出部分702具有沿著朝向基板100的方向逐漸減少的寬度。亦即，突出部分702為尖端部分(tip portion)。在一些實施例中，第二導電層700的突出部分702的底表面低於第一導電層400的突出部分401的頂表面。在一些實施例中，第二導電層700的突出部分702在橫向方向上覆蓋第一導電層400的突出部分401。因此，能夠減少半導體結構的電場的最大值，進而使得電荷分布更為均勻，來提升半導體結構的崩潰電壓。在另一些實施例中，第二導電層700的突出部分702具有均勻的寬度。As shown in FIG. 9 , in some embodiments, the second conductive layer 700 has a protruding portion 702 . In some embodiments, the protruding portion 702 of the second conductive layer 700 has a width that gradually decreases along a direction toward the substrate 100 . That is, the protruding portion 702 is a tip portion. In some embodiments, the bottom surface of the protruding portion 702 of the second conductive layer 700 is lower than the top surface of the protruding portion 401 of the first conductive layer 400 . In some embodiments, the protruding portion 702 of the second conductive layer 700 covers the protruding portion 401 of the first conductive layer 400 in a lateral direction. Therefore, the maximum value of the electric field of the semiconductor structure can be reduced, thereby making the charge distribution more uniform, and increasing the breakdown voltage of the semiconductor structure. In other embodiments, the protruding portion 702 of the second conductive layer 700 has a uniform width.

在一些實施例中，在以剖面圖觀察時，第二導電層700的突出部分702在朝向基板100的方向上具有弧形輪廓。如第9圖所示，在一些實施例中，第二導電層700的下部為鉗形(clamp-shape)部分或是扳手形(wrench-shape)部分，且第二導電層700的階梯部分701的寬度大於鉗形部分的寬度。第二導電層700的鉗形部分的外側表面為弧形且在對應於溝槽201的最深處具有一凹部。第一導電層400的突出部分401延伸至第二導電層700的前述凹部中。第二導電層700的鉗形部分的鉗尖在橫向方向上覆蓋第一導電層400。在一些實施例中，第二導電層700的突出部分702可具有蓋形(cap shape)的剖面。In some embodiments, when viewed in a cross-sectional view, the protruding portion 702 of the second conductive layer 700 has an arc-shaped profile in a direction toward the substrate 100 . As shown in FIG. 9, in some embodiments, the lower part of the second conductive layer 700 is a clamp-shape part or a wrench-shape part, and the stepped part 701 of the second conductive layer 700 is The width is greater than the width of the pincer portion. The outer surface of the pincer portion of the second conductive layer 700 is arc-shaped and has a recess corresponding to the deepest part of the trench 201 . The protruding portion 401 of the first conductive layer 400 extends into the aforementioned concave portion of the second conductive layer 700 . The pincer tips of the pincer portion of the second conductive layer 700 cover the first conductive layer 400 in the lateral direction. In some embodiments, the protruding portion 702 of the second conductive layer 700 may have a cap shape in cross section.

參照第10圖，在一些實施例中，形成第一摻雜區710及第二摻雜區720於半導體層300的遠離基板100的表面處。在一些實施例中，形成第一摻雜區710及/或第二摻雜區720的方式包括離子植入(ion implantation)或擴散(diffusion)製程來形成，但不限於此。另外，還可藉由快速熱退火(rapid thermal annealing，RTA)製程來活化被植入的摻質。在一些實施例中，第一摻雜區710具有第一導電型態，且第二摻雜區720具有不同於第一導電形態的第二導電形態。在一些實施例中，第二摻雜區720的摻雜濃度大於半導體層300的摻雜濃度。具體而言，當基板100與磊晶層200為N型，半導體層300為P型，則第一摻雜區710可為重摻雜的N+型態，且第二摻雜區720可為重摻雜的P+型態。Referring to FIG. 10 , in some embodiments, the first doped region 710 and the second doped region 720 are formed on the surface of the semiconductor layer 300 away from the substrate 100 . In some embodiments, the method of forming the first doped region 710 and/or the second doped region 720 includes ion implantation or diffusion process, but is not limited thereto. In addition, the implanted dopants can also be activated by a rapid thermal annealing (RTA) process. In some embodiments, the first doped region 710 has a first conductivity type, and the second doped region 720 has a second conductivity type different from the first conductivity type. In some embodiments, the doping concentration of the second doped region 720 is greater than that of the semiconductor layer 300 . Specifically, when the substrate 100 and the epitaxial layer 200 are N-type, and the semiconductor layer 300 is P-type, the first doped region 710 can be heavily doped N+ type, and the second doped region 720 can be heavily doped The P+ type.

參照第11圖，在一些實施例中，可形成層間介電(interlayer dielectric)層730於第二導電層700及第一摻雜區710上。在一些實施例中，用於形成層間介電層730的材料及製程可與用於形成第一介電層330及/或第二介電層600的材料及製程相同或不同。如第11圖所示，可進一步形成金屬層740於層間介電層730上，且金屬層740可與第二摻雜區720電性連接，以獲得半導體結構1。在一些實施例中，金屬層740可進一步包括貫穿層間介電層730的接觸插塞。在一些實施例中，金屬層740可包括金屬材料、導電材料、其他合適的材料或其組合。在一些實施例中，半導體結構1可為或可經過進一步加工而作為SGT-MOSFET。Referring to FIG. 11 , in some embodiments, an interlayer dielectric (interlayer dielectric) layer 730 may be formed on the second conductive layer 700 and the first doped region 710 . In some embodiments, the material and process used to form the interlayer dielectric layer 730 may be the same as or different from those used to form the first dielectric layer 330 and/or the second dielectric layer 600 . As shown in FIG. 11 , a metal layer 740 can be further formed on the interlayer dielectric layer 730 , and the metal layer 740 can be electrically connected to the second doped region 720 to obtain the semiconductor structure 1 . In some embodiments, the metal layer 740 may further include contact plugs penetrating the interlayer dielectric layer 730 . In some embodiments, the metal layer 740 may include metal materials, conductive materials, other suitable materials, or combinations thereof. In some embodiments, the semiconductor structure 1 can be or can be further processed as a SGT-MOSFET.

如第11圖所示，在一些實施例中，第一導電層400可視為源極遮蔽電極(source shield electrode)，或稱為源極場板(source field plate)。在一些實施例中，源極遮蔽電極可與後續加工後所得的SGT-MOSFET的源極電極連接，或者源極遮蔽電極可視為後續加工後所得的SGT-MOSFET的源極電極的一部分。在一些實施例中，基板100可與汲極電極電性連接，且金屬層740可與源極電極電性連接，因此第一導電層400可與金屬層740電性連接。在此實施例中，汲極電極可設置在基板100的下方，且源極電極可設置在基板100的上方，因此可產生垂直的電流路徑。As shown in FIG. 11 , in some embodiments, the first conductive layer 400 can be regarded as a source shield electrode, or called a source field plate. In some embodiments, the source shielding electrode can be connected to the source electrode of the SGT-MOSFET obtained after subsequent processing, or the source shielding electrode can be regarded as a part of the source electrode of the SGT-MOSFET obtained after subsequent processing. In some embodiments, the substrate 100 can be electrically connected to the drain electrode, and the metal layer 740 can be electrically connected to the source electrode, so the first conductive layer 400 can be electrically connected to the metal layer 740 . In this embodiment, the drain electrode can be disposed below the substrate 100 , and the source electrode can be disposed above the substrate 100 , so that a vertical current path can be generated.

如第11圖所示，在一些實施例中，第二導電層700可具有階梯部分701，所以當以剖面圖觀察時，第二導電層700可具有階梯狀(step-shape)的剖面。在一些實施例中，第二導電層700的下部可視為閘極場板(gate field plate)。在一些實施例中，第二導電層700的閘極場板在橫向方向上與第一導電層400的突出部分401重疊，也就是說，第二導電層700的閘極場板在橫向方向上覆蓋第一導電層400的突出部分401，避免第二導電層700與第一導電層400之間的電場增大，導致漏電流增加的問題。所以能夠使得在介於汲極電極與源極電極之間的電場分布更為均勻，而獲得更為平緩的電荷分布曲線，來提高崩潰電壓。據此，在本揭露中，半導體結構1可同時包括源極場板及閘極場板的兩種場板。As shown in FIG. 11 , in some embodiments, the second conductive layer 700 may have a stepped portion 701 , so when viewed in a cross-sectional view, the second conductive layer 700 may have a step-shape profile. In some embodiments, the lower portion of the second conductive layer 700 can be regarded as a gate field plate. In some embodiments, the gate field plate of the second conductive layer 700 overlaps with the protruding portion 401 of the first conductive layer 400 in the lateral direction, that is, the gate field plate of the second conductive layer 700 overlaps in the lateral direction. Covering the protruding portion 401 of the first conductive layer 400 avoids the increase of the electric field between the second conductive layer 700 and the first conductive layer 400 , resulting in increased leakage current. Therefore, the electric field distribution between the drain electrode and the source electrode can be made more uniform, and a gentler charge distribution curve can be obtained to increase the breakdown voltage. Accordingly, in the present disclosure, the semiconductor structure 1 may include both the source field plate and the gate field plate.

如第11圖所示，在一些實施例中，半導體結構1可視為將溝槽式閘極場效電晶體(trench gate field effect transistor)、閘極場板場效電晶體(gate field plate field effect transistor)及源極場板場效電晶體(source field plate field effect transistor)以串聯連接所得的結構。在一些實施例中，當第一介電層330及第二介電層600皆為諸如氧化矽的氧化物，第一介電層330及第二介電層600可不具有界面。在此情況中，閘極場板可延伸至漂移區，且閘極場板鄰接具有兩種不同厚度的介電層。其中，第一種介電層僅包括作為閘極介電層(gate dielectric layer)的第二介電層600，而第二種介電層則為同時包括第一介電層330的上部及第二介電層600的下部的閘極場板遮蔽介電層(shielded dielectric layer)，因此閘極場板遮蔽介電層的厚度可大於閘極介電層的厚度。As shown in FIG. 11, in some embodiments, the semiconductor structure 1 can be regarded as a trench gate field effect transistor (trench gate field effect transistor), a gate field plate field effect transistor (gate field plate field effect transistor) transistor) and a source field plate field effect transistor (source field plate field effect transistor) are connected in series to obtain a structure. In some embodiments, when both the first dielectric layer 330 and the second dielectric layer 600 are oxides such as silicon oxide, the first dielectric layer 330 and the second dielectric layer 600 may not have an interface. In this case, the gate field plate can extend into the drift region, and the gate field plate adjoins dielectric layers having two different thicknesses. Wherein, the first type of dielectric layer only includes the second dielectric layer 600 as the gate dielectric layer (gate dielectric layer), while the second type of dielectric layer includes both the upper part of the first dielectric layer 330 and the second The gate field plate shielded dielectric layer under the second dielectric layer 600 can be thicker than the gate dielectric layer.

接續上述，第一介電層330的下部可作為源極場板遮蔽介電層，且閘極場板遮蔽介電層的厚度可小於作為源極場板遮蔽介電層的第一厚度t1。是以，在第一介電層330及第二介電層600整體化地具有階梯狀剖面的情況中，能夠使得電場分布更為均勻，來降低導通電阻及/或提高半導體結構的崩潰電壓。此外，當靠近如第1圖所示的溝槽201的底表面處的源極場板遮蔽介電層具有較厚的厚度時，能夠減少集中在如第1圖所示的溝槽201的底表面處的電場，而使得電荷分布更為均勻。Following the above, the lower part of the first dielectric layer 330 can serve as a source field plate shielding dielectric layer, and the thickness of the gate field plate shielding dielectric layer can be smaller than the first thickness t1 of the source field plate shielding dielectric layer. Therefore, when the first dielectric layer 330 and the second dielectric layer 600 integrally have a stepped cross-section, the electric field distribution can be made more uniform to reduce the on-resistance and/or increase the breakdown voltage of the semiconductor structure. In addition, when the source field plate shielding dielectric layer near the bottom surface of the trench 201 as shown in FIG. 1 has a thicker thickness, the concentration at the bottom of the trench 201 as shown in FIG. The electric field at the surface makes the charge distribution more uniform.

在下文中，參照第12圖，來具體說明半導體結構1及1’的電場與深度的分布示意圖。在第12圖，顯示在半導體結構的不同深度處的電場大小的分布圖。In the following, referring to FIG. 12 , a schematic diagram of the electric field and depth distribution of the semiconductor structures 1 and 1' will be described in detail. In Fig. 12, a distribution diagram of the electric field magnitude at different depths of the semiconductor structure is shown.

參照第12圖，顯示另一半導體結構1’。前述半導體結構1’可包括基板100’、磊晶層200’、半導體層300’、第一介電層330’、第一導電層400’、第二介電層600’、第二導電層700’、第一摻雜區710’、第二摻雜區720’、層間介電層730’及金屬層740’，且半導體結構1’為習知的半導體結構。為簡要說明，半導體結構1’與半導體結構1相同或相似處不再予以贅述。Referring to Figure 12, another semiconductor structure 1' is shown. The aforementioned semiconductor structure 1' may include a substrate 100', an epitaxial layer 200', a semiconductor layer 300', a first dielectric layer 330', a first conductive layer 400', a second dielectric layer 600', and a second conductive layer 700 ', the first doped region 710', the second doped region 720', the interlayer dielectric layer 730' and the metal layer 740', and the semiconductor structure 1' is a conventional semiconductor structure. For brief description, the same or similar parts of the semiconductor structure 1' and the semiconductor structure 1 will not be repeated here.

如第12圖所示，習知的半導體結構1’的第二導電層700’的端部a處具有一電場峰值，且在第一導電層400’的端部b具有一電場峰值，因此習知的半導體結構1’具有兩個電場峰值。然而，本揭露的半導體結構1的第二導電層700的階梯部分701的端部c處具有一電場峰值，第二導電層700的突出部分702的端部d處具有一電場峰值，且在第一導電層400的端部e具有一電場峰值，因此本揭露的半導體結構1共具有三個電場峰值。由於本揭露的半導體結構1的電場峰值數量大於習知的半導體結構1’的電場峰值數量，因此代表半導體結構1的電荷分布更為均勻。如第12圖所示，半導體結構1的端部c、d及e的電場峰值的數值皆顯著小於半導體結構1’的端部a及b的電場峰值的數值，因此半導體結構1的崩潰電壓可高於半導體結構1’的崩潰電壓。As shown in FIG. 12, there is an electric field peak at the end a of the second conductive layer 700' of the conventional semiconductor structure 1', and there is an electric field peak at the end b of the first conductive layer 400', so conventional The known semiconductor structure 1' has two electric field peaks. However, in the semiconductor structure 1 of the present disclosure, there is an electric field peak at the end c of the stepped portion 701 of the second conductive layer 700, and there is an electric field peak at the end d of the protruding portion 702 of the second conductive layer 700, and at the The end e of a conductive layer 400 has an electric field peak, so the semiconductor structure 1 of the present disclosure has three electric field peaks in total. Since the number of electric field peaks in the semiconductor structure 1 of the present disclosure is greater than that of the conventional semiconductor structure 1', it means that the charge distribution of the semiconductor structure 1 is more uniform. As shown in FIG. 12, the values of the electric field peak values at the ends c, d and e of the semiconductor structure 1 are significantly smaller than the values of the electric field peak values at the ends a and b of the semiconductor structure 1', so the breakdown voltage of the semiconductor structure 1 can be higher than the breakdown voltage of the semiconductor structure 1'.

再者，由於第二導電層700的突出部分702在橫向方向上與第一導電層400的突出部分401重疊，因此相較於半導體結構1’，半導體結構1的電場分布更為平緩。詳細而言，由於半導體結構1’的第二導電層700’與第一導電層400’在橫向方向上不重疊，所以在半導體結構1’的端部a及端部b之間的電場分布隨著深度改變具有較大的起伏。然而，半導體結構1的第一導電層400的突出部分401可作為緩衝部分，而使得電場分布曲線較為平緩。Furthermore, since the protruding portion 702 of the second conductive layer 700 overlaps with the protruding portion 401 of the first conductive layer 400 in the lateral direction, the electric field distribution of the semiconductor structure 1 is gentler than that of the semiconductor structure 1'. In detail, since the second conductive layer 700' and the first conductive layer 400' of the semiconductor structure 1' do not overlap in the lateral direction, the electric field distribution between the end a and the end b of the semiconductor structure 1' varies with The depth change has a large fluctuation. However, the protruding portion 401 of the first conductive layer 400 of the semiconductor structure 1 can serve as a buffer portion, so that the electric field distribution curve is relatively gentle.

綜上所述，根據本揭露的一些實施例，藉由設置具有階梯部分331的第一介電層330來調整溝槽201中的介電層的厚度，使得在溝槽201中的介電層具有階梯狀剖面，進而降低電場的峰值，來達到電荷平衡的目的。同時，藉由設置具有階梯部分701及突出部分702的第二導電層700，來增加電場峰值的數量，進而降低電場的峰值，使得電荷更為平衡。另外，藉由調整第一導電層400、第二導電層700、第一介電層330及第二介電層600的相互設置關係及尺寸，來使得在半導體結構中的漂移區中的介電層的厚度向上減少。換句話說，從汲極電極朝向源極電極的方向，減少在漂移區中的介電層的厚度。據此，藉由調整介電層的厚度來減少漏電流並降低電場的峰值，使得電荷更為平衡。是以，本揭露可提供具有優異的電荷平衡特性且具有更大的崩潰電壓的半導體結構。In summary, according to some embodiments of the present disclosure, the thickness of the dielectric layer in the trench 201 is adjusted by disposing the first dielectric layer 330 with the stepped portion 331 , so that the dielectric layer in the trench 201 It has a stepped profile, thereby reducing the peak value of the electric field to achieve the purpose of charge balance. At the same time, by disposing the second conductive layer 700 with the stepped portion 701 and the protruding portion 702 , the number of electric field peaks is increased, thereby reducing the electric field peak value, so that the charge is more balanced. In addition, by adjusting the relationship and size of the first conductive layer 400, the second conductive layer 700, the first dielectric layer 330 and the second dielectric layer 600, the dielectric in the drift region in the semiconductor structure The thickness of the layers decreases upwards. In other words, from the direction of the drain electrode towards the source electrode, the thickness of the dielectric layer in the drift region decreases. Accordingly, by adjusting the thickness of the dielectric layer to reduce the leakage current and reduce the peak value of the electric field, the charges are more balanced. Therefore, the present disclosure can provide a semiconductor structure with excellent charge balance characteristics and greater breakdown voltage.

本揭露的保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本揭露一些實施例的揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本揭露一些實施例使用。因此，本揭露的保護範圍包括前述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本揭露的保護範圍也包括各個申請專利範圍及實施例的組合。The protection scope of the present disclosure is not limited to the process, machine, manufacture, material composition, device, method and steps in the specific embodiments described in the specification, and anyone with ordinary knowledge in the technical field can learn from some embodiments of the present disclosure In the content of the disclosure, it is understood that the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps can be used in accordance with this disclosure as long as they can perform substantially the same functions or obtain substantially the same results in the embodiments described here. Some examples use . Therefore, the protection scope of the present disclosure includes the aforementioned process, machine, manufacture, composition of matter, device, method and steps. In addition, each patent application scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes combinations of various patent application scopes and embodiments.

以上概述數個實施例，以便在所屬技術領域中具有通常知識者可以更理解本揭露實施例的觀點。在所屬技術領域中具有通常知識者應該理解，他們能以本揭露實施例為基礎，設計或修改其他製程及結構，以達到與在此介紹的實施例相同目的及/或優點。在所屬技術領域中具有通常知識者也應該理解到，此類等效的製程及結構並無悖離本揭露的精神與範圍，且他們能在不違背本揭露的精神及範圍下，做各式各樣的改變、取代及替換。Several embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art should understand that they can design or modify other processes and structures based on the disclosed embodiments, so as to achieve the same purpose and/or advantages as the disclosed embodiments. Those with ordinary knowledge in the technical field should also understand that such equivalent processes and structures do not deviate from the spirit and scope of this disclosure, and they can be made in various ways without departing from the spirit and scope of this disclosure. Various changes, substitutions and substitutions.

1,1’:半導體結構 100,100’:基板 200,200’:磊晶層 201:溝槽 300,300’:半導體層 310:第一硬遮罩 320:第二硬遮罩 330,330’:第一介電層 331,701:階梯部分 400,400’:第一導電層 401,702:突出部分 500:犧牲層 600,600’:第二介電層 700,700’:第二導電層 710,710’:第一摻雜區 720,720’:第二摻雜區 730,730’:層間介電層 740,740’:金屬層 a,b,c,d,e:端部 t1:第一厚度 t2:第二厚度 t3:第三厚度 h1:第一高度 h2:第二高度1,1': Semiconductor structure 100,100': Substrate 200,200': epitaxial layer 201: Groove 300,300': semiconductor layer 310:First hard mask 320: second hard mask 330,330': the first dielectric layer 331,701: ladder part 400,400': the first conductive layer 401,702: overhangs 500: sacrificial layer 600,600': the second dielectric layer 700,700': the second conductive layer 710,710': the first doped region 720,720': the second doped region 730,730': interlayer dielectric layer 740,740': metal layer a,b,c,d,e: end t1: first thickness t2: the second thickness t3: third thickness h1: first height h2: second height

藉由以下的詳述配合所附圖式，能夠更加理解本揭露實施例的觀點。值得注意的是，根據工業上的標準慣例，一些部件(feature)可能沒有按照比例繪製。事實上，為了能清楚地討論，不同部件的尺寸可能被增加或減少。 第1圖至第11圖是根據本揭露的一些實施例，繪示在各個階段形成半導體結構的剖面示意圖。 第12圖是根據本揭露的一些實施例，繪示半導體結構的電場分布示意圖。 The viewpoints of the embodiments of the present disclosure can be better understood through the following detailed description combined with the accompanying drawings. It is worth noting that, in accordance with the standard practice in the industry, some features may not be drawn to scale. In fact, the dimensions of the various components may have been increased or decreased for clarity of discussion. FIG. 1 to FIG. 11 are schematic cross-sectional views illustrating the formation of semiconductor structures in various stages according to some embodiments of the present disclosure. FIG. 12 is a schematic diagram illustrating an electric field distribution of a semiconductor structure according to some embodiments of the present disclosure.

1:半導體結構 1: Semiconductor structure

100:基板 100: Substrate

200:磊晶層 200: epitaxial layer

300:半導體層 300: semiconductor layer

330:第一介電層 330: the first dielectric layer

331,701:階梯部分 331,701: ladder part

400:第一導電層 400: the first conductive layer

401,702:突出部分 401,702: overhangs

600:第二介電層 600: second dielectric layer

700:第二導電層 700: second conductive layer

710:第一摻雜區 710: the first doped region

720:第二摻雜區 720: the second doped region

730:層間介電層 730: interlayer dielectric layer

740:金屬層 740: metal layer

Claims (17)

一種半導體結構的形成方法，包括： 依序形成一磊晶層及一半導體層在一基板上； 形成一溝槽在該磊晶層及該半導體層中； 順應性地形成一第一介電層在該溝槽中； 形成一第一導電層在該第一介電層上； 移除該第一介電層的一第一部分，以暴露該第一導電層的一側表面且使該第一介電層的一第二部分覆蓋該半導體層的一側表面； 移除該第一介電層的該第二部分，以暴露該半導體層的該側表面，使得該第一介電層具有一階梯部分； 形成一第二介電層在經暴露的該半導體層的該側表面、該第一介電層的該階梯部分及該第一導電層上；以及 形成一第二導電層於該第二介電層上。 A method of forming a semiconductor structure, comprising: sequentially forming an epitaxial layer and a semiconductor layer on a substrate; forming a trench in the epitaxial layer and the semiconductor layer; conformally forming a first dielectric layer in the trench; forming a first conductive layer on the first dielectric layer; removing a first portion of the first dielectric layer to expose one side surface of the first conductive layer and making a second portion of the first dielectric layer cover one side surface of the semiconductor layer; removing the second portion of the first dielectric layer to expose the side surface of the semiconductor layer, so that the first dielectric layer has a stepped portion; forming a second dielectric layer on the exposed side surface of the semiconductor layer, the stepped portion of the first dielectric layer, and the first conductive layer; and A second conductive layer is formed on the second dielectric layer. 如請求項1之形成方法，其中移除該第一介電層的該第二部分更包括： 形成一犧牲層於該第一導電層及該第一介電層上，以使該犧牲層覆蓋該第一導電層的該側表面及該第一介電層的一凹狀頂表面；以及 藉由該犧牲層作為蝕刻遮罩，來移除該第一介電層的該第二部分，使得該第一介電層具有該階梯部分。 The forming method according to claim 1, wherein removing the second portion of the first dielectric layer further comprises: forming a sacrificial layer on the first conductive layer and the first dielectric layer such that the sacrificial layer covers the side surface of the first conductive layer and a concave top surface of the first dielectric layer; and Using the sacrificial layer as an etching mask, the second portion of the first dielectric layer is removed so that the first dielectric layer has the stepped portion. 如請求項2之形成方法，其中移除該第一介電層的該第二部分更包括： 在移除該第一介電層的該第二部分之後，移除該犧牲層，以暴露該第一導電層的該側表面。 The forming method according to claim 2, wherein removing the second portion of the first dielectric layer further comprises: After removing the second portion of the first dielectric layer, the sacrificial layer is removed to expose the side surface of the first conductive layer. 如請求項2之形成方法，其中移除該第一介電層的該第二部分，使得該第一介電層的該階梯部分的一頂表面低於該犧牲層的一頂表面。The forming method of claim 2, wherein the second portion of the first dielectric layer is removed such that a top surface of the stepped portion of the first dielectric layer is lower than a top surface of the sacrificial layer. 如請求項2之形成方法，其中移除該第一介電層的該第二部分，使該第一介電層的該階梯部分的一頂表面高於該第一導電層的一頂表面。The forming method of claim 2, wherein the second portion of the first dielectric layer is removed such that a top surface of the stepped portion of the first dielectric layer is higher than a top surface of the first conductive layer. 如請求項1之形成方法，其中該第一介電層的該第一部分位於該半導體層的該側表面上，且移除該第一介電層的該第一部分以減薄該第一介電層，且經減薄的該第一介電層包括覆蓋該半導體層的該側表面的該第二部分。The forming method of claim 1, wherein the first portion of the first dielectric layer is located on the side surface of the semiconductor layer, and the first portion of the first dielectric layer is removed to thin the first dielectric layer. layer, and the thinned first dielectric layer includes the second portion covering the side surface of the semiconductor layer. 如請求項1之形成方法，其中順應性地形成該第二介電層在該半導體層、該第一介電層的該階梯部分與該第一導電層上。The forming method of claim 1, wherein the second dielectric layer is conformally formed on the semiconductor layer, the stepped portion of the first dielectric layer, and the first conductive layer. 如請求項1之形成方法，其中在移除該第一介電層的該第一部分之後，移除該第一介電層的該第二部分。The forming method of claim 1, wherein after removing the first portion of the first dielectric layer, the second portion of the first dielectric layer is removed. 如請求項1之形成方法，更包括： 形成一第一摻雜區及一第二摻雜區於該半導體層中； 形成一層間介電層於該第二導電層及該第一摻雜區上；以及 形成一金屬層於該層間介電層上，且該金屬層電性連接該第二摻雜區。 For example, the formation method of claim 1 further includes: forming a first doped region and a second doped region in the semiconductor layer; forming an interlayer dielectric layer on the second conductive layer and the first doped region; and A metal layer is formed on the interlayer dielectric layer, and the metal layer is electrically connected to the second doped region. 一種半導體結構，包括： 一基板，具有一第一導電型態； 一磊晶層，具有該第一導電型態且設置在該基板上； 一半導體層，具有不同於該第一導電型態的一第二導電型態，設置在該磊晶層上，且該磊晶層與該半導體層包括一溝槽； 一第一介電層，設置在該溝槽中，且具有與該溝槽的一側表面接觸的一階梯部分； 一第一導電層，設置在該第一介電層上； 一第二介電層，設置在該第一介電層的該階梯部分的一頂表面與一側表面及該第一導電層的一頂表面與一側表面上；以及 一第二導電層，設置在該第二介電層上。 A semiconductor structure comprising: a substrate having a first conductivity type; an epitaxial layer having the first conductivity type and disposed on the substrate; a semiconductor layer having a second conductivity type different from the first conductivity type disposed on the epitaxial layer, and the epitaxial layer and the semiconductor layer include a trench; a first dielectric layer disposed in the trench and having a stepped portion in contact with one side surface of the trench; a first conductive layer disposed on the first dielectric layer; a second dielectric layer disposed on a top surface and a side surface of the stepped portion of the first dielectric layer and a top surface and a side surface of the first conductive layer; and A second conductive layer is disposed on the second dielectric layer. 如請求項10之半導體結構，其中該第二導電層的一側表面具有一階梯部分，且該第二導電層的該階梯部分對應於該第一介電層的該階梯部分。The semiconductor structure according to claim 10, wherein one side surface of the second conductive layer has a stepped portion, and the stepped portion of the second conductive layer corresponds to the stepped portion of the first dielectric layer. 如請求項11之半導體結構，其中該第二導電層的該階梯部分在橫向方向上向朝向該磊晶層的方向突出。The semiconductor structure according to claim 11, wherein the stepped portion of the second conductive layer protrudes toward the epitaxial layer in a lateral direction. 如請求項11之半導體結構，其中該第二導電層具有一突出部分，且該第二導電層的該突出部分具有沿著朝向該基板的方向逐漸減少的寬度。The semiconductor structure according to claim 11, wherein the second conductive layer has a protruding portion, and the protruding portion of the second conductive layer has a width gradually decreasing along a direction toward the substrate. 如請求項10之半導體結構，其中該第一介電層具有分別接觸該溝槽的相對側表面的一對階梯部分及介於該對階梯部分之間的一凹狀頂表面。The semiconductor structure of claim 10, wherein the first dielectric layer has a pair of stepped portions respectively contacting opposite side surfaces of the trench and a concave top surface between the pair of stepped portions. 如請求項14之半導體結構，其中該第一導電層具有一突出部分，且該第一導電層的該突出部分從該第一介電層的該凹狀頂表面向上突出。The semiconductor structure of claim 14, wherein the first conductive layer has a protruding portion, and the protruding portion of the first conductive layer protrudes upward from the concave top surface of the first dielectric layer. 如請求項10之半導體結構，其中該第一介電層的該階梯部分的寬度大於該第二介電層的厚度。The semiconductor structure of claim 10, wherein the width of the stepped portion of the first dielectric layer is greater than the thickness of the second dielectric layer. 如請求項10之半導體結構，其中該第一介電層覆蓋該第一導電層的該側表面的一部分，且該第二介電層覆蓋該第一導電層的該側表面的一剩餘部分。The semiconductor structure of claim 10, wherein the first dielectric layer covers a portion of the side surface of the first conductive layer, and the second dielectric layer covers a remaining portion of the side surface of the first conductive layer.
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TW201642462A (en) * 2015-05-21 2016-12-01 蘇烱光 Adaptive duo-gate MOSFET
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120235229A1 (en) * 2011-03-16 2012-09-20 Probst Dean E Inter-poly dielectric in a shielded gate mosfet device
US20140319606A1 (en) * 2013-04-26 2014-10-30 Anup Bhalla Shielded gate trench (sgt) mosfet devices and manufacturing processes
TW201642462A (en) * 2015-05-21 2016-12-01 蘇烱光 Adaptive duo-gate MOSFET
US20210296434A1 (en) * 2020-03-17 2021-09-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

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