TWI763033B - Semiconductor structure and method of forming the same - Google Patents

Semiconductor structure and method of forming the same Download PDF

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TWI763033B
TWI763033B TW109131090A TW109131090A TWI763033B TW I763033 B TWI763033 B TW I763033B TW 109131090 A TW109131090 A TW 109131090A TW 109131090 A TW109131090 A TW 109131090A TW I763033 B TWI763033 B TW I763033B
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dielectric layer
groove
conductive
layer
substrate
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TW202211316A (en
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陳暐鈞
陳曠舉
劉漢英
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新唐科技股份有限公司
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Priority to CN202110588154.7A priority patent/CN114171453A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of forming a semiconductor structure includes forming a recess on a substrate. The recess has side surfaces and a bottom surface. A first dielectric layer is formed on the side surfaces and the bottom surface of the recess and the substrate, so that the first dielectric layer has a trench. The trench is filled with a first conductive material. The first conductive material is etched back to form a first conductive layer and expose a portion of the first dielectric layer on the side surfaces of the recess. The first dielectric layer is etched so that the portion of the first dielectric layer located on the side surface of the recess has a width that becomes smaller in a direction away from the bottom surface of the recess. A second conductive material is filled in the trench to form a second conductive layer on the first conductive layer.

Description

半導體結構及其形成方法Semiconductor structure and method of forming the same

本揭露係關於一種半導體結構及其形成方法，特別是關於一種能夠減少導電層中的缺陷之半導體結構及其形成方法。The present disclosure relates to a semiconductor structure and a method for forming the same, and more particularly, to a semiconductor structure capable of reducing defects in a conductive layer and a method for forming the same.

近年來，因為遮蔽閘極溝槽式(shielded gate trench，SGT)MOSFET具有較低的導通電阻(R ds_on)，而能顯著減少功率消耗的優點，所以SGT-MOSFET被廣泛應用與研究，並成為高頻低壓功率元件的主流。 In recent years, because the shielded gate trench (SGT) MOSFET has the advantage of lower on-resistance (R ds_on ) and can significantly reduce power consumption, SGT-MOSFET has been widely used and researched, and has become the The mainstream of high frequency and low voltage power components.

而在SGT-MOSFET中，經常依據使用者的需求而選擇不同的導電材料作為不同電極來配置。一般而言，常見的電極材料包含金屬、多晶矽、導電金屬氧化物等。然而，由於SGT-MOSFET中具有溝槽結構，因此填充電極材料時會受到溝槽結構本身的形狀、溝槽的深寬比、及/或電極材料的種類所致的缺陷，影響被形成的電極的電性特徵。進一步來說，甚至會影響整體SGT-MOSFET的電性特徵及可靠性。In SGT-MOSFET, different conductive materials are often selected as different electrodes to configure according to the needs of users. In general, common electrode materials include metals, polysilicon, conductive metal oxides, and the like. However, since the SGT-MOSFET has a trench structure, the electrode material will be filled with defects caused by the shape of the trench structure itself, the aspect ratio of the trench, and/or the type of electrode material, which will affect the electrode to be formed. electrical characteristics. Further, it will even affect the electrical characteristics and reliability of the overall SGT-MOSFET.

因此，雖然現存的半導體結構及其形成方法已逐步滿足它們既定的用途，但它們仍未在各方面皆徹底的符合要求。因此，關於進一步加工後可做為SGT-MOSFET之半導體結構及其形成方法仍有一些問題需要克服。Thus, although existing semiconductor structures and methods of forming them have gradually met their intended uses, they have not yet fully met the requirements in all respects. Therefore, there are still some problems to be overcome with respect to the semiconductor structure and the method of forming it which can be used as SGT-MOSFET after further processing.

鑒於上述問題，本揭露藉由回蝕(etch back)導電材料；蝕刻介電層的一部分；以及再次填入導電材料的至少兩階段式形成製程，減少或避免產生在被形成的導電結構中的缺陷，來獲得具有更優良的電性特徵及可靠性的半導體結構。In view of the above-mentioned problems, the present disclosure reduces or avoids the generation of the conductive material in the formed conductive structure by at least two-stage formation process of etch back (etching back) the conductive material; etching a part of the dielectric layer; and refilling the conductive material. defects to obtain a semiconductor structure with better electrical characteristics and reliability.

根據一些實施例，提供半導體結構的形成方法。形成凹槽在基板上。凹槽具有側表面與底表面。形成第一介電層於凹槽的側表面與底表面、以及基板上，以使第一介電層具有溝槽。填填充第一導電材料於溝槽中。回蝕第一導電材料，以形成第一導電層並暴露位於凹槽的側表面上的第一介電層的一部分。蝕刻第一介電層，使得位於凹槽的側表面上的第一介電層的上述部分具有沿著遠離凹槽的底表面的方向變小的寬度。填充第二導電材料於溝槽中，以形成在第一導電層上的第二導電層。According to some embodiments, methods of forming semiconductor structures are provided. Form grooves on the substrate. The groove has side surfaces and a bottom surface. A first dielectric layer is formed on the side surface and the bottom surface of the groove and the substrate, so that the first dielectric layer has a groove. Filling the trenches with the first conductive material. The first conductive material is etched back to form a first conductive layer and expose a portion of the first dielectric layer on the side surface of the recess. The first dielectric layer is etched such that the above-mentioned portions of the first dielectric layer on the side surfaces of the grooves have a width that decreases in a direction away from the bottom surface of the grooves. A second conductive material is filled in the trench to form a second conductive layer on the first conductive layer.

根據一些實施例，提供半導體結構。半導體結構包含基板、第一介電層、遮蔽電極、第二介電層、閘極電極、以及源極電極。基板具有凹槽。凹槽包含第一凹槽及第二凹槽。第一介電層設置於第一凹槽的側表面及底表面上、以及第二凹槽的側表面及底表面上，且具有對應於第一凹槽的第一溝槽、以及對應於第二凹槽的第二溝槽。遮蔽電極設置於第一溝槽中。第二介電層設置於第一溝槽中且於遮蔽電極上。閘極電極設置於第一溝槽中且於第二介電層上。源極電極設置於第二溝槽中。其中，位於第二凹槽的側表面上的第一介電層的一部分具有沿著遠離第二凹槽的底表面的方向變小的寬度。According to some embodiments, semiconductor structures are provided. The semiconductor structure includes a substrate, a first dielectric layer, a shielding electrode, a second dielectric layer, a gate electrode, and a source electrode. The base plate has grooves. The grooves include a first groove and a second groove. The first dielectric layer is disposed on the side surface and the bottom surface of the first groove and on the side surface and the bottom surface of the second groove, and has a first groove corresponding to the first groove, and a first groove corresponding to the first groove. The second groove of the two grooves. The shielding electrode is arranged in the first trench. The second dielectric layer is disposed in the first trench and on the shielding electrode. The gate electrode is disposed in the first trench and on the second dielectric layer. The source electrode is disposed in the second trench. Wherein, a portion of the first dielectric layer on the side surface of the second groove has a width that becomes smaller in a direction away from the bottom surface of the second groove.

本揭露的半導體結構可應用於多種類型的半導體裝置，為讓本揭露之特徵和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下。The semiconductor structure of the present disclosure can be applied to various types of semiconductor devices. In order to make the features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are given below and described in detail with the accompanying drawings.

以下揭露提供了很多不同的實施例或範例，用於實施所提供的半導體結構之不同元件。各元件和其配置的具體範例描述如下，以簡化本揭露實施例。當然，這些僅僅是範例，並非用以限定本揭露。舉例而言，敘述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接觸的實施例，也可能包含額外的元件形成在第一和第二元件之間，使得它們不直接接觸的實施例。此外，本揭露實施例可能在不同的範例中重複參考數字及/或字母。如此重複是為了簡明和清楚，而非用以表示所討論的不同實施例及/或形態之間的關係。The following disclosure provides many different embodiments or examples for implementing different elements of the provided semiconductor structures. Specific examples of elements and their configurations are described below to simplify the disclosed embodiments. Of course, these are just examples, and are not intended to limit the present disclosure. For example, if the description mentions that the first element is formed on the second element, it may include embodiments in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements , so that they are not in direct contact with the examples. Furthermore, embodiments of the present disclosure may repeat reference numerals and/or letters in different examples. This repetition is for brevity and clarity and is not intended to represent a relationship between the different embodiments and/or aspects discussed.

在不同圖式及說明的實施例中，相同或相似的元件符號被用來標明相同或相似的元件。可以理解的是，在方法的前、中、後可以提供額外的操作，且一些敘述的操作可為了該方法的其他實施例被取代或刪除。In the different drawings and the illustrated embodiments, the same or similar reference numerals are used to designate the same or similar elements. It will be appreciated that additional operations may be provided before, during, and after the method, and that some of the described operations may be replaced or deleted for other embodiments of the method.

第1至9圖是根據本揭露的一些實施例，說明在各個階段形成半導體結構1的剖面示意圖。FIGS. 1-9 are schematic cross-sectional views illustrating the formation of a semiconductor structure 1 at various stages according to some embodiments of the present disclosure.

參照第1圖，提供半導體結構的基板100，且設置圖案化硬遮罩101於基板100上。基板100可為晶圓，例如為矽晶圓。基板100可為塊材(bulk)半導體、或絕緣上覆半導體(semiconductor-on-insulation，SOI)基板。一般而言，絕緣上覆半導體基板包含形成在絕緣層上的一層半導體材料。絕緣層可例如為埋置氧化(buried oxide，BOX)層、氧化矽層或類似的材料，其提供絕緣層在矽或玻璃基板上。其他的基板種類則包含例如為多重層或梯度(gradient)基板。Referring to FIG. 1 , a semiconductor structure substrate 100 is provided, and a patterned hard mask 101 is disposed on the substrate 100 . The substrate 100 can be a wafer, such as a silicon wafer. The substrate 100 may be a bulk semiconductor or a semiconductor-on-insulation (SOI) substrate. Generally speaking, a semiconductor-on-insulator substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or a similar material, which provides an insulating layer on a silicon or glass substrate. Other types of substrates include, for example, multi-layer or gradient substrates.

基板100可為元素半導體，其包含矽(silicon)、鍺(germanium)；基板100亦可為化合物半導體，其包含：舉例而言，碳化矽(silicon carbide)、砷化鎵(gallium arsenide)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide)，但不限於此；基板100亦可為合金半導體，其包含：舉例而言，SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP或其任意組合，但不限於此。The substrate 100 can be an elemental semiconductor, including silicon and germanium; the substrate 100 can also be a compound semiconductor, including, for example, silicon carbide, gallium arsenide, phosphorus Gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide, but not limited thereto; the substrate 100 can also be an alloy semiconductor, including: for example For example, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP or any combination thereof, but not limited thereto.

基板100可選擇性地包含磊晶層(未顯示)及/或半導體層(未顯示)。或者，半導體層可於後續製程中以離子佈植的方式形成。磊晶層可包含矽、鍺、矽與鍺、III-V族化合物或上述之組合。上述磊晶層可藉由磊晶成長(epitaxial growth)製程形成。The substrate 100 may optionally include an epitaxial layer (not shown) and/or a semiconductor layer (not shown). Alternatively, the semiconductor layer can be formed by ion implantation in the subsequent process. The epitaxial layer may comprise silicon, germanium, silicon and germanium, III-V compounds, or combinations thereof. The above-mentioned epitaxial layer can be formed by an epitaxial growth process.

在一些實施例，基板100及磊晶層具有第一導電型態，且半導體層具有不同於第一導電型態的第二導電型態。舉例而言，若基板100及磊晶層具有的第一導電型態為N型，則半導體層具有的第二導電型態為P型；反之，若基板100及磊晶層具有的第一導電型態為P型，則半導體層具有的第二導電型態為N型。第一導電型態與第二導電型態可依據需求調整，同時，摻雜濃度、摻雜深度及摻雜區域大小亦可依據需求調整。In some embodiments, the substrate 100 and the epitaxial layer have a first conductivity type, and the semiconductor layer has a second conductivity type different from the first conductivity type. For example, if the first conductivity type of the substrate 100 and the epitaxial layer is N-type, the second conductivity type of the semiconductor layer is P-type; conversely, if the substrate 100 and the epitaxial layer have the first conductivity type If the type is P-type, the second conductivity type of the semiconductor layer is N-type. The first conductivity type and the second conductivity type can be adjusted according to requirements, and at the same time, the doping concentration, the doping depth and the size of the doping region can also be adjusted according to the requirements.

根據使用者的不同需求，圖案化硬遮罩101可具有對應於後續形成於基板100上的凹槽的形狀。圖案化硬遮罩101可暴露出基板100的頂表面的一部分。圖案化硬遮罩101可包含氧化物、氮化物或其組合。在一些實施例中，氧化物層可包含：舉例而言，由四乙氧基矽烷(tetraethyl orthosilicate，TEOS)作為前驅物的氧化物或其他適合的氧化物。氮化物可包含氮化矽(SiN)、氮氧化矽(SiON)、氮化鈦(TiN)、氮化鉭(TaN)、或其他適合的氮化物。可理解的是，能夠依據製程條件搭配適合的硬遮罩材料，因此本揭露之實施例並不限於此。According to different needs of users, the patterned hard mask 101 may have a shape corresponding to the grooves subsequently formed on the substrate 100 . The patterned hard mask 101 may expose a portion of the top surface of the substrate 100 . The patterned hard mask 101 may include oxide, nitride, or a combination thereof. In some embodiments, the oxide layer may include, for example, an oxide with tetraethyl orthosilicate (TEOS) as a precursor or other suitable oxide. The nitride may include silicon nitride (SiN), silicon oxynitride (SiON), titanium nitride (TiN), tantalum nitride (TaN), or other suitable nitrides. It can be understood that suitable hard mask materials can be matched according to process conditions, so the embodiments of the present disclosure are not limited thereto.

在一些實施例中，圖案化硬遮罩層101為氧化物。在一些實施例中，在基板100上形成圖案化硬遮罩層101的步驟可進一步包含：沉積作為硬遮罩層的氧化物層於基板100上：形成光阻層於氧化物層上；依照需求對光阻層進行曝光，以獲得圖案化光阻層；使用圖案化光阻層作為蝕刻遮罩，蝕刻氧化物層來形成圖案化氧化物層；以及移除圖案化光阻層，以獲得在基板100上的圖案化硬遮罩層101。上述氧化物層可藉由化學氣相沉積(chemical vapor deposition，CVD)沉積、或其他合適的製程而得。而上述光阻層則可使用灰化(ashing)及/或濕式去除(wet strip)製程來移除。In some embodiments, the patterned hard mask layer 101 is an oxide. In some embodiments, the step of forming the patterned hard mask layer 101 on the substrate 100 may further include: depositing an oxide layer as a hard mask layer on the substrate 100 ; forming a photoresist layer on the oxide layer; It is required to expose the photoresist layer to obtain a patterned photoresist layer; use the patterned photoresist layer as an etch mask, etch the oxide layer to form a patterned oxide layer; and remove the patterned photoresist layer to obtain a Patterned hard mask layer 101 on substrate 100 . The above oxide layer can be deposited by chemical vapor deposition (CVD), or other suitable processes. The above-mentioned photoresist layer can be removed by ashing and/or wet strip process.

參照第2圖，使用圖案化硬遮罩層101作為蝕刻遮罩，並蝕刻基板100，以形成在基板100上的凹槽120。在一些實施例中，後續形成的電極設置於凹槽120中，也就是說，電極的設置位置對應於凹槽120的位置。在一些實施例中，根據圖案化硬遮罩層101的開口的形狀，凹槽120可提供為複數個。在一些實施例中，凹槽120可包含第一凹槽121與第二凹槽122。在一些實施例中，後續形成的SGT-MOSFET中的遮蔽電極與閘極電極可對應於第一凹槽121設置，且後續形成的SGT-MOSFET中的源極電極可對應於第二凹槽122設置。Referring to FIG. 2 , the patterned hard mask layer 101 is used as an etching mask, and the substrate 100 is etched to form grooves 120 on the substrate 100 . In some embodiments, the electrodes formed subsequently are disposed in the grooves 120 , that is, the disposed positions of the electrodes correspond to the positions of the grooves 120 . In some embodiments, the grooves 120 may be provided in plural according to the shape of the opening of the patterned hard mask layer 101 . In some embodiments, the groove 120 may include a first groove 121 and a second groove 122 . In some embodiments, the shield electrode and the gate electrode in the subsequently formed SGT-MOSFET may be disposed corresponding to the first groove 121 , and the source electrode in the subsequently formed SGT-MOSFET may correspond to the second groove 122 set up.

為使便於說明後續形成的SGT-MOSFET中的遮蔽電極、閘極電極、以及源極電極的相對設置，在下文中，以凹槽120包含第一凹槽121與第二凹槽122的情況進行詳細敘述，然而本揭露係不限於此。也就是說，第一凹槽121與第二凹槽122可在相同製程中同時形成，因此可同時形成遮蔽電極與源極電極；或者，第一凹槽121與第二凹槽122之兩者可在不同的製程中先後形成，因此遮蔽電極與源極電極可在不同製程中先後形成。In order to facilitate the description of the relative arrangement of the shielding electrode, the gate electrode, and the source electrode in the SGT-MOSFET formed later, in the following, the case where the groove 120 includes the first groove 121 and the second groove 122 is described in detail. description, however the present disclosure is not limited thereto. That is, the first groove 121 and the second groove 122 can be formed at the same time in the same process, so that the shield electrode and the source electrode can be formed at the same time; or, both the first groove 121 and the second groove 122 can be formed at the same time. It can be formed successively in different processes, so the shielding electrode and the source electrode can be formed successively in different processes.

另外，還須說明的是，為使便於理解，在下文中，以第一凹槽121與第二凹槽122的形狀、深度、以及寬度皆為相同的情況進行詳細敘述並示於圖式中，然而本揭露係不限於此。也就是說，根據實際需求，第一凹槽121與第二凹槽122的形狀、深度、以及寬度可為實質上不同。In addition, it should be noted that, in order to facilitate understanding, hereinafter, the shape, depth and width of the first groove 121 and the second groove 122 are described in detail and shown in the drawings. However, the present disclosure is not limited thereto. That is, according to actual requirements, the shapes, depths, and widths of the first grooves 121 and the second grooves 122 may be substantially different.

參照第3圖，移除圖案化硬遮罩層101。可藉由執行蝕刻製程或其他合適的製程來移除圖案化硬遮罩層101。蝕刻製程可包含乾式蝕刻、或濕式蝕刻、或其他合適的蝕刻方式。乾式蝕刻可包含但不限於電漿蝕刻、無電漿氣體蝕刻、濺射蝕刻(sputter etching)、離子研磨(ion milling)、反應離子蝕刻(reactive ion etching，RIE)。濕式蝕刻可包含但不限於使用酸性溶液、鹼性溶液或是溶劑來移除待移除結構的至少一部分。此外，蝕刻製程也可以是純化學蝕刻、純物理蝕刻、或其任意組合。Referring to FIG. 3, the patterned hard mask layer 101 is removed. The patterned hard mask layer 101 may be removed by performing an etching process or other suitable process. The etching process may include dry etching, wet etching, or other suitable etching methods. Dry etching may include, but is not limited to, plasma etching, plasmaless gas etching, sputter etching, ion milling, reactive ion etching (RIE). Wet etching may include, but is not limited to, the use of acidic solutions, alkaline solutions, or solvents to remove at least a portion of the structure to be removed. In addition, the etching process can also be pure chemical etching, pure physical etching, or any combination thereof.

如第3圖所示，形成於基板100中的第一凹槽121具有第一深度L1及第一寬度W1，且第二凹槽122具有與第一凹槽121實質上相同的深度及寬度。第一凹槽121具有側表面及底表面，第二凹槽122亦具有側表面及底表面。As shown in FIG. 3 , the first groove 121 formed in the substrate 100 has a first depth L1 and a first width W1 , and the second groove 122 has substantially the same depth and width as the first groove 121 . The first groove 121 has side surfaces and a bottom surface, and the second groove 122 also has side surfaces and a bottom surface.

參照第4圖，順應性地(conformally)，亦即共形地形成第一介電層200於凹槽120的側表面上、底表面上、以及基板100的一部分上，以使第一介電層200具有溝槽T。由於凹槽120可包含第一凹槽121及第二凹槽122，因此第一介電層200可包含對應於第一凹槽121的子介電層210、以及對應於第二凹槽122的子介電層220。且因為第一介電層200包含子介電層210及子介電層220，因此溝槽T可包含對應於子介電層210的第一溝槽T1及對應於子介電層220的第二溝槽T2。Referring to FIG. 4 , the first dielectric layer 200 is conformally, ie, conformally, formed on the side surface, the bottom surface, and a portion of the substrate 100 of the groove 120 , so that the first dielectric layer 200 is formed. Layer 200 has trenches T. Since the groove 120 may include the first groove 121 and the second groove 122 , the first dielectric layer 200 may include the sub-dielectric layer 210 corresponding to the first groove 121 and the sub-dielectric layer 210 corresponding to the second groove 122 Sub-dielectric layer 220 . And because the first dielectric layer 200 includes the sub-dielectric layer 210 and the sub-dielectric layer 220 , the trench T may include the first trench T1 corresponding to the sub-dielectric layer 210 and the first trench T1 corresponding to the sub-dielectric layer 220 . Two trenches T2.

在一些實施例中，第一介電層200可為氧化矽、氮化矽、氮氧化矽、高介電常數(high-k)介電材料、或其它任何適合之介電材料、或上述之組合。高介電常數介電材料之材料可為金屬氧化物、金屬氮化物、金屬矽化物、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽化物、金屬的氮氧化物、金屬鋁酸鹽、鋯矽酸鹽、鋯鋁酸鹽。舉例而言，高介電常數介電材料可為LaO、AlO、ZrO、TiO、Ta 2O 5、Y 2O 3、SrTiO 3(STO)、BaTiO 3(BTO)、BaZrO、HfO 2、HfO 3、HfZrO、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、HfTaTiO、HfAlON、(Ba，Sr)TiO 3(BST)、Al 2O 3、其它適合的介電材料、或上述組合，但不限於此。在一些實施例中，第一介電層200可包含氧化物。 In some embodiments, the first dielectric layer 200 may be silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, or any other suitable dielectric material, or any of the above combination. The material of the high dielectric constant dielectric material can be metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, metal aluminate, zirconium Silicates, zirconium aluminates. For example, the high-k dielectric material can be LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfO 2 , HfO 3 , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr)TiO 3 (BST), Al 2 O 3 , other suitable dielectric materials, or a combination of the above, but not limited to this. In some embodiments, the first dielectric layer 200 may include oxide.

在一些實施例中，第一介電層200可藉由CVD或熱氧化法(thermal oxidation)形成。CVD可為低壓化學氣相沉積法(low pressure chemical vapor deposition，LPCVD)、低溫化學氣相沉積法(low temperature chemical vapor deposition，LTCVD)、快速升溫化學氣相沉積法(rapid thermal chemical vapor deposition，RTCVD)、PECVD、原子層化學氣相沉積法之原子層沉積法(atomic layer deposition，ALD)或其它合適的CVD製程。在一些實施例中，第一介電層200藉由在爐管中進行熱氧化法形成。In some embodiments, the first dielectric layer 200 may be formed by CVD or thermal oxidation. CVD can be low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD) ), PECVD, atomic layer deposition (ALD) or other suitable CVD process. In some embodiments, the first dielectric layer 200 is formed by thermal oxidation in a furnace tube.

詳細而言，第一介電層200可包含順應性地形成於第一凹槽121上的子介電層210、以及順應性地形成於第二凹槽122上的子介電層220。子介電層210設置於第一凹槽121的側表面及底表面上，因此子介電層210具有第一溝槽T1。子介電層220設置於第二凹槽122的側表面及底表面上，因此子介電層220具有第二溝槽T2。如第4圖所示，第一溝槽T1具有第二深度L2及第二寬度W2，且第二溝槽T2具有與第一溝槽T1實質上相同的深度及寬度。在一些實施例中，由於第一介電層200具有特定的厚度，因此第一溝槽T1的第二深度L2小於第一凹槽121的第一深度L1，且第一溝槽T1的第二寬度W2小於第一凹槽121的第一寬度W1。In detail, the first dielectric layer 200 may include a sub-dielectric layer 210 compliantly formed on the first groove 121 and a sub-dielectric layer 220 compliantly formed on the second groove 122 . The sub-dielectric layer 210 is disposed on the side surface and the bottom surface of the first groove 121, so the sub-dielectric layer 210 has the first trench T1. The sub-dielectric layer 220 is disposed on the side surface and the bottom surface of the second groove 122, so the sub-dielectric layer 220 has the second trench T2. As shown in FIG. 4, the first trench T1 has a second depth L2 and a second width W2, and the second trench T2 has substantially the same depth and width as the first trench T1. In some embodiments, since the first dielectric layer 200 has a specific thickness, the second depth L2 of the first trench T1 is smaller than the first depth L1 of the first groove 121 , and the second depth L2 of the first trench T1 The width W2 is smaller than the first width W1 of the first groove 121 .

也就是說，搭配參照第3圖及第4圖所示，由於第一介電層200的一部分形成於凹槽120中，因此在凹槽120中尚未形成有第一介電層200時，凹槽120的深寬比(aspect ratio)為第一深度L1與第一寬度W1的比值。然而，在凹槽120中形成有第一介電層200之後，第一介電層200具有的溝槽T的深寬比為第二深度L2與第二寬度W2。因此，在第一溝槽T1的第二深度L2小於第一凹槽121的第一深度L1，且第一溝槽T1的第二寬度W2小於第一凹槽121的第一寬度W1的情況下，形成第一介電層200之後，增加了深寬比。然而，當待填充的溝槽、凹槽、凹洞、凹部、或其類似結構具有較大的深寬比時，諸如導電材料之填充材料難以均勻的被填充於上述結構中，可能會產生在導電材料本體中的空隙、孔洞、接縫缺陷(seam defect)、及/或在導電材料表面處之凹陷部(recess)等不良結構，致使半導體結構中的導電結構之電性特徵劣化，而降低後續形成的SGT-MOSFET的可靠性。That is to say, referring to FIG. 3 and FIG. 4 , since a part of the first dielectric layer 200 is formed in the groove 120 , when the first dielectric layer 200 has not been formed in the groove 120 , the concave The aspect ratio of the groove 120 is the ratio of the first depth L1 to the first width W1. However, after the first dielectric layer 200 is formed in the groove 120, the first dielectric layer 200 has the trench T with an aspect ratio of the second depth L2 and the second width W2. Therefore, in the case where the second depth L2 of the first trench T1 is smaller than the first depth L1 of the first groove 121 and the second width W2 of the first trench T1 is smaller than the first width W1 of the first groove 121 , after the first dielectric layer 200 is formed, the aspect ratio is increased. However, when the trenches, grooves, concavities, concave portions, or similar structures to be filled have a large aspect ratio, it is difficult to fill the above-mentioned structures uniformly with filling materials such as conductive materials, which may cause problems in Undesirable structures such as voids, holes, seam defects, and/or recesses at the surface of the conductive material in the body of the conductive material degrade the electrical characteristics of the conductive structure in the semiconductor structure, thereby reducing the The reliability of the subsequently formed SGT-MOSFET.

為了減少或預防填充步驟，也就是形成導電結構的製程中產生的不良導電結構，本揭露的一些實施例藉由多階段形成製程，舉例而言，至少兩階段式形成製程，減少被形成的導電結構中的不良結構，來獲得具有更優良的電性特徵及可靠性的半導體結構。在下文中，參照第5圖至第9圖，詳細說明本揭露的一些實施例之藉由回蝕(etch back)第一導電層；蝕刻第一介電層的一部分；以及在第一導電層上形成第二導電層之兩階段式形成製程。In order to reduce or prevent the filling step, that is, the poor conductive structure generated in the process of forming the conductive structure, some embodiments of the present disclosure use a multi-stage formation process, for example, at least a two-stage formation process, to reduce the formed conductive structure. The defective structure in the structure can be obtained to obtain a semiconductor structure with better electrical characteristics and reliability. Hereinafter, with reference to FIGS. 5-9, some embodiments of the present disclosure are described in detail by etching back the first conductive layer; etching a portion of the first dielectric layer; and on the first conductive layer A two-stage formation process for forming the second conductive layer.

如第5圖所示，填充第一導電材料300於溝槽T中。也就是說，以第一導電材料300將第一溝槽T1及第二溝槽T2填滿，獲得設置於第一溝槽T1及第二溝槽T2中的第一導電層。上述第一導電材料300可包含多晶矽(polycrystalline silicon)、金屬、金屬氮化物、導電金屬氧化物、或其他合適的材料。在一些實施例中，第一導電材料300可為多晶矽。填充第一導電材料300的方法可包含：CVD、濺鍍法、電阻加熱蒸鍍法、電子束蒸鍍法、或其它任何適合的沈積製程，但不限於此。在一些實施例中，填充第一導電材料300的方式為原位(in-situ)沉積。As shown in FIG. 5 , the trench T is filled with the first conductive material 300 . That is, the first trench T1 and the second trench T2 are filled with the first conductive material 300 to obtain the first conductive layer disposed in the first trench T1 and the second trench T2. The above-mentioned first conductive material 300 may include polycrystalline silicon, metal, metal nitride, conductive metal oxide, or other suitable materials. In some embodiments, the first conductive material 300 may be polysilicon. The method of filling the first conductive material 300 may include, but is not limited to, CVD, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process. In some embodiments, the manner of filling the first conductive material 300 is in-situ deposition.

在一些實施例中，當第一導電材料300為多晶矽時，在對應於溝槽T的中心軸線處，第一導電材料300的表面可能會產生凹陷部，且在溝槽T中的第一導電材料300本身可能會具有如第5圖繪示之虛線所示的接縫缺陷。在一些實施例中，以剖面圖觀察時，第一導電材料300的表面可能產生的凹陷部具有V型(V shape)形狀、U型形狀(U shape)、圓弧型形狀(round shape)、或其他不規則的凹陷形狀。In some embodiments, when the first conductive material 300 is polysilicon, a depression may be formed on the surface of the first conductive material 300 at the center axis corresponding to the trench T, and the first conductive material in the trench T The material 300 itself may have seam defects as shown by the dashed lines depicted in FIG. 5 . In some embodiments, when viewed in a cross-sectional view, the concave portion that may be generated on the surface of the first conductive material 300 has a V shape, a U shape, a round shape, or other irregular concave shapes.

接著，如第6圖所示，回蝕第一導電材料300，直至暴露第一介電層200的頂表面，以形成設置於第一溝槽T1中的第一導電層310、以及設置於第二溝槽T2中的第一導電層320。在一些實施例中，第一導電層310的頂表面低於子介電層210的頂表面，且第一導電層320的頂表面低於子介電層220的頂表面。在一些實施例中，由於回蝕第一導電材料300，因此會暴露位於凹槽120的側表面上的第一介電層200的一部分，並形成位於溝槽T上部的開口OP。回蝕第一導電材料300的深度影響被暴露出的第一介電層200的上述部分的尺寸。開口OP的寬度可實質上與溝槽T的第二寬度W2相同。當回蝕第一導電材料300的深度越深，也就是第一導電層310及320的長度越短時，被暴露出的第一介電層200的上述部分的尺寸越大。在一些實施例中，即使已經對第一導電材料300進行回蝕，然而在對應於溝槽T的中心軸線處，經回蝕的第一導電材料300的表面仍會產生凹陷部，且在溝槽T中的第一導電材料300本身仍具有接縫缺陷。Next, as shown in FIG. 6 , the first conductive material 300 is etched back until the top surface of the first dielectric layer 200 is exposed, so as to form the first conductive layer 310 disposed in the first trench T1 and the first conductive layer 310 disposed in the first The first conductive layer 320 in the two trenches T2. In some embodiments, the top surface of the first conductive layer 310 is lower than the top surface of the sub-dielectric layer 210 , and the top surface of the first conductive layer 320 is lower than the top surface of the sub-dielectric layer 220 . In some embodiments, since the first conductive material 300 is etched back, a portion of the first dielectric layer 200 on the side surface of the groove 120 is exposed, and an opening OP is formed on the upper portion of the trench T. The depth to which the first conductive material 300 is etched back affects the size of the exposed portion of the first dielectric layer 200 described above. The width of the opening OP may be substantially the same as the second width W2 of the trench T. When the depth of the etch-back of the first conductive material 300 is deeper, that is, the lengths of the first conductive layers 310 and 320 are shorter, the size of the exposed portion of the first dielectric layer 200 is larger. In some embodiments, even if the first conductive material 300 has been etched back, at the central axis corresponding to the trench T, the etched back surface of the first conductive material 300 still produces a depression, and the trench T is The first conductive material 300 in the trench T itself still has seam defects.

在一些實施例中，由於回蝕第一導電材料300的深度會影響位於第一導電層310及320之上的待填充區域的深寬比，因此能夠藉由適當地回蝕第一導電材料300，來減少在第一導電層310及320之上的待填充區域的深寬比。在一些實施例中，以第三深度L3回蝕第一導電材料300，因此，經暴露的位於凹槽120的側表面上的第一介電層200的一部分的深度實質上為第三深度L3。其中，第三深度L3與第二深度L2的比值可為1/2~1/7。較佳地，第三深度L3與第二深度L2的比值可為2/5~1/7；更佳地，第三深度L3與第二深度L2的比值可為1/3~1/7。在一些實施例中，第三深度L3與第二深度L2的比值可為1/2~1/7之間的任意數值範圍。若第三深度L3與第二深度L2的比值過大，代表回蝕深度過深時，在第一導電層310及320之上待填充區域的深寬比，亦即第三深度L3與第二寬度W2的比值仍然會太大，致使接縫缺陷及/或凹陷會再次出現在待填充區域。若第三深度L3與第二深度L2的比值過小，代表回蝕深度過淺時，難以有效消除或減少在第一導電層310及320本身中的接縫缺陷。另外，須說明的是，在一些實施例中，即使在第一導電層310及320本身中的接縫缺陷未被完全消除，由於本揭露之一些實施例的半導體結構及其形成方法能夠使得接縫缺陷較為遠離後續形成的SGT-MOSFET中的接觸插塞，因此，仍能夠提升整體半導體結構的電性特徵與可靠度。In some embodiments, since the depth of the etch-back of the first conductive material 300 will affect the aspect ratio of the area to be filled above the first conductive layers 310 and 320 , the first conductive material 300 can be etched back appropriately , to reduce the aspect ratio of the area to be filled above the first conductive layers 310 and 320 . In some embodiments, the first conductive material 300 is etched back at the third depth L3, so that the exposed portion of the first dielectric layer 200 on the side surface of the groove 120 has a depth substantially at the third depth L3 . The ratio of the third depth L3 to the second depth L2 may be 1/2˜1/7. Preferably, the ratio of the third depth L3 to the second depth L2 may be 2/5˜1/7; more preferably, the ratio of the third depth L3 to the second depth L2 may be 1/3˜1/7. In some embodiments, the ratio of the third depth L3 to the second depth L2 may be in any numerical range between 1/2˜1/7. If the ratio of the third depth L3 to the second depth L2 is too large, it represents the aspect ratio of the area to be filled above the first conductive layers 310 and 320 when the etch back depth is too deep, that is, the third depth L3 and the second width The ratio of W2 will still be too large, causing seam defects and/or depressions to reappear in the area to be filled. If the ratio of the third depth L3 to the second depth L2 is too small, it means that when the etch back depth is too shallow, it is difficult to effectively eliminate or reduce the seam defects in the first conductive layers 310 and 320 themselves. In addition, it should be noted that, in some embodiments, even if the seam defects in the first conductive layers 310 and 320 themselves are not completely eliminated, the semiconductor structure and the forming method thereof in some embodiments of the present disclosure can make the connection The seam defects are relatively far away from the contact plugs in the subsequently formed SGT-MOSFET, so the electrical characteristics and reliability of the overall semiconductor structure can still be improved.

再者，如第7圖所示，蝕刻第一介電層200，以移除第一介電層200的一部分，而使得位於凹槽120的側表面上的第一介電層200的上述部分具有沿著遠離凹槽120的底表面的方向變小的寬度。蝕刻第一介電層200的製程可包含乾式蝕刻、或濕式蝕刻、或其他合適的蝕刻方式。在一些實施例中，藉由濕式蝕刻製程蝕刻第一介電層200。在一些實施例中，使用緩衝氧化物刻蝕液(BOE，Buffered Oxide Etch)作為濕式蝕刻劑。BOE係包含氫氟酸(HF，fluorhydric acid)、氟化銨(NH 4F，ammonium fluoride)、以及水，但不限制於此，可以使用任何能夠蝕刻第一介電層200的蝕刻劑。此外，再搭配使用第一導電層310及320作為蝕刻遮罩，來進行濕式蝕刻。若在沒有作為蝕刻遮罩的第一導電層310及320的情況下，可能會難以在上述特定部分處執行濕式蝕刻製程，因此無法有效地移除第一介電層200的上述部分。 Furthermore, as shown in FIG. 7 , the first dielectric layer 200 is etched to remove a part of the first dielectric layer 200 so that the above-mentioned part of the first dielectric layer 200 is located on the side surface of the groove 120 It has a decreasing width in a direction away from the bottom surface of the groove 120 . The process of etching the first dielectric layer 200 may include dry etching, wet etching, or other suitable etching methods. In some embodiments, the first dielectric layer 200 is etched by a wet etch process. In some embodiments, Buffered Oxide Etch (BOE) is used as the wet etchant. The BOE system includes hydrofluoric acid (HF, fluorhydric acid), ammonium fluoride (NH 4 F, ammonium fluoride), and water, but is not limited thereto, and any etchant capable of etching the first dielectric layer 200 may be used. In addition, wet etching is performed by using the first conductive layers 310 and 320 as etching masks. Without the first conductive layers 310 and 320 serving as etch masks, it may be difficult to perform the wet etching process at the above-mentioned specific portion, so the above-mentioned portion of the first dielectric layer 200 cannot be removed effectively.

接著，在對第一介電層200進行濕式蝕刻製程後，由於位於凹槽120的側表面上的第一介電層200的一部分、以及位於基板100的頂表面上的第一介電層200的一部分被濕式蝕刻製程移除，因此使得第一介電層200的上部的第五寬度W5小於第一介電層200的下部的第四寬度W4，且使得位於開口OP上部的第三寬度W3大於位於開口OP的下部的第二寬度W2。在一些實施例中，第二寬度W2對應於第四寬度W4，且第三寬度W3對應於第五寬度W5，且能夠藉由調整濕式蝕刻製程的蝕刻速率、蝕刻選擇性等參數，來改變開口OP的形狀。在一些實施例中，第三寬度W3與第二寬度W2的比值可為1.1~1.5。對應地，第五寬度W5與第四寬度W4的比值可小於1；較佳地可為0.5~1。當第三寬度W3與第二寬度W2的比值過大時，可能會導致後續形成於溝槽T中的電極的側壁的絕緣性質不佳，而產生漏電流或短路的問題；然而當第三寬度W3與第二寬度W2的比值過小時，無法顯著地將開口OP的形狀轉變為上寬下窄的形狀，所以難以提升後續填充第二導電材料的容易性，此外在後續填充的第二導電材料本身中可能仍然會存在接縫缺陷。Next, after the wet etching process is performed on the first dielectric layer 200 , due to the part of the first dielectric layer 200 located on the side surface of the groove 120 and the first dielectric layer located on the top surface of the substrate 100 A part of 200 is removed by the wet etching process, so that the fifth width W5 of the upper part of the first dielectric layer 200 is smaller than the fourth width W4 of the lower part of the first dielectric layer 200, and the third width W4 of the upper part of the opening OP is made The width W3 is greater than the second width W2 at the lower portion of the opening OP. In some embodiments, the second width W2 corresponds to the fourth width W4, and the third width W3 corresponds to the fifth width W5, which can be changed by adjusting parameters such as etching rate and etching selectivity of the wet etching process The shape of the opening OP. In some embodiments, the ratio of the third width W3 to the second width W2 may be 1.1˜1.5. Correspondingly, the ratio of the fifth width W5 to the fourth width W4 may be less than 1; preferably, it may be 0.5˜1. When the ratio of the third width W3 to the second width W2 is too large, the insulating properties of the sidewalls of the electrodes subsequently formed in the trench T may be poor, resulting in leakage current or short circuit problems; however, when the third width W3 When the ratio to the second width W2 is too small, the shape of the opening OP cannot be significantly changed to a shape with a wide upper and a narrow lower, so it is difficult to improve the ease of subsequent filling of the second conductive material. There may still be seam defects.

如第8圖所示，填充第二導電材料400於溝槽T中，以形成在第一導電層310及320上的第二導電層。在一些實施例中，第一導電材料300與第二導電材料400可為相同或不同。在一些實施例中，第一導電材料300與第二導電材料400為相同，因此經填充的第一導電材料300與第二導電材料400可共同形成導電結構。在一些實施例中，第一導電材料300與第二導電材料400皆為多晶矽，因此儘管先後設置第一導電材料300與第二導電材料400，第一導電材料300與第二導電材料400能被一體化為導電結構。As shown in FIG. 8 , a second conductive material 400 is filled in the trench T to form a second conductive layer on the first conductive layers 310 and 320 . In some embodiments, the first conductive material 300 and the second conductive material 400 may be the same or different. In some embodiments, the first conductive material 300 and the second conductive material 400 are the same, so the filled first conductive material 300 and the second conductive material 400 can jointly form a conductive structure. In some embodiments, the first conductive material 300 and the second conductive material 400 are both polysilicon, so although the first conductive material 300 and the second conductive material 400 are arranged in sequence, the first conductive material 300 and the second conductive material 400 can be Integrated into a conductive structure.

詳細而言，由於溝槽T內已經設置有第一導電層310及320，因此在第一導電層310及320之上的待填充區域的深寬比較小，也就是第三深度L3與第二寬度W2的比值小於第二深度L2與第二寬度W2的比值(如第7圖所示)，因此，進一步填充於溝槽T中的第二導電材料400本身不具有接縫缺陷，而具有良好的電性特徵。此外，還能填充第二導電材料400，有效地將第一導電層310及320表面處的凹陷部填滿，而使得同時包含第一導電材料300與第二導電材料400的導電結構具有良好的電性特徵。In detail, since the first conductive layers 310 and 320 are already disposed in the trench T, the depth and width of the area to be filled above the first conductive layers 310 and 320 is relatively small, that is, the third depth L3 and the second depth L3 The ratio of the width W2 is smaller than the ratio of the second depth L2 to the second width W2 (as shown in FIG. 7 ), therefore, the second conductive material 400 further filled in the trench T itself does not have seam defects, but has good electrical characteristics. In addition, the second conductive material 400 can also be filled, effectively filling the recesses on the surfaces of the first conductive layers 310 and 320, so that the conductive structure including the first conductive material 300 and the second conductive material 400 at the same time has good performance. electrical characteristics.

如第9圖所示，藉由平坦化第二導電材料400，形成設置於第一導電層310上的第二導電層410、以及設置於第一導電層320上的第二導電層420。在一些實施例中，平坦化製程可包含化學機械研磨(chemical mechanical polishing，CMP)製程，但不限於此，以使第二導電層410及420的頂表面與第一介電層200的頂表面實質上為共平面。在一些實施例中，平坦化製程也可包含回蝕(etch back)的方式，但不限於此，以使第二導電層410及420的頂表面與第一介電層200的頂表面實質上為共平面。在一些實施例中，雖然採用回蝕(etch back)的方式處理的第二導電材料400的表面仍然可能會具有些微凹陷，然而回蝕(etch back)後產生的些微凹陷已對於整體半導體結構的電性無太大影響。也就是說，藉由平坦化第二導電材料400的製程，能夠輕易地消除第二導電材料400的表面存在凹陷部、或凹陷部影響電性的問題，以形成電性良好的第二導電層410及420，進而獲得本揭露之一些實施例的半導體結構1。As shown in FIG. 9 , by planarizing the second conductive material 400 , the second conductive layer 410 disposed on the first conductive layer 310 and the second conductive layer 420 disposed on the first conductive layer 320 are formed. In some embodiments, the planarization process may include, but is not limited to, a chemical mechanical polishing (CMP) process, so that the top surfaces of the second conductive layers 410 and 420 and the top surface of the first dielectric layer 200 are substantially coplanar. In some embodiments, the planarization process may also include, but is not limited to, etch back, so that the top surfaces of the second conductive layers 410 and 420 and the top surface of the first dielectric layer 200 are substantially substantially is coplanar. In some embodiments, although the surface of the second conductive material 400 processed by the etch back method may still have slight concavities, the slight concavities generated after the etch back have no effect on the overall semiconductor structure. Electricity is not much affected. That is to say, through the process of planarizing the second conductive material 400 , the problem of the presence of recesses on the surface of the second conductive material 400 or the problem that the recesses affect the electrical properties can be easily eliminated, so as to form a second conductive layer with good electrical properties 410 and 420 are performed, thereby obtaining the semiconductor structure 1 of some embodiments of the present disclosure.

在一些實施例中，由於開口OP(如第7圖所示)具有上寬下窄的形狀，因此第二導電層410及420具有對應於開口OP的形狀，換句話說，由於開口OP形狀對應於第一介電層200的形狀，因此第二導電層410及420具有對應第一介電層200的形狀。在一些實施例中，第二導電層410及420的頂表面寬度大於底表面的寬度。In some embodiments, since the opening OP (as shown in FIG. 7 ) has a shape that is wide at the top and narrow at the bottom, the second conductive layers 410 and 420 have a shape corresponding to the opening OP. In other words, since the shape of the opening OP corresponds to Due to the shape of the first dielectric layer 200 , the second conductive layers 410 and 420 have shapes corresponding to the first dielectric layer 200 . In some embodiments, the width of the top surface of the second conductive layers 410 and 420 is greater than the width of the bottom surface.

簡言之，在本揭露的一些實施例中，藉由回蝕第一導電材料300，來調整位於第一導電層310及320之上的待填充區域的深度；藉由使用濕式蝕刻製程移除第一介電層200的一部分，使得開口OP具有上寬下窄的形狀；以及填充第二導電材料400之兩階段式形成製程，達到(1)減少經填充的第二導電材料400中的接縫缺陷、(2)形成電性良好的第二導電層410及420、及/或(3)藉由被填充的第二導電材料400來填滿第一導電層310及320表面處的凹陷部，消除第一導電層310及320的缺陷之優點，因此能夠而形成具有良好電性特徵的半導體結構1。In short, in some embodiments of the present disclosure, the depth of the area to be filled above the first conductive layers 310 and 320 is adjusted by etching back the first conductive material 300; A part of the first dielectric layer 200 is removed, so that the opening OP has a shape that is wide at the top and narrow at the bottom; and a two-stage formation process for filling the second conductive material 400 to achieve (1) reduce the amount of the filled second conductive material 400 Seam defects, (2) forming the second conductive layers 410 and 420 with good electrical properties, and/or (3) filling the recesses on the surfaces of the first conductive layers 310 and 320 with the filled second conductive material 400 part, the advantages of eliminating the defects of the first conductive layers 310 and 320 are eliminated, so that the semiconductor structure 1 with good electrical characteristics can be formed.

接著，在獲得本揭露之一些實施例的半導體結構1後，可執行進一步的製程來獲得具有本揭露之半導體結構1的SGT-MOSFET。因此，在下文中，詳細說明基於半導體結構1的SGT-MOSFET結構。Next, after obtaining the semiconductor structure 1 of some embodiments of the present disclosure, further processes may be performed to obtain the SGT-MOSFET having the semiconductor structure 1 of the present disclosure. Therefore, in the following, the SGT-MOSFET structure based on the semiconductor structure 1 is explained in detail.

需特別說明的是，為使便於說明，以下針對包含設置於第一溝槽T1中的遮蔽電極與閘極電極、以及設置於第二溝槽T2中的源極電極之SGT-MOSFET結構進行詳細敘述。然而，本揭露係不限於此。It should be noted that, for the convenience of description, the following describes the SGT-MOSFET structure including the shielding electrode and the gate electrode arranged in the first trench T1 and the source electrode arranged in the second trench T2 in detail. narrative. However, the present disclosure is not limited thereto.

參照第10圖，由於第一溝槽T1中的第一導電層310與第二導電層410後續將形成為遮蔽電極，因此需要移除第二導電層410的一部分，以便於設置位於遮蔽電極上的閘極電極。然而，由於第二溝槽T2中的第一導電層320與第二導電層420後續將形成為源極電極，因此可藉由設置光阻層430來保護第一導電層320與第二導電層420。所以移除設置於第一溝槽T1中的第二導電層410的一部分，使得第二導電層410的頂表面低於基板100的頂表面，並在第一溝槽T1中留下作為遮蔽電極的導電結構。其中，作為遮蔽電極的導電結構包含第一導電層310及剩餘的第二導電層410。可藉由執行蝕刻製程或其他合適的製程來移除第二導電層410的一部分。此處的蝕刻製程可包含前述蝕刻製程中的任意蝕刻製程。Referring to FIG. 10, since the first conductive layer 310 and the second conductive layer 410 in the first trench T1 will be formed as shielding electrodes later, a part of the second conductive layer 410 needs to be removed so as to be disposed on the shielding electrodes gate electrode. However, since the first conductive layer 320 and the second conductive layer 420 in the second trench T2 will be formed as source electrodes later, the photoresist layer 430 can be provided to protect the first conductive layer 320 and the second conductive layer 420. Therefore, a part of the second conductive layer 410 disposed in the first trench T1 is removed, so that the top surface of the second conductive layer 410 is lower than the top surface of the substrate 100, and is left in the first trench T1 as a shielding electrode conductive structure. The conductive structure serving as the shielding electrode includes the first conductive layer 310 and the remaining second conductive layer 410 . A portion of the second conductive layer 410 may be removed by performing an etching process or other suitable process. The etching process here can include any etching process in the foregoing etching process.

在一些實施例中，移除第二導電層410的一部分直至第二導電層410的頂表面與第一導電層310的頂表面共平面，然而本揭露不限於此。在一些實施例中，第二導電層410的頂表面可高於第一導電層310的頂表面，因此須說明的是，只要在移除第二導電層410的一部分之後，剩餘的第二導電層410仍能完全填充第一導電層310的表面處的凹陷部，即能消除第一導電層310的缺陷。In some embodiments, a portion of the second conductive layer 410 is removed until the top surface of the second conductive layer 410 and the top surface of the first conductive layer 310 are coplanar, although the present disclosure is not limited thereto. In some embodiments, the top surface of the second conductive layer 410 may be higher than the top surface of the first conductive layer 310, so it should be noted that as long as a part of the second conductive layer 410 is removed, the remaining second conductive layer 410 The layer 410 can still completely fill the recesses at the surface of the first conductive layer 310 , that is, the defects of the first conductive layer 310 can be eliminated.

參照第11圖，移除第一介電層200的一部分，也就是移除對應於第一溝槽T1的子介電層210的一部分，使得子介電層210的頂表面平行或低於導電結構的頂表面。在一些實施例中，子介電層210的頂表面低於第二導電層410的頂表面。在一些實施例中，移除光阻層430，以暴露子介電層220及第二導電層420。Referring to FIG. 11, a part of the first dielectric layer 200 is removed, that is, a part of the sub-dielectric layer 210 corresponding to the first trench T1 is removed, so that the top surface of the sub-dielectric layer 210 is parallel or lower than the conductive layer the top surface of the structure. In some embodiments, the top surface of the sub-dielectric layer 210 is lower than the top surface of the second conductive layer 410 . In some embodiments, the photoresist layer 430 is removed to expose the sub-dielectric layer 220 and the second conductive layer 420 .

參照第12圖，順應性地形成第二介電層500於導電結構上，亦即形成於第二導電層420上。在一些實施例中，第二介電層500的底表面具有對應於子介電層210以及導電結構的形狀。在一些實施例中，第二介電層500的底表面可為實質上平坦的表面。在一些實施例中，由於第二導電層420的頂表面高於基板100的頂表面，因此第二介電層500可為階梯狀(step-shape)。在一些實施例中，第二介電層500作為閘極介電層。第二介電層500可為氧化矽、氮化矽、氮氧化矽、低介電常數(low-k)介電材料、或其它任何適合之介電材料、或上述之組合，但不限制於此。在一些實施例中，第二介電層500可包含氧化物。在一些實施例中，第二介電層500與第一介電層200可以相同或不同的製程形成。Referring to FIG. 12 , the second dielectric layer 500 is conformably formed on the conductive structure, that is, formed on the second conductive layer 420 . In some embodiments, the bottom surface of the second dielectric layer 500 has a shape corresponding to the sub-dielectric layer 210 and the conductive structure. In some embodiments, the bottom surface of the second dielectric layer 500 may be a substantially flat surface. In some embodiments, since the top surface of the second conductive layer 420 is higher than the top surface of the substrate 100 , the second dielectric layer 500 may be step-shaped. In some embodiments, the second dielectric layer 500 acts as a gate dielectric layer. The second dielectric layer 500 can be silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, or any other suitable dielectric material, or a combination of the above, but not limited to this. In some embodiments, the second dielectric layer 500 may include oxide. In some embodiments, the second dielectric layer 500 and the first dielectric layer 200 may be formed by the same or different processes.

參照第13圖，填充第三導電材料600，以形成第三導電層610於第二介電層500上。在一些實施例中，類似於第5圖所示的第一導電材料300，第三導電材料600的表面可能產生凹陷部，然而由於第一凹槽121的深寬比，因此凹陷部可不出現在第一凹槽121中。在一些實施例中，第三導電材料600可與第一導電材料300及第二導電材料400為相同或不同。在一些實施例中，第三導電材料600可為多晶矽。在一些實施例中，第三導電層610作為閘極電極。在一些實施例中，由於第二介電層500順應性地形成於子介電層210及導電結構上，因此第三導電層610具有朝向導電結構延伸的延伸部，也就是說，第三導電層610的底表面的一部分低於第二導電層410的頂表面。Referring to FIG. 13 , a third conductive material 600 is filled to form a third conductive layer 610 on the second dielectric layer 500 . In some embodiments, similar to the first conductive material 300 shown in FIG. 5 , the surface of the third conductive material 600 may have a concave portion, but due to the aspect ratio of the first groove 121 , the concave portion may not appear. in the first groove 121 . In some embodiments, the third conductive material 600 may be the same as or different from the first conductive material 300 and the second conductive material 400 . In some embodiments, the third conductive material 600 may be polysilicon. In some embodiments, the third conductive layer 610 acts as a gate electrode. In some embodiments, since the second dielectric layer 500 is compliantly formed on the sub-dielectric layer 210 and the conductive structure, the third conductive layer 610 has an extension extending toward the conductive structure, that is, the third conductive layer A portion of the bottom surface of the layer 610 is lower than the top surface of the second conductive layer 410 .

參照第14圖，在一實施例中，填充第三導電材料600的製程可與填充第一導電材料300及第二導電材料400的製程相同或不同。詳細而言，在一些實施例中，可填充第三導電材料600於第二介電層500上，然後進一步執行平坦化製程，以暴露第二介電層500的頂表面。在一些實施例中，在執行平坦化製程，諸如：多晶矽回蝕(polysilicon etch back)的製程期間，蝕刻第二介電層500的一部分，使得第二介電層500的一部分的厚度減少，然而，仍保留第二介電層500而使第二介電層500可不被全部蝕刻。在一些實施例中，藉由第二介電層500保護的第一導電層320及第二導電層420可共同作為源極電極。 Referring to FIG. 14 , in one embodiment, the process of filling the third conductive material 600 may be the same as or different from the process of filling the first conductive material 300 and the second conductive material 400 . In detail, in some embodiments, the third conductive material 600 may be filled on the second dielectric layer 500 , and then a planarization process may be further performed to expose the top surface of the second dielectric layer 500 . In some embodiments, during a planarization process, such as a polysilicon etch back process, a portion of the second dielectric layer 500 is etched such that the thickness of the portion of the second dielectric layer 500 is reduced, however , the second dielectric layer 500 is still retained so that the second dielectric layer 500 may not be completely etched. In some embodiments, the first conductive layer 320 and the second conductive layer 420 protected by the second dielectric layer 500 may collectively serve as a source electrode.

參照第15圖，執行平坦化製程後，第二介電層500的一部分厚度減少，接著，形成第三介電層700於閘極電極與源極電極上。第三介電層700形成於作為閘極電極的第三導電層610上，且第三介電層700形成於作為源極電極的一部分的第二導電層420上，並且第三介電層700與基板100頂表面上的第一介電層200以及第二介電層500形成層間介電(interlayer dielectric)層ILD。在一些實施例中，基板100頂表面上的第一介電層200可為子介電層220在基板100頂表面上的一部分。第三介電層700可為氧化矽、氮化矽、氮氧化矽、低介電常數(low-k)介電材料、或其它任何適合之介電材料、或上述之組合，但不限制於此。在一些實施例中，第三介電層700與第二介電層500或第一介電層200可以相同或不同材料形成。在一些實施例中，第三介電層700與第二介電層500或第一介電層200可以相同或不同的製程形成。 Referring to FIG. 15, after the planarization process is performed, a part of the thickness of the second dielectric layer 500 is reduced, and then a third dielectric layer 700 is formed on the gate electrode and the source electrode. The third dielectric layer 700 is formed on the third conductive layer 610 as a gate electrode, and the third dielectric layer 700 is formed on the second conductive layer 420 as a part of the source electrode, and the third dielectric layer 700 An interlayer dielectric layer ILD is formed with the first dielectric layer 200 and the second dielectric layer 500 on the top surface of the substrate 100 . In some embodiments, the first dielectric layer 200 on the top surface of the substrate 100 may be a portion of the sub-dielectric layer 220 on the top surface of the substrate 100 . The third dielectric layer 700 can be silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, or any other suitable dielectric material, or a combination of the above, but not limited to this. In some embodiments, the third dielectric layer 700 and the second dielectric layer 500 or the first dielectric layer 200 may be formed of the same material or different materials. In some embodiments, the third dielectric layer 700 and the second dielectric layer 500 or the first dielectric layer 200 may be formed by the same or different processes.

參照第16圖，為方便後續說明及理解，將第一介電層200、第二介電層500以及第三介電層700僅以層間介電層ILD表示，在基板100中形成第一摻雜區110與第二摻雜區120。第二摻雜區120相較於第一摻雜區110更遠離基板100的頂表面，也就是第二摻雜區120相較於第一摻雜區110更遠離層間介電層ILD。 形成第一摻雜區110與第二摻雜區120的方式包含：舉例而言，離子植入(ion implantation)或擴散(diffusion)製程來形成，但不限於此。另外，還可藉由快速熱退火(rapid thermal annealing，RTA)製程來活化被植入的摻質。在一些實施例中，第一摻雜區110與第二摻雜區120具有相同或不同的導電型態。在一些實施例中，第一摻雜區110與第二摻雜區120具有相同的導電型態。在一些實施例中，基板100具有第一導電型態，第一摻雜區110及第二摻雜區120具有不同於第一導電型態的第二導電型態。舉例而言，若基板100具有的第一導電型態為N型，則第一摻雜區110及第二摻雜區120具有的第二導電型態為P型，第一導電型態與第二導電型態可依據需求調整。 Referring to FIG. 16 , for the convenience of subsequent description and understanding, the first dielectric layer 200 , the second dielectric layer 500 and the third dielectric layer 700 are only represented by the interlayer dielectric layer ILD, and a first dopant is formed in the substrate 100 The impurity region 110 and the second impurity region 120 . The second doped region 120 is further away from the top surface of the substrate 100 than the first doped region 110 , that is, the second doped region 120 is further away from the interlayer dielectric layer ILD than the first doped region 110 . The manner of forming the first doped region 110 and the second doped region 120 includes, for example, ion implantation or diffusion process, but is not limited thereto. In addition, the implanted dopants can be activated by a rapid thermal annealing (RTA) process. In some embodiments, the first doped region 110 and the second doped region 120 have the same or different conductivity types. In some embodiments, the first doped region 110 and the second doped region 120 have the same conductivity type. In some embodiments, the substrate 100 has a first conductivity type, and the first doped region 110 and the second doped region 120 have a second conductivity type different from the first conductivity type. For example, if the first conductivity type of the substrate 100 is N-type, the second conductivity type of the first doped region 110 and the second doped region 120 is P-type, and the first conductivity type and the second conductivity type are P-type. The two-conductivity type can be adjusted according to needs.

參照第17圖所示，形成接觸通孔CT。接觸通孔CT可貫穿層間介電層ILD。在一些實施例中，接觸通孔CT的底表面低於第三導電層610的頂表面，以確保後續在接觸通孔CT中形成的接觸插塞與作為閘極電極的第三導電層610、以及共同作為源極電極的第一導電層320及第二導電層420有良好的電性接觸。在一些實施例中，接觸通孔CT的底表面低於第二導電層420的頂表面。在一些實施例中，接觸通孔CT貫穿第一摻雜區110但不貫穿第二摻雜區120。在一些實施例中，第一摻雜區110與第二摻雜區120共同覆蓋後續形成的接觸插塞。接觸通孔CT暴露設置於第三導電層610與第二導電層420的一部分。在另一些實施例中，接觸通孔CT的底表面與第三導電層610的頂表面齊平，且接觸通孔CT的底表面與第二導電層420的頂表面齊平。 Referring to FIG. 17, contact vias CT are formed. The contact via CT may penetrate through the interlayer dielectric layer ILD. In some embodiments, the bottom surface of the contact through hole CT is lower than the top surface of the third conductive layer 610, so as to ensure that the contact plugs formed in the contact through hole CT and the third conductive layer 610, the gate electrode and the third conductive layer 610, which are gate electrodes, are formed in the contact through hole CT. And the first conductive layer 320 and the second conductive layer 420, which together serve as the source electrode, have good electrical contact. In some embodiments, the bottom surface of the contact via CT is lower than the top surface of the second conductive layer 420 . In some embodiments, the contact via CT penetrates the first doped region 110 but does not penetrate the second doped region 120 . In some embodiments, the first doped region 110 and the second doped region 120 together cover the contact plugs formed subsequently. The contact via CT is exposed to a part of the third conductive layer 610 and the second conductive layer 420 . In other embodiments, the bottom surface of the contact via CT is flush with the top surface of the third conductive layer 610 , and the bottom surface of the contact via CT is flush with the top surface of the second conductive layer 420 .

在一些實施例中，形成第一摻雜區110與第二摻雜 區120的步驟可依需求與形成接觸通孔CT的步驟的順序可依製程上的需求進行調整，本發明不以此為限。 In some embodiments, the first doped region 110 and the second doped region are formed The steps of the region 120 can be adjusted according to the requirements and the sequence of the steps of forming the contact vias CT can be adjusted according to the requirements of the process, and the invention is not limited thereto.

參照第18圖，填入通孔材料701於接觸通孔CT中，以形成接觸插塞710、720及730。在一些實施例中，通孔材料可包含金屬材料、導電材料、或其他合適的材料。在一些實施例中，移除層間介電層ILD及接觸通孔CT上的通孔材料701的一部分，以形成接觸插塞710、720及730。參照第19圖所示，接著形成金屬層800於層間介電層ILD上，使金屬層800與接觸插塞710、720及730彼此接觸，以獲得本揭露的一些實施例的SGT-MOSFET。在一些實施例中，接觸插塞710與作為閘極電極的第三導電層610、及金屬層800電性連接，且接觸插塞720及730與作為源極電極的第一導電層320與第二導電層420、及金屬層800電性連接。 Referring to FIG. 18 , the through hole material 701 is filled in the contact through hole CT to form the contact plugs 710 , 720 and 730 . In some embodiments, the via material may comprise metallic material, conductive material, or other suitable material. In some embodiments, a portion of the via material 701 on the interlayer dielectric layer ILD and the contact via CT is removed to form the contact plugs 710 , 720 and 730 . Referring to FIG. 19 , a metal layer 800 is then formed on the interlayer dielectric layer ILD, so that the metal layer 800 and the contact plugs 710 , 720 and 730 are in contact with each other, so as to obtain the SGT-MOSFET of some embodiments of the present disclosure. In some embodiments, the contact plug 710 is electrically connected to the third conductive layer 610 serving as the gate electrode and the metal layer 800, and the contact plugs 720 and 730 are electrically connected to the first conductive layer 320 and the third conductive layer serving as the source electrode. The two conductive layers 420 and the metal layer 800 are electrically connected.

綜上所述，根據本揭露的一些實施例，本揭露藉由兩階段式形成製程與特定的半導體結構來進一步改善半導體結構的電性特徵，相應地提升包含本揭露之半導體結構的SGT-MOSFET的電性特徵與可靠性。舉例而言，由於本揭露的第一導電層310及第二導電層420表面處的凹陷部及接縫缺陷藉由兩階段式形成製程來改善，因此降低閘極源極漏電流(gate-source leakage)與崩潰(breakdown)的問題，進而改善包含本揭露之半導體結構的SGT-MOSFET的電性特徵與可靠性。此外，由於本揭露係提供一種包含優良地填充導電材料的步驟的半導體結構之形成方法，因此本揭露所述的形成方法能夠廣泛應用於各種導電材料的填充製程，並為一種能以簡單的步驟形成缺陷較少的電極之形成方法。舉例而言，本揭露之半導體結構的形成方法可廣泛地用於各種填充多晶矽以形成電極的製程中。To sum up, according to some embodiments of the present disclosure, the present disclosure further improves the electrical characteristics of the semiconductor structure through a two-stage forming process and a specific semiconductor structure, and accordingly improves the SGT-MOSFET including the semiconductor structure of the present disclosure electrical characteristics and reliability. For example, since the recesses and seam defects on the surfaces of the first conductive layer 310 and the second conductive layer 420 of the present disclosure are improved by the two-stage formation process, the gate-source leakage current is reduced. leakage) and breakdown problems, thereby improving the electrical characteristics and reliability of the SGT-MOSFET including the semiconductor structure of the present disclosure. In addition, since the present disclosure provides a method for forming a semiconductor structure including the step of filling conductive materials well, the forming method described in the present disclosure can be widely used in filling processes of various conductive materials, and is a simple step A method of forming electrodes with fewer defects. For example, the method of forming the semiconductor structure of the present disclosure can be widely used in various processes for filling polysilicon to form electrodes.

應理解的是，儘管本揭露實施例僅揭示特定之半導體結構及其製造方法，然而本揭露實施例之至少兩階段式形成製程亦可應用於其它任何需要填充諸如多晶矽之導電材料的半導體結構及/或裝置的形成方法中，例如互補式MOS(CMOS)電晶體、雙載子接面電晶體(BJT)、橫向擴散型MOS(LDMOS)電晶體、垂直型MOS(VDMOS)電晶體、高功率MOS電晶體或任何其他類型的電晶體等。It should be understood that, although the disclosed embodiments only disclose specific semiconductor structures and fabrication methods thereof, the at least two-stage formation process of the disclosed embodiments can also be applied to any other semiconductor structures that need to be filled with conductive materials such as polysilicon and and/or device formation methods, such as complementary MOS (CMOS) transistors, bipolar junction transistors (BJT), laterally diffused MOS (LDMOS) transistors, vertical MOS (VDMOS) transistors, high power MOS transistor or any other type of transistor etc.

雖然本揭露的實施例及其優點已揭露如上，但應該瞭解的是，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作更動、替代與潤飾。此外，本揭露之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本揭露一些實施例之揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本揭露一些實施例使用。因此，本揭露之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本揭露之保護範圍也包括各個申請專利範圍及實施例的組合。Although the embodiments of the present disclosure and their advantages have been disclosed above, it should be understood that those skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the process, machine, manufacture, material composition, device, method and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the technical field can learn some implementations from the present disclosure. In the disclosure of the examples, it is understood that processes, machines, manufactures, compositions of matter, devices, methods and steps developed in the present or in the future, as long as substantially the same functions can be implemented or substantially the same results can be obtained in the embodiments described herein. Some embodiments of the present disclosure are used. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufactures, compositions of matter, devices, methods and steps. In addition, each claimed scope constitutes a separate embodiment, and the protection scope of the present disclosure also includes the combination of each claimed scope and the embodiments.

以上概述數個實施例，以便在本揭露所屬技術領域中具有通常知識者可以更理解本揭露實施例的觀點。在本揭露所屬技術領域中具有通常知識者應該理解，他們能以本揭露實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本揭露所屬技術領域中具有通常知識者也應該理解到，此類等效的製程和結構並無悖離本揭露的精神與範圍，且他們能在不違背本揭露之精神和範圍之下，做各式各樣的改變、取代和替換。Several embodiments are summarized above, so that those with ordinary knowledge in the technical field to which the present disclosure pertains can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure pertains should understand that they can, based on the embodiments of the present disclosure, design or modify other processes and structures to achieve the same purposes and/or advantages of the embodiments described herein. Those with ordinary knowledge in the technical field to which the present disclosure pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure, and they can, without departing from the spirit and scope of the present disclosure, Make all kinds of changes, substitutions, and substitutions.

1：半導體結構 100：基板 101：圖案化硬遮罩 110：第一摻雜區 120：第二摻雜區 120:凹槽 121:第一凹槽 122：第二凹槽 200；第一介電層 210,220：子介電層 300：第一導電材料 310,320：第一導電層 400：第二導電材料 410,420：第二導電層 430：光阻層 500：第二介電層 600；第三導電材料 610：第三導電層 700：第三介電層 701：通孔材料 710,720,730：接觸插塞 800：金屬層 CT：接觸通孔 ILD:層間介電層 L1：第一深度 L2：第二深度 L3：第三深度 L4：第四深度 OP：開口 T：溝槽 T1：第一溝槽 T2：第二溝槽 W1：第一寬度 W2：第二寬度 W3：第三寬度 W4：第四寬度 W5：第五寬度 1: Semiconductor structure 100: Substrate 101: Patterned Hardmask 110: first doped region 120: the second doping region 120: groove 121: The first groove 122: Second groove 200; first dielectric layer 210, 220: Sub-dielectric layer 300: first conductive material 310, 320: First Conductive Layer 400: Second Conductive Material 410, 420: Second Conductive Layer 430: photoresist layer 500: Second Dielectric Layer 600; The third conductive material 610: Third Conductive Layer 700: Third Dielectric Layer 701: Through-hole material 710, 720, 730: Contact Plugs 800: Metal layer CT: Contact Via ILD: Interlayer Dielectric Layer L1: first depth L2: second depth L3: third depth L4: Fourth depth OP: open mouth T: groove T1: First trench T2: Second trench W1: first width W2: Second width W3: third width W4: Fourth width W5: Fifth width

藉由以下的詳述配合所附圖式，我們能更加理解本揭露實施例的觀點。值得注意的是，根據工業上的標準慣例，一些部件(feature)可能沒有按照比例繪製。事實上，為了能清楚地討論，不同部件的尺寸可能被增加或減少。 第1圖至第9圖是根據本揭露的一些實施例，繪示在各個階段形成半導體結構的剖面示意圖；及 第10圖至第19圖是根據本揭露的一些實施例，繪示出基於第9圖所示之半導體結構，在各個階段形成本揭露之一些實施例的SGT-MOSFET的剖面示意圖。 With the following detailed description in conjunction with the accompanying drawings, we can better understand the viewpoints of the embodiments of the present disclosure. Notably, according to standard industry practice, some features may not be drawn to scale. In fact, the dimensions of various components may be increased or decreased for clarity of discussion. FIGS. 1-9 are schematic cross-sectional views illustrating the formation of semiconductor structures at various stages according to some embodiments of the present disclosure; and FIGS. 10 to 19 are schematic cross-sectional views illustrating the formation of SGT-MOSFETs according to some embodiments of the present disclosure at various stages based on the semiconductor structure shown in FIG. 9 , according to some embodiments of the present disclosure.

1：半導體結構 100：基板 200：第一介電層 210,220：子介電層 310,320：第一導電層 400：第二導電材料 410,420：第二導電層 T1：第一溝槽 T2：第二溝槽 1: Semiconductor structure 100: Substrate 200: first dielectric layer 210, 220: Sub-dielectric layer 310, 320: First Conductive Layer 400: Second Conductive Material 410, 420: Second Conductive Layer T1: First trench T2: Second trench

Claims (12)

一種半導體結構的形成方法，其包含：形成一凹槽在一基板上，該凹槽具有一側表面與一底表面；形成一第一介電層於該凹槽的該側表面與該底表面、以及該基板上，以使該第一介電層具有一溝槽；填充一第一導電材料於該溝槽中；回蝕該第一導電材料，以形成一第一導電層並暴露位於該凹槽的該側表面上的該第一介電層的一部分；蝕刻該第一介電層，使得位於該凹槽的該側表面上的該第一介電層的該部分具有沿著遠離該凹槽的該底表面的方向變小的寬度，且該第一介電層在該凹槽的頂部處具有逐漸變小的寬度；及填充一第二導電材料於該溝槽中，以形成在該第一導電層上的一第二導電層。 A method for forming a semiconductor structure, comprising: forming a groove on a substrate, the groove has a side surface and a bottom surface; forming a first dielectric layer on the side surface and the bottom surface of the groove , and on the substrate, so that the first dielectric layer has a groove; a first conductive material is filled in the groove; the first conductive material is etched back to form a first conductive layer and exposed in the groove a portion of the first dielectric layer on the side surface of the groove; etching the first dielectric layer so that the portion of the first dielectric layer on the side surface of the groove has a distance along the The direction of the bottom surface of the groove is reduced in width, and the first dielectric layer has a gradually reduced width at the top of the groove; and a second conductive material is filled in the groove to be formed in the groove a second conductive layer on the first conductive layer. 如請求項1之形成方法，其中蝕刻該第一介電層的步驟包含：蝕刻在該凹槽的該側表面上的該第一介電層的一部分、以及在該基板的頂表面上的該第一介電層。 The forming method of claim 1, wherein the step of etching the first dielectric layer comprises: etching a portion of the first dielectric layer on the side surface of the groove, and the etching on the top surface of the substrate first dielectric layer. 如請求項1之形成方法，其中蝕刻該第一介電層的步驟包含：使用該第一導電層作為蝕刻遮罩，並藉由濕式蝕刻製程蝕刻該第一介電層。 The forming method of claim 1, wherein the step of etching the first dielectric layer comprises: using the first conductive layer as an etching mask, and etching the first dielectric layer by a wet etching process. 如請求項1之形成方法，其中在填充該第二導電材 料於該溝槽之步驟中進一步包含：平坦化該第二導電材料，使該第二導電材料的頂表面與該第一介電層的頂表面共平面。 The forming method of claim 1, wherein the second conductive material is filled The step of preparing the trench further includes: planarizing the second conductive material so that the top surface of the second conductive material is coplanar with the top surface of the first dielectric layer. 如請求項1之形成方法，其進一步包含：移除該第二導電層的一部分，使得該第二導電層的頂表面平行或低於該基板的頂表面，並留下一導電結構；移除該第一介電層的一部分，使得該第一介電層的頂表面低於該導電結構的頂表面；形成一第二介電層於該第二導電層上；及形成一第三導電層於該第二介電層上。 The forming method of claim 1, further comprising: removing a part of the second conductive layer so that the top surface of the second conductive layer is parallel to or lower than the top surface of the substrate, and leaving a conductive structure; removing a portion of the first dielectric layer such that the top surface of the first dielectric layer is lower than the top surface of the conductive structure; forming a second dielectric layer on the second conductive layer; and forming a third conductive layer on the second dielectric layer. 如請求項5之形成方法，其中該導電結構包含該第一導電層與剩餘的該第二導電層。 The forming method of claim 5, wherein the conductive structure includes the first conductive layer and the remaining second conductive layer. 如請求項5之形成方法，其進一步包含：形成一層間介電層於該第三導電層上；形成一第一摻雜區於該基板；形成一第二摻雜區於該基板，且該第二摻雜區相較於該第一摻雜區更遠離該層間介電層；形成一接觸通孔，該接觸通孔暴露該第三導電層的一部分；填充一通孔材料於該接觸通孔中，以形成一接觸插塞；及形成一金屬層於該層間介電層上，以使該金屬層與該接觸插塞彼此接觸。 The forming method of claim 5, further comprising: forming an interlayer dielectric layer on the third conductive layer; forming a first doped region on the substrate; forming a second doped region on the substrate, and the The second doped region is farther away from the interlayer dielectric layer than the first doped region; a contact through hole is formed, and the contact through hole exposes a part of the third conductive layer; a through hole material is filled in the contact through hole in order to form a contact plug; and form a metal layer on the interlayer dielectric layer, so that the metal layer and the contact plug are in contact with each other. 一種半導體結構，其包含：一基板，具有一凹槽，該凹槽包含一第一凹槽及一第二凹槽；一第一介電層，設置於該第一凹槽的一側表面及一底表面 上、及該第二凹槽的一側表面及一底表面上，且具有對應於該第一凹槽的一第一溝槽、及對應於該第二凹槽的一第二溝槽；一遮蔽電極，設置於該第一溝槽中；一第二介電層，設置於該第一溝槽中且於該遮蔽電極上；一閘極電極，設置於該第一溝槽中且於該第二介電層上；及一源極電極，設置於該第二溝槽中；其中，位於該第二凹槽的該側表面上的該第一介電層的一部分具有沿著遠離該第二凹槽的該底表面的方向變小的寬度。 A semiconductor structure, comprising: a substrate having a groove, the groove comprising a first groove and a second groove; a first dielectric layer disposed on one side surface of the first groove; a bottom surface on one side surface and a bottom surface of the second groove, and has a first groove corresponding to the first groove, and a second groove corresponding to the second groove; a A shielding electrode is arranged in the first trench; a second dielectric layer is arranged in the first trench and on the shielding electrode; a gate electrode is arranged in the first trench and on the shielding electrode on the second dielectric layer; and a source electrode disposed in the second trench; wherein, a part of the first dielectric layer on the side surface of the second groove has a direction along a distance away from the first The direction of the bottom surface of the two grooves becomes smaller in width. 如請求項8之半導體結構，其中該源極電極的一部分的形狀對應於該第二凹槽的該側表面上的該第一介電層的該部分的形狀。 The semiconductor structure of claim 8, wherein a shape of a portion of the source electrode corresponds to a shape of the portion of the first dielectric layer on the side surface of the second groove. 如請求項8之半導體結構，其中該源極電極的頂表面的寬度大於底表面的寬度。 The semiconductor structure of claim 8, wherein the width of the top surface of the source electrode is greater than the width of the bottom surface. 如請求項8之半導體結構，其中該閘極電極具有朝向該遮蔽電極延伸的延伸部。 The semiconductor structure of claim 8, wherein the gate electrode has an extension extending toward the shielding electrode. 如請求項8之半導體結構，其進一步包含：一層間介電層，設置於該閘極電極及該源極電極上；一第一摻雜區，設置於該基板上；一第二摻雜區，設置於該基板上且相較於該第一摻雜區更遠離該層間介電層；一閘極插塞，貫穿該層間介電層，且與該閘極電極接觸；及一源極插塞，貫穿該層間介電層，且與該源極電極接觸。 The semiconductor structure of claim 8, further comprising: an interlayer dielectric layer disposed on the gate electrode and the source electrode; a first doping region disposed on the substrate; a second doping region , disposed on the substrate and farther from the interlayer dielectric layer than the first doped region; a gate plug, penetrating the interlayer dielectric layer and in contact with the gate electrode; and a source plug The plug penetrates through the interlayer dielectric layer and is in contact with the source electrode.
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US20070059887A1 (en) * 2005-08-30 2007-03-15 Infineon Technologies Ag Method for producing a trench transistor and trench transistor
CN102299109A (en) * 2010-06-24 2011-12-28 大中积体电路股份有限公司 Semiconductor power component and manufacturing method thereof
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