TWI787089B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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TWI787089B
TWI787089B TW111106112A TW111106112A TWI787089B TW I787089 B TWI787089 B TW I787089B TW 111106112 A TW111106112 A TW 111106112A TW 111106112 A TW111106112 A TW 111106112A TW I787089 B TWI787089 B TW I787089B
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electrode
substrate
conductive
dielectric layer
layer
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TW202335186A (en
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丁榕泉
胡誌廷
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旺宏電子股份有限公司
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Abstract

A semiconductor device includes a substrate, a driving circuit layer, a memory device and a staircase structure. The memory device includes conductive layers and insulating layers alternating stacked over the conductive layers, bit lines over the conductive layers and the insulating layers, and channel layers through the conductive layers and the insulating layers. The staircase structure is disposed on the substrate and electrically connected to the memory device and the driving circuit layer. The driving circuit layer includes a capacitor structure. The capacitor structure includes a doped portion in the substrate, a first electrode, a first dielectric layer, a second electrode, and a second dielectric layer. The first electrode is disposed on the doped portion, and the bottom portion of the first electrode is within the doped portion. The first dielectric layer is disposed between the first electrode and the doped portion. The second electrode is disposed on the first electrode and a bottom surface of the bottom portion of the second electrode is below a top surface of the substrate. The second dielectric layer is disposed between the first electrode and the second electrode.

Description

半導體元件 semiconductor element

本揭露內容是有關於一種半導體元件。The present disclosure relates to a semiconductor device.

近年來，半導體元件的結構不斷改變，且半導體元件的儲存容量不斷增加。半導體元件被應用於許多產品(例如MP3播放器、數位相機及電腦檔案等)的儲存元件中。隨著這些應用的增加，半導體元件需要較大的電容以穩定電壓。為了滿足此條件，需要具有高電容值的半導體元件及其製造方法。In recent years, the structure of semiconductor elements has been constantly changing, and the storage capacity of semiconductor elements has been increasing. Semiconductor components are used in storage components of many products such as MP3 players, digital cameras, and computer files. As these applications increase, semiconductor elements require larger capacitances to stabilize voltages. In order to satisfy this condition, a semiconductor element having a high capacitance value and a method of manufacturing the same are required.

本揭露之一技術態樣為一種半導體元件。One technical aspect of the present disclosure is a semiconductor device.

根據本揭露一些實施方式，一種半導體元件包括基板、驅動電路層、記憶體元件以及階梯結構。記憶體元件位於基板上。記憶體元件包括交替堆疊的複數個導電層及複數個絕緣層、位於導電層及絕緣層上的複數個位元線以及穿過導電層及絕緣層的複數個通道層，且通道層的每一者分別電性連接至位元線。階梯結構位於基板上，且階梯結構電性連接記憶體元件與驅動電路層。驅動電路層包括電容結構，電容結構包括基板內的摻雜部分、第一電極、第一介電層、第二電極以及第二介電層。第一電極位於基板的摻雜部分上，第一電極具有底部分與頂部分，其中第一電極的底部分位於基板的摻雜部分內。第一介電層位於第一電極與基板的摻雜部分之間。第二電極位於第一電極上，其中第二電極具有底部分與頂部分，第二電極的底部分嵌設於第一電極，且第二電極的底部分的底面在基板的頂面下方。第二介電層位於第一電極與第二電極之間。According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a driving circuit layer, a memory device, and a ladder structure. The memory element is located on the substrate. The memory element includes a plurality of conductive layers and a plurality of insulating layers stacked alternately, a plurality of bit lines on the conductive layer and the insulating layer, and a plurality of channel layers passing through the conductive layer and the insulating layer, and each of the channel layers are respectively electrically connected to the bit lines. The ladder structure is located on the substrate, and the ladder structure is electrically connected to the memory element and the driving circuit layer. The driving circuit layer includes a capacitive structure, and the capacitive structure includes a doped part in the substrate, a first electrode, a first dielectric layer, a second electrode and a second dielectric layer. The first electrode is located on the doped portion of the substrate. The first electrode has a bottom portion and a top portion, wherein the bottom portion of the first electrode is located in the doped portion of the substrate. The first dielectric layer is between the first electrode and the doped portion of the substrate. The second electrode is located on the first electrode, wherein the second electrode has a bottom portion and a top portion, the bottom portion of the second electrode is embedded in the first electrode, and the bottom surface of the bottom portion of the second electrode is below the top surface of the substrate. The second dielectric layer is located between the first electrode and the second electrode.

在本揭露一些實施方式中，第一電極比第二電極寬。In some embodiments of the present disclosure, the first electrode is wider than the second electrode.

在本揭露一些實施方式中，第一電極的最高頂面的一部分被第二電極覆蓋，且第一電極的最高頂面的其餘部分未被第二電極覆蓋。In some embodiments of the present disclosure, a part of the highest top surface of the first electrode is covered by the second electrode, and the rest of the highest top surface of the first electrode is not covered by the second electrode.

在本揭露一些實施方式中，第二電極的厚度大於第一電極的厚度。In some embodiments of the present disclosure, the thickness of the second electrode is greater than that of the first electrode.

在本揭露一些實施方式中，電容結構更包括第一摻雜區域與第二摻雜區域，位於基板內，且基板的摻雜部分更具有位於第一摻雜區域與第一電極之間的一部分。In some embodiments of the present disclosure, the capacitor structure further includes a first doped region and a second doped region located in the substrate, and the doped portion of the substrate further has a portion located between the first doped region and the first electrode .

在本揭露一些實施方式中，第一介電層接觸基板的摻雜部分、第一摻雜區域、第二摻雜區域及第一電極，以及第二介電層接觸第一電極及第二電極。In some embodiments of the present disclosure, the first dielectric layer contacts the doped portion of the substrate, the first doped region, the second doped region and the first electrode, and the second dielectric layer contacts the first electrode and the second electrode .

在本揭露一些實施方式中，電容結構更包括間隔件。間隔件位於第二電極的頂部分的側壁上且與第二電極的底部分分隔。In some embodiments of the present disclosure, the capacitor structure further includes a spacer. A spacer is located on a sidewall of the top portion of the second electrode and is separated from the bottom portion of the second electrode.

本揭露之另一技術態樣為一種半導體元件。Another technical aspect of the present disclosure is a semiconductor device.

根據本揭露一些實施方式，一種半導體元件包括基板、驅動電路層、記憶體元件以及階梯結構。記憶體元件位於基板上。記憶體元件包括複數個導電層以及穿過導電層的複數個通道層。階梯結構位於基板上，階梯結構包括第一導電接觸、第二導電接觸與互連結構，第一導電接觸連接互連結構與驅動電路層，第二導電接觸連接互連結構與記憶體元件的導電層的其中一者。驅動電路層包括電容結構，電容結構包括基板內的摻雜部分、第一電極以及第二電極。第一電極位於基板的摻雜部分上，其中第一電極的最低底面在基板的摻雜部分的最高頂面下方。第二電極位於第一電極上，第一電極圍繞第二電極，第二電極的最低底面在第一電極的最高頂面的下方，且第一電極的最高頂面與第二電極的最高頂面不重疊。According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a driving circuit layer, a memory device, and a ladder structure. The memory element is located on the substrate. The memory device includes a plurality of conductive layers and a plurality of channel layers passing through the conductive layers. The ladder structure is located on the substrate, the ladder structure includes a first conductive contact, a second conductive contact and an interconnection structure, the first conductive contact is connected to the interconnection structure and the driving circuit layer, and the second conductive contact is connected to the conductive structure of the interconnection structure and the memory element one of the layers. The driving circuit layer includes a capacitive structure, and the capacitive structure includes a doped part in the substrate, a first electrode and a second electrode. The first electrode is located on the doped portion of the substrate, wherein the lowest bottom surface of the first electrode is below the highest top surface of the doped portion of the substrate. The second electrode is located on the first electrode, the first electrode surrounds the second electrode, the lowest bottom surface of the second electrode is below the highest top surface of the first electrode, and the highest top surface of the first electrode is the highest top surface of the second electrode. Do not overlap.

在本揭露一些實施方式中，電容結構更包括第一介電層與第二介電層。第一介電層位於基板的摻雜部分與第一電極之間。第二介電層位於第一電極與第二電極之間。In some embodiments of the present disclosure, the capacitor structure further includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located between the doped portion of the substrate and the first electrode. The second dielectric layer is located between the first electrode and the second electrode.

在本揭露一些實施方式中，電容結構更包括第三介電層。第三介電層位於第二電極上，且與第一介電層分隔。In some embodiments of the present disclosure, the capacitor structure further includes a third dielectric layer. The third dielectric layer is located on the second electrode and separated from the first dielectric layer.

根據本揭露上述實施方式，由於基板的摻雜部分為可視為下電極且第一電極可視為上電極，而第一電極可視為另一個下電極且第二電極可視為另一個上電極。經由上述的配置，可增加電容結構的電容值。此外，也可以減少電容結構在半導體元件所占用的空間。According to the above embodiments of the present disclosure, since the doped portion of the substrate can be regarded as a lower electrode and the first electrode can be regarded as an upper electrode, and the first electrode can be regarded as another lower electrode and the second electrode can be regarded as another upper electrode. Through the above configuration, the capacitance value of the capacitor structure can be increased. In addition, the space occupied by the capacitor structure in the semiconductor element can also be reduced.

以下將以圖式揭露本揭露之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本揭露。也就是說，在本揭露部分實施方式中，這些實務上的細節是非必要的，因此不應用以限制本揭露。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。另外，為了便於讀者觀看，圖式中各元件的尺寸並非依實際比例繪示。The following will disclose multiple implementations of the present disclosure with diagrams, and for the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. That is to say, in some embodiments of the present disclosure, these practical details are unnecessary, and thus should not be used to limit the present disclosure. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings. In addition, for the convenience of readers, the size of each element in the drawings is not drawn according to actual scale.

本文所用「約」、「近似」或「實質上」應通常是指給定值或範圍的百分之二十以內，優選地為百分之十以內，且更優選地為百分之五以內。在此給出的數值是近似的，意味著若沒有明確說明，則術語「約」、「近似」或「實質上」的涵意可被推斷出來。"About," "approximately," or "substantially" as used herein shall generally mean within twenty percent, preferably within ten percent, and more preferably within five percent of a given value or range . Numerical values given herein are approximate, meaning that the meaning of the terms "about", "approximately" or "substantially" can be inferred if not expressly stated.

第1A圖繪示根據本揭露一些實施方式之半導體元件100的立體圖，以及第1B圖繪示第1A圖的上視圖。半導體元件100包含基板102、驅動電路層104、記憶體元件110與階梯結構120。驅動電路層104位於基板102上方。記憶體元件110位於基板102上。階梯結構120位於基板102上，且階梯結構120電性連接記憶體元件110與驅動電路層104。FIG. 1A shows a perspective view of a semiconductor device 100 according to some embodiments of the present disclosure, and FIG. 1B shows a top view of FIG. 1A . The semiconductor device 100 includes a substrate 102 , a driving circuit layer 104 , a memory device 110 and a ladder structure 120 . The driving circuit layer 104 is located above the substrate 102 . The memory element 110 is located on the substrate 102 . The ladder structure 120 is located on the substrate 102 , and the ladder structure 120 is electrically connected to the memory device 110 and the driving circuit layer 104 .

基板102可以是半導體基板，例如體半導體、絕緣體上半導體(SOI)基板，或其類似物，半導體基板可以被摻雜（例如，具有p型或n型摻雜）或未摻雜。基板102的半導體材料可以包含矽、鍺、化合物半導體、合金半導體，或其組合。前述的化合物半導體包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦。前述的合金半導體包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP。The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (eg, with p-type or n-type doping) or undoped. The semiconductor material of the substrate 102 may include silicon, germanium, compound semiconductors, alloy semiconductors, or combinations thereof. The aforementioned compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide. The aforementioned alloy semiconductors include SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP.

驅動電路層104至少用以對記憶體元件110的導電層111(即字元線)提供電訊號。驅動電路層104可以是陣列下電路(circuit under array；CuA)層。在一些實施方式中，驅動電路層104包含複數個主動元件(例如電晶體)、被動元件(例如電容結構)，或其他電子元件。The driving circuit layer 104 is at least used for providing electrical signals to the conductive layer 111 of the memory device 110 (ie, the word line). The driving circuit layer 104 may be a circuit under array (CuA) layer. In some embodiments, the driving circuit layer 104 includes a plurality of active components (such as transistors), passive components (such as capacitor structures), or other electronic components.

記憶體元件110包含導電層111、通道層112、絕緣層113及位元線116。導電層111及絕緣層113在方向X與方向Y的平面交錯堆疊於記憶體元件110中。導電層111可被視為閘極層或字元線層。在一些實施方式中，導電層111包含金屬(例如鎢)或其他適當的導電材料，且絕緣層113可包含氧化物，如氧化矽或其他適當的介電材料。記憶體元件110可包含位於驅動電路層104與最底層絕緣層113之間的共用源極(如第3圖的共用源極260)。通道層112的每一者包含一串記憶體單元並通過對應的導電通孔115分別電性連接至位元線116。通道層112穿過導電層111與絕緣層113的堆疊電性連接至共用源極與位元線116。在一些實施方式中，通道層112包含複數個層，例如穿隧層、電子補獲層與阻擋層。穿隧層可包含氧化矽，或氧化物、氮化物與氧化物的組合物(例如ONO)。電子補獲層可包含氮化矽(SiN)或其他能夠補獲電子的材料。阻擋層可包含氧化矽、氧化鋁和/或其組合。接觸通道層112的外表面的導電層111的部分可視為記憶體元件110的閘極。相交於導電層111的每個通道層112中的填充材料(例如，穿隧層、電子補獲層、阻擋層及多晶矽)可以形成沿垂直方向(例如方向Z)的記憶體單元的串。The memory device 110 includes a conductive layer 111 , a channel layer 112 , an insulating layer 113 and a bit line 116 . The conductive layer 111 and the insulating layer 113 are alternately stacked in the memory device 110 in the planes of the direction X and the direction Y. The conductive layer 111 can be regarded as a gate layer or a word line layer. In some embodiments, the conductive layer 111 includes metal (such as tungsten) or other suitable conductive materials, and the insulating layer 113 may include oxides, such as silicon oxide or other suitable dielectric materials. The memory device 110 may include a common source (such as the common source 260 in FIG. 3 ) located between the driving circuit layer 104 and the bottommost insulating layer 113 . Each of the channel layers 112 includes a string of memory cells and is electrically connected to the bit lines 116 through corresponding conductive vias 115 . The channel layer 112 is electrically connected to the common source and the bit line 116 through the stack of the conductive layer 111 and the insulating layer 113 . In some embodiments, the channel layer 112 includes multiple layers, such as a tunneling layer, an electron harvesting layer, and a blocking layer. The tunneling layer may comprise silicon oxide, or a combination of oxide, nitride, and oxide (eg, ONO). The electron harvesting layer may include silicon nitride (SiN) or other materials capable of harvesting electrons. The barrier layer can include silicon oxide, aluminum oxide, and/or combinations thereof. The portion of the conductive layer 111 contacting the outer surface of the channel layer 112 can be regarded as the gate of the memory device 110 . The filling material (eg, tunneling layer, electron harvesting layer, barrier layer, and polysilicon) in each channel layer 112 intersecting the conductive layer 111 can form a string of memory cells along a vertical direction (eg, direction Z).

在一些實施方式中，串選擇線(String Select Line, SSL)114可形成於導電層111與位元線116之間，串選擇線114控制通道層112與對應的位元線116之間的電性連接。在一些其他的實施方式中，導電層111中的最頂層作為串選擇線，且導電層111的其餘部分作為字元線。在一些實施方式中，如第1B圖所示，導電層111更包含導電狹縫(conductive silt)130。導電狹縫130是先在導電層111中形成溝槽，並在溝槽的側壁與底部形成介電層(例如氧化物層)。接著，移除位於溝槽底部的介電層，且填入導電材料於溝槽中，以與下方的共用源極電性連接，因此，共用源極可藉由導電狹縫130向外接至一源極訊號源。導電狹縫130可包含與導電層111相同的材料(例如鎢)。In some embodiments, a string select line (String Select Line, SSL) 114 can be formed between the conductive layer 111 and the bit line 116, and the string select line 114 controls the electrical connection between the channel layer 112 and the corresponding bit line 116. sexual connection. In some other embodiments, the topmost layer of the conductive layer 111 is used as a string selection line, and the rest of the conductive layer 111 is used as a word line. In some embodiments, as shown in FIG. 1B , the conductive layer 111 further includes a conductive slit 130 . For the conductive slit 130 , a trench is first formed in the conductive layer 111 , and a dielectric layer (such as an oxide layer) is formed on the sidewall and bottom of the trench. Next, the dielectric layer at the bottom of the trench is removed, and a conductive material is filled in the trench to be electrically connected to the underlying common source. Therefore, the common source can be externally connected to a via the conductive slit 130. Source signal source. The conductive slit 130 may comprise the same material as the conductive layer 111 (eg, tungsten).

階梯結構120包含導電接觸122、互連結構123及導電接觸124。半導體元件100的階梯結構120配置以將導電層111電性連接至驅動電路層104。半導體元件100的階梯結構120可作為記憶體元件110的延伸，使得導電層111的每一者可以在著陸區126分別連接到對應的導電接觸124。具體而言，導電接觸122連接互連結構123與驅動電路層104，且導電接觸124連接互連結構123與導電層111的著陸區126。導電接觸122可視為穿透陣列接觸，且導電接觸124可視為字元線接觸。導電接觸122與導電接觸124通過互連結構123彼此電性連接。在一些實施方式中，導電層111從記憶體元件110延伸至階梯結構120，且具有與導電接觸124電性連接的著陸墊。在一些實施方式中，半導體元件100包含絕緣結構128，其形成於記憶體元件110與階梯結構120上方，絕緣結構128覆蓋著陸區126且圍繞導電接觸122與導電接觸124的一部份。The ladder structure 120 includes a conductive contact 122 , an interconnection structure 123 and a conductive contact 124 . The ladder structure 120 of the semiconductor device 100 is configured to electrically connect the conductive layer 111 to the driving circuit layer 104 . The stepped structure 120 of the semiconductor device 100 can be used as an extension of the memory device 110 , so that each of the conductive layers 111 can be respectively connected to the corresponding conductive contacts 124 at the landing area 126 . Specifically, the conductive contact 122 connects the interconnection structure 123 and the driving circuit layer 104 , and the conductive contact 124 connects the interconnection structure 123 and the landing area 126 of the conductive layer 111 . Conductive contact 122 may be considered a through-array contact, and conductive contact 124 may be considered a word line contact. The conductive contact 122 and the conductive contact 124 are electrically connected to each other through the interconnection structure 123 . In some embodiments, the conductive layer 111 extends from the memory device 110 to the stepped structure 120 and has a landing pad electrically connected to the conductive contact 124 . In some embodiments, the semiconductor device 100 includes an insulating structure 128 formed above the memory device 110 and the stepped structure 120 , the insulating structure 128 covers the landing area 126 and surrounds a portion of the conductive contact 122 and the conductive contact 124 .

第2圖繪示根據本揭露一些實施方式之包含電容結構250的半導體元件200的示意圖。半導體元件200包含基板202、驅動電路層204、記憶體元件210與階梯結構220。驅動電路層204位於基板202上方，且驅動電路層204包含電容結構250。記憶體元件210位於基板202上方。階梯結構220位於基板202上方，且階梯結構220電性連接驅動電路層204與記憶體元件210。階梯結構220包含導電層221、導電接觸222、互連結構223及導電接觸224。導電層221從記憶體元件210延伸至階梯結構220中，且導電層221的每一者可以在著陸區226分別連接到對應的導電接觸224。導電接觸222連接互連結構223與驅動電路層204的電容結構250，且導電接觸224連接互連結構223與導電層221的著陸區226。在一些實施方式中，記憶體元件210對應於第1A圖與第1B圖的記憶體元件110。例如，記憶體元件210可包含第1A圖及第1B圖之記憶體元件110的導電層111、通道層112、絕緣層113、串選擇線114、導電通孔115及位元線116。階梯結構220電性連接記憶體元件210與電容結構250。詳細來說，電容結構250通過階梯結構220的導電接觸222、互連結構223、導電接觸224及導電層221電性連接至記憶體元件210。FIG. 2 is a schematic diagram of a semiconductor device 200 including a capacitor structure 250 according to some embodiments of the present disclosure. The semiconductor device 200 includes a substrate 202 , a driving circuit layer 204 , a memory device 210 and a ladder structure 220 . The driving circuit layer 204 is located above the substrate 202 , and the driving circuit layer 204 includes a capacitor structure 250 . The memory device 210 is located above the substrate 202 . The ladder structure 220 is located above the substrate 202 , and the ladder structure 220 is electrically connected to the driving circuit layer 204 and the memory device 210 . The ladder structure 220 includes a conductive layer 221 , a conductive contact 222 , an interconnection structure 223 and a conductive contact 224 . The conductive layers 221 extend from the memory device 210 into the stepped structure 220 , and each of the conductive layers 221 can be respectively connected to the corresponding conductive contacts 224 at the landing area 226 . The conductive contact 222 connects the interconnection structure 223 and the capacitive structure 250 of the driving circuit layer 204 , and the conductive contact 224 connects the interconnection structure 223 and the landing area 226 of the conductive layer 221 . In some embodiments, the memory device 210 corresponds to the memory device 110 of FIGS. 1A and 1B . For example, the memory device 210 may include the conductive layer 111 , the channel layer 112 , the insulating layer 113 , the string selection line 114 , the conductive via 115 and the bit line 116 of the memory device 110 in FIG. 1A and FIG. 1B . The ladder structure 220 is electrically connected to the memory element 210 and the capacitor structure 250 . In detail, the capacitor structure 250 is electrically connected to the memory device 210 through the conductive contact 222 of the ladder structure 220 , the interconnection structure 223 , the conductive contact 224 and the conductive layer 221 .

應理解到，第2圖的基板202、記憶體元件210及階梯結構220(包含導電接觸222、互連結構223、導電接觸224)的配置及材料類似於第1A圖與第1B圖的基板102、記憶體元件110及階梯結構120(包含導電接觸122、互連結構123、導電接觸124)的配置及材料，故在以下的說明將不再重複描述。It should be understood that the configuration and materials of the substrate 202, the memory element 210, and the stepped structure 220 (including the conductive contact 222, the interconnection structure 223, and the conductive contact 224) in FIG. 2 are similar to those of the substrate 102 in FIGS. 1A and 1B. , the configuration and materials of the memory element 110 and the ladder structure 120 (including the conductive contact 122 , the interconnection structure 123 , and the conductive contact 124 ), so the description will not be repeated in the following description.

第3圖繪示根據本揭露另一實施方式之包含電容結構250a的半導體元件200a的示意圖。如第3圖所示，半導體元件200a包含基板202、驅動電路層204、記憶體元件210與階梯結構220。驅動電路層204位於基板202上方，且驅動電路層204包含電容結構250a，其中電容結構250a的一部分位於基板202內，而電容結構250a的另一部分位於驅動電路層204內。記憶體元件210位於基板202上方。階梯結構220位於基板202上方，且階梯結構220電性連接驅動電路層204與記憶體元件210。階梯結構220包含導電層221、互連結構223、導電接觸224、導電接觸228、互連結構230及共用源極260從記憶體元件210中延伸。在一些實施方式中，基板202、導電層221、導電接觸224、互連結構223、記憶體元件210的配置與第2圖所示的實施方式相似，故在以下的說明將不再重複描述。FIG. 3 is a schematic diagram of a semiconductor device 200 a including a capacitor structure 250 a according to another embodiment of the disclosure. As shown in FIG. 3 , the semiconductor device 200 a includes a substrate 202 , a driving circuit layer 204 , a memory device 210 and a ladder structure 220 . The driving circuit layer 204 is located above the substrate 202 , and the driving circuit layer 204 includes a capacitive structure 250 a, wherein a part of the capacitive structure 250 a is located in the substrate 202 , and another part of the capacitive structure 250 a is located in the driving circuit layer 204 . The memory device 210 is located above the substrate 202 . The ladder structure 220 is located above the substrate 202 , and the ladder structure 220 is electrically connected to the driving circuit layer 204 and the memory device 210 . The ladder structure 220 includes a conductive layer 221 , an interconnect structure 223 , a conductive contact 224 , a conductive contact 228 , an interconnect structure 230 and a common source 260 extending from the memory device 210 . In some embodiments, the configurations of the substrate 202 , the conductive layer 221 , the conductive contacts 224 , the interconnection structure 223 , and the memory device 210 are similar to those of the embodiment shown in FIG. 2 , so the following description will not be repeated.

如第3圖所示，包含電容結構250a的驅動電路層204設置於記憶體元件210下方，且包含電容結構250a的驅動電路層204通過階梯結構220的導電接觸228及互連結構230電性連接至記憶體元件210(例如第1A圖記憶體元件110內的導電層111)。As shown in FIG. 3 , the driving circuit layer 204 including the capacitive structure 250 a is disposed under the memory element 210 , and the driving circuit layer 204 including the capacitive structure 250 a is electrically connected through the conductive contact 228 of the ladder structure 220 and the interconnection structure 230 to the memory device 210 (for example, the conductive layer 111 in the memory device 110 of FIG. 1A ).

第4圖繪示根據本揭露一些實施方式之半導體結構300的剖面圖，以及第5A圖繪示第4圖的半導體結構300的電容結構C1於第一區域322的上視圖，其中第4圖的電容結構C1繪示第5A圖沿線段4-4的剖面圖。第5B圖繪示沿第4圖的線段5B-5B的上視圖，以及第6圖繪示第4圖的半導體結構300的周邊元件C2於第二區域324的上視圖，其中第4圖的周邊元件C2繪示第6圖沿線段4’-4’的剖面圖。第4圖至第6圖的半導體結構300的電容結構C1可對應於第2圖的電容結構250或第3圖的電容結構250a。也就是說，第4圖至第6圖的半導體結構300的電容結構C1設置於半導體元件的基板302上，且電性連接第2圖及第3圖的記憶體元件210，其中基板302對應於第2圖及第3圖的基板202。半導體結構300的周邊元件C2可以與電容結構C1連接階梯結構220中不同的導電接觸。半導體結構300可設置於第2、3圖的驅動電路層204或第1A圖的驅動電路層104，且半導體結構300具有第一區域322與第二區域324，其中電容結構C1位於第一區域322且周邊元件C2位於第二區域324。電容結構C1包含基板302中的摻雜部分306、第一電極330、第一介電層360、第二電極340以及第二介電層370。第一電極330位於基板302的摻雜部分306上，且第一電極330具有底部分332與頂部分334，其中第一電極330的底部分332位於基板302內。第二電極340位於第一電極330上，其中第二電極340具有底部分342與頂部分344。第二電極340的底部分342嵌設於第一電極330，且第二電極340的底部分342的底面341在基板302的最高頂面303下方。第一介電層360位於第一電極330下方，且位於基板302的摻雜部分306與第一電極330之間。第二介電層370位於第一電極330與第二電極340之間。在本揭露之一些實施方式中，基板302的摻雜部分306、第一介電層360及第一電極330視為第一電容，且第一電極330、第二介電層370及第二電極340視為第二電容。亦即，基板302的摻雜部分306為第一電容的下電極且第一電極330為第一電容的上電極，而第一電極330為第二電容的下電極且第二電極340為第二電容的上電極。經由上述的配置，可增加電容結構C1的電容值。此外，也可以減少電容結構C1在半導體元件(例如第2圖的半導體元件200或第3圖的半導體元件200a)所占用的空間。FIG. 4 shows a cross-sectional view of a semiconductor structure 300 according to some embodiments of the present disclosure, and FIG. 5A shows a top view of the capacitor structure C1 of the semiconductor structure 300 in FIG. 4 in the first region 322, wherein FIG. 4 Capacitor structure C1 is a cross-sectional view along line 4-4 in FIG. 5A. FIG. 5B shows a top view along the line segment 5B-5B in FIG. 4, and FIG. 6 shows a top view of the peripheral element C2 of the semiconductor structure 300 in FIG. 4 in the second region 324, wherein the periphery of FIG. 4 Component C2 shows a cross-sectional view along line 4'-4' in FIG. 6 . The capacitive structure C1 of the semiconductor structure 300 in FIGS. 4 to 6 may correspond to the capacitive structure 250 in FIG. 2 or the capacitive structure 250 a in FIG. 3 . That is to say, the capacitive structure C1 of the semiconductor structure 300 in FIGS. 4 to 6 is disposed on the substrate 302 of the semiconductor element, and is electrically connected to the memory element 210 in FIGS. 2 and 3, wherein the substrate 302 corresponds to The substrate 202 of FIG. 2 and FIG. 3 . The peripheral element C2 of the semiconductor structure 300 may connect to different conductive contacts in the ladder structure 220 with the capacitor structure C1 . The semiconductor structure 300 can be disposed on the driving circuit layer 204 in FIGS. 2 and 3 or the driving circuit layer 104 in FIG. 1A, and the semiconductor structure 300 has a first region 322 and a second region 324, wherein the capacitor structure C1 is located in the first region 322 And the peripheral element C2 is located in the second area 324 . The capacitor structure C1 includes a doped portion 306 in the substrate 302 , a first electrode 330 , a first dielectric layer 360 , a second electrode 340 and a second dielectric layer 370 . The first electrode 330 is located on the doped portion 306 of the substrate 302 , and the first electrode 330 has a bottom portion 332 and a top portion 334 , wherein the bottom portion 332 of the first electrode 330 is located in the substrate 302 . The second electrode 340 is located on the first electrode 330 , wherein the second electrode 340 has a bottom portion 342 and a top portion 344 . The bottom portion 342 of the second electrode 340 is embedded in the first electrode 330 , and the bottom surface 341 of the bottom portion 342 of the second electrode 340 is below the highest top surface 303 of the substrate 302 . The first dielectric layer 360 is located under the first electrode 330 and between the doped portion 306 of the substrate 302 and the first electrode 330 . The second dielectric layer 370 is located between the first electrode 330 and the second electrode 340 . In some embodiments of the present disclosure, the doped portion 306 of the substrate 302, the first dielectric layer 360 and the first electrode 330 are regarded as a first capacitor, and the first electrode 330, the second dielectric layer 370 and the second electrode 340 is regarded as the second capacitor. That is, the doped portion 306 of the substrate 302 is the lower electrode of the first capacitor and the first electrode 330 is the upper electrode of the first capacitor, while the first electrode 330 is the lower electrode of the second capacitor and the second electrode 340 is the second electrode. The upper electrode of the capacitor. Through the above configuration, the capacitance value of the capacitance structure C1 can be increased. In addition, the space occupied by the capacitor structure C1 in the semiconductor device (such as the semiconductor device 200 in FIG. 2 or the semiconductor device 200 a in FIG. 3 ) can also be reduced.

電容結構C1的第一電極330的頂部分334從底部分332向外延伸。第一電極330的頂部分334凸出於第二電極340的頂部分344。具體而言，第二電極340的頂部分344在基板302上的垂直投影位於第一電極330的頂部分334在基板302上的垂直投影之內。此外，第二電極340的底部分342在基板302上的垂直投影也位於第一電極330的底部分332在基板302上的垂直投影之內。在一些實施方式中，第二電極340的最低底面341在第一電極330的最高頂面335下方。第二電極340的頂部分344具有位於第一電極330的最高頂面335正上方的底面343。第二電極340的頂部分344的最高頂面345部分地覆蓋第一電極330的頂部分334。也就是說，第一電極330的最高頂面335的一部分被第二電極340的頂部分344的底面343覆蓋，而第一電極330的最高頂面335的其餘部分未被第二電極340的頂部分344的底面343覆蓋。在一些實施方式中，第一電極330的底部分332與頂部分334具有不同的形狀。例如，第一電極330的底部分332具有U形輪廓，而第一電極330的頂部分334具有矩形的輪廓。The top portion 334 of the first electrode 330 of the capacitive structure C1 extends outward from the bottom portion 332 . The top portion 334 of the first electrode 330 protrudes from the top portion 344 of the second electrode 340 . Specifically, the vertical projection of the top portion 344 of the second electrode 340 on the substrate 302 is located within the vertical projection of the top portion 334 of the first electrode 330 on the substrate 302 . In addition, the vertical projection of the bottom portion 342 of the second electrode 340 on the substrate 302 is also located within the vertical projection of the bottom portion 332 of the first electrode 330 on the substrate 302 . In some embodiments, the lowest bottom surface 341 of the second electrode 340 is below the highest top surface 335 of the first electrode 330 . The top portion 344 of the second electrode 340 has a bottom surface 343 directly above the highest top surface 335 of the first electrode 330 . The highest top surface 345 of the top portion 344 of the second electrode 340 partially covers the top portion 334 of the first electrode 330 . That is, a portion of the highest top surface 335 of the first electrode 330 is covered by the bottom surface 343 of the top portion 344 of the second electrode 340, while the rest of the highest top surface 335 of the first electrode 330 is not covered by the top of the second electrode 340. The bottom surface 343 of the sub-section 344 is covered. In some embodiments, the bottom portion 332 and the top portion 334 of the first electrode 330 have different shapes. For example, the bottom portion 332 of the first electrode 330 has a U-shaped profile, while the top portion 334 of the first electrode 330 has a rectangular profile.

在一些實施方式中，第一電極330與第二電極340具有不同的剖面形狀。第二電極340的底部分342與頂部分344可以是矩形輪廓，但具有不同的厚度與寬度。在一些實施方式中，第一電極330的底部分332具有第一厚度T1，且第二電極340具有第二厚度T2，其中第二厚度T2大於第一厚度T1。舉例來說，第一電極330的底部分332的第一厚度T1在約700埃(Å)至約900埃的範圍間(例如800埃)，且第二電極340的第二厚度T2在約1100埃至約1300埃的範圍間(例如1200埃)。當第一電極330的底部分332的第一厚度T1與第二電極340的第二厚度T2在上述的範圍間時，第二電極340可具有填充在第一電極330內底部分342與在第一電極330上方的頂部分344，以確保第二電極340可位於第一電極330上方並在第二電極340的底部分342與頂部分344交界的位置形成階梯狀的側壁，從而增加電容結構C1的第二電容的電容值。此外，由於第一電極330與基板302的摻雜部分306交界的位置具有階梯狀的側壁，可增加電容結構C1的第一電容的電容值。In some embodiments, the first electrode 330 and the second electrode 340 have different cross-sectional shapes. The bottom portion 342 and the top portion 344 of the second electrode 340 may have a rectangular profile but have different thicknesses and widths. In some embodiments, the bottom portion 332 of the first electrode 330 has a first thickness T1, and the second electrode 340 has a second thickness T2, wherein the second thickness T2 is greater than the first thickness T1. For example, the first thickness T1 of the bottom portion 332 of the first electrode 330 is in the range of about 700 angstroms (Å) to about 900 angstroms (for example, 800 Å), and the second thickness T2 of the second electrode 340 is about 1100 Å. Angstroms to about 1300 Angstroms (eg, 1200 Angstroms). When the first thickness T1 of the bottom portion 332 of the first electrode 330 and the second thickness T2 of the second electrode 340 are between the above-mentioned ranges, the second electrode 340 may have the bottom portion 342 and the second thickness filled in the first electrode 330 The top portion 344 above the first electrode 330 to ensure that the second electrode 340 can be located above the first electrode 330 and form a stepped sidewall at the junction of the bottom portion 342 and the top portion 344 of the second electrode 340, thereby increasing the capacitance structure C1 The capacitance value of the second capacitor. In addition, since the junction of the first electrode 330 and the doped portion 306 of the substrate 302 has a stepped sidewall, the capacitance of the first capacitor of the capacitor structure C1 can be increased.

在一些實施方式中，如第4圖與第5B圖所示，電容結構C1的第一電極330比第二電極340寬。電容結構C1的第一電極330在上視圖中具有合併部分336，以使導電接觸(例如導電接觸400)可設置於第一電極330上。電容結構C1的合併部分336具有小於1600埃的寬度W1。In some embodiments, as shown in FIG. 4 and FIG. 5B , the first electrode 330 of the capacitive structure C1 is wider than the second electrode 340 . The first electrode 330 of the capacitive structure C1 has a merged portion 336 in a top view, so that a conductive contact (eg, the conductive contact 400 ) can be disposed on the first electrode 330 . The merged portion 336 of the capacitive structure C1 has a width W1 less than 1600 Angstroms.

在一些實施方式中，基板302具有摻雜區域304a及304b。且摻雜區域304a及304b具有相同的電性。在一些實施方式中，基板302的摻雜部分306與摻雜區域304a及304b具有不同導電類型的摻雜劑。舉例來說，摻雜部分306包含諸如P或As等的N型摻雜劑，而摻雜區域304a及304b是包含諸如硼或二氟化硼(BF 2)等的P型摻雜劑的P型重摻雜區域(P+)。或者，基板302的摻雜部分306包含P型摻雜劑，而摻雜區域304a及304b是N型重摻雜區域(N+)。在一些實施方式中，摻雜區域304a及304b的頂面305在第一電極330的最高頂面335的下方。在一些實施方式中，基板302的摻雜部分306更具有區塊A1及A2，區塊A1位於摻雜區域304a與第一電極330之間，以及區塊A2位於摻雜區域304b與第一電極330之間。基板302的摻雜部分306的最高頂面307在第一電極330的最低底面331的上方。 In some embodiments, the substrate 302 has doped regions 304a and 304b. And the doped regions 304a and 304b have the same electrical properties. In some embodiments, the doped portion 306 of the substrate 302 and the doped regions 304 a and 304 b have dopants of different conductivity types. For example, doped portion 306 includes an N-type dopant such as P or As, while doped regions 304a and 304b are P containing a P-type dopant such as boron or boron difluoride (BF 2 ). Type heavily doped region (P+). Alternatively, the doped portion 306 of the substrate 302 includes P-type dopants, while the doped regions 304a and 304b are heavily N-type doped regions (N+). In some embodiments, the top surfaces 305 of the doped regions 304 a and 304 b are below the highest top surface 335 of the first electrode 330 . In some embodiments, the doped portion 306 of the substrate 302 further has areas A1 and A2, the area A1 is located between the doped region 304a and the first electrode 330, and the area A2 is located between the doped area 304b and the first electrode. Between 330. The highest top surface 307 of the doped portion 306 of the substrate 302 is above the lowest bottom surface 331 of the first electrode 330 .

半導體結構300包含位於基板302內的隔離結構350。隔離結構350鄰接且接觸基板302的摻雜區域304a及304b。隔離結構350可以是淺溝槽隔離(STI)結構以定義並電性隔離各個主動區域，從而防止漏電流在相鄰主動區域之間流動。The semiconductor structure 300 includes an isolation structure 350 within a substrate 302 . The isolation structure 350 adjoins and contacts the doped regions 304 a and 304 b of the substrate 302 . The isolation structure 350 may be a shallow trench isolation (STI) structure to define and electrically isolate active regions, thereby preventing leakage current from flowing between adjacent active regions.

在一些實施方式中，第一介電層360接觸摻雜部分306、摻雜區域304a及304b、隔離結構350及第一電極330，以及第二介電層370接觸第一電極330及第二電極340。在一些實施方式中，隔離結構350具有位於摻雜區域304a及304b上方的側壁351，且第一介電層360覆蓋隔離結構350的側壁351的全體。In some embodiments, the first dielectric layer 360 contacts the doped portion 306, the doped regions 304a and 304b, the isolation structure 350 and the first electrode 330, and the second dielectric layer 370 contacts the first electrode 330 and the second electrode 340. In some embodiments, the isolation structure 350 has sidewalls 351 above the doped regions 304 a and 304 b , and the first dielectric layer 360 covers the entirety of the sidewalls 351 of the isolation structure 350 .

電容結構C1包含第一間隔件380及第二間隔件390。第一間隔件380位於第一電極330的頂部分334的側壁337上且與第一電極330的底部分332分隔，且第一間隔件380位於基板302的摻雜區域304a及304b的正上方。第一間隔件380接觸第一電極330、第一介電層360及第二介電層370。第二間隔件390位於第二電極340的頂部分344的側壁347上且與第二電極340的底部分342分隔。第二間隔件390接觸第二電極340與第二介電層370，且第二間隔件390與第一電極330被第二介電層370分隔。The capacitor structure C1 includes a first spacer 380 and a second spacer 390 . The first spacer 380 is located on the sidewall 337 of the top portion 334 of the first electrode 330 and separated from the bottom portion 332 of the first electrode 330 , and the first spacer 380 is located directly above the doped regions 304 a and 304 b of the substrate 302 . The first spacer 380 contacts the first electrode 330 , the first dielectric layer 360 and the second dielectric layer 370 . The second spacer 390 is located on the sidewall 347 of the top portion 344 of the second electrode 340 and separated from the bottom portion 342 of the second electrode 340 . The second spacer 390 contacts the second electrode 340 and the second dielectric layer 370 , and the second spacer 390 and the first electrode 330 are separated by the second dielectric layer 370 .

半導體結構300的電容結構C1包含電性連接第一電極330的導電接觸400與電性連接第二電極340的導電接觸410。在一些實施方式中，導電接觸400與導電接觸410施加不同的電壓。例如，電性連接第一電極330的導電接觸400連接電源訊號(VDD)，而電性連接第二電極340的導電接觸410接地(ground)。此外，電容結構C1包含電性連接基板302的摻雜區域304a及304b的導電接觸420。導電接觸420與電性連接第二電極340的導電接觸410具有相同的電位。換句話說，電性連接摻雜區域304a及304b的導電接觸420與電性連接電容結構C1的第一電極330的導電接觸400具有不同的電位，使得鄰接摻雜區域304a及304b的摻雜部分306與第一電極330之間產生電位差，以形成第一電容。同樣地，由於導電接觸400及410具有不同的電位，使得第一電極330與第二電極340之間產生電位差，以形成第二電容。The capacitor structure C1 of the semiconductor structure 300 includes a conductive contact 400 electrically connected to the first electrode 330 and a conductive contact 410 electrically connected to the second electrode 340 . In some embodiments, different voltages are applied to conductive contact 400 than to conductive contact 410 . For example, the conductive contact 400 electrically connected to the first electrode 330 is connected to the power signal (VDD), and the conductive contact 410 electrically connected to the second electrode 340 is grounded. In addition, the capacitive structure C1 includes a conductive contact 420 electrically connected to the doped regions 304 a and 304 b of the substrate 302 . The conductive contact 420 has the same potential as the conductive contact 410 electrically connected to the second electrode 340 . In other words, the conductive contact 420 electrically connected to the doped regions 304a and 304b and the conductive contact 400 electrically connected to the first electrode 330 of the capacitive structure C1 have different potentials, so that the doped portions adjacent to the doped regions 304a and 304b A potential difference is generated between 306 and the first electrode 330 to form a first capacitor. Likewise, since the conductive contacts 400 and 410 have different potentials, a potential difference is generated between the first electrode 330 and the second electrode 340 to form a second capacitor.

在一些實施方式中，半導體結構300包含層間介電(ILD)層375。層間介電層375圍繞導電接觸400、410及420且覆蓋隔離結構350、第一介電層360、第二介電層370及第二電極340。In some embodiments, the semiconductor structure 300 includes an interlayer dielectric (ILD) layer 375 . The interlayer dielectric layer 375 surrounds the conductive contacts 400 , 410 and 420 and covers the isolation structure 350 , the first dielectric layer 360 , the second dielectric layer 370 and the second electrode 340 .

半導體結構300的周邊元件C2包含基板302的摻雜部分306a、位於基板302上的介電層360a、第一導電結構330a及位於第一導電結構330a上方的第二導電結構340a。此外，周邊元件C2更包含位於基板302內的摻雜區域304c及304d，且摻雜部分306a位於摻雜區域304c及304d之間。在一些實施方式中，周邊元件C2視為另一個電容結構，周邊元件C2的導電結構(第一導電結構330a及第二導電結構340a)視為上電極，而基板302的摻雜部分306a視為下電極。在一些其他的實施方式中，周邊元件C2視為電晶體，周邊元件C2的導電結構(第一導電結構330a及第二導電結構340a)視為閘極、摻雜區域304c及304d視為源極/汲極，且基板302的摻雜部分306a視為通道。The peripheral element C2 of the semiconductor structure 300 includes a doped portion 306 a of the substrate 302 , a dielectric layer 360 a on the substrate 302 , a first conductive structure 330 a and a second conductive structure 340 a above the first conductive structure 330 a. In addition, the peripheral device C2 further includes doped regions 304c and 304d located in the substrate 302, and the doped portion 306a is located between the doped regions 304c and 304d. In some embodiments, the peripheral element C2 is regarded as another capacitive structure, the conductive structure of the peripheral element C2 (the first conductive structure 330a and the second conductive structure 340a ) is regarded as the upper electrode, and the doped portion 306a of the substrate 302 is regarded as lower electrode. In some other implementations, the peripheral element C2 is regarded as a transistor, the conductive structure of the peripheral element C2 (the first conductive structure 330a and the second conductive structure 340a ) is regarded as the gate, and the doped regions 304c and 304d are regarded as the source /drain, and the doped portion 306a of the substrate 302 is regarded as a channel.

第二導電結構340a覆蓋第一導電結構330a。具體而言，第二導電結構340a在基板302上的垂直投影與第一導電結構330a在基板302上的垂直投影重疊。第二導電結構340a在垂直方向上與第一導電結構330a對齊。具體而言，第二導電結構340a的側壁349與第一導電結構330a的側壁339大致齊平。在一些實施方式中，第一導電結構330a與第二導電結構340a具有相同的形狀。例如，第一導電結構330a及第二導電結構340a皆具有矩形輪廓。在一些實施方式中，周邊元件C2的第二導電結構340a的最高頂面348與電容結構C1的第二電極340的最高頂面345大致齊平。 The second conductive structure 340a covers the first conductive structure 330a. Specifically, the vertical projection of the second conductive structure 340 a on the substrate 302 overlaps with the vertical projection of the first conductive structure 330 a on the substrate 302 . The second conductive structure 340a is aligned with the first conductive structure 330a in the vertical direction. Specifically, the sidewall 349 of the second conductive structure 340a is substantially flush with the sidewall 339 of the first conductive structure 330a. In some embodiments, the first conductive structure 330a and the second conductive structure 340a have the same shape. For example, both the first conductive structure 330a and the second conductive structure 340a have a rectangular outline. In some embodiments, the highest top surface 348 of the second conductive structure 340 a of the peripheral element C2 is substantially flush with the highest top surface 345 of the second electrode 340 of the capacitor structure C1 .

在一些實施方式中，周邊元件C2的介電層360a位於第一導電結構330a下方，且介電層360a接觸基板302、摻雜區域304c及304d、隔離結構350及第一導電結構330a。而周邊元件C2的介電層360a僅部分地覆蓋隔離結構350的側壁351。亦即，至少有部分的隔離結構350的側壁351未被介電層360a覆蓋。在一些實施方式中，周邊元件C2包含間隔件390a，且間隔件390a形成於第一導電結構330a的側壁339及第二導電結構340a的側壁349上。間隔件390a接觸介電層360a、第一導電結構330a及第二導電結構340a。 In some embodiments, the dielectric layer 360a of the peripheral device C2 is located under the first conductive structure 330a, and the dielectric layer 360a contacts the substrate 302, the doped regions 304c and 304d, the isolation structure 350, and the first conductive structure 330a. The dielectric layer 360 a of the peripheral element C2 only partially covers the sidewall 351 of the isolation structure 350 . That is, at least part of the sidewall 351 of the isolation structure 350 is not covered by the dielectric layer 360a. In some embodiments, the peripheral element C2 includes a spacer 390a, and the spacer 390a is formed on the sidewall 339 of the first conductive structure 330a and the sidewall 349 of the second conductive structure 340a. The spacer 390a contacts the dielectric layer 360a, the first conductive structure 330a and the second conductive structure 340a.

在一些實施方式中，周邊元件C2包含導電接觸400a及420b。導電接觸400a電性連接第二導電結構340a、導電接觸420a電性連接基板302的摻雜區域304c，以及導電接觸420b電性連接基板302的摻雜區域304d。在周邊元件C2為電容結構的實施方式中，電性連接摻雜區域304c的導電接觸420a與電性連接摻雜區域304d的導電接觸420b具有相同的電位。在周邊元件C2為電晶體的實施方式中，電性連接摻雜區域304c的導電接觸420a與電性連接摻雜區域304d的導電接觸420b具有不同的電位。在第二區域324中，層間介電層375圍繞導電接觸400a、420a及420b且覆蓋隔離結構350、介電層360a及第二導電結構340a。In some embodiments, peripheral element C2 includes conductive contacts 400a and 420b. The conductive contact 400 a is electrically connected to the second conductive structure 340 a , the conductive contact 420 a is electrically connected to the doped region 304 c of the substrate 302 , and the conductive contact 420 b is electrically connected to the doped region 304 d of the substrate 302 . In an embodiment where the peripheral element C2 is a capacitor structure, the conductive contact 420a electrically connected to the doped region 304c has the same potential as the conductive contact 420b electrically connected to the doped region 304d. In an embodiment where the peripheral element C2 is a transistor, the conductive contact 420a electrically connected to the doped region 304c and the conductive contact 420b electrically connected to the doped region 304d have different potentials. In the second region 324 , the interlayer dielectric layer 375 surrounds the conductive contacts 400 a , 420 a and 420 b and covers the isolation structure 350 , the dielectric layer 360 a and the second conductive structure 340 a.

第7A圖至第7O圖繪示根據本揭露一些實施方式之半導體結構300的製造方法在各步驟的剖面圖。FIG. 7A to FIG. 70 are cross-sectional views of various steps in the method of fabricating the semiconductor structure 300 according to some embodiments of the present disclosure.

參閱第7A圖，在基板302上方依序形成介電層360a、導電層330a’及遮罩層430。接著，蝕刻遮罩層430、導電層330a’、介電層360a及基板302，以形成第一凹陷R1。在一些實施方式中，如第7A圖所示，第一凹陷R1暴露第一區域322的基板302的中央部分及邊緣部分，而第一凹陷R1暴露第二區域324的基板302的邊緣部分。基板302具有位於第一區域322的摻雜部分306及位於第二區域324的摻雜部分306a。在一些實施方式中，介電層360a包含氧化物，如氧化矽或其他適當的介電材料。導電層330a’可包含半導體材料(例如多晶矽)、金屬或其他適當的導電材料。遮罩層430可包含氮化物，如氮化矽或其他適當的介電材料。在一些實施方式中，形成介電層360a、導電層330a’及/或遮罩層430透過化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、原子層沉積(ALD)、可流動式化學氣相沉積(FCVD)、低壓化學氣相沉積(LPCVD)或其他適當的沉積方法形成。在一些實施方式中，蝕刻遮罩層430、導電層330a’、介電層360a及基板302可以使用乾式或濕式蝕刻。Referring to FIG. 7A, a dielectric layer 360a, a conductive layer 330a' and a mask layer 430 are sequentially formed on the substrate 302. Referring to FIG. Next, the mask layer 430, the conductive layer 330a', the dielectric layer 360a and the substrate 302 are etched to form the first recess R1. In some embodiments, as shown in FIG. 7A , the first recess R1 exposes the central portion and the edge portion of the substrate 302 in the first region 322 , and the first recess R1 exposes the edge portion of the substrate 302 in the second region 324 . The substrate 302 has a doped portion 306 located in the first region 322 and a doped portion 306 a located in the second region 324 . In some embodiments, the dielectric layer 360a includes oxide, such as silicon oxide or other suitable dielectric materials. The conductive layer 330a' may include semiconductor material (such as polysilicon), metal or other suitable conductive materials. The mask layer 430 may include nitride, such as silicon nitride or other suitable dielectric materials. In some embodiments, the dielectric layer 360a, the conductive layer 330a' and/or the mask layer 430 are formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), Formed by flowable chemical vapor deposition (FCVD), low pressure chemical vapor deposition (LPCVD) or other suitable deposition methods. In some embodiments, etching the mask layer 430, the conductive layer 330a', the dielectric layer 360a, and the substrate 302 may use dry or wet etching.

參閱第7A圖與第7B圖，在第一凹陷R1中填入介電材料，以形成隔離結構350。在一些實施方式中，在形成隔離結構350之後，進行平坦化製程，如化學機械研磨製程(CMP)，以移除隔離結構350的一部分，使得隔離結構350的頂面與遮罩層430的頂面大致齊平。在一些實施方式中，隔離結構350包含氧化矽、氮化矽、氮氧化矽或其他適當的材料。形成隔離結構350可透過高密度電漿沉積(HDP)、化學氣相沉積(CVD)、原子層沉積(ALD)或其他適當的沉積方法形成。Referring to FIG. 7A and FIG. 7B , a dielectric material is filled in the first recess R1 to form an isolation structure 350 . In some embodiments, after the isolation structure 350 is formed, a planarization process, such as a chemical mechanical polishing process (CMP), is performed to remove a part of the isolation structure 350 so that the top surface of the isolation structure 350 is aligned with the top surface of the mask layer 430 The surface is roughly even. In some embodiments, the isolation structure 350 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. The isolation structure 350 can be formed by high density plasma deposition (HDP), chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition methods.

參閱第7B圖與第7C圖，在形成隔離結構350之後，移除遮罩層430，使得導電層330a’的頂面t1與隔離結構350的側壁被暴露。在一些實施方式中，蝕刻遮罩層430可以使用磷酸(H 3PO 4)或其他適當的蝕刻劑。 Referring to FIG. 7B and FIG. 7C, after the isolation structure 350 is formed, the mask layer 430 is removed, so that the top surface t1 of the conductive layer 330a' and the sidewall of the isolation structure 350 are exposed. In some embodiments, phosphoric acid (H 3 PO 4 ) or other suitable etchant may be used to etch the mask layer 430 .

參閱第7D圖，回蝕隔離結構350，使得隔離結構350的頂面353接近導電層330a’的頂面t1。在一些實施方式中，隔離結構350的頂面353在導電層330a’的頂面t1上方。在一些其他的實施方式中，隔離結構350的頂面353與導電層330a’的頂面t1大致齊平。蝕刻隔離結構350可以使用濕式蝕刻或其他適當的蝕刻方法。Referring to FIG. 7D, the isolation structure 350 is etched back so that the top surface 353 of the isolation structure 350 is close to the top surface t1 of the conductive layer 330a'. In some embodiments, the top surface 353 of the isolation structure 350 is above the top surface t1 of the conductive layer 330a'. In some other embodiments, the top surface 353 of the isolation structure 350 is substantially flush with the top surface t1 of the conductive layer 330a'. Etching the isolation structure 350 may use wet etching or other suitable etching methods.

參閱第7E圖，在第一區域322與第二區域324中形成圖案化的光阻層440。在第一區域322中，圖案化的光阻層440覆蓋隔離結構350的一部分並暴露導電層330a’；在第二區域324中，圖案化的光阻層440覆蓋隔離結構350與導電層330a’的全體。圖案化的光阻層440可以透過適當的沉積、顯影及/或蝕刻技術形成。接著，使用圖案化的光阻層440作為蝕刻遮罩，對未被圖案化的光阻層440覆蓋的隔離結構350與導電層330a’進行蝕刻，以在第一區域322形成第二凹陷R2暴露第一區域322的基板302與隔離結構350。詳細來說，第二凹陷R2暴露隔離結構350的表面355與垂直表面355且往上延伸的側壁351，其中隔離結構350的表面355與基板302的最高頂面303大致齊平。Referring to FIG. 7E , a patterned photoresist layer 440 is formed in the first region 322 and the second region 324 . In the first region 322, the patterned photoresist layer 440 covers a part of the isolation structure 350 and exposes the conductive layer 330a'; in the second region 324, the patterned photoresist layer 440 covers the isolation structure 350 and the conductive layer 330a' of the whole. The patterned photoresist layer 440 can be formed by suitable deposition, development and/or etching techniques. Next, using the patterned photoresist layer 440 as an etching mask, the isolation structure 350 and the conductive layer 330a' not covered by the patterned photoresist layer 440 are etched to form the second recess R2 in the first region 322 to expose The substrate 302 and the isolation structure 350 in the first region 322 . In detail, the second recess R2 exposes the surface 355 of the isolation structure 350 and the sidewall 351 perpendicular to the surface 355 and extending upward, wherein the surface 355 of the isolation structure 350 is substantially flush with the highest top surface 303 of the substrate 302 .

參閱第7E圖與第7F圖，在形成第二凹陷R2後，移除光阻層440。移除光阻層440可以透過使用光阻剝離製程，例如灰化(ashing)製程、蝕刻製程或其他適當的製程。接著，在第一區域322與第二區域324中共形地形成第一介電層360。在第一區域322中，第一介電層360覆蓋隔離結構350與基板302；在第二區域324中，第一介電層360覆蓋隔離結構350與導電層330a’。在一些實施方式中，第一介電層360具有厚度T3在約350埃至450埃的範圍間(例如400埃)。在一些實施方式中，第一介電層360包含氧化物，如氧化矽或其他適當的介電材料。第一介電層360可包含與介電層360a相同的材料。第一介電層360可透過化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、原子層沉積(ALD)、可流動式化學氣相沉積(FCVD)、低壓化學氣相沉積(LPCVD)或其他適當的沉積方法形成。Referring to FIG. 7E and FIG. 7F, after forming the second recess R2, the photoresist layer 440 is removed. The photoresist layer 440 can be removed by using a photoresist stripping process, such as an ashing process, an etching process, or other suitable processes. Next, a first dielectric layer 360 is formed conformally in the first region 322 and the second region 324 . In the first region 322, the first dielectric layer 360 covers the isolation structure 350 and the substrate 302; in the second region 324, the first dielectric layer 360 covers the isolation structure 350 and the conductive layer 330a'. In some embodiments, the first dielectric layer 360 has a thickness T3 in the range of about 350 angstroms to 450 angstroms (eg, 400 angstroms). In some embodiments, the first dielectric layer 360 includes oxide, such as silicon oxide or other suitable dielectric materials. The first dielectric layer 360 may include the same material as the dielectric layer 360a. The first dielectric layer 360 can be deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), flowable chemical vapor deposition (FCVD), low pressure chemical vapor deposition (LPCVD) or other suitable deposition methods.

參閱第7G圖，在第一介電層360上方形成第一導電層330’。在第一區域322中，第一導電層330’的最低底面331在隔離結構350的最高頂面357下方；在第二區域324中，第一導電層330’的全體位於隔離結構350上方。第一導電層330’的底部分332’的第一厚度T1(對應於第4圖的第一電極330的底部分332的第一厚度T1)在約700埃至約900埃的範圍間(例如800埃)。若第一導電層330’的底部分332’的第一厚度T1大於900埃時，製造電容結構的製程成本會過高；若第一導電層330’的底部分332’的第一厚度T1小於700埃時，後續形成電容(第4圖的電容結構C1)的阻值會過高，使電容無法達到預期的效果。第一導電層330’可包含半導體材料(例如多晶矽)、金屬或其他適當的導電材料。在一些實施方式中，第一導電層330’與導電層330a’包含相同的材料(例如多晶矽)。在一些實施方式中，形成第一導電層330’透過化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適當的沉積方法形成。Referring to FIG. 7G , a first conductive layer 330 ′ is formed over the first dielectric layer 360 . In the first region 322, the lowest bottom surface 331 of the first conductive layer 330′ is below the highest top surface 357 of the isolation structure 350; The first thickness T1 of the bottom portion 332' of the first conductive layer 330' (corresponding to the first thickness T1 of the bottom portion 332 of the first electrode 330 in FIG. 800 Angstroms). If the first thickness T1 of the bottom part 332' of the first conductive layer 330' is greater than 900 angstroms, the process cost of manufacturing the capacitor structure will be too high; if the first thickness T1 of the bottom part 332' of the first conductive layer 330' is less than When it is 700 angstroms, the resistance value of the subsequently formed capacitor (the capacitor structure C1 in FIG. 4 ) will be too high, so that the capacitor cannot achieve the desired effect. The first conductive layer 330' may include semiconductor material (such as polysilicon), metal or other suitable conductive materials. In some embodiments, the first conductive layer 330' and the conductive layer 330a' comprise the same material (such as polysilicon). In some embodiments, the first conductive layer 330' is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable deposition methods.

參閱第7H圖，在形成第一導電層330’之後，進行平坦化製程，以移除第一導電層330’與第一介電層360的部分，其中平坦化製程停止於第一介電層360。詳細來說，在第一區域322中，平坦化製程暴露隔離結構350、第一介電層360與第一導電層330’，使得隔離結構350的最高頂面、第一介電層360的最高頂面與第一導電層330’的最高頂面大致齊平；在第二區域324中，平坦化製程暴露隔離結構350及第一介電層360，使得隔離結構350的頂面與第一介電層360的頂面大致齊平且在第二區域324中無第一導電層330’。Referring to FIG. 7H, after forming the first conductive layer 330', a planarization process is performed to remove parts of the first conductive layer 330' and the first dielectric layer 360, wherein the planarization process stops at the first dielectric layer 360. In detail, in the first region 322 , the planarization process exposes the isolation structure 350 , the first dielectric layer 360 and the first conductive layer 330 ′, so that the highest top surface of the isolation structure 350 and the highest surface of the first dielectric layer 360 The top surface is substantially flush with the highest top surface of the first conductive layer 330'; in the second region 324, the planarization process exposes the isolation structure 350 and the first dielectric layer 360, so that the top surface of the isolation structure 350 is aligned with the first dielectric layer. The top surface of the electrical layer 360 is substantially flush and there is no first conductive layer 330 ′ in the second region 324 .

參閱第7I圖，在第一區域322與第二區域324中共形地形成第二介電層370。在第一區域322中，第二介電層370覆蓋隔離結構350、第一介電層360與第一導電層330’；在第二區域324中，第二介電層370覆蓋隔離結構350與第一介電層360。在一些實施方式中，第二介電層370具有厚度T4在約350埃至450埃的範圍間(例如400埃)。第二介電層370的厚度T4實質上等於第一介電層360的厚度T3。在一些實施方式中，第二介電層370包含氧化物，如氧化矽或其他適當的介電材料。第二介電層370可包含與第一介電層360及/或介電層360a相同的材料。第二介電層370可透過化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、原子層沉積(ALD)、可流動式化學氣相沉積(FCVD)、低壓化學氣相沉積(LPCVD)或其他適當的沉積方法形成。Referring to FIG. 7I , the second dielectric layer 370 is formed conformally in the first region 322 and the second region 324 . In the first region 322 , the second dielectric layer 370 covers the isolation structure 350 , the first dielectric layer 360 and the first conductive layer 330 ′; in the second region 324 , the second dielectric layer 370 covers the isolation structure 350 and the first conductive layer 330 ′. The first dielectric layer 360 . In some embodiments, the second dielectric layer 370 has a thickness T4 in the range of about 350 angstroms to 450 angstroms (eg, 400 angstroms). The thickness T4 of the second dielectric layer 370 is substantially equal to the thickness T3 of the first dielectric layer 360 . In some embodiments, the second dielectric layer 370 includes oxide, such as silicon oxide or other suitable dielectric materials. The second dielectric layer 370 may include the same material as the first dielectric layer 360 and/or the dielectric layer 360a. The second dielectric layer 370 can be deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), flowable chemical vapor deposition (FCVD), low pressure chemical vapor deposition (LPCVD) or other suitable deposition methods.

參閱第7I圖與第7J圖，在第一區域322中形成圖案化的光阻層450，其中圖案化的光阻層450覆蓋第二介電層370的一部分，且在第二區域324中無光阻層450。圖案化的光阻層450可以透過適當的沉積、顯影及/或蝕刻技術形成。接著，使用圖案化的光阻層450作為蝕刻遮罩，對未被圖案化的光阻層450覆蓋的第二介電層370進行蝕刻，以在第一區域322暴露隔離結構350、第一介電層360及第一導電層330’。此外，在第二區域324中，第一介電層360及第二介電層370被移除，以暴露隔離結構350及導電層330a’。Referring to FIG. 7I and FIG. 7J, a patterned photoresist layer 450 is formed in the first region 322, wherein the patterned photoresist layer 450 covers a part of the second dielectric layer 370, and there is no photoresist layer 450 . The patterned photoresist layer 450 can be formed by suitable deposition, development and/or etching techniques. Next, using the patterned photoresist layer 450 as an etching mask, etch the second dielectric layer 370 not covered by the patterned photoresist layer 450, so as to expose the isolation structure 350, the first dielectric layer in the first region 322, etc. The electrical layer 360 and the first conductive layer 330'. In addition, in the second region 324, the first dielectric layer 360 and the second dielectric layer 370 are removed to expose the isolation structure 350 and the conductive layer 330a'.

參閱第7J圖與第7K圖，移除第一區域322中的光阻層450，以暴露下面的第二介電層370。移除光阻層450可以透過使用光阻剝離製程，例如灰化製程、蝕刻製程或其他適當的製程。接著，在第一區域322與第二區域324中形成第二導電層340’。第二導電層340’的第二厚度T2(對應於第4圖的第二電極340的第二厚度T2)大於第一導電層330’的底部分332’的第一厚度T1，其中第二導電層340’的第二厚度T2在約1100埃至約1300埃的範圍間(例如1200埃)。若第二導電層340’的第二厚度T2大於1300埃時，製造電容結構的製程成本會過高；若第二導電層340’的第二厚度T2小於1100埃時，後續形成電容(第4圖的電容結構C1)的阻值會過高，且第二導電層340’可能無法填充第一導電層330’內的開口O1而使第二導電層340’的頂面無法容納導電接觸(例如第4圖的導電接觸410)，從而導致電容無法達到預期的效果。第二導電層340’可包含半導體材料(例如多晶矽)、金屬或其他適當的導電材料。第二導電層340’可包含與第一導電層330’相同的材料(例如多晶矽)。在一些實施方式中，形成第二導電層340’透過化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適當的沉積方法形成。Referring to FIGS. 7J and 7K, the photoresist layer 450 in the first region 322 is removed to expose the underlying second dielectric layer 370 . The photoresist layer 450 can be removed by using a photoresist stripping process, such as an ashing process, an etching process, or other suitable processes. Next, a second conductive layer 340' is formed in the first region 322 and the second region 324. Referring to FIG. The second thickness T2 of the second conductive layer 340' (corresponding to the second thickness T2 of the second electrode 340 in FIG. 4 ) is greater than the first thickness T1 of the bottom portion 332' of the first conductive layer 330', wherein the second conductive The second thickness T2 of the layer 340' is in the range of about 1100 angstroms to about 1300 angstroms (eg, 1200 angstroms). If the second thickness T2 of the second conductive layer 340' is greater than 1300 angstroms, the process cost of manufacturing the capacitor structure will be too high; The resistance value of the capacitive structure C1) in the figure will be too high, and the second conductive layer 340' may not be able to fill the opening O1 in the first conductive layer 330', so that the top surface of the second conductive layer 340' cannot accommodate conductive contacts (eg The conductive contact 410 in FIG. 4 ), so that the capacitance cannot achieve the expected effect. The second conductive layer 340' may include semiconductor material (such as polysilicon), metal or other suitable conductive materials. The second conductive layer 340' may include the same material as the first conductive layer 330' (such as polysilicon). In some embodiments, the second conductive layer 340' is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable deposition methods.

參閱第7K圖與第7L圖，在第一區域322與第二區域324中形成圖案化的光阻層460。在第一區域322中，圖案化的光阻層460覆蓋第二介電層370的一部分；在第二區域324中，圖案化的光阻層460覆蓋第二導電層340’的一部分。圖案化的光阻層460可以透過適當的沉積、顯影及/或蝕刻技術形成。接著，使用圖案化的光阻層460作為蝕刻遮罩，對未被圖案化的光阻層460覆蓋的第二導電層340’進行蝕刻。在第一區域322中，第一導電層330’與第二導電層340’被蝕刻，以定義第一電極330與第二電極340，並暴露隔離結構350、第一介電層360及第一電極330。第一電極330的側壁337與第二電極340的側壁347也被暴露。此外，在第二區域324中，導電層330a’與第二導電層340’被蝕刻，以定義第一導電結構330a與第二導電結構340a，並暴露隔離結構350及介電層360a。隨後，摻雜基板302，以在基板302中形成位於第一區域322的摻雜區域304a及304b以及位於第二區域324的摻雜區域304c及304d。Referring to FIG. 7K and FIG. 7L , a patterned photoresist layer 460 is formed in the first region 322 and the second region 324 . In the first region 322, the patterned photoresist layer 460 covers a part of the second dielectric layer 370; in the second region 324, the patterned photoresist layer 460 covers a part of the second conductive layer 340'. The patterned photoresist layer 460 can be formed by suitable deposition, development and/or etching techniques. Next, using the patterned photoresist layer 460 as an etching mask, the second conductive layer 340' not covered by the patterned photoresist layer 460 is etched. In the first region 322, the first conductive layer 330' and the second conductive layer 340' are etched to define the first electrode 330 and the second electrode 340, and expose the isolation structure 350, the first dielectric layer 360 and the first electrode 330 . The sidewall 337 of the first electrode 330 and the sidewall 347 of the second electrode 340 are also exposed. In addition, in the second region 324, the conductive layer 330a' and the second conductive layer 340' are etched to define the first conductive structure 330a and the second conductive structure 340a, and expose the isolation structure 350 and the dielectric layer 360a. Subsequently, the substrate 302 is doped to form doped regions 304 a and 304 b located in the first region 322 and doped regions 304 c and 304 d located in the second region 324 in the substrate 302 .

在本揭露之一些實施方式中，第7L圖的蝕刻製程定義電容結構C1。具體而言，電容結構C1包含第一電容與第二電容，基板302的摻雜部分306為第一電容的下電極、第一電極330為第一電容的上電極及第二電容的下電極，以及第二電極340為第二電容的上電極。此外，第7L圖的蝕刻製程定義周邊元件C2。在周邊元件C2視為電晶體之一些實施方式中，周邊元件C2的導電結構(第一導電結構330a及第二導電結構340a)視為閘極、摻雜區域304c及304d視為源極/汲極，且基板302的摻雜部分306a視為通道。在周邊元件C2視為另一個電容結構之一些實施方式中，周邊元件C2的導電結構(第一導電結構330a及第二導電結構340a)視為上電極，而基板302的摻雜部分306a視為下電極。In some embodiments of the present disclosure, the etch process of FIG. 7L defines capacitive structure C1. Specifically, the capacitor structure C1 includes a first capacitor and a second capacitor, the doped portion 306 of the substrate 302 is the lower electrode of the first capacitor, the first electrode 330 is the upper electrode of the first capacitor and the lower electrode of the second capacitor, And the second electrode 340 is the upper electrode of the second capacitor. In addition, the etch process of FIG. 7L defines peripheral element C2. In some embodiments where the peripheral element C2 is regarded as a transistor, the conductive structures of the peripheral element C2 (the first conductive structure 330a and the second conductive structure 340a ) are regarded as gates, and the doped regions 304c and 304d are regarded as source/drain electrodes. pole, and the doped portion 306a of the substrate 302 is considered a channel. In some embodiments where the peripheral element C2 is regarded as another capacitive structure, the conductive structures of the peripheral element C2 (the first conductive structure 330a and the second conductive structure 340a ) are regarded as the upper electrode, and the doped portion 306a of the substrate 302 is regarded as the upper electrode. lower electrode.

參閱第7L圖與第7M圖，移除光阻層460，以暴露第一區域322中的第二電極340及第二區域324中的第二導電結構340a。移除光阻層460可以透過使用光阻剝離製程，例如灰化製程、蝕刻製程或其他適當的製程。接著，形成在第一區域中322形成第一間隔件380及第二間隔件390以及在第二區域324中形成間隔件。詳細來說，在第一區域322中，在第一電極330的相對側壁337上形成第一間隔件380以及在第二電極340的相對側壁339上形成第二間隔件390；在第二區域324中，在第一導電結構330a的相對側壁339與第二導電結構340a的相對側壁349形成間隔件390a。第一間隔件380、第二間隔件390及間隔件390a可包含一或多種介電材料，例如氧化矽、氮化矽、矽氮氧化物、SiCN、SiC xO yN z或其組合。第一間隔件380、第二間隔件390及間隔件390a可透過電漿增強化學氣相沉積(PECVD)、低壓化學氣相沉積(LPCVD)、亞大氣壓化學氣相沉積(SACVD)或其他適當的沉積方法形成。 Referring to FIG. 7L and FIG. 7M, the photoresist layer 460 is removed to expose the second electrode 340 in the first region 322 and the second conductive structure 340a in the second region 324 . The photoresist layer 460 can be removed by using a photoresist stripping process, such as an ashing process, an etching process, or other suitable processes. Next, a first spacer 380 and a second spacer 390 are formed in the first region 322 and a spacer is formed in the second region 324 . In detail, in the first region 322, the first spacer 380 is formed on the opposite sidewall 337 of the first electrode 330 and the second spacer 390 is formed on the opposite sidewall 339 of the second electrode 340; in the second region 324 In this case, a spacer 390a is formed on the opposite sidewall 339 of the first conductive structure 330a and the opposite sidewall 349 of the second conductive structure 340a. The first spacer 380, the second spacer 390, and the spacer 390a may comprise one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiCN , SiCxOyNz , or combinations thereof. The first spacer 380, the second spacer 390, and the spacer 390a can be deposited by plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric pressure chemical vapor deposition (SACVD), or other suitable The deposition method is formed.

在一些實施方式中，第7L圖的摻雜區域304a至304d是輕摻雜區域(LDD)。在形成第一間隔件380、第二間隔件390及間隔件390a之後，進行離子佈植製程以摻雜輕摻雜區域。然後，可以進行退火製程以激活摻雜區域304a至304d的佈植摻雜劑。在這種情況下，摻雜區域304a至304d被重摻雜以形成重摻雜區域，其中摻雜區域304a至304d與基板302具有不同導電類型的摻雜劑。In some embodiments, the doped regions 304 a - 304 d of FIG. 7L are lightly doped regions (LDDs). After the first spacer 380 , the second spacer 390 and the spacer 390 a are formed, an ion implantation process is performed to dope the lightly doped region. Then, an annealing process may be performed to activate the implanted dopants in the doped regions 304a to 304d. In this case, the doped regions 304a to 304d are heavily doped to form heavily doped regions, wherein the doped regions 304a to 304d and the substrate 302 have dopants of different conductivity types.

在基板302上方形成層間介電(ILD)層375。在第一區域322中，層間介電層375覆蓋隔離結構350、第一介電層360、第二介電層370及第二電極340；在第二區域324中，層間介電層375覆蓋隔離結構350、介電層360a及第二導電結構340a。在一些實施方式中，層間介電層375包含氧化矽、磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)、氟化矽玻璃(FSG)或其他適當的介電材料。層間介電層375可包含氮氧化矽、氮化矽、包括Si、O、C及/或H的化合物(例如，氧化矽、SiCOH和SiOC)、低介電常數的介電材料(介電常數小於約3.9的熱氧化矽的介電材料)或有機材料(例如聚合物)。層間介電層375可透過化學氣相沉積(CVD)、高密度電漿沉積(HDP)或其他適當的沉積方法形成。在一些實施方式中，在形成層間介電層375之後，進行平坦化製程，以移除層間介電層375的一部分。An interlayer dielectric (ILD) layer 375 is formed over the substrate 302 . In the first region 322, the interlayer dielectric layer 375 covers the isolation structure 350, the first dielectric layer 360, the second dielectric layer 370, and the second electrode 340; in the second region 324, the interlayer dielectric layer 375 covers the isolation structure 350, a dielectric layer 360a, and a second conductive structure 340a. In some embodiments, the interlayer dielectric layer 375 includes silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluoride silicon glass (FSG), or other suitable dielectric materials. The interlayer dielectric layer 375 may include silicon oxynitride, silicon nitride, compounds including Si, O, C, and/or H (for example, silicon oxide, SiCOH, and SiOC), low dielectric constant dielectric materials (dielectric constant Dielectric materials with a thermal silicon oxide of less than about 3.9) or organic materials such as polymers. The ILD layer 375 can be formed by chemical vapor deposition (CVD), high density plasma deposition (HDP) or other suitable deposition methods. In some embodiments, after forming the interlayer dielectric layer 375 , a planarization process is performed to remove a portion of the interlayer dielectric layer 375 .

參閱第7N圖，在形成層間介電層375之後，蝕刻層間介電層375，以形成接觸開口405、405a、415、425及425a。在第一區域322中，接觸開口405暴露第一電極330、接觸開口415暴露第二電極340以及接觸開口425暴露摻雜區域304a及304b；在第二區域324中，接觸開口405a暴露第二導電結構340a以及接觸開口425a暴露摻雜區域304c及304d。Referring to FIG. 7N, after forming the interlayer dielectric layer 375, the interlayer dielectric layer 375 is etched to form contact openings 405, 405a, 415, 425 and 425a. In the first region 322, the contact opening 405 exposes the first electrode 330, the contact opening 415 exposes the second electrode 340 and the contact opening 425 exposes the doped regions 304a and 304b; in the second region 324, the contact opening 405a exposes the second conductive Structure 340a and contact opening 425a expose doped regions 304c and 304d.

參閱第7N圖與第7O圖，繼續蝕刻層間介電層375，以在層間介電層中形成複數個溝槽，且溝槽分別連通於接觸開口405、405a、415、425及425a。在一些實施方式中，蝕刻製程包含使用電漿蝕刻的蝕刻步驟且使用適當的蝕刻劑，例如含氟蝕刻劑，以選擇性地蝕刻層間介電層375。Referring to FIG. 7N and FIG. 7O, the interlayer dielectric layer 375 is continuously etched to form a plurality of trenches in the interlayer dielectric layer, and the trenches are respectively connected to the contact openings 405, 405a, 415, 425, and 425a. In some embodiments, the etching process includes an etching step using plasma etching and using a suitable etchant, such as a fluorine-containing etchant, to selectively etch the ILD layer 375 .

回到第4圖，在第7O圖的蝕刻製程完成之後，在溝槽及接觸開口405、405a、415、425及425a中填充導電材料，以形成導電接觸400、400a、410、420a及420b。隨後，執行平坦化製程，以移除導電材料的多餘部分，使得導電接觸400、400a、410、420a及420b共面。詳細來說，在第一區域322中，導電接觸400形成於第一電極330上、導電接觸410形成於第二電極340上以及導電接觸420形成於摻雜區域304a及304b上；在第二區域324中，導電接觸400a形成於第二導電結構340a、導電接觸420a形成於摻雜區域304c上，以及導電接觸420b形成於摻雜區域304d上。如此一來，可以獲得如第4圖所示的半導體結構300。Returning to FIG. 4, after the etching process in FIG. 7O is completed, conductive material is filled in the trenches and contact openings 405, 405a, 415, 425, and 425a to form conductive contacts 400, 400a, 410, 420a, and 420b. Subsequently, a planarization process is performed to remove excess portions of the conductive material so that the conductive contacts 400, 400a, 410, 420a, and 420b are coplanar. Specifically, in the first region 322, the conductive contact 400 is formed on the first electrode 330, the conductive contact 410 is formed on the second electrode 340, and the conductive contact 420 is formed on the doped regions 304a and 304b; in the second region In 324, a conductive contact 400a is formed on the second conductive structure 340a, a conductive contact 420a is formed on the doped region 304c, and a conductive contact 420b is formed on the doped region 304d. In this way, a semiconductor structure 300 as shown in FIG. 4 can be obtained.

第8圖繪示根據本揭露另一實施方式之半導體結構500的剖面圖、第9圖繪示第8圖的半導體結構300的電容結構C1’的上視圖，以及第10圖繪示第8圖的半導體結構300的周邊元件C2’的上視圖，其中第8圖的電容結構C1’繪示第9圖沿線段8-8的剖面圖，且第8圖的周邊元件C2’繪示第10圖沿線段8’-8’的剖面圖。第8圖至第10圖的半導體結構500的電容結構C1’可對應於第2圖的電容結構250或第3圖的電容結構250a。也就是說，第8圖至第10圖的半導體結構500的電容結構C1’設置於半導體元件的基板502上，且電性連接第2圖及第3圖的記憶體元件210，其中基板502對應於第2圖及第3圖的基板202。半導體結構500的周邊元件C2’可以與電容結構C1’連接階梯結構220中不同的導電接觸。半導體結構500可設置於第2、3圖的驅動電路層204或第1A圖的驅動電路層104，且半導體結構300具有第一區域522與第二區域524，其中。電容結構C1’位於第一區域522且周邊元件C2’位於第二區域524。電容結構C1’包含基板502中的摻雜部分506、第一電極530、第一介電層560、第二電極540以及第二介電層370。第一電極530位於基板502的摻雜部分506上，且第一電極530具有底部分532與頂部分534，其中第一電極530的底部分532位於基板502內，且第二電極540位於第一電極530上。第一電極530的頂部分534圍繞第二電極540，且第二電極540的最低底面541在第一電極530的最高頂面535的下方。第一介電層560位於第一電極530下方，且位於基板502的摻雜部分506與第一電極530之間。第二介電層570位於第一電極530與第二電極540之間。第一電極530的最高頂面535與第二電極540的最高頂面545不重疊。在本揭露之一些實施方式中，基板502的摻雜部分506、第一介電層560及第一電極530視為第一電容，且第一電極530、第二介電層570及第二電極540視為第二電容。亦即，基板502的摻雜部分506為第一電容的下電極且第一電極530為第一電容的上電極，而第一電極530為第二電容的下電極且第二電極540為第二電容的上電極。經由上述的配置，可增加電容結構C1’的電容值。此外，也可以減少電容結構C1’在半導體元件(例如第2圖的半導體元件200或第3圖的半導體元件200a)所占用的空間。FIG. 8 shows a cross-sectional view of a semiconductor structure 500 according to another embodiment of the present disclosure, FIG. 9 shows a top view of the capacitor structure C1' of the semiconductor structure 300 of FIG. The top view of the peripheral element C2' of the semiconductor structure 300, wherein the capacitor structure C1' in FIG. 8 shows the cross-sectional view along the line 8-8 in FIG. Sectional view along line 8'-8'. The capacitor structure C1' of the semiconductor structure 500 in FIGS. 8 to 10 may correspond to the capacitor structure 250 in FIG. 2 or the capacitor structure 250a in FIG. 3 . That is to say, the capacitive structure C1' of the semiconductor structure 500 in FIGS. 8 to 10 is disposed on the substrate 502 of the semiconductor element, and is electrically connected to the memory element 210 in FIGS. 2 and 3, wherein the substrate 502 corresponds to Substrate 202 in FIGS. 2 and 3 . The peripheral element C2' of the semiconductor structure 500 may be connected to different conductive contacts in the ladder structure 220 with the capacitor structure C1'. The semiconductor structure 500 can be disposed on the driving circuit layer 204 in FIGS. 2 and 3 or the driving circuit layer 104 in FIG. 1A , and the semiconductor structure 300 has a first region 522 and a second region 524 , wherein. The capacitor structure C1' is located in the first area 522 and the peripheral element C2' is located in the second area 524. The capacitive structure C1' includes a doped portion 506 in a substrate 502, a first electrode 530, a first dielectric layer 560, a second electrode 540, and a second dielectric layer 370. The first electrode 530 is located on the doped portion 506 of the substrate 502, and the first electrode 530 has a bottom portion 532 and a top portion 534, wherein the bottom portion 532 of the first electrode 530 is located in the substrate 502, and the second electrode 540 is located on the first on the electrode 530. The top portion 534 of the first electrode 530 surrounds the second electrode 540 , and the lowest bottom surface 541 of the second electrode 540 is below the highest top surface 535 of the first electrode 530 . The first dielectric layer 560 is located under the first electrode 530 and between the doped portion 506 of the substrate 502 and the first electrode 530 . The second dielectric layer 570 is located between the first electrode 530 and the second electrode 540 . The highest top surface 535 of the first electrode 530 does not overlap with the highest top surface 545 of the second electrode 540 . In some embodiments of the present disclosure, the doped portion 506 of the substrate 502, the first dielectric layer 560 and the first electrode 530 are regarded as a first capacitor, and the first electrode 530, the second dielectric layer 570 and the second electrode 540 is regarded as the second capacitor. That is, the doped portion 506 of the substrate 502 is the lower electrode of the first capacitor and the first electrode 530 is the upper electrode of the first capacitor, while the first electrode 530 is the lower electrode of the second capacitor and the second electrode 540 is the second electrode. The upper electrode of the capacitor. Through the above configuration, the capacitance value of the capacitance structure C1' can be increased. In addition, the space occupied by the capacitor structure C1' in the semiconductor device (such as the semiconductor device 200 in FIG. 2 or the semiconductor device 200a in FIG. 3 ) can also be reduced.

電容結構C1’的第一電極530具有底部分532與頂部分534。第一電極530的底部分532位於第二電極540的下方，且第一電極530的底部分532的寬度比第二電極540寬。第二電極540被第一電極530的頂部分534圍繞且在垂直方向上凸出於第一電極530的頂部分534。也就是說，第二電極540的頂面545在第一電極530的最高頂面535上方。在一些實施方式中，第二電極540在基板502上的垂直投影位於第一電極530在基板502上的垂直投影之內。此外，第二電極540的最高頂面545與第一電極530的最高頂面535不重疊。具體而言，第二電極540的最高頂面545在基板502的垂直投影與第一電極530的最高頂面535在基板502的垂直投影分隔。在一些實施方式中，第二電極540部分地覆蓋第一電極530的底部分532。也就是說，第一電極530的最低底面533的一部分被第二電極540的底面541覆蓋，而第一電極530的最低底面533的其餘部分未被第二電極540的底面541覆蓋。在一些實施方式中，第一電極530與第二電極540具有不同的剖面形狀。例如，第一電極530具有U形輪廓，而第二電極540是矩形輪廓。在一些實施方式中，第一電極530的底部分532具有第一厚度T5，且第二電極540具有第二厚度T6。第一電極530的底部分532的第一厚度T5在約700埃(Å)至約900埃的範圍間(例如800埃)，且第二電極540的第二厚度T6在約700埃(Å)至約900埃的範圍間(例如800埃)。當第一電極530的底部分532的第一厚度T5與第二電極540的第二厚度T6在上述的範圍間時，第二電極540可填充在第一電極530內的開口O2，以確保第一電極530與第二電極540交界的位置形成階梯狀的側壁，從而增加電容結構C1’的電容值。在一些實施方式中，第二電極540的第二厚度T6大於或實質上等於第一電極530的第一厚度T5。在一些實施方式中，第一電極530的底部分532與頂部分534交界的位置具有階梯狀的側壁，可增加電容結構C1’的第二電容的電容值。此外，由於第一電極530與基板502的摻雜部分506交界的位置具有階梯狀的側壁，可增加電容結構C1’的第一電容的電容值。The first electrode 530 of the capacitive structure C1' has a bottom portion 532 and a top portion 534. The bottom portion 532 of the first electrode 530 is located below the second electrode 540 , and the width of the bottom portion 532 of the first electrode 530 is wider than that of the second electrode 540 . The second electrode 540 is surrounded by the top portion 534 of the first electrode 530 and protrudes from the top portion 534 of the first electrode 530 in a vertical direction. That is to say, the top surface 545 of the second electrode 540 is above the highest top surface 535 of the first electrode 530 . In some embodiments, the vertical projection of the second electrode 540 on the substrate 502 is located within the vertical projection of the first electrode 530 on the substrate 502 . In addition, the highest top surface 545 of the second electrode 540 does not overlap with the highest top surface 535 of the first electrode 530 . Specifically, the vertical projection of the highest top surface 545 of the second electrode 540 on the substrate 502 is separated from the vertical projection of the highest top surface 535 of the first electrode 530 on the substrate 502 . In some embodiments, the second electrode 540 partially covers the bottom portion 532 of the first electrode 530 . That is, a part of the lowest bottom surface 533 of the first electrode 530 is covered by the bottom surface 541 of the second electrode 540 , while the rest of the lowest bottom surface 533 of the first electrode 530 is not covered by the bottom surface 541 of the second electrode 540 . In some embodiments, the first electrode 530 and the second electrode 540 have different cross-sectional shapes. For example, the first electrode 530 has a U-shaped profile, while the second electrode 540 has a rectangular profile. In some embodiments, the bottom portion 532 of the first electrode 530 has a first thickness T5, and the second electrode 540 has a second thickness T6. The first thickness T5 of the bottom portion 532 of the first electrode 530 is in the range of about 700 angstroms (Å) to about 900 angstroms (for example, 800 angstroms), and the second thickness T6 of the second electrode 540 is about 700 angstroms (Å). to about 900 angstroms (eg, 800 angstroms). When the first thickness T5 of the bottom portion 532 of the first electrode 530 and the second thickness T6 of the second electrode 540 are within the above-mentioned range, the second electrode 540 can fill the opening O2 in the first electrode 530 to ensure that the second electrode 540 The junction of the first electrode 530 and the second electrode 540 forms a stepped sidewall, thereby increasing the capacitance of the capacitor structure C1 ′. In some embodiments, the second thickness T6 of the second electrode 540 is greater than or substantially equal to the first thickness T5 of the first electrode 530 . In some embodiments, the junction of the bottom portion 532 and the top portion 534 of the first electrode 530 has a stepped sidewall, which can increase the capacitance of the second capacitor of the capacitor structure C1'. In addition, since the junction of the first electrode 530 and the doped portion 506 of the substrate 502 has a stepped sidewall, the capacitance of the first capacitor of the capacitor structure C1' can be increased.

在一些實施方式中，基板502具有摻雜區域504a及504b，且摻雜區域504a及504b具有相同的電性。此外，摻雜區域504a及504b具有與基板502不同的電性。摻雜區域504a及504b的頂面505在第一電極530的最高頂面535的下方。隔離結構550鄰接且接觸基板502的摻雜區域504a及504b。在一些實施方式中，基板502的摻雜部分506更具有區塊A1’及A2’，區塊A1’位於摻雜區域504a的正下方，以及區塊A2’位於摻雜區域504b的正下方。換句話說，基板502的摻雜部分506的區塊A1’及A2’位於隔離結構550與第一電極530之間。基板502的摻雜部分506的最高頂面507在第一電極530的最低底面533的上方。應理解到，第8圖至第10圖的基板502、摻雜區域504a及504b以及隔離結構550之材料與配置分別類似於第4圖至第6圖的基板302、摻雜區域304a及304b以及隔離結構350，故為簡化起見，在以下的說明將不再重複描述。In some embodiments, the substrate 502 has doped regions 504a and 504b, and the doped regions 504a and 504b have the same electrical property. In addition, the doped regions 504 a and 504 b have electrical properties different from those of the substrate 502 . The top surfaces 505 of the doped regions 504 a and 504 b are below the highest top surface 535 of the first electrode 530 . The isolation structure 550 adjoins and contacts the doped regions 504 a and 504 b of the substrate 502 . In some embodiments, the doped portion 506 of the substrate 502 further has blocks A1' and A2', the block A1' is directly below the doped region 504a, and the block A2' is directly below the doped region 504b. In other words, the regions A1' and A2' of the doped portion 506 of the substrate 502 are located between the isolation structure 550 and the first electrode 530. The highest top surface 507 of the doped portion 506 of the substrate 502 is above the lowest bottom surface 533 of the first electrode 530 . It should be understood that the materials and configurations of the substrate 502, doped regions 504a and 504b, and isolation structure 550 in FIGS. 8 to 10 are similar to those of the substrate 302, doped regions 304a and 304b and The isolation structure 350 will not be repeated in the following description for the sake of simplicity.

在一些實施方式中，電容結構C1’包含位於第二電極540上方的介電層590。第一介電層560接觸基板502、摻雜區域504a及504b、隔離結構550以及第一電極530，且第二介電層570接觸隔離結構550、第一介電層560、第一電極530及第二電極540。在一些實施方式中，第一介電層560接觸隔離結構550的側壁551，而第二介電層570接觸隔離結構550的頂面553。介電層590接觸第二電極540，且與第一電極530分隔。在一些實施方式中，周邊元件C2’包含位於在第二區域524的基板502上方的介電層590a。介電層590a位於導電結構580下方，且介電層590a接觸摻雜區域504c及504d、隔離結構550及導電結構580。 In some embodiments, the capacitive structure C1' includes a dielectric layer 590 over the second electrode 540. The first dielectric layer 560 contacts the substrate 502, the doped regions 504a and 504b, the isolation structure 550, and the first electrode 530, and the second dielectric layer 570 contacts the isolation structure 550, the first dielectric layer 560, the first electrode 530, and the second electrode 540 . In some embodiments, the first dielectric layer 560 contacts the sidewall 551 of the isolation structure 550 , and the second dielectric layer 570 contacts the top surface 553 of the isolation structure 550 . The dielectric layer 590 contacts the second electrode 540 and is separated from the first electrode 530 . In some embodiments, the peripheral element C2' includes a dielectric layer 590a over the substrate 502 in the second region 524. The dielectric layer 590 a is located under the conductive structure 580 , and the dielectric layer 590 a contacts the doped regions 504 c and 504 d , the isolation structure 550 and the conductive structure 580 .

半導體結構500的電容結構C1’包含電性連接第一電極530的導電接觸600與電性連接第二電極540的導電接觸610。在一些實施方式中，導電接觸600與導電接觸610施加不同的電壓。例如，電性連接第一電極530的導電接觸600連接電源訊號(VDD)，而電性連接第二電極540的導電接觸610接地(ground)。此外，電容結構C1’包含電性連接基板502的摻雜區域504a及504b的導電接觸620。導電接觸620與電性連接第二電極540的導電接觸610具有相同的電位。換句話說，電性連接摻雜區域504a及504b的導電接觸620與電性連接電容結構C1’的第一電極530的導電接觸600具有不同的電位，使得鄰接摻雜區域504a及504b的摻雜部分506與第一電極530之間產生電位差，以形成第一電容。同樣地，由於導電接觸600及610具有不同的電位，使得第一電極530與第二電極540之間產生電位差，以形成第二電容。 The capacitor structure C1' of the semiconductor structure 500 includes a conductive contact 600 electrically connected to the first electrode 530 and a conductive contact 610 electrically connected to the second electrode 540. In some embodiments, different voltages are applied to conductive contact 600 than to conductive contact 610 . For example, the conductive contact 600 electrically connected to the first electrode 530 is connected to the power signal (VDD), and the conductive contact 610 electrically connected to the second electrode 540 is grounded. In addition, the capacitive structure C1' includes a conductive contact 620 electrically connecting the doped regions 504a and 504b of the substrate 502 . The conductive contact 620 has the same potential as the conductive contact 610 electrically connected to the second electrode 540 . In other words, the conductive contact 620 electrically connected to the doped regions 504a and 504b and the conductive contact 600 electrically connected to the first electrode 530 of the capacitive structure C1′ have different potentials, so that the doped regions adjacent to the doped regions 504a and 504b A potential difference is generated between the portion 506 and the first electrode 530 to form a first capacitance. Likewise, since the conductive contacts 600 and 610 have different potentials, a potential difference is generated between the first electrode 530 and the second electrode 540 to form a second capacitor.

在一些實施方式中，半導體結構500包含層間介電層575。層間介電層575圍繞導電接觸600、610及620且覆蓋隔離結構550、第二介電層570、介電層590。In some embodiments, the semiconductor structure 500 includes an interlayer dielectric layer 575 . The interlayer dielectric layer 575 surrounds the conductive contacts 600 , 610 and 620 and covers the isolation structure 550 , the second dielectric layer 570 , and the dielectric layer 590 .

半導體結構500的周邊元件C2’包含位於基板502的摻雜部分506a、位於基板302上的介電層590a以及位於介電層590a上的導電結構580。此外，周邊元件C2’更包含位於基板302內的摻雜區域504c及504d，且摻雜部分506a位於摻雜區域504c及504d之間。在一些實施方式中，周邊元件C2’視為另一個電容結構，周邊元件C2’的導電結構580視為上電極，而基板502的摻雜部分506a視為下電極。在一些其他的實施方式中，周邊元件C2’視為電晶體，周邊元件C2’的導電結構580視為閘極、摻雜區域504c及504d視為源極/汲極，且基板502的摻雜部分506a視為通道。The peripheral component C2' of the semiconductor structure 500 includes a doped portion 506a on the substrate 502, a dielectric layer 590a on the substrate 302, and a conductive structure 580 on the dielectric layer 590a. In addition, the peripheral device C2' further includes doped regions 504c and 504d located in the substrate 302, and the doped portion 506a is located between the doped regions 504c and 504d. In some embodiments, the peripheral element C2' is regarded as another capacitive structure, the conductive structure 580 of the peripheral element C2' is regarded as the upper electrode, and the doped portion 506a of the substrate 502 is regarded as the lower electrode. In some other embodiments, the peripheral element C2' is regarded as a transistor, the conductive structure 580 of the peripheral element C2' is regarded as a gate, the doped regions 504c and 504d are regarded as a source/drain, and the doping of the substrate 502 Section 506a is considered a channel.

導電結構580的頂面581在電容結構C1’的第二電極540的頂面545上方。在一些實施方式中，導電結構580的底面583與電容結構C1’的第二電極540的頂面545大致齊平。在一些實施方式中，導電結構580具有矩形輪廓。在一些實施方式中，周邊元件C2’包含間隔件630，且間隔件630形成於導電結構580的側壁589上。間隔件630接觸介電層590及導電結構580，且與摻雜區域504c及504d分隔。The top surface 581 of the conductive structure 580 is above the top surface 545 of the second electrode 540 of the capacitive structure C1'. In some embodiments, the bottom surface 583 of the conductive structure 580 is substantially flush with the top surface 545 of the second electrode 540 of the capacitive structure C1'. In some embodiments, conductive structure 580 has a rectangular outline. In some embodiments, the peripheral element C2' includes a spacer 630, and the spacer 630 is formed on the sidewall 589 of the conductive structure 580. Spacer 630 contacts dielectric layer 590 and conductive structure 580 and separates doped regions 504c and 504d.

在一些實施方式中，周邊元件C2’包含導電接觸610a、620a及620b。導電接觸610a電性連接導電結構580、導電接觸620a電性連接基板502的摻雜區域504c，以及導電接觸620b電性連接基板502的摻雜區域504d。在周邊元件C2’為電容結構的實施方式中，電性連接摻雜區域504c的導電接觸620a與電性連接摻雜區域504d的導電接觸620b具有相同的電位。在周邊元件C2’為電晶體的實施方式中，電性連接摻雜區域504c的導電接觸620a與電性連接摻雜區域504d的導電接觸620b具有不同的電位。在第二區域524中，層間介電層575圍繞導電接觸610a、620a及620b且覆蓋隔離結構550、介電層570a、介電層590及導電結構580。In some embodiments, peripheral element C2' includes conductive contacts 610a, 620a, and 620b. The conductive contact 610 a is electrically connected to the conductive structure 580 , the conductive contact 620 a is electrically connected to the doped region 504 c of the substrate 502 , and the conductive contact 620 b is electrically connected to the doped region 504 d of the substrate 502 . In an embodiment where the peripheral element C2' is a capacitor structure, the conductive contact 620a electrically connected to the doped region 504c has the same potential as the conductive contact 620b electrically connected to the doped region 504d. In an embodiment where the peripheral component C2' is a transistor, the conductive contact 620a electrically connected to the doped region 504c and the conductive contact 620b electrically connected to the doped region 504d have different potentials. In the second region 524 , the interlayer dielectric layer 575 surrounds the conductive contacts 610 a , 620 a and 620 b and covers the isolation structure 550 , the dielectric layer 570 a , the dielectric layer 590 and the conductive structure 580 .

第11A圖至第11O圖繪示根據本揭露一些實施方式之半導體結構500的製造方法在各步驟的剖面圖。FIG. 11A to FIG. 110 are cross-sectional views of various steps in the method of fabricating the semiconductor structure 500 according to some embodiments of the present disclosure.

參閱第11A圖，在基板502上方依序形成介電層560a與遮罩層640，其中遮罩層640接觸介電層560a。接著，蝕刻遮罩層640、介電層560a及基板502，以形成凹陷R3。在一些實施方式中，如第11A圖所示，凹陷R3暴露位於第一區域522的基板502的中央部分及邊緣部分，而凹陷R3暴露位於第二區域524的基板502的邊緣部分。基板502具有位於第一區域522的摻雜部分506及位於第二區域524的摻雜部分506a。在一些實施方式中，第11A圖的介電層560a及遮罩層640之材料與製程方法分別類似於第7A圖的介電層360a及遮罩層430，故為簡化起見，在以下的說明將不再重複描述。Referring to FIG. 11A, a dielectric layer 560a and a mask layer 640 are sequentially formed on the substrate 502, wherein the mask layer 640 is in contact with the dielectric layer 560a. Next, the mask layer 640, the dielectric layer 560a and the substrate 502 are etched to form the recess R3. In some embodiments, as shown in FIG. 11A , the recess R3 exposes the central portion and the edge portion of the substrate 502 located in the first region 522 , and the recess R3 exposes the edge portion of the substrate 502 located in the second region 524 . The substrate 502 has a doped portion 506 located in the first region 522 and a doped portion 506 a located in the second region 524 . In some embodiments, the materials and manufacturing methods of the dielectric layer 560a and the mask layer 640 in FIG. 11A are similar to the dielectric layer 360a and the mask layer 430 in FIG. 7A respectively, so for the sake of simplicity, the following Description will not repeat the description.

參閱第11A圖與第11B圖，在凹陷R3中填入介電材料，以形成隔離結構550。在一些實施方式中，在形成隔離結構550之後，進行平坦化製程，如化學機械研磨製程(CMP)，以移除隔離結構550的一部分，使得隔離結構550的頂面與遮罩層640的頂面大致齊平。Referring to FIG. 11A and FIG. 11B , a dielectric material is filled in the recess R3 to form an isolation structure 550 . In some embodiments, after the isolation structure 550 is formed, a planarization process, such as a chemical mechanical polishing process (CMP), is performed to remove a part of the isolation structure 550 so that the top surface of the isolation structure 550 is aligned with the top surface of the mask layer 640 The surface is roughly even.

參閱第11C圖，回蝕隔離結構550，以暴露遮罩層640的側壁641。此外，回蝕隔離結構550，使得隔離結構550的頂面553接近介電層560a的頂面t2。蝕刻隔離結構550可以使用濕式蝕刻或其他適當的蝕刻方法。Referring to FIG. 11C , the isolation structure 550 is etched back to expose the sidewall 641 of the mask layer 640 . In addition, the isolation structure 550 is etched back so that the top surface 553 of the isolation structure 550 is close to the top surface t2 of the dielectric layer 560 a. Etching the isolation structure 550 may use wet etching or other suitable etching methods.

參閱第11C圖與第11D圖，蝕刻隔離結構550之後，移除遮罩層640，以暴露介電層560a。在一些實施方式中，移除遮罩層640可以使用磷酸(H 3PO 4)或其他適當的蝕刻劑。 Referring to FIG. 11C and FIG. 11D, after etching the isolation structure 550, the mask layer 640 is removed to expose the dielectric layer 560a. In some embodiments, phosphoric acid (H 3 PO 4 ) or other suitable etchant may be used to remove the mask layer 640 .

參閱第11E圖，在第一區域522與第二區域524中形成圖案化的光阻層650。在第一區域522中，圖案化的光阻層650覆蓋隔離結構550與介電層560a的一部分，並暴露介電層560a的其餘部分；在第二區域524中，圖案化的光阻層650覆蓋隔離結構550與介電層560a的全體。圖案化的光阻層650可以透過適當的沉積、顯影及/或蝕刻技術形成。接著，使用圖案化的光阻層650作為蝕刻遮罩，對未被圖案化的光阻層650覆蓋的介電層560a進行蝕刻，以在第一區域522形成凹陷R4暴露第一區域522的基板502與介電層560a的側壁561。Referring to FIG. 11E , a patterned photoresist layer 650 is formed in the first region 522 and the second region 524 . In the first region 522, the patterned photoresist layer 650 covers the isolation structure 550 and a part of the dielectric layer 560a, and exposes the rest of the dielectric layer 560a; in the second region 524, the patterned photoresist layer 650 It covers the whole of the isolation structure 550 and the dielectric layer 560a. The patterned photoresist layer 650 can be formed by suitable deposition, development and/or etching techniques. Next, using the patterned photoresist layer 650 as an etching mask, the dielectric layer 560a not covered by the patterned photoresist layer 650 is etched to form a recess R4 in the first region 522 to expose the substrate of the first region 522 502 and the sidewall 561 of the dielectric layer 560a.

參閱第11E圖與第11F圖，在形成第二凹陷R2後，移除光阻層650。移除光阻層650可以透過使用光阻剝離製程，例如灰化製程、蝕刻製程或其他適當的製程。接著，在凹陷R4中形成第一介電層560。在一些實施方式中，形成第一介電層560可透過熱氧化製程，使得第一介電層560接續在介電層560a的側壁561生長並形成於基板502上。在一些實施方式中，第一介電層560具有厚度T7在約350埃至450埃的範圍間(例如400埃)。Referring to FIG. 11E and FIG. 11F , after forming the second recess R2 , the photoresist layer 650 is removed. The photoresist layer 650 can be removed by using a photoresist stripping process, such as an ashing process, an etching process, or other suitable processes. Next, a first dielectric layer 560 is formed in the recess R4. In some embodiments, the first dielectric layer 560 may be formed through a thermal oxidation process, so that the first dielectric layer 560 is continuously grown on the sidewall 561 of the dielectric layer 560 a and formed on the substrate 502 . In some embodiments, the first dielectric layer 560 has a thickness T7 in a range of about 350 angstroms to 450 angstroms (eg, 400 angstroms).

參閱第11G圖，在第一介電層560上方形成第一導電層530’。在第一區域522中，第一導電層530’的最低底面533在隔離結構550的最高頂面553下方；在第二區域524中，第一導電層530’的全體位於隔離結構550上方。第一導電層530’的底部分532’的厚度T5(對應於第8圖的第一電極530的底部分532的第一厚度T5)在約700埃至約900埃的範圍間(例如800埃)。若第一導電層530’的底部分532’的厚度T5大於900埃時，製造電容結構的製程成本會過高；若第一導電層530’的底部分532’的厚度T5小於700埃時，後續形成電容(第4圖的電容結構C1’)的阻值會過高，使電容無法達到預期的效果。第一導電層530’可包含半導體材料(例如多晶矽)、金屬或其他適當的導電材料。在一些實施方式中，第11G圖的第一導電層530’之材料與製程方法類似於第7G圖的第一電極330，故為簡化起見，在以下的說明將不再重複描述。Referring to FIG. 11G , a first conductive layer 530 ′ is formed over the first dielectric layer 560 . In the first region 522, the lowest bottom surface 533 of the first conductive layer 530' is below the highest top surface 553 of the isolation structure 550; The thickness T5 of the bottom portion 532' of the first conductive layer 530' (corresponding to the first thickness T5 of the bottom portion 532 of the first electrode 530 in FIG. ). If the thickness T5 of the bottom part 532' of the first conductive layer 530' is greater than 900 angstroms, the process cost of manufacturing the capacitor structure will be too high; if the thickness T5 of the bottom part 532' of the first conductive layer 530' is less than 700 angstroms, The resistance value of the subsequently formed capacitor (the capacitor structure C1' in FIG. 4 ) will be too high, so that the capacitor cannot achieve the desired effect. The first conductive layer 530' may include semiconductor material (such as polysilicon), metal or other suitable conductive materials. In some embodiments, the material and manufacturing method of the first conductive layer 530' in FIG. 11G are similar to the first electrode 330 in FIG. 7G, so for the sake of simplicity, the following description will not be repeated.

參閱第11G圖與第11H圖，在形成第一導電層530’之後，進行平坦化製程，以移除第一導電層530’的一部分，並定義第一電極530，其中平坦化製程停止於隔離結構550。詳細來說，在第一區域522中，平坦化製程暴露隔離結構550、第一介電層560與第一電極530，使得隔離結構550的最高頂面553、第一介電層560的最高頂面563與第一電極530的最高頂面535大致齊平；在第二區域524中，平坦化製程暴露隔離結構550及介電層560a，使得隔離結構550的頂面553與介電層560a的頂面大致齊平且在第二區域524中無第一導電層530’。Referring to FIG. 11G and FIG. 11H, after forming the first conductive layer 530', a planarization process is performed to remove a part of the first conductive layer 530' and define the first electrode 530, wherein the planarization process stops at the isolation Structure 550. In detail, in the first region 522, the planarization process exposes the isolation structure 550, the first dielectric layer 560 and the first electrode 530, so that the highest top surface 553 of the isolation structure 550, the highest top surface of the first dielectric layer 560 The surface 563 is substantially flush with the highest top surface 535 of the first electrode 530; in the second region 524, the planarization process exposes the isolation structure 550 and the dielectric layer 560a, so that the top surface 553 of the isolation structure 550 and the dielectric layer 560a The top surface is substantially flush and there is no first conductive layer 530 ′ in the second region 524 .

參閱第11I圖，在第一區域522形成第二介電層570以及在第二區域524中形成介電層570a。在第一區域522中，第二介電層570覆蓋隔離結構550、第一介電層560與第一電極530，且第二介電層570與第一介電層560的一部分被第一電極530分隔；在第二區域524中，介電層570a覆蓋隔離結構550與第一介電層560。在一些實施方式中，第二介電層570及介電層570a具有厚度T8在約350埃至450埃的範圍間(例如400埃)。第二介電層570及介電層570a的厚度T8實質上等於第一介電層560的厚度T7。在一些實施方式中，第11I圖的第二介電層570及介電層570a之材料與製程方法類似於第7I圖的第二介電層370，故為簡化起見，在以下的說明將不再重複描述。Referring to FIG. 11I, a second dielectric layer 570 is formed in the first region 522 and a dielectric layer 570a is formed in the second region 524. Referring to FIG. In the first region 522, the second dielectric layer 570 covers the isolation structure 550, the first dielectric layer 560 and the first electrode 530, and part of the second dielectric layer 570 and the first dielectric layer 560 are covered by the first electrode. 530 ; in the second region 524 , the dielectric layer 570 a covers the isolation structure 550 and the first dielectric layer 560 . In some embodiments, the second dielectric layer 570 and the dielectric layer 570a have a thickness T8 ranging from about 350 angstroms to 450 angstroms (eg, 400 angstroms). The thickness T8 of the second dielectric layer 570 and the dielectric layer 570 a is substantially equal to the thickness T7 of the first dielectric layer 560 . In some embodiments, the material and process method of the second dielectric layer 570 and the dielectric layer 570a in Figure 11I are similar to the second dielectric layer 370 in Figure 7I, so for the sake of simplicity, the following description will be The description will not be repeated.

參閱第11J圖，在形成第二介電層570及介電層570a之後，在第一區域522與第二區域524中形成第二導電層540’。第11J圖的第二導電層540’之材料與製程方法類似於第7K圖的第二導電層340’，故為簡化起見，在以下的說明將不再重複描述。Referring to FIG. 11J, after forming the second dielectric layer 570 and the dielectric layer 570a, the second conductive layer 540' is formed in the first region 522 and the second region 524. Referring to FIG. The material and manufacturing method of the second conductive layer 540' in FIG. 11J are similar to the second conductive layer 340' in FIG. 7K, so for the sake of simplicity, the following description will not be repeated.

參閱第11J圖與第11K圖，在形成第二導電層540’之後，進行平坦化製程，以移除第二導電層540’的一部分，以定義第二電極540，其中平坦化製程停止於第二介電層570及介電層570a。詳細來說，在第一區域522中，平坦化製程暴露第二介電層570與第二電極540，使得第二介電層570的最高頂面571與第二電極540的最高頂面545大致齊平；在第二區域524中，平坦化製程暴露介電層570a，使得在第二區域524中無第二導電層540’。在本揭露之一些實施方式中，第11K圖的蝕刻製程定義電容結構C1’。具體而言，電容結構C1’包含第一電容與第二電容，基板502的摻雜部分506為第一電容的下電極、第一電極530為第一電容的上電極及第二電容的下電極，以及第二電極540為第二電容的上電極。在一些實施方式中，第二電極540的第二厚度T6在約700埃至約900埃的範圍間(例如800埃)。若第二電極540的第二厚度T6大於900埃時，製造電容結構的製程成本會過高；若第二電極540的第二厚度T6小於700埃時，後續形成電容(第8圖的電容結構C1’)的阻值會過高，且第二電極540可能無法填充第一電極530內的開口O2而使第二電極540的頂面無法容納導電接觸(例如第8圖的導電接觸610)，從而導致電容無法達到預期的效果。在一些實施方式中，第二電極540的第二厚度T6大於或實質上等於第一電極530的第一厚度T5。Referring to Figures 11J and 11K, after forming the second conductive layer 540', a planarization process is performed to remove a part of the second conductive layer 540' to define the second electrode 540, wherein the planarization process stops at the first Two dielectric layers 570 and a dielectric layer 570a. Specifically, in the first region 522, the planarization process exposes the second dielectric layer 570 and the second electrode 540, so that the highest top surface 571 of the second dielectric layer 570 and the highest top surface 545 of the second electrode 540 are approximately flush; in the second region 524 , the planarization process exposes the dielectric layer 570 a such that there is no second conductive layer 540 ′ in the second region 524 . In some embodiments of the present disclosure, the etch process of FIG. 11K defines capacitive structure C1'. Specifically, the capacitor structure C1' includes a first capacitor and a second capacitor, the doped portion 506 of the substrate 502 is the lower electrode of the first capacitor, and the first electrode 530 is the upper electrode of the first capacitor and the lower electrode of the second capacitor. , and the second electrode 540 is the upper electrode of the second capacitor. In some embodiments, the second thickness T6 of the second electrode 540 is in the range of about 700 angstroms to about 900 angstroms (eg, 800 angstroms). If the second thickness T6 of the second electrode 540 is greater than 900 angstroms, the process cost of manufacturing the capacitor structure will be too high; The resistance value of C1′) will be too high, and the second electrode 540 may not be able to fill the opening O2 in the first electrode 530 so that the top surface of the second electrode 540 cannot accommodate a conductive contact (such as the conductive contact 610 in FIG. 8 ), As a result, the capacitor cannot achieve the expected effect. In some embodiments, the second thickness T6 of the second electrode 540 is greater than or substantially equal to the first thickness T5 of the first electrode 530 .

參閱第11L圖，在第一區域522與第二區域524中形成圖案化的光阻層660。在第一區域522中，圖案化的光阻層660覆蓋第二介電層570與第二電極540；在第二區域524中，圖案化的光阻層660覆蓋介電層570a的一部分。接著，使用圖案化的光阻層660作為蝕刻遮罩，對未被圖案化的光阻層660覆蓋的介電層570a進行蝕刻。在第二區域524中，介電層570a與介電層560a被蝕刻，以暴露隔離結構550與基板502，而第一區域522的結構實質上不變。Referring to FIG. 11L , a patterned photoresist layer 660 is formed in the first region 522 and the second region 524 . In the first region 522, the patterned photoresist layer 660 covers the second dielectric layer 570 and the second electrode 540; in the second region 524, the patterned photoresist layer 660 covers a part of the dielectric layer 570a. Next, using the patterned photoresist layer 660 as an etching mask, the dielectric layer 570a not covered by the patterned photoresist layer 660 is etched. In the second region 524, the dielectric layer 570a and the dielectric layer 560a are etched to expose the isolation structure 550 and the substrate 502, while the structure of the first region 522 is substantially unchanged.

參閱第11M圖，在第一區域522形成介電層590以及在第二區域524形成介電層590a。在第一區域522中，介電層590覆蓋並接觸第二電極540，且介電層590在第二介電層570上方；在第二區域524中，介電層590a覆蓋基板502，且介電層590a的頂面591在介電層570a的頂面571下方。在一些實施方式中，介電層590及介電層590a具有厚度T9在約350埃至450埃的範圍間(例如400埃)。介電層590及介電層590a的厚度T9實質上等於第一介電層560的厚度及/或第二介電層570的厚度。在一些實施方式中，在一些實施方式中，介電層590及介電層590a包含氧化物，如氧化矽或其他適當的介電材料。介電層590及介電層590a可包含與第一介電層560及/或第二介電層570相同的材料。介電層590可透過熱氧化沉積、化學氣相沉積(CVD)、原子層沉積(ALD)或其他適當的沉積方法形成。Referring to FIG. 11M, a dielectric layer 590 is formed in the first region 522 and a dielectric layer 590a is formed in the second region 524. Referring to FIG. In the first region 522, the dielectric layer 590 covers and contacts the second electrode 540, and the dielectric layer 590 is above the second dielectric layer 570; in the second region 524, the dielectric layer 590a covers the substrate 502, and the dielectric layer 590 a The top surface 591 of the electrical layer 590a is below the top surface 571 of the dielectric layer 570a. In some embodiments, the dielectric layer 590 and the dielectric layer 590a have a thickness T9 ranging from about 350 angstroms to 450 angstroms (eg, 400 angstroms). The thickness T9 of the dielectric layer 590 and the dielectric layer 590 a is substantially equal to the thickness of the first dielectric layer 560 and/or the thickness of the second dielectric layer 570 . In some embodiments, the dielectric layer 590 and the dielectric layer 590a include oxide, such as silicon oxide or other suitable dielectric materials. The dielectric layer 590 and the dielectric layer 590 a may include the same material as the first dielectric layer 560 and/or the second dielectric layer 570 . The dielectric layer 590 can be formed by thermal oxidation deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods.

參閱第11N圖，在形成介電層590之後，在第一區域522與第二區域524中形成導電層580’。在第一區域522中，導電層580’形成於第二電極540上方，且接觸第二介電層570與介電層590；在第二區域524中，導電層580’形成於基板502上方，且接觸第二介電層570、隔離結構550與介電層590。在一些實施方式中，導電層580’具有厚度T10在約700埃(Å)至約900埃的範圍間(例如800埃)。導電層580’可包含半導體材料(例如多晶矽)、金屬或其他適當的導電材料。在一些實施方式中，導電層580’與第一電極530及/或第二電極540包含相同的材料(例如多晶矽)。在一些實施方式中，形成導電層580’透過化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適當的沉積方法形成。Referring to FIG. 11N, after forming the dielectric layer 590, a conductive layer 580' is formed in the first region 522 and the second region 524. Referring to FIG. In the first region 522, the conductive layer 580' is formed on the second electrode 540 and contacts the second dielectric layer 570 and the dielectric layer 590; in the second region 524, the conductive layer 580' is formed on the substrate 502, And contact the second dielectric layer 570 , the isolation structure 550 and the dielectric layer 590 . In some embodiments, the conductive layer 580' has a thickness T10 in the range of about 700 angstroms (Å) to about 900 angstroms (eg, 800 Å). The conductive layer 580' may include semiconductor material (such as polysilicon), metal or other suitable conductive materials. In some embodiments, the conductive layer 580' and the first electrode 530 and/or the second electrode 540 include the same material (such as polysilicon). In some embodiments, the conductive layer 580' is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition methods.

參閱第11N圖與第11O圖，在第二區域524中形成圖案化的光阻層670，以覆蓋導電層580’的一部分。圖案化的光阻層670可以透過適當的沉積、顯影及/或蝕刻技術形成。接著，使用圖案化的光阻層670作為蝕刻遮罩，對未被圖案化的光阻層670覆蓋的導電層580’進行蝕刻。在第一區域522中，導電層580’被全部蝕刻，以暴露第二介電層570及介電層590；在第二區域524中，導電層580’的一部分被蝕刻，以定義導電結構580，並暴露第二介電層570、隔離結構550與介電層590。隨後，摻雜基板502，以在基板502形成摻雜區域504a至504d。在本揭露之一些實施方式中，第11O圖的蝕刻製程定義周邊元件C2’。在周邊元件C2’視為電晶體之一些實施方式中，周邊元件C2’的導電結構580視為閘極、摻雜區域504c及504d視為源極/汲極，且基板502的摻雜部分506a視為通道。在周邊元件C2’視為另一個電容結構之一些實施方式中，周邊元件C2’的導電結構580視為上電極，而基板502的摻雜部分506a視為下電極。Referring to FIG. 11N and FIG. 11O, a patterned photoresist layer 670 is formed in the second region 524 to cover a portion of the conductive layer 580'. The patterned photoresist layer 670 can be formed by suitable deposition, development and/or etching techniques. Next, using the patterned photoresist layer 670 as an etching mask, the conductive layer 580' not covered by the patterned photoresist layer 670 is etched. In the first region 522, the conductive layer 580' is fully etched to expose the second dielectric layer 570 and the dielectric layer 590; in the second region 524, a part of the conductive layer 580' is etched to define the conductive structure 580 , and expose the second dielectric layer 570 , the isolation structure 550 and the dielectric layer 590 . Subsequently, the substrate 502 is doped to form doped regions 504 a to 504 d on the substrate 502 . In some embodiments of the present disclosure, the etch process of FIG. 110 defines peripheral element C2'. In some embodiments where peripheral element C2' is considered a transistor, conductive structure 580 of peripheral element C2' is considered a gate, doped regions 504c and 504d are considered source/drains, and doped portion 506a of substrate 502 considered as a channel. In some embodiments where the peripheral element C2' is considered another capacitive structure, the conductive structure 580 of the peripheral element C2' is considered the upper electrode and the doped portion 506a of the substrate 502 is considered the lower electrode.

回到第8圖，在第11O圖的製程完成之後，移除光阻層670，以暴露導電結構580。接著，在第二區域524的導電結構580的相對側壁589上形成間隔件630。在基板502上方形成層間介電層575，以在第一區域522中覆蓋第二介電層570與介電層590，以及在第二區域524中覆蓋隔離結構550、介電層570a及介電層590a。在形成層間介電層575之後，形成導電接觸600、610、610a、620、620a及620b於層間介電層575中。詳細來說，在第一區域522中，導電接觸600形成於第一電極530上、導電接觸610形成於第二電極540上以及導電接觸620形成於摻雜區域504a及504b上；在第二區域524中，導電接觸610a形成於導電結構580、導電接觸620a形成於摻雜區域504c以及導電接觸620b形成於摻雜區域504d上。如此一來，可以獲得如第8圖所示的半導體結構500。Returning to FIG. 8 , after the process of FIG. 110 is completed, the photoresist layer 670 is removed to expose the conductive structure 580 . Next, spacers 630 are formed on opposite sidewalls 589 of the conductive structure 580 in the second region 524 . An interlayer dielectric layer 575 is formed over the substrate 502 to cover the second dielectric layer 570 and the dielectric layer 590 in the first region 522, and to cover the isolation structure 550, the dielectric layer 570a and the dielectric layer in the second region 524. Layer 590a. After forming the ILD layer 575 , conductive contacts 600 , 610 , 610 a , 620 , 620 a , and 620 b are formed in the ILD layer 575 . Specifically, in the first region 522, the conductive contact 600 is formed on the first electrode 530, the conductive contact 610 is formed on the second electrode 540, and the conductive contact 620 is formed on the doped regions 504a and 504b; in the second region In 524, conductive contact 610a is formed on conductive structure 580, conductive contact 620a is formed on doped region 504c, and conductive contact 620b is formed on doped region 504d. In this way, a semiconductor structure 500 as shown in FIG. 8 can be obtained.

應理解到，層間介電層575及導電接觸(導電接觸600、610、610a、620、620a及620b)之材料、配置及形成方法類似於第4圖之層間介電層375及導電接觸(導電接觸400、400a、410、420、420a及420b)，故為在此不重複描述。It should be understood that the material, configuration and formation method of the interlayer dielectric layer 575 and the conductive contacts (conductive contacts 600, 610, 610a, 620, 620a, and 620b) are similar to those of the interlayer dielectric layer 375 and the conductive contacts (conductive contacts 400, 400a, 410, 420, 420a, and 420b), so the description will not be repeated here.

在本揭露的上述實施方式中，電容結構包括第一電容及第二電容，其中第一電容包括基板的摻雜部分及第一電極，第二電容包括第一電極與第二電極，第二電極的底部分嵌設於第一電極，可減少電容結構的電容面積且增加電容值。由於記憶體元件(例如3D NAND記憶體元件)具有多層的導電層(即字元線)，因此需要提供記憶體元件較高的電流以維持運作，故需要具有較大電容值的電容結構對記憶體元件的每層字元線提供電訊號。本揭露之一些實施方式的電容結構可在記憶體元件佔用較少的空間且滿足前述較大電容值的需求。In the above embodiments of the present disclosure, the capacitor structure includes a first capacitor and a second capacitor, wherein the first capacitor includes the doped portion of the substrate and the first electrode, the second capacitor includes the first electrode and the second electrode, and the second electrode The bottom part of the bottom part is embedded in the first electrode, which can reduce the capacitance area of the capacitance structure and increase the capacitance value. Since memory elements (such as 3D NAND memory elements) have multiple layers of conductive layers (ie, word lines), it is necessary to provide a higher current for memory elements to maintain operation, so a capacitor structure with a larger capacitance value is required for memory Each word line of the body device provides electrical signals. The capacitor structure of some embodiments of the present disclosure can occupy less space in the memory device and meet the above-mentioned requirement for larger capacitance.

雖然本揭露已以實施方式揭露如上，然其並非用以限定本揭露，任何熟習此技藝者，在不脫離本揭露之精神和範圍內，當可作各種之更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。Although this disclosure has been disclosed as above in the form of implementation, it is not intended to limit this disclosure. Anyone who is familiar with this technology can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection of this disclosure The scope shall be defined by the appended patent application scope.

100:半導體元件 102:基板 104:驅動電路層 110:記憶體元件 111:導電層 112:通道層 113:絕緣層 114:串選擇線 115:導電通孔 116:位元線 120:階梯結構 122:導電接觸 123:互連結構 124:導電接觸 126:著陸區 128:絕緣結構 130:導電狹縫 200:半導體元件 200a:半導體元件 202:基板 204:驅動電路層 210:記憶體元件 220:階梯結構 221:導電層 222:導電接觸 223:互連結構 224:導電接觸 226:著陸區 228:導電接觸 230:互連結構 250:電容結構 250a:電容結構 260:共用源極 300:半導體結構 302:基板 303:頂面 304a:摻雜區域 304b:摻雜區域 304c:摻雜區域 304d:摻雜區域 305:頂面 306:摻雜部分 306a:摻雜部分 307:頂面 322:第一區域 324:第二區域 330:第一電極 330’:第一導電層 330a:第一導電結構 330a’:導電層 331:底面 332:底部分 332’:底部分 334:頂部分 335:頂面 336:合併部分 337:側壁 339:側壁 340:第二電極 340’:第二導電層 340a:第二導電結構 341:底面 342:底部分 343:底面 344:頂部分 345:頂面 347:側壁 348:頂面 349:側壁 350:隔離結構 351:側壁 353:頂面 357:頂面 360:第一介電層 360a:介電層 370:第二介電層 375:層間介電層 380:第一間隔件 390:第二間隔件 390a:間隔件 400:導電接觸 400a:導電接觸 405:接觸開口 405a:接觸開口 410:導電接觸 415:接觸開口 420:導電接觸 420a:導電接觸 420b:導電接觸 425:接觸開口 425a:接觸開口 430:遮罩層 440:光阻層 450:光阻層 460:光阻層 500:半導體結構 502:基板 504a:摻雜區域 504b:摻雜區域 504c:摻雜區域 504d:摻雜區域 505:頂面 506:摻雜部分 506a:摻雜部分 507:頂面 522:第一區域 524:第二區域 530:第一電極 530’:第一導電層 532:底部分 532’:底部分 533:底面 534:頂部分 535:頂面 540:第二電極 540’:第二導電層 541:底面 545:頂面 550:隔離結構 551:側壁 553:頂面 560:第一介電層 560a:介電層 561:側壁 563:頂面 570:第二介電層 570a:介電層 571:頂面 575:層間介電層 580:導電結構 580’:導電層 581:頂面 583:底面 589:側壁 590:介電層 590a:介電層 591:頂面 600:導電接觸 610:導電接觸 610a:導電接觸 620:導電接觸 620a:導電接觸 620b:導電接觸 630:間隔件 640:遮罩層 641:側壁 650:光阻層 660:光阻層 670:光阻層 4-4:線段 4’-4’:線段 5B-5B:線段 8-8:線段 8’-8’:線段 A1:區塊 A1’:區塊 A2:區塊 A2’:區塊 C1:電容結構 C2:周邊元件 C1’:電容結構 C2’:周邊元件 O1:開口 O2:開口 R1:第一凹陷 R2:第二凹陷 R3:凹陷 R4:凹陷 t1:頂面 t2:頂面 T1:第一厚度 T2:第二厚度 T3:厚度 T4:厚度 T5:厚度 T6:厚度 T7:厚度 T8:厚度 T9:厚度 T10:厚度 X:方向 Y:方向 Z:方向 100: Semiconductor components 102: Substrate 104: Driving circuit layer 110: memory components 111: conductive layer 112: Channel layer 113: insulation layer 114: string selection line 115: Conductive via 116: bit line 120: Ladder structure 122: Conductive contact 123:Interconnect structure 124: Conductive contact 126: Landing Zone 128: Insulation structure 130: conductive slit 200: Semiconductor components 200a: Semiconductor components 202: Substrate 204: Driving circuit layer 210: memory components 220: ladder structure 221: conductive layer 222: Conductive contact 223:Interconnect structure 224: Conductive contact 226: Landing Zone 228: Conductive contact 230:Interconnect structure 250: capacitor structure 250a: capacitor structure 260: Shared source 300: Semiconductor Structures 302: Substrate 303: top surface 304a: Doped region 304b: doped region 304c: doped region 304d: doped region 305: top surface 306: doping part 306a: doping part 307: top surface 322: The first area 324: second area 330: first electrode 330': the first conductive layer 330a: first conductive structure 330a': conductive layer 331: Bottom 332: Bottom part 332': Bottom part 334: top part 335: top surface 336: merge part 337: side wall 339: side wall 340: second electrode 340': second conductive layer 340a: Second Conductive Structure 341: Bottom 342: Bottom part 343: Bottom 344: top part 345: top surface 347: side wall 348: top surface 349: side wall 350: Isolation structure 351: side wall 353: top surface 357: top surface 360: the first dielectric layer 360a: dielectric layer 370: second dielectric layer 375: interlayer dielectric layer 380: first spacer 390: second spacer 390a: spacer 400: conductive contact 400a: Conductive contact 405: contact opening 405a: contact opening 410: Conductive contact 415: contact opening 420: conductive contact 420a: Conductive contact 420b: Conductive contact 425: contact opening 425a: contact opening 430: mask layer 440: photoresist layer 450: photoresist layer 460: photoresist layer 500: Semiconductor Structures 502: Substrate 504a: Doped region 504b: Doped region 504c: doped region 504d: doped region 505: top surface 506: doping part 506a: doping part 507: top surface 522: The first area 524: second area 530: first electrode 530': the first conductive layer 532: Bottom part 532': Bottom part 533: Bottom 534: top part 535: top surface 540: second electrode 540': second conductive layer 541: Bottom 545: top surface 550: Isolation structure 551: side wall 553: top surface 560: the first dielectric layer 560a: dielectric layer 561: side wall 563: top surface 570: second dielectric layer 570a: dielectric layer 571: top surface 575: interlayer dielectric layer 580: Conductive structure 580': conductive layer 581: top surface 583: Bottom 589: side wall 590: dielectric layer 590a: dielectric layer 591: top surface 600: conductive contact 610: Conductive contact 610a: Conductive contact 620: conductive contact 620a: Conductive contact 620b: Conductive contact 630: spacer 640: mask layer 641: side wall 650: photoresist layer 660: photoresist layer 670: photoresist layer 4-4: Line segment 4’-4’: line segment 5B-5B: Line segment 8-8: Line segment 8’-8’: line segment A1: block A1': block A2: block A2': block C1: capacitor structure C2: peripheral components C1': capacitor structure C2': Peripheral components O1: Open O2: Open R1: first depression R2: second depression R3: concave R4: sunken t1: top surface t2: top surface T1: first thickness T2: second thickness T3: Thickness T4: Thickness T5: Thickness T6: Thickness T7: Thickness T8: Thickness T9: Thickness T10: Thickness X: direction Y: Direction Z: Direction

為讓本揭露之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下： 第1A圖繪示根據本揭露一些實施方式之半導體元件的立體圖； 第1B圖繪示第1A圖的上視圖； 第2圖繪示根據本揭露一些實施方式之包含電容結構的半導體元件的示意圖； 第3圖繪示根據本揭露另一實施方式之包含電容結構的半導體元件的示意圖； 第4圖繪示根據本揭露一些實施方式之半導體結構的剖面圖； 第5A圖繪示第4圖的半導體結構的電容結構的上視圖； 第5B圖繪示沿第4圖的線段5B-5B的上視圖； 第6圖繪示第4圖的半導體結構的周邊元件的上視圖； 第7A圖至第7O圖繪示根據本揭露一些實施方式之半導體結構的製造方法在各步驟的剖面圖； 第8圖繪示根據本揭露另一實施方式之半導體結構的剖面圖； 第9圖繪示第8圖的半導體結構的電容結構的上視圖； 第10圖繪示第8圖的半導體結構的周邊元件的上視圖；以及 第11A圖至第11O圖繪示根據本揭露一些實施方式之半導體結構的製造方法在各步驟的剖面圖。 In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more comprehensible, the accompanying drawings are described as follows: FIG. 1A illustrates a perspective view of a semiconductor device according to some embodiments of the present disclosure; Figure 1B shows the top view of Figure 1A; FIG. 2 shows a schematic diagram of a semiconductor device including a capacitor structure according to some embodiments of the present disclosure; FIG. 3 shows a schematic diagram of a semiconductor device including a capacitor structure according to another embodiment of the present disclosure; FIG. 4 illustrates a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure; FIG. 5A shows a top view of the capacitor structure of the semiconductor structure of FIG. 4; Figure 5B shows a top view along the line segment 5B-5B in Figure 4; FIG. 6 shows a top view of peripheral components of the semiconductor structure of FIG. 4; FIG. 7A to FIG. 7O are cross-sectional views of various steps in the manufacturing method of the semiconductor structure according to some embodiments of the present disclosure; FIG. 8 illustrates a cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure; FIG. 9 shows a top view of the capacitor structure of the semiconductor structure of FIG. 8; FIG. 10 illustrates a top view of peripheral components of the semiconductor structure of FIG. 8; and FIG. 11A to FIG. 110 are cross-sectional views of various steps in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

300:半導體結構 300: Semiconductor Structures

302:基板 302: Substrate

303:頂面 303: top surface

304a:摻雜區域 304a: Doped region

304b:摻雜區域 304b: doped region

304c:摻雜區域 304c: doped region

304d:摻雜區域 304d: doped region

305:頂面 305: top surface

306:摻雜部分 306: doping part

306a:摻雜部分 306a: doping part

307:頂面 307: top surface

322:第一區域 322: The first area

324:第二區域 324: second area

330:第一電極 330: first electrode

330a:第一導電結構 330a: first conductive structure

331:底面 331: Bottom

332:底部分 332: Bottom part

334:頂部分 334: top part

335:頂面 335: top surface

337:側壁 337: side wall

339:側壁 339: side wall

340:第二電極 340: second electrode

340a:第二導電結構 340a: Second Conductive Structure

341:底面 341: Bottom

342:底部分 342: Bottom part

343:底面 343: Bottom

344:頂部分 344: top part

345:頂面 345: top surface

347:側壁 347: side wall

348:頂面 348: top surface

349:側壁 349: side wall

350:隔離結構 350: Isolation structure

351:側壁 351: side wall

360:第一介電層 360: the first dielectric layer

360a:介電層 360a: dielectric layer

370:第二介電層 370: second dielectric layer

375:層間介電層 375: interlayer dielectric layer

380:第一間隔件 380: first spacer

390:第二間隔件 390: second spacer

390a:間隔件 390a: spacer

400:導電接觸 400: conductive contact

400a:導電接觸 400a: Conductive contact

410:導電接觸 410: Conductive contact

420:導電接觸 420: conductive contact

420a:導電接觸 420a: Conductive contact

420b:導電接觸 420b: Conductive contact

A1:區塊 A1: block

A2:區塊 A2: block

C1:電容結構 C1: capacitor structure

C2:周邊元件 C2: peripheral components

T1:第一厚度 T1: first thickness

T2:第二厚度 T2: second thickness

5B-5B:線段 5B-5B: Line segment

Claims (10)

一種半導體元件，包含： 一基板； 一驅動電路層，位於該基板上； 一記憶體元件，位於該基板上，該記憶體元件包含： 交替堆疊的複數個導電層及複數個絕緣層； 複數個位元線，位於該些導電層及該些絕緣層上； 複數個通道層，穿過該些導電層及該些絕緣層，且該些通道層的每一者分別電性連接至該些位元線；以及 一階梯結構，位於該基板上，且該階梯結構電性連接該記憶體元件與該驅動電路層，其中該驅動電路層包含一電容結構，該電容結構包含： 該基板內的一摻雜部分； 一第一電極，位於該基板的該摻雜部分上，該第一電極具有一底部分與一頂部分，其中該第一電極的該底部分位於該基板的該摻雜部分內； 一第一介電層，位於該第一電極與該基板的該摻雜部分之間； 一第二電極，位於該第一電極上，其中該第二電極具有一底部分與一頂部分，該第二電極的該底部分嵌設於該第一電極，且該第二電極的該底部分的一底面在該基板的一頂面下方；以及 一第二介電層，位於該第一電極與該第二電極之間。 A semiconductor element comprising: a substrate; a driving circuit layer located on the substrate; A memory element is located on the substrate, and the memory element includes: a plurality of conductive layers and a plurality of insulating layers stacked alternately; a plurality of bit lines located on the conductive layers and the insulating layers; a plurality of channel layers passing through the conductive layers and the insulating layers, and each of the channel layers is electrically connected to the bit lines; and A ladder structure is located on the substrate, and the ladder structure is electrically connected to the memory element and the driving circuit layer, wherein the driving circuit layer includes a capacitor structure, and the capacitor structure includes: a doped portion within the substrate; a first electrode located on the doped portion of the substrate, the first electrode having a bottom portion and a top portion, wherein the bottom portion of the first electrode is located within the doped portion of the substrate; a first dielectric layer located between the first electrode and the doped portion of the substrate; A second electrode located on the first electrode, wherein the second electrode has a bottom portion and a top portion, the bottom portion of the second electrode is embedded in the first electrode, and the bottom portion of the second electrode a bottom surface of the portion is below a top surface of the substrate; and A second dielectric layer is located between the first electrode and the second electrode. 如請求項1所述之半導體元件，其中該第一電極比該第二電極寬。The semiconductor device according to claim 1, wherein the first electrode is wider than the second electrode. 如請求項1所述之半導體元件，其中該第一電極的一最高頂面的一部分被該第二電極覆蓋，且該第一電極的該最高頂面的其餘部分未被該第二電極覆蓋。The semiconductor device as claimed in claim 1, wherein a part of a highest top surface of the first electrode is covered by the second electrode, and the rest of the highest top surface of the first electrode is not covered by the second electrode. 如請求項1所述之半導體元件，其中該第二電極的一厚度大於該第一電極的一厚度。The semiconductor device as claimed in claim 1, wherein a thickness of the second electrode is greater than a thickness of the first electrode. 如請求項1所述之半導體元件，其中該電容結構更包含： 一第一摻雜區域與一第二摻雜區域，位於該基板內，且該基板的該摻雜部分更具有位於該第一摻雜區域與該第一電極之間的一區塊。 The semiconductor device as described in claim 1, wherein the capacitor structure further comprises: A first doped region and a second doped region are located in the substrate, and the doped portion of the substrate further has a region between the first doped region and the first electrode. 如請求項1所述之半導體元件，其中該第一介電層接觸該基板的該摻雜部分、該第一摻雜區域、該第二摻雜區域及該第一電極，以及該第二介電層接觸該第一電極及該第二電極。The semiconductor device as claimed in claim 1, wherein the first dielectric layer contacts the doped portion of the substrate, the first doped region, the second doped region and the first electrode, and the second dielectric layer The electrical layer is in contact with the first electrode and the second electrode. 如請求項1所述之半導體元件，其中該電容結構更包含： 一間隔件，位於該第二電極的該頂部分的側壁上且與該第二電極的該底部分分隔。 The semiconductor device as described in claim 1, wherein the capacitor structure further comprises: A spacer is located on the sidewall of the top portion of the second electrode and separated from the bottom portion of the second electrode. 一種半導體元件，包含： 一基板； 一驅動電路層，位於該基板上； 一記憶體元件，位於該基板上，該記憶體元件包含： 複數個導電層；以及 複數個通道層，垂直穿過該些導電層；以及 一階梯結構，位於該基板上，該階梯結構包含一第一導電接觸、一第二導電接觸與一互連結構，該第一導電接觸連接該互連結構與該驅動電路層，該第二導電接觸連接該互連結構與該記憶體元件的該些導電層的其中一者，其中該驅動電路層包含一電容結構，該電容結構包含： 該基板內的一摻雜部分； 一第一電極，位於該基板的該摻雜部分上，其中該第一電極的一最低底面在該基板的該摻雜部分的一最高頂面下方；以及 一第二電極，位於該第一電極上，其中該第一電極圍繞該第二電極，該第二電極的一最低底面在該第一電極的一最高頂面的下方，且該第一電極的該最高頂面與該第二電極的一最高頂面不重疊。 A semiconductor element comprising: a substrate; a driving circuit layer located on the substrate; A memory element is located on the substrate, and the memory element includes: a plurality of conductive layers; and a plurality of channel layers vertically passing through the conductive layers; and A ladder structure located on the substrate, the ladder structure includes a first conductive contact, a second conductive contact and an interconnection structure, the first conductive contact connects the interconnection structure and the driving circuit layer, the second conductive Contacting one of the conductive layers connecting the interconnection structure and the memory element, wherein the driving circuit layer includes a capacitor structure, and the capacitor structure includes: a doped portion within the substrate; a first electrode on the doped portion of the substrate, wherein a lowest bottom surface of the first electrode is below a highest top surface of the doped portion of the substrate; and a second electrode located on the first electrode, wherein the first electrode surrounds the second electrode, a lowest bottom surface of the second electrode is below a highest top surface of the first electrode, and a The highest top surface does not overlap with a highest top surface of the second electrode. 如請求項8所述之半導體元件，其中該電容結構更包含： 一第一介電層，位於該基板的該摻雜部分與該第一電極之間；以及 一第二介電層，位於該第一電極與該第二電極之間。 The semiconductor device as claimed in item 8, wherein the capacitor structure further comprises: a first dielectric layer between the doped portion of the substrate and the first electrode; and A second dielectric layer is located between the first electrode and the second electrode. 如請求項9所述之半導體元件，其中該電容結構更包含： 一第三介電層，位於該第二電極上，且該第三介電層與該第一介電層分隔。 The semiconductor device as claimed in item 9, wherein the capacitor structure further comprises: A third dielectric layer is located on the second electrode, and the third dielectric layer is separated from the first dielectric layer.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1018769A2 (en) * 1998-12-03 2000-07-12 Lucent Technologies Inc. Semiconductor device with increased gate insulator lifetime
TW201926652A (en) * 2017-11-21 2019-07-01 大陸商長江存儲科技有限責任公司 Three-dimensional memory device and fabrication method thereof
US20210098029A1 (en) * 2019-10-01 2021-04-01 Sandisk Technologies Llc Three-dimensional memory device including contact-level bit-line-connection structures and methods of making the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1018769A2 (en) * 1998-12-03 2000-07-12 Lucent Technologies Inc. Semiconductor device with increased gate insulator lifetime
TW201926652A (en) * 2017-11-21 2019-07-01 大陸商長江存儲科技有限責任公司 Three-dimensional memory device and fabrication method thereof
US20210098029A1 (en) * 2019-10-01 2021-04-01 Sandisk Technologies Llc Three-dimensional memory device including contact-level bit-line-connection structures and methods of making the same

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