TWI785934B - 天線整合式封裝結構及其製造方法 - Google Patents
天線整合式封裝結構及其製造方法 Download PDFInfo
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Abstract
一種天線整合式封裝結構,其包括晶片、線路結構、遮
蔽體、密封體、第一天線層、介電體以及第二天線層。線路結構電性連接於晶片。遮蔽體位於線路結構上且具有容置空間。晶片位於遮蔽體的容置空間內。密封體位於線路結構上且包覆晶片。第一天線層位於線路結構上且電性連接於線路結構。介電體位於密封體上。第二天線層位於介電體上。一種天線整合式封裝結構的製造方法亦被提供。
Description
本發明是有關於一種封裝結構及其製造方法,且特別是有關於一種天線整合式封裝結構及其製造方法。
隨著科技進步,電子產品的功能越來越豐富,例如是目前的行動通訊裝置,為了在一台行動通訊裝置中配置不同功能的電子元件,各個電子元件的尺寸都要很小,才有辦法將所有電子元件都配置於符合輕、薄概念的行動通訊裝置中。
現有的電子元件中的天線與晶片封裝結構分開,且天線需藉由電路板上的線路而與封裝結構中的晶片電性連接,導致整個電子元件的體積難以縮小,因此,目前亟需一種解決上述問題的方法。
本發明提供一種天線整合式封裝結構及其製造方法,其體積可以較小且具有較佳的品質。
本發明的天線整合式封裝結構包括晶片、線路結構、遮蔽體、密封體、第一天線層、介電體以及第二天線層。線路結構電性連接於晶片。遮蔽體位於線路結構上且具有容置空間。晶片位於遮蔽體的容置空間內。密封體位於線路結構上且包覆晶片。第一天線層位於線路結構上且電性連接於線路結構。介電體位於密封體上。第二天線層位於介電體上。
本發明的天線整合式封裝結構的製造方法包括以下步驟:形成線路結構;配置晶片於線路結構上,以與線路結構電性連接;形成遮蔽體於線路結構上,其中遮蔽體具有容置空間,且晶片位於遮蔽體的容置空間內;形成密封體於線路結構上,以包覆晶片;形成第一天線層於線路結構,以與線路結構電性連接;形成介電體於密封體上;以及形成第二天線層於介電體上。
基於上述,本發明的天線整合式封裝結構及其製造方法,可以使其體積可以較小且具有較佳的品質。
100、200、300:天線整合式封裝結構
110:晶片
110a:主動面
110b:背面
111:連接墊
112:導電凸塊
113:鈍化層
120:線路結構
121、123:導電層
122:絕緣層
130:遮蔽體
131:容置空間
134:導電件或第一導電部分
135:第二導電部分
140、142、142a、142b、142c:導電件
140b:上表面
148:支撐件
150:導電層
156、356:第一天線層
177:介電體
160:導電層
165:遮蔽層
166:第二天線層
174:密封體
174a、174b:密封表面
180:導電端子
183:接地端子
91:載板
92:離型層
圖1A至圖1F是依照本發明的第一實施例的一種天線整合式封裝結構的部分製造方法的部分剖視示意圖。
圖1G是依照本發明的第一實施例的一種天線整合式封裝結構的部分上視示意圖。
圖2是依照本發明的第二實施例的一種天線整合式封裝結構
的部分製造方法的部分剖視示意圖。
圖3是依照本發明的第三實施例的一種天線整合式封裝結構的部分製造方法的部分剖視示意圖。
除非另有明確說明,本文所使用之方向用語(例如,上、下、左、右、前、後、頂部、底部)僅作為參看所繪圖式使用且不意欲暗示絕對定向。
除非另有明確說明,否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。
參照本實施例之圖式以更全面地闡述本發明。然而,本發明亦可以各種不同的形式體現,而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件,以下段落將不再一一贅述。
圖1A至圖1F是依照本發明的第一實施例的一種晶片封裝結構的部分製造方法的部分剖視示意圖。
請參照圖1A,形成線路結構120於載板91上。本發明對於載板91並無特別的限制,只要載板91可以適於承載形成於其上膜層或配置於其上的元件即可。
在一實施例中,載板91上可以具有離型層92,但本發明不限於此。離型層92可以包括光熱轉換(light to heat conversion;
LTHC)黏著層或其他適宜的膜層。
在本實施例中,線路結構120可以包括絕緣層122以及導電層121。導電層121可以構成對應的線路。線路的佈線設計(layout design)可以依據需求而加以調整,於本發明並不加以限制。舉例而言,於線路結構120的線路中,在圖式上未相連的部分可能會藉由其他未繪示處及/或其他的導電元件而加以電性連接。
在本實施例中,線路結構120可以藉由一般常用的半導體製程(如:沉積製程、微影製程及/或蝕刻製程)形成,故於此不加以贅述。
在一實施例中,線路結構120可以被稱為重佈線路結構,但本發明不限於此。
在一實施例中,最頂的導電層123(即,導電層121中最遠離載板91的該層)可以位於最頂的絕緣層122上,且最頂的導電層123中的一部分可以嵌入最頂的絕緣層122。
在一未繪示的實施例中,最頂的絕緣層122可以具有多個開口,且開口可以暴露出最遠離載板91的導電層121。
請繼續參照圖1A,形成導電件140於線路結構120上。至少部分的導電件140可以電性連接於最頂的導電層123中對應的部分。導電件140可以包括柱狀導電件142及框型導電件134。在一實施例中,框型導電件134可以包括框型區及從前述框型區向外延伸的其他區域。換句話說,框型導電件134只要具有可使
一物件(如:類似於後續圖1B中所述的晶片110;但不限)可置於其內的區域即可,本發明對於框型導電件134的外觀並未加以特別的限制。
在一實施例中,導電件140可以包括預先成型(pre-formed)的導電件。舉例而言,導電件140可以包括預先成型的導電柱(pre-formed conductive pillar)或預先成型的導電框(pre-formed conductive frame),但本發明不限於此。
在一實施例中,導電件140可以藉由一般常用的半導體製程(如:微影製程、濺鍍製程、電鍍製程及/或蝕刻製程)形成,但本發明不限於此。在一實施例中,導電件140可以包括鍍覆核心層(plating core layer)及種子層(seed layer),但本發明不限於此。種子層可以位於最頂的導電層123與前述的鍍覆核心層之間。在一實施例中,種子層可能更可以環繞鍍覆核心層,但本發明不限於此。
請參照圖1B,配置晶片110於線路結構120上。晶片110的一側具有元件區(未繪示),而元件區所位於的表面可以被稱為主動面110a,且相對於主動面110a的另一表面可以被稱為背面110b。晶片110以其主動面110a面向線路結構120的方式配置於線路結構120上。且晶片110中對應的元件可以與線路結構120中對應的線路電性連接。
在本實施例中,可以如圖1A所繪示地先形成導電件140,然後,如圖1B所繪示地配置晶片110。
在一未繪示的實施例中,可以先配置晶片110,然後,形成導電件140。
值得注意的是,若在將晶片110配置於線路結構120上之前,晶片110的背面110b上具有適宜的膜、層及/或元件,則可被視為晶片110的一部分。
請參照圖1C,在形成導電件140及配置晶片110之後,形成密封體174於載板91上。密封體174至少直接覆蓋晶片110的背面110b,且密封體174暴露出導電件140。
密封體174具有第一密封表面174a及第二密封表面174b。第二密封表面174b相對於第一密封表面174a。密封體174的第一密封表面174a面向線路結構120。密封體174可以完全覆蓋晶片110的整個背面110b及整個側面110c,但本發明不限於此。
舉例而言,可以於載板91上形成模封材料。並且,在將模封材料固化之後,可以進行平整化製程。於進行平整化製程之後,密封體174可以暴露出導電件140。換句話說,密封體174的第二密封表面174b可以與導電件140的上表面140b(即,導電件140最遠離線路結構120的表面)共面(coplanar)。在前述的平整化製程中,部分固化的模封材料及/或部分的導電件140可以被些微地移除。
在本實施例中,部分的密封體174可以位於晶片110及線路結構120之間。舉例而言,晶片110可以藉由對應的導電凸塊112而與線路結構120中對應的線路電性連接,且位於晶片110
及線路結構120之間的部分密封體174可以覆蓋導電凸塊112。也就是說,密封體174的第一密封表面174a可以不與晶片110的主動面110a、晶片110上的連接墊(contact pad)111(如:晶片墊(die pad))及/或晶片110上的鈍化層(passivation layer)113共面,但本發明不限於此。
請繼續參照圖1C,在本實施例中,在形成密封體174之後,可以在密封體174的第二密封表面174b上形成導電層150。導電層150可以包括第一天線層156及異於前述第一天線層156的導電部分135。導電層150可以藉由一般常用的半導體製程(如:沉積製程、微影製程及/或蝕刻製程;或,網印(screen printing))形成,於本發明並不加以限定。
第一天線層156的天線圖案(antenna pattern)可以依據設計上的需求而加以調整,於本發明並不加以限定。
前述的導電部分135(可被稱為:第二導電部分135)與框型導電件134(可被稱為:第一導電部分134)可以電性連接(或;進一步地直接接觸),而可以構成遮蔽體130。
在本實施例中,導電層150的底面、密封體174的第二密封表面174b及導電件140的上表面140b可以共面(coplanar)。換句話說,導電層150可以直接接觸密封體174中對應的一部分及/或對應的導電件140。也就是說,在垂直於第一密封表面174a或第二密封表面174b的一方向上,導電層150與密封體174之間基本上不具有其他的物質,且/或導電層150與導電件140之間基
本上不具有其他的物質。如此一來,對應的製程可以較為簡單。
在本實施例中,在垂直於第一密封表面174a或第二密封表面174b的一方向上,晶片110的整個背面110b與第二導電部分135之間可以僅具有位於其之間的密封體174。藉由上述的製程,位於晶片110與第二導電部分135之間的部分密封體174已足以提供良好的保護及/或分隔。如此一來,可以省略位於晶片110與第二導電部分135之間的其他物質或膜層(如:晶片黏著膜(Die Attach Film;DAF)),而可以對應地降低結構的厚度;且/或製程上較為簡單。
請參照圖1D,在形成密封體174及導電層150之後,於密封體174上形成介電體177。
在本實施例中,可以於密封體174上塗佈半固化的介電材料。並且,在將介電材料固化之後,可以形成對應的介電體177。介電材料可以包括高分子材料(如:聚酰亞胺(polyimide;PI)),但本發明並不加以限定。
在一未繪示的實施例中,可以於密封體174上配置固化或固態的介電體(如:玻璃、高分子板或高分子膜;但不限)。前述固化或固態的介電體與密封體174之間可以藉由絕緣的黏著材而彼此連接,而對應地構成介電體177。
請繼續參照圖1D,在形成介電體177之後,可以在介電體177上形成導電層160。導電層160至少可以包括第二天線層166。導電層160可以藉由一般常用的半導體製程(如:沉積製程、
微影製程及/或蝕刻製程;或,網印(screen printing))形成,於本發明並不加以限定。
在本實施例中,導電層160可以包括第二天線層166及遮蔽層165。
請參照圖1E,於形成導電層160之後,可以移除載板91。
請參照圖1E至圖1F,可以對如1E中所繪示的結構進行單一化製程(singulation process/dicing process)或其他適宜的製程,以形成多個如1F中所繪示的天線整合式封裝結構100。前述的單一化製程至少是對線路結構120、密封體174及/或介電體177進行切割。
值得注意的是,在進行單一化製程之後,相似的元件符號將用於單一化後的元件。舉例而言,晶片110(如圖1E所示)於單一化後可以為晶片110(如圖1F所示),線路結構120(如圖1E所示)於單一化後可以為線路結構120(如圖1F所示),密封體174(如圖1E所示)於單一化後可以為密封體174(如圖1F所示),介電體177(如圖1E所示)於單一化後可以為介電體177(如圖1F所示),諸如此類。其他單一化後的膜、層或元件將依循上述相同的元件符號規則,於此不加以贅述或特別繪示。
值得注意的是,於本實施例中,是先移除載板91,然後,進行形成多個天線整合式封裝結構100的單一化製程或其他適宜的製程。在一未繪示的實施例中,可以先對載板91上的結構進行單一化製程,然後,於移除載板91後才形成多個天線整合式封裝
結構100。
請參照圖1F,在本實施例中,於移除載板91後,可以於線路結構120上形成多個導電端子180,以形成對應的天線整合式封裝結構100。
於一實施例中,可以是先移除載板91,然後,形成多個導電端子180,然後,進行單一化製程。在一實施例中,可以先進行單一化製程,然後,移除載板91,然後,形成多個導電端子180。
經過上述製程後即可大致上完成本實施例之天線整合式封裝結構100的製作。
圖1F可以是依照本發明的第一實施例的一種晶片110封裝結構的部分剖視示意圖。圖1G可以是依照本發明的第一實施例的一種晶片110封裝結構的部分上視示意圖。舉例而言,圖1F可以是對應於圖1G中I-I’剖線上的剖視示意圖。另外,為求清楚表示,圖1G僅繪示的部分的膜層或構件。舉例而言,圖1G僅示例性地繪示了介電體177、遮蔽層165或第二天線層166;以及,以透視的方式繪示了晶片100、第一導電部分134、導電件142或支撐件148。
請參照圖1F及圖1G,天線整合式封裝結構100包括晶片110、線路結構120、遮蔽體130、密封體174、第一天線層156、介電體177以及第二天線層166。晶片110電性連接於線路結構120中對應的線路。遮蔽體130位於線路結構120上。遮蔽體130具有容置空間131。晶片110位於遮蔽體130的容置空間131內。
密封體174位於線路結構120上。密封體174包覆晶片110。第一天線層156位於線路結構120上。第一天線層156中對應的天線電性連接於線路結構120中對應的線路。介電體177位於密封體174的第二密封表面174b上。第二天線層166位於介電體177上。
在本實施例中,遮蔽體130可以包括第一導電部分134以及第二導電部分135。第一導電部分134與第二導電部分135構成容置空間131。第一導電部分134貫穿密封體174且圍繞晶片110。第二導電部分135位於密封體174的第二密封表面174b上。於垂直於第一密封表面174a或第二密封表面174b的一方向上(如:圖1G所示),第二導電部分135重疊於晶片110。如此一來,可以降低晶片110與天線之間的干擾。
在一實施例中,遮蔽體130可以接地。前述的接地可以包括浮動接地(floating ground)或物理性接地(physical ground)。舉例而言,遮蔽體130可以藉由線路結構120中的接地線路(ground circuit)及接地端子183(導電端子180的其中一個)而接地。
在一實施例中,第一導電部分134於第一密封表面174a或第二密封表面174b上的投影位於第二導電部分135於第一密封表面174a或第二密封表面174b上的投影內。如此一來,可以具有較佳的製程裕度(process window)。
在本實施例中,天線整合式封裝結構100可以更包括柱狀的導電連接件142。導電連接件142貫穿密封體174。第一天線
層156中對應的天線可以藉由對應的導電連接件142電性連接於線路結構120中對應的線路。
在一實施例中,遮蔽體130的第一導電部分134與導電連接件142可以是藉由相同的製程所形成。也就是說,第一導電部分134的材質基本上相同於導電連接件142的材質,且第一導電部分134的厚度142基本上相同於導電連接件的厚度142。
在一實施例中,若第一天線層156中具有多個彼此電分離的天線,則在平行於第一密封表面174a或第二密封表面174b的一方向上,遮蔽體130位於前述的多個天線之間。舉例而言,遮蔽體130的第二導電部分135位於前述的多個天線之間。如此一來,可以降低多個天線彼此之間的干擾,而可以提升天線整合式封裝結構100的應用及/或對應的訊號品質。
在一實施例中,若第一天線層156中具有多個彼此電分離的天線,則在平行於第一密封表面174a或第二密封表面174b的一方向上,遮蔽體130位於用於連接前述的多個天線的導電連接件142之間。舉例而言,遮蔽體130的第二導電部分134位於用於連接前述的多個天線的導電連接件142之間。又舉例而言,遮蔽體130位於導電連接件142a與導電連接件142b之間,遮蔽體130位於導電連接件142b與導電連接件142c之間,且/或遮蔽體130位於導電連接件142a與導電連接件142c之間。如此一來,可以降低多個天線之間的干擾,而可以提升天線整合式封裝結構100的應用及/或對應的訊號品質。
在本實施例中,第二天線層166的天線圖案可以對應於第一天線層156的天線圖案。也就是說,於垂直於第一密封表面174a或第二密封表面174b的一方向上,第二天線層166的天線圖案不與晶片110重疊;或是,更進一步地,第二天線層166的天線圖案更不與遮蔽體130重疊。如此一來,可以降低天線與晶片110之間的干擾,而可以提升天線整合式封裝結構100的應用及/或對應的訊號品質。
在一實施例中,第一天線層156中對應的天線可以與第二天線層166中對應的天線耦合(coupling),且前述相耦合的天線之間並沒有電性連接。在一示例性的應用方式中,第一天線層156中對應的一天線可以為被勵天線(driven antenna),且第二天線層166中對應的一天線可以為寄生天線(parasitic antenna),但本發明不限於此。
在本實施例中,天線整合式封裝結構100可以更包括遮蔽層165。遮蔽層165位於介電體177上。於垂直於第一密封表面174a或第二密封表面174b的一方向上,遮蔽層165重疊於晶片110。如此一來,可以降低外界電磁波對晶片110的干擾。
在一實施例中,遮蔽層165的圖案可以重疊或對應於第二導電部分135的圖案。如此一來,可以提升遮蔽層165的遮蔽品質。
在一實施例中,如圖1G所示,晶片110於第一密封表面174a或第二密封表面174b上的投影位於遮蔽層165於第一密封表
面174a或第二密封表面174b上的投影內,且晶片110於第一密封表面174a或第二密封表面174b上的投影完全重疊遮蔽層165於第一密封表面174a或第二密封表面174b上的投影內。如此一來,可以降低外界電磁波對晶片110的干擾。
在一實施例中,若第二天線層166中具有多個彼此電分離的天線,則在平行於第一密封表面174a或第二密封表面174b的一方向上,遮蔽層165位於前述的多個天線之間。如此一來,可以降低多個天線之間的干擾,而可以提升天線整合式封裝結構100的應用及/或對應的訊號品質。
在一實施例中,遮蔽層165可以接地,但本發明不限於此。舉例而言,遮蔽層165可以浮動接地。
在一實施例中,就電性上而言,遮蔽層165與第二導電部分135彼此之間並沒有電性連接。在一實施例中,就結構上而言,遮蔽層165與第二導電部分135之間並沒有任何的導電物質。
在一實施例中,遮蔽層165的寬度(即,在垂直於遮蔽層165具有最大尺寸方向上的另一尺寸)大於第二天線層166中任意天線的寬度(即,在垂直於該天線延伸方向上的尺寸)。如此一來,藉由上述的圖案設計方式(如:調整遮蔽層165的寬度)較為簡單,且可以省略其他的構件及/或製程(如:不需使遮蔽層165與天線整合式封裝結構100中其他的導體電性連接而接地),但仍可能可以提升遮蔽層165的整體電荷容量,而可能使遮蔽層165具有良好的遮蔽效果。
在一實施例中,遮蔽層165於介電體177的表面上的投影面積大於第二天線層166於介電體177的前述表面上的投影面積。如此一來,可能可以提升遮蔽層165的整體電荷容量,而可能使遮蔽層165具有良好的遮蔽效果。
在本實施例中,天線整合式封裝結構100可以更包括支撐件148。支撐件148可以貫穿密封體174。支撐件148的材質、外觀及/或製作方式可以相同於導電連接件142,差別在於:於垂直於第一密封表面174a或第二密封表面174b的一方向上,支撐件148可以不重疊於第一天線層156及/或第二天線層166。
支撐件148的配置處或對應的數量可以依據設計上的需求而加以調整,於本發明並不加以限定。舉例而言,支撐件148可以被配置於導電連接件142較稀疏處。除此一來,在天線整合式封裝結構100的製造過程中及/或應用上,可以使對應的結構或其對應的應力承受上具有較佳的平衡。
在一實施例中,支撐件148對於天線整合式封裝結構100的訊號處理或訊號傳輸上可以是虛設構件(dummy component)。也就是說,支撐件148基本上可以不參與訊號處理或訊號傳輸。
值得注意的是,本發明並未限定支撐件148不與任何的導體電性連接。舉例而言,在一未直接繪示的實施例中,支撐件148可以藉由線路結構120中對應的線路電性連接於遮蔽體130。如此一來,可以提升遮蔽體130及電性連接於其的導體(如:導電件140及/或支撐件148)的整體電荷容量。
圖2是依照本發明的第二實施例的一種天線整合式封裝結構的部分製造方法的部分剖視示意圖。本實施例的天線整合式封裝結構200的製造方法與天線整合式封裝結構100的製造方法相似,其類似的構件以相同的標號表示,且具有類似的功能、材質或形成方式,並省略描述。
請參照圖2,天線整合式封裝結構200與天線整合式封裝結構100的一差異在於:天線整合式封裝結構200可以不具有相同或相似於前述遮蔽層165的遮蔽層(因無,故無繪示或標示)。
圖3是依照本發明的第三實施例的一種天線整合式封裝結構的部分製造方法的部分剖視示意圖。本實施例的天線整合式封裝結構300的製造方法與天線整合式封裝結構100的製造方法相似,其類似的構件以相同的標號表示,且具有類似的功能、材質或形成方式,並省略描述。
請參照圖3,天線整合式封裝結構300包括晶片110、線路結構120、遮蔽體130、密封體174、第一天線層356、介電體177以及第二天線層166。第一天線層356位於線路結構120上。第一天線層356中對應的天線電性連接於線路結構120中對應的線路。
在本實施例中,密封體174可以位於第一天線層356與介電體177之間。
在一實施例中,於線路結構120中,最頂的絕緣層122(如:最接近密封體174的一絕緣層122)可以具有多個開口,最
頂的導電層123的一部分可以嵌入於前述的開口內。線路結構120中最頂的導電層123(如:最接近密封體174的一導電層121)的一部分可以構成第一天線層356,但本發明不限於此。
綜上所述,本發明的天線整合式封裝結構及其製造方法,其體積可以較小且具有較佳的品質。
100:天線整合式封裝結構
110:晶片
110a:主動面
110b:背面
120:線路結構
121、123:導電層
122:絕緣層
130:遮蔽體
131:容置空間
134:導電件或第一導電部分
135:第二導電部分
142:導電件
156:第一天線層
177:介電體
165:遮蔽層
166:第二天線層
174:密封體
174a、174b:密封表面
180:導電端子
183:接地端子
Claims (8)
- 一種天線整合式封裝結構,包括:晶片;線路結構,電性連接於所述晶片;遮蔽體,位於所述線路結構上且具有容置空間,其中所述晶片位於所述遮蔽體的所述容置空間內;密封體,位於所述線路結構上且包覆所述晶片,其中所述遮蔽體包括:第一導電部分,貫穿所述密封體且圍繞所述晶片;以及第二導電部分,位於所述密封體上且重疊於所述晶片,其中所述第一導電部分與所述第二導電部分電性連接,且所述第一導電部分與所述第二導電部分構成所述容置空間;第一天線層,位於所述線路結構上且電性連接於所述線路結構;介電體,位於所述密封體上;以及第二天線層,位於所述介電體上,其中所述第一天線層與所述第二導電部分為相同的膜層。
- 一種天線整合式封裝結構,包括:晶片;線路結構,電性連接於所述晶片;遮蔽體,位於所述線路結構上且具有容置空間,其中所述晶片位於所述遮蔽體的所述容置空間內; 密封體,位於所述線路結構上且包覆所述晶片,其中所述遮蔽體包括:第一導電部分,貫穿所述密封體且圍繞所述晶片;以及第二導電部分,位於所述密封體上且重疊於所述晶片,其中所述第一導電部分與所述第二導電部分電性連接,且所述第一導電部分與所述第二導電部分構成所述容置空間;第一天線層,位於所述線路結構上且電性連接於所述線路結構;介電體,位於所述密封體上;第二天線層,位於所述介電體上;以及導電連接件,貫穿所述密封體,其中:所述第一天線層藉由所述導電連接件電性連接至所述線路結構;且所述第一導電部分的材質與厚度相同於所述導電連接件的材質與厚度。
- 如請求項2所述的天線整合式封裝結構,更包括:支撐件,貫穿所述密封體,其中所述支撐件的材質與厚度相同於所述導電連接件的材質與厚度。
- 如請求項1或2所述的天線整合式封裝結構,其中所述密封體位於所述第一天線層與所述介電體之間。
- 如請求項1或2所述的天線整合式封裝結構,更包括:遮蔽層,位於所述介電體上且重疊於所述晶片,其中所述遮 蔽層與所述第二天線層為相同的膜層。
- 如請求項5所述的天線整合式封裝結構,其中所述第二天線層包括彼此電分離的第一天線區及第二天線區,且所述遮蔽層位於所述第一天線區與所述第二天線區之間。
- 如請求項5所述的天線整合式封裝結構,其中所述遮蔽層接地。
- 一種天線整合式封裝結構的製造方法,包括:形成線路結構;配置晶片於所述線路結構上,以與所述線路結構電性連接;形成遮蔽體於所述線路結構上,其中所述遮蔽體具有容置空間,且所述晶片位於所述遮蔽體的所述容置空間內;形成密封體於所述線路結構上,以包覆所述晶片,其中所述遮蔽體包括:第一導電部分,且於形成所述遮蔽體及所述密封體後,所述第一導電部分貫穿所述密封體且圍繞所述晶片;以及第二導電部分,且於形成所述遮蔽體及所述密封體後,所述第二導電部分位於所述密封體上且重疊於所述晶片,其中所述第一導電部分與所述第二導電部分電性連接,且所述第一導電部分與所述第二導電部分構成所述容置空間;形成第一天線層於所述線路結構上,以與所述線路結構電性連接;形成介電體於所述密封體上;以及 形成第二天線層於所述介電體上,其中:所述第一天線層與所述第二導電部分為相同的膜層;或所述的天線整合式封裝結構更包括貫穿所述密封體的導電連接件,其中所述第一天線層藉由所述導電連接件電性連接至所述線路結構,且所述第一導電部分的材質與厚度相同於所述導電連接件的材質與厚度。
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TWM515702U (zh) * | 2015-05-22 | 2016-01-11 | Smart Approach Co Ltd | 天線模組 |
US20180277457A1 (en) * | 2015-12-04 | 2018-09-27 | Murata Manufacturing Co., Ltd. | Shielded module |
US20210242593A1 (en) * | 2018-12-14 | 2021-08-05 | Samsung Electro-Mechanics Co., Ltd. | Antenna module and electronic device including the same |
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TWM515702U (zh) * | 2015-05-22 | 2016-01-11 | Smart Approach Co Ltd | 天線模組 |
US20180277457A1 (en) * | 2015-12-04 | 2018-09-27 | Murata Manufacturing Co., Ltd. | Shielded module |
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