TWI785864B - 半導體基板以及電晶體 - Google Patents
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Abstract
一種半導體基板以及電晶體。所述半導體基板包括基底、絕緣層、半導體層、寬能隙擴散緩衝層以及成核層。所述絕緣層設置於所述基底上。所述半導體層設置於所述絕緣層上。所述寬能隙擴散緩衝層設置於所述半導體層上，其中所述寬能隙擴散緩衝層的能隙高於2.5 eV。所述成核層設置於所述寬能隙擴散緩衝層上，其中所述成核層包括含鋁層。
Description
本發明是有關於一種半導體元件，且特別是有關於一種半導體基板以及包括所述半導體基板的電晶體。
為了使功率元件能夠具有低導通電阻、高切換頻率、高崩潰電壓及高溫操作等性能，氮化鎵（GaN）半導體元件為目前高功率元件所矚目的選擇。
本發明提供一種半導體基板，其中寬能隙擴散緩衝層設置於成核層與半導體層之間。
本發明提供一種電晶體，其包括上述的半導體基板。
本發明的半導體基板包括基底（base）、絕緣層、半導體層、寬能隙擴散緩衝層以及成核層。所述絕緣層設置於所述基底上。所述半導體層設置於所述絕緣層上。所述寬能隙擴散緩衝層設置於所述半導體層上，其中所述寬能隙擴散緩衝層的能隙高於2.5 eV。所述成核層設置於所述寬能隙擴散緩衝層上，其中所述成核層包括含鋁層。
本發明的電晶體包括半導體基板、通道層、阻障層、閘極、源極以及汲極。所述半導體基板包括基底、絕緣層、半導體層、寬能隙擴散緩衝層以及成核層。所述絕緣層設置於所述基底上。所述半導體層設置於所述絕緣層上。所述寬能隙擴散緩衝層設置於所述半導體層上，其中所述寬能隙擴散緩衝層的能隙高於2.5 eV。所述成核層設置於所述寬能隙擴散緩衝層上，其中所述成核層包括含鋁層。所述通道層設置於所述成核層上。所述阻障層設置於所述通道層上。所述閘極設置於所述阻障層上。所述源極和汲極設置於所述阻障層上且分別位於所述閘極的相對兩側。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合附圖作詳細說明如下。
下文列舉實施例並配合附圖來進行詳細地說明，但所提供的實施例並非用以限制本發明所涵蓋的範圍。此外，附圖僅以說明為目的，並未依照原尺寸作圖。為了方便理解，在下述說明中相同的元件將以相同的符號標示來說明。
關於本文中所提到「包含」、「包括」、「具有」等的用語均為開放性的用語，也就是指「包含但不限於」。
當以「第一」、「第二」等的用語來說明元件時，僅用於將這些元件彼此區分，並不限制這些元件的順序或重要性。因此，在一些情況下，第一元件亦可稱作第二元件，第二元件亦可稱作第一元件，且此不偏離本發明的範疇。
此外，在本文中，由「一數值至另一數值」表示的範圍是一種避免在說明書中逐一列舉所述範圍中的所有數值的概要性表示方式。因此，某一特定數值範圍的記載涵蓋了所述數值範圍內的任意數值，以及涵蓋由所述數值範圍內的任意數值界定出的較小數值範圍。
圖1A至圖1B為本發明的實施例的半導體基板的製造流程剖面示意圖。首先，參照圖1A，提供複合基底100。在本實施例中，複合基底100包括基底100a、絕緣層100b以及半導體層100c。基底100a的材料例如為矽、氮化鋁、碳化矽（SiC）、藍寶石（sapphire）或其組合。絕緣層100b設置於基底100a上。絕緣層100b例如為氧化矽層，但本發明不限於此。絕緣層100b的厚度例如介於100 nm至200 nm之間。半導體層100c設置於絕緣層100b上。半導體層100c例如為矽層、碳化矽層或其組合。半導體層100c的厚度例如介於30 nm至3 μm之間，較佳介於70 nm至200 m之間。換句話說，在本實施例中，複合基底100可為一般熟知的絕緣體上覆矽（silicon-on-insulator，SOI）基底或QST基底，其具有高阻值而特別適用於高頻元件。在本實施例中，基底100a可具有大於1.4 W/cm·K的熱傳導係數，因此複合基底100除了可作為支撐基底之外，還可作為散熱基底。
接著，於複合基底100的半導體層100c上形成寬能隙擴散緩衝層102。在本實施例中，寬能隙擴散緩衝層102的能隙高於2.5 eV，較佳是介於3.2 eV至9.1 eV之間，更佳是介於4.5 eV至5.5 eV之間。寬能隙擴散緩衝層102例如為氮化矽層、氧化矽層、氧化鋅層、氧化鋁層、氧化鎵層或其組合。在本實施例中，寬能隙擴散緩衝層102可為非晶形（amorphous）層，例如非晶氮化矽層。在本實施例中，寬能隙擴散緩衝層102的厚度介於30 nm至120 nm之間，較佳是介於35 nm至100 nm之間，更佳是介於40 nm至90 nm之間。在本實施例中，寬能隙擴散緩衝層102的形成方法例如是進行電漿增強化學氣相沉積（plasma-enhanced chemical vapor deposition，PECVD）製程、電子槍蒸鍍（E-gun evaporation）製程或濺鍍沉積（sputtering deposition）製程。此外，在本實施例中，寬能隙擴散緩衝層102可具有介於1×10
4ohm·cm至1×10
14ohm·cm之間的電阻值。
之後，參照圖1B，於寬能隙擴散緩衝層102上形成成核層104，以製成本實施例的半導體基板10。在本實施例中，成核層104為含鋁層，例如氮化鋁層，但本發明不限於此。
一般來說，當成核層104在高溫製程中形成時，成核層104中所含的鋁會擴散至下方的膜層中。鋁擴散至半導體層100c中會形成P型摻雜的導電層。在本實施例中，由於複合基底100的半導體層100c與成核層104之間形成有寬能隙擴散緩衝層102，因此在高溫製程中成核層104中的鋁會擴散到寬能隙擴散緩衝層102中。當寬能隙擴散緩衝層102的厚度接近鋁擴散的深度時，可避免成核層104中所含的鋁擴散至半導體層100c中而形成P型摻雜的導電層，進而避免所形成的半導體元件在運作時在複合基底100處產生漏電現象。在本實施例中，寬能隙擴散緩衝層102的厚度大於鋁擴散的深度，因此可確實避免成核層104中所含的鋁擴散至半導體層100c中。此外，因為寬能隙擴散緩衝層102的能隙高於2.5 eV，所以即使鋁擴散到寬能隙擴散緩衝層102中也不會形成P型摻雜的導電層。
此外，在本實施例中，寬能隙擴散緩衝層102的材料可為非晶形的，相較於單晶形材料，非晶形的寬能隙擴散緩衝層102可有效地降低成核層104中所含的鋁擴散至半導體層100c中的速度以及鋁擴散至寬能隙擴散緩衝層102中的深度。一般來說，鋁擴散的深度介於50 nm至100 nm之間。寬能隙擴散緩衝層102能降低鋁擴散的速度和深度，使鋁擴散的深度減少至介於40 nm到90 nm之間。在最佳的情況，寬能隙擴散緩衝層102的厚度可設計為40 nm到90 nm，以避免鋁擴散至半導體層100c中。
在本實施例中，在形成成核層104的過程中或在後續的高溫製程中，成核層104中所含的鋁會擴散至寬能隙擴散緩衝層102中，因此形成了擴散層104a。如圖1B所示，在本實施例中，成核層104中所含的鋁僅擴散至寬能隙擴散緩衝層102的上部中，使得擴散層104a形成於鄰近寬能隙擴散緩衝層102的上表面處，但本發明不限於此。在其他實施例中，成核層104中所含的鋁可能擴散至整個寬能隙擴散緩衝層102中，亦即擴散層104a的厚度可實質上等於寬能隙擴散緩衝層102的厚度。
圖2為本發明的實施例的半導體基板中鋁離子濃度與鋁離子擴散深度的關係圖。參照圖2，半導體基板10的成核層104上形成有緩衝層200（例如為AlGaN層），且寬能隙擴散緩衝層102與成核層104依序設置於半導體層100c上。在高溫製程中，成核層104中所含的鋁會向上擴散至緩衝層200中以及向下擴散至寬能隙擴散緩衝層102中。當成核層104中所含的鋁擴散至寬能隙擴散緩衝層102中之後，寬能隙擴散緩衝層102中的鋁濃度會呈梯度分佈。也就是說，在寬能隙擴散緩衝層102中，鋁會相對大量地累積在寬能隙擴散緩衝層102中鄰近表面的部分，且隨著擴散深度增加鋁濃度大幅降低，使得寬能隙擴散緩衝層102中鄰近成核層104的部分的鋁濃度會大於遠離成核層104的部分的鋁濃度。此外，由於寬能隙擴散緩衝層102可減少（甚至避免）成核層104中所含的鋁擴散至半導體層100c中，因此即使當成核層104中所含的鋁穿透寬能隙擴散緩衝層102而擴散至半導體層100c中時，半導體層100c中僅會含有相當微量的鋁。此時，鋁含量例如小於10
17atom/cm
3，甚至可接近0。如此一來，當半導體基板10用來作為電晶體、發光二極體或其他電子元件的基板時，可有效地減少或避免電晶體或發光二極體在運作時的漏電流以及電訊號的損耗。
以下將以半導體基板10為例來對包括本發明的半導體基板的電晶體作說明。
圖3為本發明的實施例的電晶體的剖面示意圖。參照圖3，在電晶體20的製造過程中，可於半導體基板10的成核層104上形成緩衝層200。緩衝層200例如為AlGaN層，但本發明不限於此。因為複合基底100與其上生長的GaN層之間的晶格常數差異會造成應力，影響複合基底100上的磊晶層的品質，因此於複合基底100和通道層202之間加入緩衝層200，以平衡複合基底100與後續形成於其上的磊晶層（例如通道層202）之間的應力。在本實施例中，緩衝層200的厚度例如介於100 nm至2.3 μm之間。在其他的實施例中，也可省略緩衝層200，讓通道層202直接與成核層104接觸。
然後，依序形成通道層202與阻障層204。通道層202例如為GaN層。通道層202的厚度例如介於20 nm至100 nm之間。阻障層204例如為AlGaN層、AlInN層、AlN層、AlGaInN層或其組合。阻障層204的厚度例如介於5 nm至50 nm之間。通道層202中具有二維電子氣（2DEG）202a，其位於通道層202與阻障層204之間的界面下方。之後，於阻障層204上形成閘極206、源極208s以及汲極208d，其中閘極206位於源極208s和汲極208d之間。閘極206的材料例如為Ni、Mo、W、TiN或其組合。源極208s和汲極208d的材料例如為Al、Ti、Au或其合金，或者可為其他能夠與III-V族化合物形成歐姆接觸（ohmic contact）的材料。
在電晶體20中，由於使用半導體基板10作為其基板，因此在運作過程中可有效地減少或避免漏電流的產生，同時減少或避免了電訊號的損耗。
特別一提的是，在本實施例中，電晶體20是以高電子移動率晶體電晶體（high electron mobility transistor，HEMT）做舉例，但本發明的電晶體的結構並不限於HEMT。在其他實施例中，電晶體可以具有各種熟知的結構，只要採用本發明的半導體基板作為其基板即可。
此外，當本發明的半導體基板作為發光二極體的基板時，可於本發明的半導體基板上形成各種發光二極體的架構，本發明不對此進行限定。舉例來說，如圖4所示，發光二極體30包括半導體基板10、緩衝層200、第一導電型GaN層300、發光層302、第二導電型GaN層304、第一電極306以及第二電極308。發光層302設置於第一導電型GaN層300與第二導電型GaN層304之間。第一電極306設置於第一導電型GaN層300上。第二電極308設置於第二導電型GaN層304上。第一導電型GaN層300、發光層302、第二導電型GaN層304、第一電極306以及第二電極308的材料為本領域技術人員所熟知，於此不再另行說明。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視所附的申請專利範圍所界定者為準。
10:半導體基板
20:電晶體
30:發光二極體
100:複合基底
100a:基底
100b:絕緣層
100c:半導體層
102:寬能隙擴散緩衝層
104:成核層
104a:擴散層
200:緩衝層
202:通道層
202a:二維電子氣
204:阻障層
206:閘極
208s:源極
208d:汲極
300:第一導電型GaN層
302:發光層
304:第二導電型GaN層
306:第一電極
308:第二電極
圖1A至圖1B為本發明的實施例的半導體基板的製造流程剖面示意圖。
圖2為本發明的實施例的半導體基板中鋁離子濃度與鋁離子擴散深度的關係圖。
圖3為本發明的實施例的電晶體的剖面示意圖。
圖4為本發明的實施例的發光二極體的剖面示意圖。
10:半導體基板
100:複合基底
100a:基底
100b:絕緣層
100c:半導體層
102:寬能隙擴散緩衝層
104:成核層
104a:擴散層
Claims (18)
- 一種半導體基板，包括：基底；絕緣層，設置於所述基底上；半導體層，設置於所述絕緣層上；寬能隙擴散緩衝層，設置於所述半導體層上，其中所述寬能隙擴散緩衝層的能隙高於2.5eV；以及成核層，設置於所述寬能隙擴散緩衝層上，其中所述成核層包括含鋁層，其中所述寬能隙擴散緩衝層包括氮化矽層、氧化矽層、氧化鋅層、氧化鋁層、氧化鎵層或其組合。
- 如請求項1所述的半導體基板，其中所述寬能隙擴散緩衝層的能隙介於3.2eV至9.1eV之間。
- 如請求項1所述的半導體基板，其中所述寬能隙擴散緩衝層的電阻值為1×104ohm．cm至1×1014ohm．cm。
- 如請求項1所述的半導體基板，其中所述寬能隙擴散緩衝層的厚度介於30nm至120nm之間。
- 如請求項1所述的半導體基板，其中所述寬能隙擴散緩衝層為非晶形層。
- 如請求項1所述的半導體基板，其中所述基底的熱傳導係數大於1.4W/cm．K。
- 如請求項1所述的半導體基板，其中所述基底的材料包括矽、氮化鋁、碳化矽、藍寶石或其組合。
- 如請求項1所述的半導體基板，其中所述半導體層包括矽層、碳化矽層或其組合。
- 如請求項1所述的半導體基板，其中所述含鋁層包括氮化鋁層。
- 一種電晶體，包括：半導體基板，包括：基底；絕緣層，設置於所述基底上；半導體層，設置於所述絕緣層上；寬能隙擴散緩衝層，設置於所述半導體層上，其中所述寬能隙擴散緩衝層的能隙高於2.5eV；以及成核層，設置於所述寬能隙擴散緩衝層上，其中所述成核層包括含鋁層；通道層，設置於所述成核層上；阻障層，設置於所述通道層上；閘極，設置於所述阻障層上；以及源極和汲極，設置於所述阻障層上且分別位於所述閘極的相對兩側，其中所述寬能隙擴散緩衝層包括氮化矽層、氧化矽層、氧化鋅層、氧化鋁層、氧化鎵層或其組合。
- 如請求項10所述的電晶體，其中所述寬能隙擴散緩衝層的能隙介於3.2eV至9.1eV之間。
- 如請求項10所述的電晶體，其中所述寬能隙擴散緩衝層的電阻值為1×104ohm．cm至1×1014ohm．cm。
- 如請求項10所述的電晶體，其中所述寬能隙擴散緩衝層的厚度介於30nm至120nm之間。
- 如請求項10所述的電晶體，其中所述寬能隙擴散緩衝層為非晶形層。
- 如請求項10所述的電晶體，其中所述基底的熱傳導係數大於1.4W/cm．K。
- 如請求項10所述的電晶體，其中所述基底的材料包括矽、氮化鋁、碳化矽或藍寶石。
- 如請求項10所述的電晶體，其中所述半導體層包括矽層或碳化矽層。
- 如請求項10所述的電晶體，其中所述寬能隙擴散緩衝層含有鋁。
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