TWI785831B

TWI785831B - Display device

Info

Publication number: TWI785831B
Application number: TW110137214A
Authority: TW
Inventors: 王澄光
Original assignee: 友達光電股份有限公司
Priority date: 2021-10-06
Filing date: 2021-10-06
Publication date: 2022-12-01
Also published as: TW202316397A

Abstract

A display device is provided. The display device includes a pixel circuit and a voltage adjusting circuit. The pixel circuit includes a display element and a switch. The switch is configured to receive a display signal for driving the display element. The voltage adjusting circuit receives gate control signals, which is transited between a first voltage level and a second voltage level. The voltage adjusting circuit transformed the gate control signals to a switch control signal according to a third voltage level. The switch control signal is transited between the first voltage level and the third voltage level, and the second voltage level is between the first and third voltage levels.

Description

顯示裝置display device

本發明是有關於一種裝置，且特別是有關於一種顯示裝置。 The present invention relates to a device, and in particular to a display device.

隨著電子裝置的盛行，人們對於顯示裝置的顯示品質越來越要求。而在顯示裝置中，電濕潤顯示裝置又以高顯示品質受到消費者的青睞。 With the popularity of electronic devices, people have more and more requirements on the display quality of display devices. Among display devices, electrowetting display devices are favored by consumers for their high display quality.

本發明提供一種顯示裝置，用以改善顯示品質。 The invention provides a display device for improving display quality.

本發明的顯示裝置包括畫素電路及電壓調整電路。畫素電路包括一顯示單元及開關。開關用以接收資料訊號以驅動顯示單元。電壓調整電路耦接開關的控制端。電壓調整電路接收閘極控制訊號，其中閘極控制訊號在第一電壓準位及第二電壓準位間轉態。電壓調整電路依據第三電壓準位以將閘極控制訊號轉換為開關控制訊號，其中開關控制訊號在第一電壓準位及第三電壓準位間轉態，且第二電壓準位介於第一電壓準位及第三電壓準位之間。 The display device of the present invention includes a pixel circuit and a voltage adjustment circuit. The pixel circuit includes a display unit and a switch. The switch is used for receiving the data signal to drive the display unit. The voltage adjustment circuit is coupled to the control end of the switch. The voltage adjustment circuit receives the gate control signal, wherein the gate control signal transitions between the first voltage level and the second voltage level. The voltage adjustment circuit converts the gate control signal into a switch control signal according to the third voltage level, wherein the switch control signal transitions between the first voltage level and the third voltage level, and the second voltage level is between the first voltage level Between the first voltage level and the third voltage level.

基於上述，本發明的顯示裝置可改善畫素電路中的漏電流，故有效改善顯示品質。 Based on the above, the display device of the present invention can improve the leakage current in the pixel circuit, thus effectively improving the display quality.

1、2:顯示裝置 1, 2: display device

10:閘極訊號電路 10: Gate signal circuit

11、31、41:電壓調整電路 11, 31, 41: voltage adjustment circuit

12、22:畫素電路 12, 22: Pixel circuit

120、220:開關 120, 220: switch

121、221:顯示單元 121, 221: display unit

311、411:上拉電路 311, 411: pull-up circuit

312、412:下拉電路 312, 412: pull-down circuit

313、413:上拉開關 313, 413: pull-up switch

314、414:下拉開關 314, 414: pull-down switch

315、415:上拉控制電路 315, 415: pull-up control circuit

316:預充電電路 316: Precharge circuit

317、416:下拉控制電路 317, 416: pull-down control circuit

318:穩壓電路 318: voltage regulator circuit

C1~C3、C31、C41:電容 C1~C3, C31, C41: capacitance

Gn-2~Gn+2:閘極訊號線 Gn-2~Gn+2: Gate signal line

M1~M4、M51、M52、M6~M7、M41~M46:電晶體 M1~M4, M51, M52, M6~M7, M41~M46: Transistor

N31~N34、N41~N42:節點 N31~N34, N41~N42: nodes

NO:輸出節點 NO: output node

R1~R3:電阻 R1~R3: resistance

REF:參考電壓線 REF: reference voltage line

T31~T35:時間區間 T31~T35: time interval

VC:開關控制訊號 VC: switch control signal

VGn-2~VGn+2、VN31~VN34、VN41~VN42:電壓 VGn-2~VGn+2, VN31~VN34, VN41~VN42: Voltage

VCOM:共同電壓 VCOM: common voltage

VD:資料訊號 VD: data signal

VG:閘極控制訊號 VG: gate control signal

VR:第三電壓準位 VR: the third voltage level

VSS:參考電壓準位 VSS: reference voltage level

圖1為本發明實施例一顯示裝置的方塊示意圖。 FIG. 1 is a schematic block diagram of a display device according to an embodiment of the present invention.

圖2A為本發明實施例一顯示裝置的方塊示意圖。 FIG. 2A is a schematic block diagram of a display device according to an embodiment of the present invention.

圖2B為本發明實施例一畫素電路進行極性反轉時所施加的電壓示意圖。 2B is a schematic diagram of voltages applied when a pixel circuit performs polarity inversion according to an embodiment of the present invention.

圖2C為圖2B的畫素電路進行極性反轉時所施加的等效電壓示意圖。 FIG. 2C is a schematic diagram of an equivalent voltage applied when the pixel circuit in FIG. 2B performs polarity inversion.

圖3A為本發明實施例一電壓調整電路的示意圖。 FIG. 3A is a schematic diagram of a voltage regulation circuit according to an embodiment of the present invention.

圖3B為圖3A的電壓調整電路的操作波型示意圖。 FIG. 3B is a schematic diagram of operation waveforms of the voltage adjusting circuit shown in FIG. 3A .

圖4A為本發明實施例一電壓調整電路的示意圖。 FIG. 4A is a schematic diagram of a voltage regulation circuit according to an embodiment of the present invention.

圖4B為圖4A的電壓調整電路的操作波型示意圖。 FIG. 4B is a schematic diagram of operation waveforms of the voltage adjusting circuit shown in FIG. 4A .

圖1為本發明實施例一顯示裝置1的方塊示意圖。顯示裝置1包括閘極訊號電路10、電壓調整電路11及畫素電路12。 FIG. 1 is a schematic block diagram of a display device 1 according to an embodiment of the present invention. The display device 1 includes a gate signal circuit 10 , a voltage adjustment circuit 11 and a pixel circuit 12 .

詳細來說，畫素電路12包括互相串聯連接的開關120及顯示單元121。開關120可接收資料訊號VD來驅動顯示單元121，而顯示單元121可在每次的畫框時間中進行極性反轉。為了控制開關120，閘極訊號電路10可以產生在第一電壓準位及第二電壓準位間轉態的閘極控制訊號VG。電壓調整電路11可接收閘極控制訊號VG及第三參考電壓準位VR並將閘極控制訊號VG轉換為在第一電壓準位及第三電壓準位間轉態的開關控制訊號VC，並以開關控制訊號VC來控制開關120的導通(conduct)或截止(cutoff)。由於第二電壓準位會界於第一電壓準位及第三電壓準之間，故開關120可依據更大振幅的開關控制訊號VC來進行操作，進而避免在對顯示單元121進行極性反轉的電壓操作時，導致開關120的漏電，因而影響顯示裝置1的顯示品質。 In detail, the pixel circuit 12 includes a switch 120 and a display unit 121 connected in series. The switch 120 can receive the data signal VD to drive the display unit 121, and the display unit 121 can perform polarity inversion in each frame time. for control The switch 120 and the gate signal circuit 10 can generate a gate control signal VG that transitions between the first voltage level and the second voltage level. The voltage adjustment circuit 11 can receive the gate control signal VG and the third reference voltage level VR and convert the gate control signal VG into a switch control signal VC that transitions between the first voltage level and the third voltage level, and The conduction or cutoff of the switch 120 is controlled by the switch control signal VC. Since the second voltage level is between the first voltage level and the third voltage level, the switch 120 can be operated according to the switching control signal VC with a larger amplitude, thereby avoiding polarity inversion of the display unit 121 When operating at a lower voltage, the leakage of the switch 120 is caused, thus affecting the display quality of the display device 1 .

圖2A為本發明實施例一顯示裝置2的方塊示意圖。圖2A所繪示的顯示裝置2相似於圖1所繪示的顯示裝置1，故相同元件沿用相同的符號表示。顯示裝置2與顯示裝置1的差別在於，顯示裝置2中具有畫素電路22，而畫素電路22是以電晶體220及電濕潤顯示(Electrowetting Display,EWD)單元221來實現的。 FIG. 2A is a schematic block diagram of a display device 2 according to Embodiment 1 of the present invention. The display device 2 shown in FIG. 2A is similar to the display device 1 shown in FIG. 1 , so the same components are represented by the same symbols. The difference between the display device 2 and the display device 1 is that the display device 2 has a pixel circuit 22 , and the pixel circuit 22 is realized by a transistor 220 and an electrowetting display (Electrowetting Display, EWD) unit 221 .

詳細而言，電晶體220可例如為n型金氧半場效電晶體(n type metal-oxide-silicon field effect transistor,nMOSFET)。電晶體220的第一端(例如是源極)可接收資料訊號VD，電晶體220的第二端(例如是汲極)可耦接電濕潤顯示單元221，電晶體220的控制端(例如是閘極)可接收開關控制訊號VC。 In detail, the transistor 220 may be, for example, an n type metal-oxide-silicon field effect transistor (nMOSFET). The first end of the transistor 220 (for example, the source) can receive the data signal VD, the second end of the transistor 220 (for example, the drain) can be coupled to the electrowetting display unit 221, and the control end of the transistor 220 (for example, the Gate) can receive the switch control signal VC.

電濕潤顯示單元221可為多層結構所形成的顯示單元，具體來說，電濕潤顯示單元221的底層可例如是透明導電層，其包含有例如是氧化銦錫(Indium Tin Oxide,ITO)或其他適合的材料。透明導電層上可設置有絕緣層。絕緣層上可設置有親油層。親油層上可乘載油墨，而油墨上則覆蓋有水。而電濕潤顯示單元221可透過上下兩端所施加的電壓差來改變油墨的表面張力以及油墨表面上的弧度，也就是說電濕潤顯示單元221可依據所施加的電壓來進行相對應的顯示操作。 The electrowetting display unit 221 can be a display unit formed of a multilayer structure. Specifically, the bottom layer of the electrowetting display unit 221 can be, for example, a transparent conductive layer, which includes, for example, indium tin oxide (Indium Tin Oxide, ITO) or other suitable material material. An insulating layer may be disposed on the transparent conductive layer. An oleophilic layer may be provided on the insulating layer. The oleophilic layer can be loaded with ink, which is covered with water. The electrowetting display unit 221 can change the surface tension of the ink and the curvature on the surface of the ink through the voltage difference applied between the upper and lower ends, that is to say, the electrowetting display unit 221 can perform corresponding display operations according to the applied voltage. .

在一些實施例中，電濕潤顯示單元221由於絕緣層上可能會累積殘存電荷的緣故，故需對電濕潤顯示單元221進行極性反轉的操作，來消除電濕潤顯示單元221中的殘存電荷。在此情況下，對電濕潤顯示單元221進行極性反轉的操作可能會造成電晶體220的漏電。 In some embodiments, since residual charges may accumulate on the insulating layer of the electrowetting display unit 221 , the electrowetting display unit 221 needs to perform a polarity inversion operation to eliminate the residual charges in the electrowetting display unit 221 . In this case, the operation of inverting the polarity of the electrowetting display unit 221 may cause electric leakage of the transistor 220 .

圖2B為本發明實施例一畫素電路22進行極性反轉時所施加的電壓示意圖；圖2C為圖2B的畫素電路22進行極性反轉時所施加的等效電壓示意圖。 2B is a schematic diagram of a voltage applied when the pixel circuit 22 performs polarity inversion according to an embodiment of the present invention; FIG. 2C is a schematic diagram of an equivalent voltage applied when the pixel circuit 22 in FIG. 2B performs polarity inversion.

在此實施例中，電晶體220的致能電壓準位可例如是25V且禁能電壓準位可例如是-20V。在施加如圖2B所繪示電壓的前一個畫框時間中，電濕潤顯示單元221的上方可例如被施加-15V的資料訊號VD，且電濕潤顯示單元221的下方可例如被施加15V的共同電壓VCOM以進行顯示操作。 In this embodiment, the enabling voltage level of the transistor 220 may be, for example, 25V and the disabling voltage level may be, for example, −20V. In the previous frame time of applying the voltage shown in FIG. 2B , the upper part of the electrowetting display unit 221 may be applied with a data signal VD of -15V, for example, and the lower part of the electrowetting display unit 221 may be applied with a common voltage of 15V. Voltage VCOM for display operation.

接著，在下一個畫框時間的起始中，如圖2B所示，電濕潤顯示單元221下方所施加的共同電壓VCOM可由15V反轉為-15V。如此一來，電濕潤顯示單元221的上方同時也會被下拉-30V，使的電晶體220的第二端的電壓被改變為-45V。同時，電晶體220 的控制端可接收禁能電壓準位，且電晶體220的第一端所接收到的資料訊號VD可改變為15V。 Then, at the beginning of the next frame time, as shown in FIG. 2B , the common voltage VCOM applied under the electrowetting display unit 221 may be reversed from 15V to −15V. In this way, the upper side of the electrowetting display unit 221 is also pulled down to -30V at the same time, so that the voltage of the second terminal of the transistor 220 is changed to -45V. At the same time, the transistor 220 The control terminal of the transistor 220 can receive the disable voltage level, and the data signal VD received by the first terminal of the transistor 220 can be changed to 15V.

圖2B中對畫素電路22所施加的電壓示意圖可等效為如圖2C所繪示的電壓示意圖。詳細來說，若將畫素電路22的施加電壓進行45V的偏移，電晶體220的第一端、第二端及控制端所施加的電壓可分別為60V、0V、25V。在此情況下，電晶體220的控制端與第二端之間的電壓差並無法有效控制電晶體220在截止，而導致漏電流。 The schematic diagram of the voltage applied to the pixel circuit 22 in FIG. 2B can be equivalent to the schematic diagram of the voltage shown in FIG. 2C . In detail, if the applied voltage of the pixel circuit 22 is shifted by 45V, the voltages applied to the first terminal, the second terminal and the control terminal of the transistor 220 can be 60V, 0V and 25V respectively. In this case, the voltage difference between the control terminal and the second terminal of the transistor 220 cannot effectively control the transistor 220 to be cut off, resulting in leakage current.

圖3A為本發明實施例一電壓調整電路31的示意圖。電壓調整電路31包括上拉開關313、下拉開關314、上拉控制電路315、預充電電路316、下拉控制電路317、穩壓電路318及電容C1。 FIG. 3A is a schematic diagram of a voltage regulation circuit 31 according to an embodiment of the present invention. The voltage adjustment circuit 31 includes a pull-up switch 313 , a pull-down switch 314 , a pull-up control circuit 315 , a pre-charging circuit 316 , a pull-down control circuit 317 , a voltage stabilizing circuit 318 and a capacitor C1.

電壓調整電路31可接收閘極訊號線VGn-2~VGn+1切換於致能電壓準位(即第一電壓準位)及禁能電壓準位(即第二電壓準位)的訊號，以及接收參考電壓線Ref的參考電壓VSS(即第三電壓準位)。在一些實施例中，第一電壓準位可例如是25V，第二電壓準位可例如是-20V，第三電壓準位可例如是-50V。進一步，電壓調整電路31可依據閘極訊號線VGn-2~VGn+1的控制，來將在第一電壓準位及第二電壓準位間轉態的訊號，轉換為在第一電壓準位及第三電壓準位間轉態的訊號。透過調降禁能電壓準位來加大致能電壓準位及禁能電壓準位間的電壓差，故電壓調整電路31可改善上述關於畫素電路中的漏電流問題。 The voltage adjustment circuit 31 can receive the signal of switching the gate signal lines VGn-2~VGn+1 between the enabling voltage level (ie, the first voltage level) and the disabling voltage level (ie, the second voltage level), and The reference voltage VSS (ie, the third voltage level) of the reference voltage line Ref is received. In some embodiments, the first voltage level may be 25V, the second voltage level may be -20V, and the third voltage level may be -50V. Further, the voltage adjustment circuit 31 can convert the signal transitioning between the first voltage level and the second voltage level into the first voltage level according to the control of the gate signal lines VGn-2~VGn+1. and the transition signal between the third voltage levels. By reducing the disable voltage level to increase the voltage difference between the enable voltage level and the disable voltage level, the voltage adjustment circuit 31 can improve the above-mentioned leakage current problem in the pixel circuit.

上拉開關313及下拉開關314互相串聯連接，並於輸出節點NO上產生開關控制訊號VC。電容C1耦接於閘極訊號線Gn及上拉開關313的控制端之間。 The pull-up switch 313 and the pull-down switch 314 are connected in series and generate a switch control signal VC on the output node NO. The capacitor C1 is coupled between the gate signal line Gn and the control terminal of the pull-up switch 313 .

上拉控制電路315耦接閘極訊號線Gn-1、Gn+1，並據以控制上拉開關313的控制端的電壓。預充電電路316耦接閘極訊號線Gn-2，並據以對上拉控制電路315進行預充電。 The pull-up control circuit 315 is coupled to the gate signal lines Gn−1 and Gn+1, and controls the voltage of the control end of the pull-up switch 313 accordingly. The precharge circuit 316 is coupled to the gate signal line Gn- 2 , and precharges the pull-up control circuit 315 accordingly.

下拉控制電路317耦接閘極訊號線Gn+1，並據以控制下拉開關314的控制端的電壓。另外，穩壓電路318耦接閘極訊號線Gn-1、Gn，並據以下拉開關314的控制端的電壓耦接至參考電壓線Ref上，使參考電壓線Ref上的參考電壓VSS可被提供至下拉電路314的控制端上，進而對輸出節點NO進行穩壓。 The pull-down control circuit 317 is coupled to the gate signal line Gn+1, and controls the voltage of the control terminal of the pull-down switch 314 accordingly. In addition, the voltage stabilizing circuit 318 is coupled to the gate signal lines Gn-1, Gn, and the voltage of the control terminal of the pull-down switch 314 is coupled to the reference voltage line Ref, so that the reference voltage VSS on the reference voltage line Ref can be provided. to the control terminal of the pull-down circuit 314 to stabilize the voltage of the output node NO.

因此，上拉開關313可依據上拉控制電路315的控制來對輸出節點NO上的電壓進行上拉，下拉開關314可依據下拉控制電路317來對輸出節點NO上的電壓進行下拉。而預充電電路316可針對上拉控制電路315進行預充電，穩壓電路318可針對保持下拉開關314的禁能，使開關電路31整體可有效運作。 Therefore, the pull-up switch 313 can pull up the voltage on the output node NO according to the control of the pull-up control circuit 315 , and the pull-down switch 314 can pull down the voltage on the output node NO according to the pull-down control circuit 317 . The pre-charging circuit 316 can pre-charge the pull-up control circuit 315 , and the voltage-stabilizing circuit 318 can keep the pull-down switch 314 disabled, so that the whole switch circuit 31 can operate effectively.

在一實施例中，上拉開關313包括電晶體M3，電晶體M3的第一端(例如是汲極)耦接閘極訊號線Gn，電晶體M3的第二端(例如是源極)耦接輸出節點NO。電容C1耦接於電晶體M3的第一端及控制端(例如是閘極)之間。 In one embodiment, the pull-up switch 313 includes a transistor M3, a first terminal (for example, the drain) of the transistor M3 is coupled to the gate signal line Gn, and a second terminal (for example, the source) of the transistor M3 is coupled to the gate signal line Gn. Connect to output node NO. The capacitor C1 is coupled between the first terminal of the transistor M3 and a control terminal (such as a gate).

上拉控制電路315包括電晶體M1、M2及電容C4。電晶體M1的第一端(例如是汲極)耦接閘極訊號線Gn-1，電晶體M1 的第二端(例如是源極)耦接電晶體M3的控制端。電晶體M2的第一端(例如是汲極)耦接電晶體M1的第二端，電晶體M2的第二端(例如是源極)耦接參考電壓線Ref，電晶體M2的控制端(例如是閘極)耦接於閘極訊號線Gn+1。電容C4耦接電晶體M1於電晶體M1的第一端及控制端之間。 The pull-up control circuit 315 includes transistors M1, M2 and a capacitor C4. The first end of the transistor M1 (for example, the drain) is coupled to the gate signal line Gn-1, and the transistor M1 The second end (for example, the source) of the transistor M3 is coupled to the control end of the transistor M3. The first terminal (such as the drain) of the transistor M2 is coupled to the second terminal of the transistor M1, the second terminal (such as the source) of the transistor M2 is coupled to the reference voltage line Ref, and the control terminal of the transistor M2 ( For example, the gate) is coupled to the gate signal line Gn+1. The capacitor C4 is coupled to the transistor M1 between the first terminal and the control terminal of the transistor M1.

預充電電路316包括電晶體M7及電阻R1。電晶體M7的第一端(例如是汲極)及控制端(例如是閘極)耦接於閘極訊號線Gn-2，電晶體M7的第二端(例如是源極)耦接於電晶體M1的控制端。電阻R1耦接於電晶體M1的控制端與參考電壓線Ref之間。 The pre-charging circuit 316 includes a transistor M7 and a resistor R1. The first terminal (such as the drain) and the control terminal (such as the gate) of the transistor M7 are coupled to the gate signal line Gn-2, and the second terminal (such as the source) of the transistor M7 is coupled to the circuit The control terminal of crystal M1. The resistor R1 is coupled between the control terminal of the transistor M1 and the reference voltage line Ref.

下拉開關314包括電晶體M4。電晶體M4的第一端(例如是汲極)耦接輸出節點NO，電晶體M4的第二端(例如是源極)耦接參考電壓線Ref。 The pull-down switch 314 includes a transistor M4. A first end (for example, the drain) of the transistor M4 is coupled to the output node NO, and a second end (for example, the source) of the transistor M4 is coupled to the reference voltage line Ref.

下拉控制電路317包括電晶體M6及電容C2。電晶體M6的第一端(例如是汲極)耦接電晶體M4的控制端，電晶體M6的第二端(例如是源極)及控制端(例如是閘極)耦接閘極訊號Gn+1。電容C2耦接於電晶體M4的控制端(例如是閘極)及閘極訊號線Gn+1之間。 The pull-down control circuit 317 includes a transistor M6 and a capacitor C2. The first terminal (such as the drain) of the transistor M6 is coupled to the control terminal of the transistor M4, and the second terminal (such as the source) and the control terminal (such as the gate) of the transistor M6 are coupled to the gate signal Gn +1. The capacitor C2 is coupled between the control terminal (eg gate) of the transistor M4 and the gate signal line Gn+1.

穩壓電路318包括電晶體M51、M52、電阻R2、R3及電容C3、C31。電晶體M51的第一端(例如是汲極)耦接電晶體M4的控制端，電晶體M51的第二端(例如是源極)耦接參考電壓線Ref。電容C3耦接於閘極訊號Gn-1及電晶體M51的控制端(例如是閘極)之間。電阻R2耦接於電晶體M51的控制端及第二端之間。電晶體M52的第一端(例如是汲極)耦接電晶體M4的控制端，電晶體M52的第二端(例如是源極)耦接參考電壓線Ref。電容C31耦接於閘極訊號Gn及電晶體M52的控制端(例如是閘極)之間。電阻R3耦接於電晶體M52的控制端及第二端之間。 The voltage stabilizing circuit 318 includes transistors M51, M52, resistors R2, R3, and capacitors C3, C31. A first terminal (for example, the drain) of the transistor M51 is coupled to the control terminal of the transistor M4, and a second terminal (for example, the source) of the transistor M51 is coupled to the reference voltage line Ref. The capacitor C3 is coupled to the gate signal Gn-1 and the control terminal of the transistor M51 (for example If it is a gate). The resistor R2 is coupled between the control terminal and the second terminal of the transistor M51. A first terminal (for example, the drain) of the transistor M52 is coupled to the control terminal of the transistor M4, and a second terminal (for example, the source) of the transistor M52 is coupled to the reference voltage line Ref. The capacitor C31 is coupled between the gate signal Gn and the control terminal (eg gate) of the transistor M52. The resistor R3 is coupled between the control terminal and the second terminal of the transistor M52.

圖3B為圖3A的電壓調整電路31的操作波型示意圖，故接下來請共同參考圖3A，3B來理解下方關於電壓調整電路31的操作說明。電壓VGn-2~VGn+1分別為閘極訊號線Gn-2~Gn+1上所提供的電壓。電壓VN31~VN34分別為圖3A中節點N31~N34的電壓。開關控制訊號VOUT即為電壓調整電路31在輸出節點NO所產生的電壓。 FIG. 3B is a schematic diagram of the operation waveform of the voltage adjustment circuit 31 in FIG. 3A , so please refer to FIGS. 3A and 3B to understand the operation description of the voltage adjustment circuit 31 below. The voltages VGn-2˜VGn+1 are the voltages provided by the gate signal lines Gn-2˜Gn+1 respectively. The voltages VN31 - VN34 are respectively the voltages of the nodes N31 - N34 in FIG. 3A . The switch control signal VOUT is the voltage generated by the voltage adjustment circuit 31 at the output node NO.

在時間區間T31中，電壓VGn-2會被切換為致能電壓準位(例如是25V)，而其他電壓VGn-1~VGn+1則保持在禁能電壓準位(例如是-20V)。預充電電路316中的電晶體M7可被電壓VGn-2致能，以將節點N31上的電壓VN31稍微上拉，以對上拉控制電路315中的電晶體M1的控制端以及上拉開關313中的電晶體M3的控制端進行預充電。 In the time interval T31, the voltage VGn-2 is switched to an enable voltage level (for example, 25V), while the other voltages VGn-1˜VGn+1 remain at the disable voltage level (for example, -20V). The transistor M7 in the precharge circuit 316 can be enabled by the voltage VGn-2, so as to slightly pull up the voltage VN31 on the node N31, so as to control the control terminal of the transistor M1 in the pull-up control circuit 315 and the pull-up switch 313 The control end of the transistor M3 in the precharge.

在時間區間T32中，電壓VGn-1會被切換為致能電壓準位，而其他電壓VGn-2、VGn、VGn+1則為禁能電壓準位。電壓VGn-1會將電容C4第二端的電壓相對應的上拉，進而控制上拉開關313來對輸出節點NO進行預充電。 In the time interval T32, the voltage VGn−1 is switched to the enable voltage level, while the other voltages VGn−2, VGn, VGn+1 are the disable voltage levels. The voltage VGn-1 will correspondingly pull up the voltage of the second end of the capacitor C4, and then control the pull-up switch 313 to precharge the output node NO.

同時，電壓VGn-1也會將電容C3第二端的電壓VN34相對應的上拉，進而控制穩壓電路318中的電晶體M51導通，以將參考電壓線Ref上的參考電壓VSS可被提供至下拉開關314的控制端，進而保持下拉開關314的截止。 At the same time, the voltage VGn-1 will also phase the voltage VN34 at the second end of the capacitor C3 to Correspondingly pull up, and then control the transistor M51 in the voltage stabilizing circuit 318 to turn on, so that the reference voltage VSS on the reference voltage line Ref can be provided to the control terminal of the pull-down switch 314 , thereby keeping the pull-down switch 314 off.

在時間區間T33中，電壓VGn會被切換為致能電壓準位，而其他電壓VGn-2、VGn-1、VGn+1則為禁能電壓準位。電壓VGn會將電容C1第二端的電壓VN32相對應的上拉，使閘極訊號線Gn上的致能電壓準位可透過上拉開關313被提供至輸出節點NO。 In the time interval T33 , the voltage VGn is switched to the enabling voltage level, while the other voltages VGn−2 , VGn−1 , and VGn+1 are the disabling voltage levels. The voltage VGn will correspondingly pull up the voltage VN32 at the second end of the capacitor C1 , so that the enable voltage level on the gate signal line Gn can be provided to the output node NO through the pull-up switch 313 .

同時，電壓VGn會將電容C31第二端的電壓相對應的上拉，進而控制穩壓電路318中的電晶體M52導通，以將參考電壓線Ref上的參考電壓VSS可被提供至下拉開關314的控制端，進而保持下拉開關314的截止。 At the same time, the voltage VGn will correspondingly pull up the voltage at the second terminal of the capacitor C31, thereby controlling the conduction of the transistor M52 in the voltage stabilizing circuit 318, so that the reference voltage VSS on the reference voltage line Ref can be provided to the pull-down switch 314. control terminal, and keep the pull-down switch 314 off.

在時間區間T34中，電壓VGn+1會被切換為致能電壓準位，而其他電壓VGn-2、VGn-1、VGn則為禁能電壓準位。下拉控制電路317中的電晶體M6可被電壓VGn+1導通，閘極訊號線Gn+1上的致能電壓準位可被提供至下拉開關314的控制端，使控制下拉開關314導通。據此，輸出節點NO上的電壓可被下拉開關314的導通下拉至參考電壓VSS。 In the time interval T34 , the voltage VGn+1 is switched to the enabling voltage level, while the other voltages VGn−2 , VGn−1 , and VGn are the disabling voltage levels. The transistor M6 in the pull-down control circuit 317 can be turned on by the voltage VGn+1, and the enable voltage level on the gate signal line Gn+1 can be provided to the control terminal of the pull-down switch 314 to make the pull-down switch 314 turn on. Accordingly, the voltage on the output node NO can be pulled down to the reference voltage VSS by turning on the pull-down switch 314 .

同時，上拉控制電路315中的電晶體M2可被電壓VGn+1導通，據此將上拉開關313控制端的電壓下拉至參考電壓VSS，使上拉開關313截止。 At the same time, the transistor M2 in the pull-up control circuit 315 can be turned on by the voltage VGn+1, thereby pulling down the voltage of the control end of the pull-up switch 313 to the reference voltage VSS, so that the pull-up switch 313 is turned off.

在時間區間T35中，電壓VGn-2~VGn+1皆為禁能電壓準位。電容C2第一端的電壓會被下拉，使下拉開關314截止，並使輸出節點NO上的開關控制訊號VC保持在參考電壓VSS的準位。 In the time interval T35 , the voltages VGn−2˜VGn+1 are all disabled voltage levels. The voltage at the first end of the capacitor C2 will be pulled down, so that the pull-down switch 314 is cut off, and The switch control signal VC on the output node NO is kept at the level of the reference voltage VSS.

因此，電壓調整電路31可接收閘極訊號線VGn-2~VGn+1上電壓的控制，以將在第一電壓準位及第二電壓準位間轉態的電壓轉換為在第一電壓準位及第三電壓準位間轉態的開關控制訊號VC，用以控制如圖1中所繪示的開關120。透過將開關控制訊號VC的禁能電電壓準位調降至第三電壓準位，使開關120可不受到極性反轉的干擾而漏電，進而改善顯示品質。 Therefore, the voltage adjustment circuit 31 can receive the control of the voltage on the gate signal lines VGn-2~VGn+1, so as to convert the voltage between the first voltage level and the second voltage level into the first voltage level The switching control signal VC between the first and third voltage levels is used to control the switch 120 as shown in FIG. 1 . By lowering the disable voltage level of the switch control signal VC to the third voltage level, the switch 120 is not disturbed by the polarity inversion and thus the display quality is improved.

一般來說，當電晶體需要長時間承受高壓操作(例如是電晶體的跨壓大於等於60V)時，會需要使用特殊製程的高壓電晶體元件來實現，而這些高壓電晶體元件往往具有較大的尺寸並具有較高的製造成本。相較之下，在一些實施例中，在電壓調整電路31的整體操作時，電壓調整電路31可避免其中的電晶體的兩端跨壓長時間承受高壓，如此一來，電壓調整電路31即可避免使用特殊製程的高壓電晶體元件來實現，並且避免整合不同電晶體製程的需求，進而在改善整體的製造成本的同時，有效避免晶片設計流程的複雜化。 Generally speaking, when the transistor needs to withstand high-voltage operation for a long time (for example, the cross-voltage of the transistor is greater than or equal to 60V), it will need to use special process high-voltage transistor components, and these high-voltage transistor components often have Larger size and higher manufacturing cost. In contrast, in some embodiments, during the overall operation of the voltage adjustment circuit 31, the voltage adjustment circuit 31 can prevent the two ends of the transistors from being subjected to high voltage for a long time, so that the voltage adjustment circuit 31 can be It can avoid the use of high-voltage transistor elements with special processes, and avoid the need to integrate different transistor processes, so as to improve the overall manufacturing cost and effectively avoid the complexity of the chip design process.

圖4A為本發明實施例一電壓調整電路41的示意圖。電壓調整電路41包括上拉電路411及下拉電路412。上拉電路411包括上拉開關413、上拉控制電路415及電容C41。下拉電路412包括下拉開關414、下拉控制電路416。上拉開關413及下拉開關414可分別接受上拉控制電路415及下拉控制電路416的控制而被導通或截止。 FIG. 4A is a schematic diagram of a voltage regulation circuit 41 according to an embodiment of the present invention. The voltage adjustment circuit 41 includes a pull-up circuit 411 and a pull-down circuit 412 . The pull-up circuit 411 includes a pull-up switch 413 , a pull-up control circuit 415 and a capacitor C41 . The pull-down circuit 412 includes a pull-down switch 414 and a pull-down control circuit 416 . The pull-up switch 413 and the pull-down switch 414 can be controlled by the pull-up control circuit 415 and the pull-down control circuit 416 respectively. be turned on or off.

在上拉電路411中，上拉開關413包括電晶體M43，上拉控制電路415包括電晶體M41、M42。電晶體M43的第一端(例如是汲極)耦接閘極訊號線Gn，電晶體M43的第二端(例如是源極)耦接輸出節點NO。電容C41耦接於電晶體M43的第一端及控制端之間(例如是閘極)。電晶體M41的第一端(例如是汲極)及控制端(例如是閘極)耦接閘極訊號線Gn-1。電晶體M42的第一端(例如是汲極)耦接電晶體M41的第二端(例如是源極)，電晶體M42的第二端(例如是源極)耦接參考電壓線Ref，電晶體M42的控制端(例如是閘極)耦接閘極訊號線Gn+1。 In the pull-up circuit 411, the pull-up switch 413 includes a transistor M43, and the pull-up control circuit 415 includes transistors M41 and M42. A first end (for example, the drain) of the transistor M43 is coupled to the gate signal line Gn, and a second end (for example, the source) of the transistor M43 is coupled to the output node NO. The capacitor C41 is coupled between the first terminal of the transistor M43 and the control terminal (eg, gate). A first end (eg drain) and a control end (eg gate) of the transistor M41 are coupled to the gate signal line Gn-1. The first end (for example, the drain) of the transistor M42 is coupled to the second end (for example, the source) of the transistor M41, and the second end (for example, the source) of the transistor M42 is coupled to the reference voltage line Ref. A control terminal (for example, a gate) of the crystal M42 is coupled to the gate signal line Gn+1.

在下拉電路中，下拉開關414包括電晶體M44，下拉控制電路416包括電晶體M45、M46。電晶體M44的第一端(例如是汲極)耦接輸出節點NO，電晶體M44的第二端(例如是源極)耦接參考電壓線Ref。電晶體M45的第一端(例如是汲極)及控制端(例如是閘極)耦接閘極訊號線Gn+1，電晶體M45的第二端(例如是源極)耦接電晶體M44的控制端(例如是閘極)。電晶體M46的第一端(例如是汲極)耦接電晶體M45的第二端，電晶體M46的第二端(例如是源極)耦接參考電壓線Ref，電晶體M46的控制端(例如是閘極)耦接閘極訊號線Gn+2。 In the pull-down circuit, the pull-down switch 414 includes a transistor M44, and the pull-down control circuit 416 includes transistors M45 and M46. A first terminal (for example, the drain) of the transistor M44 is coupled to the output node NO, and a second terminal (for example, the source) of the transistor M44 is coupled to the reference voltage line Ref. The first terminal (such as the drain) and the control terminal (such as the gate) of the transistor M45 are coupled to the gate signal line Gn+1, and the second terminal (such as the source) of the transistor M45 is coupled to the transistor M44 The control terminal (for example, the gate). The first terminal (such as the drain) of the transistor M46 is coupled to the second terminal of the transistor M45, the second terminal (such as the source) of the transistor M46 is coupled to the reference voltage line Ref, and the control terminal of the transistor M46 ( For example, the gate) is coupled to the gate signal line Gn+2.

圖4B為圖4A的電壓調整電路41的操作波型示意圖，故接下來請共同參考圖4A，4B來理解下方關於電壓調整電路41的操作說明。電壓VGn-1~VGn+2分別為閘極訊號線Gn-1~Gn+2 上所提供的電壓。電壓VN41、VN42分別為圖4A中節點N41、N42的電壓。開關控制訊號VOUT即為電壓調整電路41在輸出節點NO所產生的電壓。 4B is a schematic diagram of the operation waveform of the voltage adjustment circuit 41 in FIG. 4A , so please refer to FIGS. 4A and 4B to understand the operation description of the voltage adjustment circuit 41 below. The voltages VGn-1~VGn+2 are the gate signal lines Gn-1~Gn+2 respectively on the supplied voltage. The voltages VN41 and VN42 are respectively the voltages of the nodes N41 and N42 in FIG. 4A . The switch control signal VOUT is the voltage generated by the voltage adjustment circuit 41 at the output node NO.

在時間區間T41中，電壓VGn-1會被切換為致能電壓準位(例如是25V)，而其他電壓VGn~VGn+2則保持在禁能電壓準位(例如是-20V)。上拉控制電路415中的電晶體M41可被電壓VGn-1致能，以將節點N41上的電壓VN41上拉，以對上拉開關313中的電晶體M3的控制端進行預充電。 In the time interval T41 , the voltage VGn−1 is switched to an enable voltage level (for example, 25V), while other voltages VGn˜VGn+2 are kept at a disable voltage level (for example, −20V). The transistor M41 in the pull-up control circuit 415 can be enabled by the voltage VGn−1 to pull up the voltage VN41 on the node N41 to precharge the control terminal of the transistor M3 in the pull-up switch 313 .

在時間區間T42中，電壓VGn會被切換為致能電壓準位，而其他電壓VGn-1、VGn+1、VGn+2則為禁能電壓準位。電壓VGn會將電容C41第二端的電壓相對應的上拉，進而控制上拉開關413來對輸出節點NO進行預充電。電壓VGn會將電容C41第二端的電壓VN41相對應的上拉，使閘極訊號線Gn上的致能電壓準位可透過上拉開關413被提供至輸出節點NO。 In the time interval T42 , the voltage VGn is switched to the enable voltage level, while the other voltages VGn−1 , VGn+1 , and VGn+2 are disabled voltage levels. The voltage VGn will correspondingly pull up the voltage of the second terminal of the capacitor C41 , and then control the pull-up switch 413 to precharge the output node NO. The voltage VGn will correspondingly pull up the voltage VN41 at the second end of the capacitor C41 , so that the enable voltage level on the gate signal line Gn can be provided to the output node NO through the pull-up switch 413 .

在時間區間T43中，電壓VGn+1會被切換為致能電壓準位，而其他電壓VGn-1、VGn、VGn+2則為禁能電壓準位。上拉控制電路415中的電晶體M42可受控於電壓VGn+1而被致能，因而將參考電壓線Ref的參考電壓VSS提供至上拉開關413的控制端，使上拉開關413禁能。另外，下拉控制電路416中的電晶體M45亦會受控於電壓VGn+1而被致能，因而將致能電壓準位提供至下拉開關414的控制端，使下拉開關導414導通，故參考電壓VSS可透過下拉開關414而被提供至輸出節點NO上。 In the time interval T43 , the voltage VGn+1 is switched to the enabling voltage level, while the other voltages VGn−1 , VGn, VGn+2 are the disabling voltage levels. The transistor M42 in the pull-up control circuit 415 is controlled by the voltage VGn+1 to be enabled, thereby providing the reference voltage VSS of the reference voltage line Ref to the control terminal of the pull-up switch 413 to disable the pull-up switch 413 . In addition, the transistor M45 in the pull-down control circuit 416 is also enabled under the control of the voltage VGn+1, thus providing the enable voltage level to the control terminal of the pull-down switch 414 to turn on the pull-down switch 414, so refer to The voltage VSS can be provided to the output node NO through the pull-down switch 414 .

在時間區間T44中，電壓VGn+2會被切換為致能電壓準位，而其他電壓VGn-1~VGn+1則為禁能電壓準位。下拉控制電路416中的電晶體M46可受控於第壓VGn+2而被導通，使參考電壓VSS被提供至下拉開關414的控制端上，進而控制下拉開關414為截止。 In the time interval T44 , the voltage VGn+2 is switched to the enabling voltage level, while the other voltages VGn−1˜VGn+1 are the disabling voltage levels. The transistor M46 in the pull-down control circuit 416 is controlled by the first voltage VGn+2 to be turned on, so that the reference voltage VSS is provided to the control terminal of the pull-down switch 414 , and then the pull-down switch 414 is controlled to be turned off.

在時間區間T45中，電壓VGn-1~VGn+1皆為禁能電壓準位。上拉開關413的控制端及下拉開關414的控制端皆為截止，故可有效保持輸出節點NO的電壓保持在參考電壓VSS的準位。 In the time interval T45 , the voltages VGn−1˜VGn+1 are all disabled voltage levels. Both the control terminal of the pull-up switch 413 and the control terminal of the pull-down switch 414 are turned off, so the voltage of the output node NO can be effectively kept at the level of the reference voltage VSS.

因此，電壓調整電路41可接收閘極訊號線VGn-1~VGn+2上電壓的控制，以將在第一電壓準位及第二電壓準位間轉態的電壓轉換為在第一電壓準位及第三電壓準位間轉態的開關控制訊號VC，用以控制如圖1中所繪示的開關120。透過將開關控制訊號VC的禁能電電壓準位調降至第三電壓準位，使開關120可不受到極性反轉的干擾而漏電，進而改善顯示品質。 Therefore, the voltage adjustment circuit 41 can receive the control of the voltage on the gate signal lines VGn-1~VGn+2, so as to convert the voltage between the first voltage level and the second voltage level into the first voltage level The switching control signal VC between the first and third voltage levels is used to control the switch 120 as shown in FIG. 1 . By lowering the disable voltage level of the switch control signal VC to the third voltage level, the switch 120 is not disturbed by the polarity inversion and thus the display quality is improved.

一般來說，當電晶體需要長時間承受高壓操作(例如是電晶體的跨壓大於等於60V)時，會需要使用特殊製程的高壓電晶體元件來實現，而這些高壓電晶體元件往往具有較大的尺寸並具有較高的製造成本。相較之下，在一些實施例中，在電壓調整電路41的整體操作時，電壓調整電路41可避免其中的電晶體的兩端跨壓長時間承受高壓，如此一來，電壓調整電路41即可避免使用特殊製程的高壓電晶體元件來實現，並且避免整合不同電晶體製程的需求，進而在改善整體的製造成本的同時，有效避免晶片設計流程的複雜化。 Generally speaking, when the transistor needs to withstand high-voltage operation for a long time (for example, the cross-voltage of the transistor is greater than or equal to 60V), it will need to use special process high-voltage transistor components, and these high-voltage transistor components often have Larger size and higher manufacturing cost. In contrast, in some embodiments, during the overall operation of the voltage adjustment circuit 41, the voltage adjustment circuit 41 can prevent the two ends of the transistors from being subjected to high voltage for a long time, so that the voltage adjustment circuit 41 can It can avoid the use of high-voltage transistor components with special processes, and avoid the need to integrate different transistor processes, thereby improving the overall manufacturing cost and effectively avoiding the chip design process of complication.

雖然上述的實施方式僅是以開關120為nMOSFET的實施方式下來進行說明，也就是開關120可在高電壓下被導通，且在低電壓下被禁能，並且搭配電壓調整電路31、41以nMOSFET的實施方式來進行說明，但本發明不限於此，本領域具通常知識者當然可依據不同的設計需求來對上述進行變更或修改，其皆屬與本發明之範疇。舉例來說，開關120亦可為pMOSFET的實施方式，也就是說開關120可在較低的致能電壓準位下導通，並在較高的禁能電壓準位下截止。而電壓調整電路可將禁能電壓準位調升，以加大致能電壓準位與禁能電壓準位間的電壓差，進而改善開關120漏電流的問題。 Although the above-mentioned implementation is only described with the switch 120 as an nMOSFET implementation, that is, the switch 120 can be turned on at a high voltage and disabled at a low voltage, and the voltage adjustment circuits 31 and 41 are used as nMOSFETs. However, the present invention is not limited thereto. Of course, those skilled in the art can make changes or modifications to the above according to different design requirements, and all of them belong to the scope of the present invention. For example, the switch 120 can also be implemented as a pMOSFET, that is to say, the switch 120 can be turned on at a lower enabling voltage level and turned off at a higher disabling voltage level. The voltage adjustment circuit can increase the disable voltage level to increase the voltage difference between the enable voltage level and the disable voltage level, thereby improving the leakage current of the switch 120 .

綜上所述，本發明的顯示裝置及電壓調整電路可有效改善應用於電濕潤顯示單元的漏電流問題，有效改善顯示裝置的顯示品質。並且，顯示裝置及電壓調整電路可有效避免電路中的電晶體被長時間承受高壓操作，故可有效避免使用特殊製程的高壓電晶體，有效降低顯示裝置及電壓調整電路的製造成本。 To sum up, the display device and the voltage regulation circuit of the present invention can effectively improve the leakage current problem of the electrowetting display unit, and effectively improve the display quality of the display device. Moreover, the display device and the voltage adjustment circuit can effectively prevent the transistors in the circuit from being subjected to high-voltage operation for a long time, thus effectively avoiding the use of high-voltage transistors with special manufacturing processes, and effectively reducing the manufacturing cost of the display device and the voltage adjustment circuit.

1:顯示裝置 1: Display device

10:閘極訊號電路 10: Gate signal circuit

11:電壓調整電路 11: Voltage adjustment circuit

12:畫素電路 12: Pixel circuit

120:開關 120: switch

121:顯示單元 121: Display unit

VC:開關控制訊號 VC: switch control signal

VD:資料訊號 VD: data signal

VG:閘極控制訊號 VG: gate control signal

VR:第三電壓準位 VR: the third voltage level

VCOM:共同電壓 VCOM: common voltage

Claims

一種顯示裝置，包括：一畫素電路，包括：一顯示單元；以及一開關，用以接收一資料訊號以驅動該顯示單元；一電壓調整電路，耦接該開關的控制端，該電壓調整電路接收多個閘極控制訊號，該些閘極控制訊號在一第一電壓準位及一第二電壓準位間轉態，該電壓調整電路依據一第三電壓準位以將該些閘極控制訊號轉換為一開關控制訊號，該開關控制訊號在該第一電壓準位及一第三電壓準位間轉態，且該第二電壓準位介於該第一電壓準位及該第三電壓準位之間。 A display device, comprising: a pixel circuit, including: a display unit; and a switch, used to receive a data signal to drive the display unit; a voltage adjustment circuit, coupled to the control terminal of the switch, the voltage adjustment circuit receiving a plurality of gate control signals, the gate control signals transition between a first voltage level and a second voltage level, the voltage adjustment circuit controls the gates according to a third voltage level The signal is converted into a switch control signal, the switch control signal transitions between the first voltage level and a third voltage level, and the second voltage level is between the first voltage level and the third voltage between quasi-positions.

如請求項1所述的顯示裝置，其中該顯示單元為一電濕潤顯示(Electrowetting Display,EWD)單元。 The display device according to claim 1, wherein the display unit is an electrowetting display (Electrowetting Display, EWD) unit.

如請求項1所述的顯示裝置，還包括一閘極訊號電路，耦接該電壓調整電路，該閘極訊號電路用以產生在該第一電壓準位及該第二電壓準位間轉態的該些閘極控制訊號。 The display device as described in claim 1, further comprising a gate signal circuit coupled to the voltage adjustment circuit, the gate signal circuit is used to generate a transition between the first voltage level and the second voltage level These gate control signals.

如請求項1所述的顯示裝置，其中該第一電壓準位為一致能電壓準位且該第二電壓準位為一禁能電壓準位，該電壓調整電路將該第二電壓準位調升或調降至該第三電壓準位，以加大該致能電壓準位與該禁能電壓準位間的電壓差。 The display device as claimed in item 1, wherein the first voltage level is an enabling voltage level and the second voltage level is a disabling voltage level, and the voltage adjustment circuit adjusts the second voltage level The third voltage level is increased or decreased to increase the voltage difference between the enabling voltage level and the disabling voltage level.

如請求項1所述的顯示裝置，其中當該開關為一第一導通型態時，該第一電壓準位大於該第二電壓準位且該第二電壓準位大於該第三電壓準位，當該開關為一第二導通型態時，該第一電壓準位小於該第二電壓準位且該第二電壓準位小於該第三電壓準位。 The display device according to claim 1, wherein when the switch is in a first conduction state, the first voltage level is greater than the second voltage level and the second voltage level is greater than the third voltage level , when the switch is in a second conducting state, the first voltage level is lower than the second voltage level and the second voltage level is lower than the third voltage level.

如請求項1所述的顯示裝置，其中該電壓調整電路包括：一上拉電路，耦接一輸出端，該上拉電路依據依序致能的多個閘極控制訊號以控制該開關控制訊號的上拉；以及一下拉電路，耦接該輸出端，該下拉電路依據該些閘極控制訊號，以控制該開關控制訊號的下拉。 The display device as described in claim 1, wherein the voltage adjustment circuit includes: a pull-up circuit coupled to an output terminal, and the pull-up circuit controls the switch control signal according to a plurality of gate control signals enabled in sequence and a pull-down circuit coupled to the output terminal, the pull-down circuit controls the pull-down of the switch control signal according to the gate control signals.

如請求項6所述的顯示裝置，其中該上拉電路包括：一上拉開關，具有第一端、第二端及控制端，該上拉開關的第一端接收一第n級閘極訊號，該上拉開關的第二端耦接該輸出端；一第一上拉電容，耦接該上拉開關的第一端及控制端之間；以及一上拉控制電路，耦接該上拉開關的控制端，該上拉控制電路依據一第n-1級閘極訊號來對該上拉開關的控制端預充電，並且該上拉控制電路依據一第n+1級閘極訊號來對該上拉開關的控制端放電。 The display device according to claim 6, wherein the pull-up circuit includes: a pull-up switch having a first terminal, a second terminal and a control terminal, and the first terminal of the pull-up switch receives an nth-level gate signal , the second terminal of the pull-up switch is coupled to the output terminal; a first pull-up capacitor is coupled between the first terminal of the pull-up switch and the control terminal; and a pull-up control circuit is coupled to the pull-up The control terminal of the switch, the pull-up control circuit precharges the control terminal of the pull-up switch according to an n-1th gate signal, and the pull-up control circuit precharges the pull-up control circuit according to an n+1th gate signal The control terminal of the pull-up switch is discharged.

如請求項7所述的顯示裝置，其中該上拉控制電路包括：一第一電晶體，具有第一端、第二端及控制端，該第一電晶體的第一端接收該第n-1級閘極訊號，該第一電晶體的第二端耦接該上拉開關的控制端，該第一電晶體的控制端接收該第n-1級閘極訊號；以及一第二電晶體，具有第一端、第二端及控制端，該第二電晶體的第一端耦接該上拉開關的控制端，該第二電晶體的第二端接收該第三電壓準位，該第二電晶體的控制端接收該第n+1級閘極訊號。 The display device as described in claim item 7, wherein the pull-up control circuit includes: a first transistor having a first terminal, a second terminal and a control terminal, and the first terminal of the first transistor receives the nth- Level 1 gate signal, the second end of the first transistor is coupled to the control end of the pull-up switch, the control end of the first transistor receives the n-1th level gate signal; and a second transistor , having a first terminal, a second terminal and a control terminal, the first terminal of the second transistor is coupled to the control terminal of the pull-up switch, the second terminal of the second transistor receives the third voltage level, the The control end of the second transistor receives the n+1th level gate signal.

如請求項8所述的顯示裝置，其中該上拉電路還包括一預充電電路，該預充電電路包括：一第三電晶體，具有第一端、第二端及控制端，該第三電晶體的第一端接收一第n-2級閘極控制訊號，該第三電晶體的第二端耦接該第一電晶體的控制端，該第三電晶體的控制端接收該第n-2級閘極控制訊號；以及一上拉電阻，具有第一端及第二端，該上拉電阻的第一端耦接該第一電晶體的控制端，該上拉電阻的第二端接收該第三電壓準位，其中該上拉控制電路還包括一第二上拉電容，耦接該第一電晶體的第一端及控制端之間。 The display device as described in claim 8, wherein the pull-up circuit further includes a pre-charging circuit, and the pre-charging circuit includes: a third transistor having a first terminal, a second terminal and a control terminal, the third transistor The first terminal of the crystal receives an n-2 gate control signal, the second terminal of the third transistor is coupled to the control terminal of the first transistor, and the control terminal of the third transistor receives the n-th gate control signal. Level 2 gate control signal; and a pull-up resistor with a first terminal and a second terminal, the first terminal of the pull-up resistor is coupled to the control terminal of the first transistor, and the second terminal of the pull-up resistor receives The third voltage level, wherein the pull-up control circuit further includes a second pull-up capacitor coupled between the first terminal of the first transistor and the control terminal.

如請求項6所述的顯示裝置，其中該下拉電路包括：一下拉開關，具有第一端、第二端及控制端，該下拉開關的第一端耦接該輸出端，該下拉開關的第二端接收該第三電壓準位；以及一下拉控制電路，耦接該下拉開關的控制端，該下拉控制電路依據該些閘極控制訊號來控制該下拉開關的導通或截止。 The display device as described in claim 6, wherein the pull-down circuit includes: a pull-down switch having a first end, a second end and a control end, the first end of the pull-down switch is coupled to the output end, and the second end of the pull-down switch Two terminals receive the third voltage level; and a pull-down control circuit coupled to the control terminal of the pull-down switch, the pull-down control circuit controls the turn-on or cut-off of the pull-down switch according to the gate control signals.

如請求項10所述的顯示裝置，其中該下拉控制電路包括：一第四電晶體，具有第一端、第二端及控制端，該第四電晶體的第一端耦接該下拉開關的控制端，該第四電晶體的第二端及控制端接收一第n+1級閘極控制訊號。 The display device according to claim 10, wherein the pull-down control circuit includes: a fourth transistor having a first terminal, a second terminal and a control terminal, the first terminal of the fourth transistor is coupled to the pull-down switch The control terminal, the second terminal of the fourth transistor and the control terminal receive an n+1th stage gate control signal.

如請求項11所述的顯示裝置，其中該下拉電路還包括一穩壓電路，耦接該下拉開關的控制端，該穩壓電路包括；一第五電晶體，具有第一端、第二端及控制端，該第五電晶體的第一端耦接該下拉開關的控制端，該第五電晶體的第二端接收該第三電壓準位；一第一下拉電容，具有第一端及第二端，該第一下拉電容的第一端接收一第n-1級閘極控制訊號，該第一下拉電容的第二端耦接該第五電晶體的控制端；一第一下拉電阻，耦接該第五電晶體的控制端與第二端之間；一第六電晶體，具有第一端、第二端及控制端，該第六電晶體的第一端耦接該下拉開關的控制端，該第五電晶體的第二端接收該第三電壓準位；一第二下拉電容，具有第一端及第二端，該第二下拉電容的第一端接收一第n級閘極控制訊號，該第二下拉電容的第二端耦接該第六電晶體的控制端；以及一第二下拉電阻，耦接該第六電晶體的控制端與第二端之間，其中該下拉控制電路還包括一第三下拉電容，耦接該第四電晶體的第一端及控制端之間。 The display device according to claim 11, wherein the pull-down circuit further includes a voltage stabilizing circuit coupled to the control terminal of the pull-down switch, and the voltage stabilizing circuit includes; a fifth transistor having a first end and a second end and a control terminal, the first terminal of the fifth transistor is coupled to the control terminal of the pull-down switch, the second terminal of the fifth transistor receives the third voltage level; a first pull-down capacitor has a first terminal and the second end, the first end of the first pull-down capacitor receives an n-1th level gate control signal, the second end of the first pull-down capacitor is coupled to the control end of the fifth transistor; a pull-down resistor, coupled between the control terminal and the second terminal of the fifth transistor; A sixth transistor, having a first terminal, a second terminal and a control terminal, the first terminal of the sixth transistor is coupled to the control terminal of the pull-down switch, and the second terminal of the fifth transistor receives the third voltage level; a second pull-down capacitor with a first end and a second end, the first end of the second pull-down capacitor receives an nth level gate control signal, and the second end of the second pull-down capacitor is coupled to the first end The control terminal of the six transistors; and a second pull-down resistor coupled between the control terminal of the sixth transistor and the second terminal, wherein the pull-down control circuit also includes a third pull-down capacitor coupled to the fourth transistor Between the first end of the crystal and the control end.

如請求項11所述的顯示裝置，其中該下拉控制電路包括一第七電晶體，具有第一端、第二端及控制端，該第七電晶體的第一端耦接該下拉開關的控制端，該第七電晶體的第二端接收該第三電壓準位，該第七電晶體的控制端接收一第n+2級閘極控制訊號。 The display device as claimed in item 11, wherein the pull-down control circuit includes a seventh transistor with a first terminal, a second terminal and a control terminal, and the first terminal of the seventh transistor is coupled to the control of the pull-down switch terminal, the second terminal of the seventh transistor receives the third voltage level, and the control terminal of the seventh transistor receives an n+2th level gate control signal.