TWI783417B - Semiconductor structure and method of operation - Google Patents

Semiconductor structure and method of operation Download PDF

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TWI783417B
TWI783417B TW110110749A TW110110749A TWI783417B TW I783417 B TWI783417 B TW I783417B TW 110110749 A TW110110749 A TW 110110749A TW 110110749 A TW110110749 A TW 110110749A TW I783417 B TWI783417 B TW I783417B
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field plate
circuit
contact
gate electrode
switch
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TW202238923A (en
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黃紹璋
陳立凡
李慶和
林功凱
莊介堯
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世界先進積體電路股份有限公司
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Abstract

A semiconductor structure including a substrate, a first well, a second well, a first doped region, a second doped region, a gate electrode layer, an insulating layer, a field plate, and a tunable circuit is provided. The first and second wells are disposed on the substrate. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The gate electrode layer is disposed over the substrate. The gate electrode layer, the first doped region and the second doped region constitute a transistor. The insulating layer is disposed over the substrate and covers a portion of the gate electrode layer. The field plate covers the insulating layer and the gate electrode layer. The tunable circuit provides a first short-circuit path between the field plate and the gate electrode layer or provides a second short-circuit path between the field plate and the first doped region.

Description

半導體結構和操作電路Semiconductor structures and operating circuits

本發明係有關於一種半導體結構，特別是有關於一種高壓半導體裝置。The present invention relates to a semiconductor structure, and more particularly to a high voltage semiconductor device.

高壓半導體裝置是利用閘極電壓來產生通道，並控制流經源極與汲極之間的電流。在傳統的高壓半導體裝置中，為了防止源極與汲極之間的擊穿效應(punch-through effect)，必須延長電晶體的通道長度。然而，如此一來會增加裝置的尺寸而使晶片面積增加且會使電晶體的導通電阻(on-resistance，Ron)上升。A high-voltage semiconductor device uses a gate voltage to create a channel and control the current flowing between the source and the drain. In conventional high-voltage semiconductor devices, in order to prevent the punch-through effect between the source and the drain, the channel length of the transistor must be extended. However, this will increase the size of the device, increase the chip area and increase the on-resistance (Ron) of the transistor.

本發明之一實施例提供一種半導體結構，包括一基板、一第一井區、一第二井區、一第一摻雜區、一第二摻雜區、一閘極電極層、一絕緣層、一場板以及一可調電路。基板具有一第一導電型。第一井區形成於基板之上，並具有第一導電型。第二井區形成於基板之上，並具有一第二導電型。第一摻雜區形成於第一井區之中，並具有第二導電型。第二摻雜區形成於第二井區之中，並具有第二導電型。閘極電極層位於基板之上。閘極電極層、第一摻雜區及第二摻雜區構成一電晶體。絕緣層位於基板之上，並重疊部分閘極電極層。場板重疊絕緣層及閘極電極層。可調電路耦接場板、閘極電極層及第一摻雜區，並在場板與閘極電極層之間提供第一短路路徑，或是在場板與第一摻雜區之間提供第二短路路徑。An embodiment of the present invention provides a semiconductor structure, including a substrate, a first well region, a second well region, a first doped region, a second doped region, a gate electrode layer, and an insulating layer , a field board and an adjustable circuit. The substrate has a first conductivity type. The first well region is formed on the substrate and has the first conductivity type. The second well region is formed on the substrate and has a second conductivity type. The first doped region is formed in the first well region and has the second conductivity type. The second doped region is formed in the second well region and has the second conductivity type. The gate electrode layer is located on the substrate. The gate electrode layer, the first doped region and the second doped region form a transistor. The insulating layer is located on the substrate and overlaps part of the gate electrode layer. The field plate overlaps the insulating layer and the gate electrode layer. The adjustable circuit is coupled to the field plate, the gate electrode layer, and the first doped region, and provides a first short-circuit path between the field plate and the gate electrode layer, or provides a circuit between the field plate and the first doped region. Second short circuit path.

本發明另提供一種操作電路，包括一第一電晶體、一第一可調電路、一第二電晶體以及一第二可調電路。第一電晶體形成於一基板的一第一區域之中，並包括一第一場板接觸端、一第一閘極接觸端、一第一源極接觸端。第一可調電路在第一場板接觸端與第一閘極接觸端之間形成一第一短路路徑，或是在第一場板接觸端與第一源極接觸端之間形成一第二短路路徑。第二電晶體形成於基板的一第二區域之中，並包括一第二場板接觸端、一第二閘極接觸端、一第二源極接觸端。第二可調電路在第二場板接觸端與第二閘極接觸端之間形成一第三短路路徑，或是在第二場板接觸端與第二源極接觸端之間形成一第四短路路徑。The present invention further provides an operating circuit, which includes a first transistor, a first adjustable circuit, a second transistor and a second adjustable circuit. The first transistor is formed in a first area of a substrate, and includes a first field plate contact end, a first gate electrode contact end, and a first source electrode contact end. The first adjustable circuit forms a first short circuit path between the first field plate contact end and the first gate electrode contact end, or forms a second short circuit path between the first field plate contact end and the first source electrode contact end short circuit path. The second transistor is formed in a second area of the substrate, and includes a second field plate contact end, a second gate electrode contact end, and a second source electrode contact end. The second adjustable circuit forms a third short-circuit path between the second field plate contact end and the second gate electrode contact end, or forms a fourth short circuit path between the second field plate contact end and the second source electrode contact end. short circuit path.

為讓本發明之目的、特徵和優點能更明顯易懂，下文特舉出實施例，並配合所附圖式，做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中，實施例中的各元件之配置係為說明之用，並非用以限制本發明。另外，實施例中圖式標號之部分重覆，係為了簡化說明，並非意指不同實施例之間的關聯性。In order to make the purpose, features and advantages of the present invention more comprehensible, the following specifically cites the embodiments, together with the accompanying drawings, for a detailed description. The description of the present invention provides different examples to illustrate the technical features of different implementations of the present invention. Wherein, the arrangement of each element in the embodiment is for illustration, not for limiting the present invention. In addition, the partial repetition of the symbols in the figures in the embodiments is for the purpose of simplifying the description, and does not imply the relationship between different embodiments.

第1圖為本發明之半導體結構的示意圖。如圖所示，半導體結構100包括一基板101、井區111、112、摻雜區121、122、一閘極結構140、一絕緣層150以及一場板160。在本實施例中，半導體結構100係為一高壓半導體結構，舉例而言，可接收18V以上的電壓。FIG. 1 is a schematic diagram of a semiconductor structure of the present invention. As shown in the figure, the semiconductor structure 100 includes a substrate 101 , well regions 111 , 112 , doped regions 121 , 122 , a gate structure 140 , an insulating layer 150 and a field plate 160 . In this embodiment, the semiconductor structure 100 is a high-voltage semiconductor structure, for example, capable of receiving a voltage above 18V.

基板101可為一半導體基板，例如是矽基板、磊晶III-V族基板、矽鍺基板、碳化矽基板或矽覆絕緣（silicon-on-insulator, SOI）基板等。另外，基板101可能包括矽、鍺化矽(SiGe)或III-V族元素的半導體材料。在本實施例中，基板101具有一第一導電型。在其它實施例中，一埋層（buried layer：BL)120、第一井區111以及第二井區112設置在基板101內。The substrate 101 can be a semiconductor substrate, such as a silicon substrate, an epitaxial III-V substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate. In addition, the substrate 101 may include silicon, silicon germanium (SiGe), or a semiconductor material of III-V elements. In this embodiment, the substrate 101 has a first conductivity type. In other embodiments, a buried layer (buried layer: BL) 120 , the first well region 111 and the second well region 112 are disposed in the substrate 101 .

井區111及112形成於基板101之中，其中，井區111具有第一導電型。井區112形成於井區111之中，其中井區112具有第二導電型。第一導電型與第二導電型相異。於一實施例中，埋層120例如具有該第二導電類型（如P型）位於井區111與基板101之間，且其摻雜濃度較佳係高於井區112的摻雜濃度。在一可能實施例中，井區111圍繞井區112。Well regions 111 and 112 are formed in the substrate 101 , wherein the well region 111 has a first conductivity type. The well region 112 is formed in the well region 111 , wherein the well region 112 has the second conductivity type. The first conductivity type is different from the second conductivity type. In one embodiment, the buried layer 120 is of the second conductivity type (eg, P type) located between the well region 111 and the substrate 101 , and its doping concentration is preferably higher than that of the well region 112 . In a possible embodiment, the well area 111 surrounds the well area 112 .

摻雜區121形成於井區111之中，並具有第二導電型。在本實施例中，摻雜區121的摻雜濃度高於井區112的摻雜濃度。在一些實施例中，半導體結構100更包括一摻雜區123。摻雜區123形成於井區111之中，並具有第一導電型。摻雜區123的摻雜濃度高於井區111的摻雜濃度。在其它實施例中，可利用一淺溝槽隔離製程(STI)形成一溝槽隔離物131於井區111之中，用以分隔摻雜區121及123。然而，亦可以其它任何適合之方式分隔摻雜區121及123，例如亦可以傳統的區域氧化法(LOCOS)形成場氧化層，用以在井區111隔離摻雜區121及123。The doped region 121 is formed in the well region 111 and has the second conductivity type. In this embodiment, the doping concentration of the doped region 121 is higher than that of the well region 112 . In some embodiments, the semiconductor structure 100 further includes a doped region 123 . The doped region 123 is formed in the well region 111 and has the first conductivity type. The doping concentration of the doped region 123 is higher than that of the well region 111 . In other embodiments, a shallow trench isolation (STI) process may be used to form a trench isolation 131 in the well region 111 to separate the doped regions 121 and 123 . However, the doped regions 121 and 123 can also be separated in any other suitable manner, for example, a field oxide layer can also be formed by a conventional area oxidation method (LOCOS) to isolate the doped regions 121 and 123 in the well region 111 .

摻雜區122形成於井區112之中，並具有第二導電型。在本實施例中，摻雜區122的摻雜濃度高於井區112的摻雜濃度。在一些實施例中，利用淺溝槽隔離製程形成一溝槽隔離物132於井區112及111之中，用以分隔井區111與摻雜區122。在其它實施例中，也可利用區域氧化法形成一場氧化層於井區111與摻雜區123之間。The doped region 122 is formed in the well region 112 and has the second conductivity type. In this embodiment, the doping concentration of the doped region 122 is higher than that of the well region 112 . In some embodiments, a trench isolation 132 is formed in the well regions 112 and 111 by shallow trench isolation process to separate the well region 111 and the doped region 122 . In other embodiments, a field oxide layer may also be formed between the well region 111 and the doped region 123 by using a region oxidation method.

閘極結構140位於基板101之上，並重疊部分的井區111及112。閘極結構140包括一閘極介電層141以及一閘極電極層142。在本實施例中，閘極介電層141係形成於井區111及112之部分表面上。閘極介電層141可包括例如氧化物(oxide)、氮化物(nitride)、氮氧化物(oxynitride)、碳氧化物(oxycarbide)、上述之組合或高介電常數(high-k，介電常數大於8)之介電材料。接著，於閘極介電層141上形成閘極電極層142。在一些實施例中，閘極電極層142係包括矽或多晶矽(polysilicon)。閘極電極層142較佳為摻雜摻質以降低其片電阻(sheet resistance)。在其他實施例中，閘極電極層142係包括非晶矽(amorphous silicon)。此外，閘極電極層142表面也可以具有金屬氮化物或金屬矽化物。在一些實施例中，閘極結構140與摻雜區122之間具有一間隙GP。換句話說，閘極結構140並未接觸摻雜區122。The gate structure 140 is located on the substrate 101 and overlaps part of the well regions 111 and 112 . The gate structure 140 includes a gate dielectric layer 141 and a gate electrode layer 142 . In this embodiment, the gate dielectric layer 141 is formed on part of the surfaces of the well regions 111 and 112 . The gate dielectric layer 141 may include, for example, oxide, nitride, oxynitride, oxycarbide, a combination thereof or a high-k dielectric. Dielectric materials with a constant greater than 8). Next, a gate electrode layer 142 is formed on the gate dielectric layer 141 . In some embodiments, the gate electrode layer 142 includes silicon or polysilicon. The gate electrode layer 142 is preferably doped with dopants to reduce its sheet resistance. In other embodiments, the gate electrode layer 142 includes amorphous silicon. In addition, the surface of the gate electrode layer 142 may also have metal nitride or metal silicide. In some embodiments, there is a gap GP between the gate structure 140 and the doped region 122 . In other words, the gate structure 140 is not in contact with the doped region 122 .

在本實施例中，閘極電極層142、摻雜區121及122構成一電晶體102。本發明並不限定電晶體102的種類。在一可能實施例中，電晶體102係為一橫向擴散金屬氧化物半導體(lateral diffused MOS；LDMOS)電晶體。在此例中，閘極電極層142作為電晶體102的閘極(gate)，摻雜區121作為電晶體102的源極(source)，摻雜區122作為電晶體102的汲極(drain)。在其它實施例中，電晶體102更包括摻雜區123。在此例中，摻雜區123作為電晶體102的基極(bulk)。In this embodiment, the gate electrode layer 142 , the doped regions 121 and 122 form a transistor 102 . The invention does not limit the type of the transistor 102 . In a possible embodiment, the transistor 102 is a lateral diffused MOS (LDMOS) transistor. In this example, the gate electrode layer 142 is used as the gate of the transistor 102, the doped region 121 is used as the source of the transistor 102, and the doped region 122 is used as the drain of the transistor 102. . In other embodiments, the transistor 102 further includes a doped region 123 . In this example, the doped region 123 serves as the bulk of the transistor 102 .

絕緣層150位於基板101之上，並重疊部分的閘極結構140。在本實施例中，絕緣層150重疊並直接接觸部分的摻雜區122、部分的井區122以及部分的閘極電極層142。絕緣層150之材料包括氧化物、氮化物、氮氧化物、低介電常數材料、其它任何適合之絕緣材料、或上述之組合，且可藉由上述化學氣相沉積步驟形成。在一些實施例中，絕緣層150與閘極介電層141係在不同的步驟形成，但並非用以限制本發明。在其它實施例中，絕緣層150與閘極介電層141係在同一步驟(如化學氣相沉積步驟)形成。在本實施例中，絕緣層150的厚度大於閘極介電層141的厚度。The insulating layer 150 is located on the substrate 101 and overlaps part of the gate structure 140 . In this embodiment, the insulating layer 150 overlaps and directly contacts part of the doped region 122 , part of the well region 122 and part of the gate electrode layer 142 . The material of the insulating layer 150 includes oxide, nitride, oxynitride, low dielectric constant material, any other suitable insulating material, or a combination thereof, and can be formed by the aforementioned chemical vapor deposition steps. In some embodiments, the insulating layer 150 and the gate dielectric layer 141 are formed in different steps, but this is not intended to limit the invention. In other embodiments, the insulating layer 150 and the gate dielectric layer 141 are formed in the same step (such as a chemical vapor deposition step). In this embodiment, the thickness of the insulating layer 150 is greater than the thickness of the gate dielectric layer 141 .

場板160位於絕緣層150之上，並重疊部分的摻雜區122及閘極介電層141。在本實施例中，場板160直接接觸絕緣層150並重疊部分的絕緣層150。場板160用以均勻化電場的分佈。在一可能實施例中，場板160的係為一導體，其材料包括金屬(metal)或矽。The field plate 160 is located on the insulating layer 150 and overlaps a portion of the doped region 122 and the gate dielectric layer 141 . In this embodiment, the field plate 160 directly contacts the insulating layer 150 and overlaps a part of the insulating layer 150 . The field plate 160 is used to homogenize the distribution of the electric field. In a possible embodiment, the field plate 160 is a conductor, and its material includes metal or silicon.

在一些實施例中，半導體結構100更包括一絕緣層170。絕緣層170覆蓋井區111、112、摻雜區121~123、溝槽隔離物131、132、閘極結構140、絕緣層150及場板160。因此，場板160與閘極介電層141位於同一絕緣層之中。在一些實施例中，絕緣層150與170係在不同的步驟形成。舉例而言，在形成絕緣層150後，先在絕緣層150之上形成場板160後，才形成絕緣層170。In some embodiments, the semiconductor structure 100 further includes an insulating layer 170 . The insulating layer 170 covers the well regions 111 , 112 , the doped regions 121 - 123 , the trench spacers 131 , 132 , the gate structure 140 , the insulating layer 150 and the field plate 160 . Therefore, the field plate 160 is located in the same insulating layer as the gate dielectric layer 141 . In some embodiments, insulating layers 150 and 170 are formed in different steps. For example, after the insulating layer 150 is formed, the insulating layer 170 is formed after the field plate 160 is formed on the insulating layer 150 .

在一些實施例中，半導體結構100更包括線路層190。線路層190具有一可調電路(tunable circuit)191、內連線L1~L3以及電極E1~E5。電極E1透過貫孔(through hole)181，電性連接摻雜區122。在一可能實施例中，電極E1作為電晶體102的汲極接觸端。電極E2透過貫孔182，電性連接場板160。在一可能實施例中，電極E2作為電晶體102的場板接觸端。電極E3透過貫孔183，電性連接閘極電極層142。在一可能實施例中，電極E3作為電晶體102的閘極接觸端。電極E4透過貫孔184，電性連接摻雜區121。在一可能實施例中，電極E4作為電晶體102的源極接觸端。電極E5透過貫孔185，電性連接摻雜區123。在一可能實施例中，電極E5作為電晶體102的基極接觸端。In some embodiments, the semiconductor structure 100 further includes a circuit layer 190 . The circuit layer 190 has a tunable circuit (tunable circuit) 191 , interconnections L1 - L3 and electrodes E1 - E5 . The electrode E1 is electrically connected to the doped region 122 through a through hole 181 . In a possible embodiment, the electrode E1 serves as a drain contact terminal of the transistor 102 . The electrode E2 is electrically connected to the field plate 160 through the through hole 182 . In a possible embodiment, the electrode E2 serves as a field plate contact terminal of the transistor 102 . The electrode E3 is electrically connected to the gate electrode layer 142 through the through hole 183 . In a possible embodiment, the electrode E3 serves as a gate contact terminal of the transistor 102 . The electrode E4 is electrically connected to the doped region 121 through the through hole 184 . In a possible embodiment, the electrode E4 serves as a source contact terminal of the transistor 102 . The electrode E5 is electrically connected to the doped region 123 through the through hole 185 . In a possible embodiment, the electrode E5 serves as a base contact terminal of the transistor 102 .

在本實施例中，可調電路191透過內連線L1~L3，電性連接電極E2~E4。在此例中，可調電路191可能在場板160與閘極電極層142之間提供一第一短路路徑，或是在場板160與摻雜區121之間提供一第二短路路徑。當場板160與閘極電極層142之間具有第一短路路徑時，場板160的電位將相同於閘極電極層142的電位。此時，電晶體102具有第一導通電阻(Ron)以及第一閘極電荷值(Gate charge；Qg)。當場板160與摻雜區121之間具有第二短路路徑時，場板160的電位將相同於摻雜區121的電壓。此時，電晶體102具有第二導通電阻以及第二閘極電荷值。在此例中，第一導通電阻小於第二導通電阻，第二閘極電荷值小於第一閘極電荷值。In this embodiment, the adjustable circuit 191 is electrically connected to the electrodes E2-E4 through the interconnection lines L1-L3. In this example, the adjustable circuit 191 may provide a first short circuit between the field plate 160 and the gate electrode layer 142 , or provide a second short circuit between the field plate 160 and the doped region 121 . When there is a first short-circuit path between the field plate 160 and the gate electrode layer 142 , the potential of the field plate 160 will be the same as that of the gate electrode layer 142 . At this time, the transistor 102 has a first on-resistance (Ron) and a first gate charge (Gate charge; Qg). When there is a second short-circuit path between the field plate 160 and the doped region 121 , the potential of the field plate 160 will be the same as the voltage of the doped region 121 . At this time, the transistor 102 has a second on-resistance and a second gate charge value. In this example, the first on-resistance is smaller than the second on-resistance, and the second gate charge value is smaller than the first gate charge value.

本發明並不限定可調電路191的架構。在一可能實施例中，可調電路191根據一控制信號(未顯示)，導通電極E2與E3之間的第一短路路徑，或是導通電極E2與E4之間的第二短路路徑。當可調電路191導通電極E2與E3之間的第一短路路徑時，場板160的電位等於閘極電極層142的電位。當可調電路191導通電極E2與E4之間的第二短路路徑時，場板160的電位等於摻雜區121的電位。The present invention does not limit the architecture of the adjustable circuit 191 . In a possible embodiment, the adjustable circuit 191 turns on the first short-circuit path between the electrodes E2 and E3 or turns on the second short-circuit path between the electrodes E2 and E4 according to a control signal (not shown). When the adjustable circuit 191 conducts the first short-circuit path between the electrodes E2 and E3 , the potential of the field plate 160 is equal to the potential of the gate electrode layer 142 . When the adjustable circuit 191 conducts the second short-circuit path between the electrodes E2 and E4 , the potential of the field plate 160 is equal to the potential of the doped region 121 .

在其它實施例中，線路層190更包括一內連線L4。內連線L4可能電性連接電極E4及E5。在一些實施例中，內連線L1~L4的材料可包括銅、鋁、鎢、摻雜多晶矽、其它任何適合之導電材料、或上述之組合。In other embodiments, the circuit layer 190 further includes an interconnection line L4. The interconnection line L4 may be electrically connected to the electrodes E4 and E5. In some embodiments, the material of the interconnections L1 - L4 may include copper, aluminum, tungsten, doped polysilicon, any other suitable conductive material, or a combination thereof.

第2圖為本發明之半導體結構100的等效電路示意圖。如圖所示，半導體結構100包括一電晶體102以及一可調電路191。電晶體102的摻雜區122電性連接電極E1(或稱汲極接觸端)。在本實施例中，電極E1耦接一接觸墊(pad)210。接觸墊210用以接收一控制電壓。在一可能實施例中，控制電壓約為40V。FIG. 2 is a schematic diagram of an equivalent circuit of the semiconductor structure 100 of the present invention. As shown in the figure, the semiconductor structure 100 includes a transistor 102 and an adjustable circuit 191 . The doped region 122 of the transistor 102 is electrically connected to the electrode E1 (or called the drain contact). In this embodiment, the electrode E1 is coupled to a contact pad (pad) 210 . The contact pad 210 is used for receiving a control voltage. In one possible embodiment, the control voltage is about 40V.

電晶體102的場板160電性連接電極E2(或稱場板接觸端)。電極E2耦接可調電路191。電晶體102的閘極電極層142電性連接電極E3(或稱閘極接觸端)。電極E3耦接一控制電路220。控制電路220用以提供一閘極電壓予電極E3。藉由控制電極E1、E3及E4的電位，便可導通或不導通電晶體102。電晶體102的摻雜區121電性連接電極E4(或稱源極接觸端)。電極E4接收一接地電壓GND。電晶體102的摻雜區123電性連接電極E5(或稱基極接觸端)。電極E5耦接電極E4。The field plate 160 of the transistor 102 is electrically connected to the electrode E2 (or called the field plate contact end). The electrode E2 is coupled to the adjustable circuit 191 . The gate electrode layer 142 of the transistor 102 is electrically connected to the electrode E3 (or called the gate contact terminal). The electrode E3 is coupled to a control circuit 220 . The control circuit 220 is used to provide a gate voltage to the electrode E3. By controlling the potentials of the electrodes E1 , E3 and E4 , the transistor 102 can be turned on or off. The doped region 121 of the transistor 102 is electrically connected to the electrode E4 (or called the source contact). The electrode E4 receives a ground voltage GND. The doped region 123 of the transistor 102 is electrically connected to the electrode E5 (or called the base contact). The electrode E5 is coupled to the electrode E4.

在本實施例中，可調電路191可能根據一控制信號SIG，導通電極E2與E3之間的一第一短路路徑，或是導通電極E2與E4之間的一第二短路路徑。本發明並不限定控制信號SIG的來源。在一可能實施例中，控制信號SIG可能來自一次性寫入記憶體(one time programmable；OTP)電路或是多次寫入記憶體(multiple time programmable；MTP)電路。In this embodiment, the adjustable circuit 191 may conduct a first short-circuit path between the electrodes E2 and E3 or a second short-circuit path between the electrodes E2 and E4 according to a control signal SIG. The invention does not limit the source of the control signal SIG. In a possible embodiment, the control signal SIG may come from a one time programmable (OTP) circuit or a multiple time programmable (MTP) circuit.

另外，本發明並不限定可調電路191的架構。任何可根據一控制信號，提供兩不同的短路路徑的電路，均可作為可調電路191。在一可能實施例中，可調電路191包括開關電路SW1及SW2。開關電路SW1耦接於電極E2與E3之間，用以在電極E2與E3之間形成一第一短路路徑。開關電路SW2耦接於電極E2與E4之間，用以在電極E2與E4之間提供一第二短路路徑。在一些實施例中，可調電路191不會同時導通第一及第二短路路徑。In addition, the present invention does not limit the architecture of the adjustable circuit 191 . Any circuit that can provide two different short-circuit paths according to a control signal can be used as the adjustable circuit 191 . In a possible embodiment, the adjustable circuit 191 includes switch circuits SW1 and SW2. The switch circuit SW1 is coupled between the electrodes E2 and E3 for forming a first short circuit path between the electrodes E2 and E3. The switch circuit SW2 is coupled between the electrodes E2 and E4 for providing a second short circuit path between the electrodes E2 and E4. In some embodiments, the adjustable circuit 191 does not conduct the first and second short-circuit paths simultaneously.

舉例而言，當控制信號SIG等於一第一位準(如高位準)時，開關電路SW1導通，開關電路SW2不導通。在此例中，由於開關電路SW1導通，故在電極E2與E3之間具有一第一短路路徑。因此，電極E2與E3具有相同的電位。此時，電晶體102具有第一導通電阻以及第一閘極電荷值。在此例中，由於開關電路SW2不導通，故開關電路SW2並未在電極E2與E4之間提供第二短路路徑。For example, when the control signal SIG is equal to a first level (such as a high level), the switch circuit SW1 is turned on, and the switch circuit SW2 is not turned on. In this example, since the switch circuit SW1 is turned on, there is a first short-circuit path between the electrodes E2 and E3. Therefore, electrodes E2 and E3 have the same potential. At this time, the transistor 102 has a first on-resistance and a first gate charge value. In this example, since the switch circuit SW2 is not conducting, the switch circuit SW2 does not provide the second short circuit path between the electrodes E2 and E4.

當控制信號SIG等於一第二位準(如低位準)時，開關電路SW1不導通，開關電路SW2導通。在此例中，由於開關電路SW2導通，故電極E2與E4之間具有一第二短路路徑。因此，電極E2的電位等於電極E4的電位，並且電晶體102具有第二導通電阻以及第二閘極電荷值。在一可能實施例中，第一導通電阻小於第二導通電阻，第二閘極電荷值小於第一閘極電荷值。在電極E2與E4之間具有第二短路路徑時，開關電路SW1不導通。因此，開關電路SW1並未在電極E2與E3之間形成第一短路路徑。When the control signal SIG is equal to a second level (such as a low level), the switch circuit SW1 is not turned on, and the switch circuit SW2 is turned on. In this example, since the switch circuit SW2 is turned on, there is a second short-circuit path between the electrodes E2 and E4. Therefore, the potential of the electrode E2 is equal to the potential of the electrode E4, and the transistor 102 has a second on-resistance and a second gate charge value. In a possible embodiment, the first on-resistance is smaller than the second on-resistance, and the second gate charge value is smaller than the first gate charge value. When there is a second short-circuit path between the electrodes E2 and E4, the switch circuit SW1 is not turned on. Therefore, the switch circuit SW1 does not form the first short circuit path between the electrodes E2 and E3.

在本實施例中，開關電路SW1及SW2接收同一控制信號，但並非用以限制本發明。在其它實施例中，開關電路SW1及SW2接收不同的控制信號。在此例中，當開關電路SW1於電極E2及E3間提供第一短路路徑時，開關電路SW2不在電極E2與E4之間提供第二短路路徑。當開關電路SW2於電極E2及E4間提供第二短路路徑時，開關電路SW1不在電極E2與E3之間提供第一短路路徑。In this embodiment, the switch circuits SW1 and SW2 receive the same control signal, but this is not intended to limit the present invention. In other embodiments, the switch circuits SW1 and SW2 receive different control signals. In this example, when the switch circuit SW1 provides the first short circuit path between the electrodes E2 and E3, the switch circuit SW2 does not provide the second short circuit path between the electrodes E2 and E4. When the switch circuit SW2 provides the second short circuit path between the electrodes E2 and E4, the switch circuit SW1 does not provide the first short circuit path between the electrodes E2 and E3.

第3圖為本發明之可調電路的一可能實施例。在本實施例中，開關電路SW1包括一反相器IV1、開關T1及T2。反相器IV1反相控制信號SIG，用以產生一反相信號SV1。開關T1耦接於電極E2與E3之間，並接收反相信號SV1。開關T2耦接於電極E2與E3之間，並接收控制信號SIG。本發明並不限定開關T1與T2的種類。在一可能實施例中，開關T1為一N型電晶體，開關T2為一P型電晶體。在此例中，開關T1的基極接收一接地電壓GND，開關T2的基極接收一高操作電壓VP。當控制信號SIG等於第一位準(如高位準)時，開關T1與T2不導通。當控制信號SIG等於第二位準(如低位準)時，開關T1與T2導通。因此，電極E2的電位等於電極E3的電位。Fig. 3 is a possible embodiment of the adjustable circuit of the present invention. In this embodiment, the switch circuit SW1 includes an inverter IV1, switches T1 and T2. The inverter IV1 inverts the control signal SIG to generate an inverted signal SV1. The switch T1 is coupled between the electrodes E2 and E3 and receives the inverted signal SV1 . The switch T2 is coupled between the electrodes E2 and E3 and receives the control signal SIG. The invention does not limit the types of the switches T1 and T2. In a possible embodiment, the switch T1 is an N-type transistor, and the switch T2 is a P-type transistor. In this example, the base of the switch T1 receives a ground voltage GND, and the base of the switch T2 receives a high operating voltage VP. When the control signal SIG is equal to the first level (eg high level), the switches T1 and T2 are not turned on. When the control signal SIG is equal to the second level (eg low level), the switches T1 and T2 are turned on. Therefore, the potential of the electrode E2 is equal to the potential of the electrode E3.

開關電路SW2包括一反相器IV2、開關T3及T4。反相器IV2反相控制信號SIG，用以產生一反相信號SV2。開關T3耦接於電極E2與E4之間，並接收控制信號SIG。開關T4耦接於電極E2與E4之間，並接收反相信號SV2。本發明並不限定開關T3與T4的種類。在一可能實施例中，開關T3為一N型電晶體，開關T4為一P型電晶體。在此例中，開關T3的基極接收接地電壓GND，開關T4的基極接收高操作電壓VP。當控制信號SIG等於第一位準(如高位準)時，開關T3與T4導通。因此，電極E2的電位等於電極E4的電位。當控制信號SIG等於第二位準(如低位準)時，開關T3與T4不導通。The switch circuit SW2 includes an inverter IV2, switches T3 and T4. The inverter IV2 inverts the control signal SIG to generate an inverted signal SV2. The switch T3 is coupled between the electrodes E2 and E4 and receives the control signal SIG. The switch T4 is coupled between the electrodes E2 and E4, and receives the inverted signal SV2. The present invention does not limit the types of the switches T3 and T4. In a possible embodiment, the switch T3 is an N-type transistor, and the switch T4 is a P-type transistor. In this example, the base of the switch T3 receives the ground voltage GND, and the base of the switch T4 receives the high operating voltage VP. When the control signal SIG is equal to the first level (eg high level), the switches T3 and T4 are turned on. Therefore, the potential of the electrode E2 is equal to the potential of the electrode E4. When the control signal SIG is equal to the second level (eg low level), the switches T3 and T4 are not turned on.

第4圖為本發明之半導體結構的另一示意圖。半導體結構400包括一基板410。基板410具有區域411~414。本發明並不限定區域的數量。在其它實施例中，基板410被劃分成更多或更少的區域。在本實施例中，區域411~414之每一者的結構相似於第1圖所示的半導體結構100。FIG. 4 is another schematic diagram of the semiconductor structure of the present invention. The semiconductor structure 400 includes a substrate 410 . The substrate 410 has regions 411 - 414 . The present invention does not limit the number of regions. In other embodiments, the substrate 410 is divided into more or fewer regions. In this embodiment, the structure of each of the regions 411 - 414 is similar to the semiconductor structure 100 shown in FIG. 1 .

區域411~414之每一者具有複數電晶體。為方便說明，第4圖僅顯示電晶體420、430、440及450。電晶體420、430、440及450分別位於區域411~414之中。在一可能實施例中，電晶體420、430、440及450係為矽電晶體(silicon MOS)，例如橫向擴散金屬氧化物半導體電晶體，或高電子遷移率電晶體(HEMT)， 例如氮化鎵高電子遷移率電晶體。在本實施例中，由於電晶體420、430、440及450的結構相同於第1圖的電晶體102的結構，故不再贅述。Each of the regions 411-414 has a plurality of transistors. For convenience of illustration, only transistors 420 , 430 , 440 and 450 are shown in FIG. 4 . The transistors 420 , 430 , 440 and 450 are respectively located in the areas 411 - 414 . In one possible embodiment, transistors 420, 430, 440, and 450 are silicon MOS transistors, such as laterally diffused metal oxide semiconductor transistors, or high electron mobility transistors (HEMT), such as nitride Gallium High Electron Mobility Transistor. In this embodiment, since the structures of the transistors 420 , 430 , 440 and 450 are the same as the structure of the transistor 102 in FIG. 1 , details are not repeated here.

電晶體420位於區域411之中，並具有一閘極接觸端G1、一汲極接觸端D1、一源極接觸端S1、一基極接觸端B1以及一場板接觸端F1。電晶體420根據閘極接觸端G1、汲極接觸端D1以及源極接觸端S1的電位而動作。在一些實施例中，基極接觸端B1可能電性連接源極接觸端S1。在此例中，一第一可調電路(未顯示)於場板接觸端F1和閘極接觸端G1之間設置一短路路徑。因此，場板接觸端F1電性連接閘極接觸端G1，但並非用以限制本發明。在其它實施例中，第一可調電路可能在場板接觸端F1與源極接觸端S1之間設置一短路路徑。在一些實施例中，第一可調電路可能位於區域411之中。The transistor 420 is located in the region 411 and has a gate contact G1 , a drain contact D1 , a source contact S1 , a base contact B1 and a field plate contact F1 . The transistor 420 operates according to the potentials of the gate terminal G1 , the drain terminal D1 and the source terminal S1 . In some embodiments, the base contact terminal B1 may be electrically connected to the source contact terminal S1. In this example, a first adjustable circuit (not shown) provides a short circuit path between the field plate contact F1 and the gate contact G1. Therefore, the field plate contact terminal F1 is electrically connected to the gate contact terminal G1, but this is not intended to limit the invention. In other embodiments, the first adjustable circuit may provide a short-circuit path between the field plate contact F1 and the source contact S1 . In some embodiments, the first tunable circuit may be located in region 411 .

電晶體430位於區域412之中，並具有一閘極接觸端G2、一汲極接觸端D2、一源極接觸端S2、一基極接觸端B2以及一場板接觸端F2。電晶體430根據閘極接觸端G2、汲極接觸端D2以及源極接觸端S2的電位而動作。在一些實施例中，基極接觸端B2可能電性連接源極接觸端S2。在此例中，一第二可調電路(未顯示)於場板接觸端F2和源極接觸端S2之間設置一短路路徑。因此，場板接觸端F2電性連接源極接觸端S2。在此例中，導通電晶體430所需的閘極電荷值小於導通電晶體420所需的閘極電荷值。因此，電晶體430具有較快的切換速度。在其它實施例中，第二可調電路可能於場板接觸端F2和閘極接觸端G2之間設置一短路路徑。在一些實施例中，第二可調電路可能位於區域412之中。The transistor 430 is located in the region 412 and has a gate contact G2 , a drain contact D2 , a source contact S2 , a base contact B2 and a field plate contact F2 . The transistor 430 operates according to the potentials of the gate terminal G2 , the drain terminal D2 and the source terminal S2 . In some embodiments, the base contact terminal B2 may be electrically connected to the source contact terminal S2. In this example, a second adjustable circuit (not shown) provides a short circuit path between the field plate contact F2 and the source contact S2. Therefore, the field plate contact F2 is electrically connected to the source contact S2. In this example, the gate charge required to turn on transistor 430 is less than the gate charge required to turn on transistor 420 . Therefore, the transistor 430 has a faster switching speed. In other embodiments, the second adjustable circuit may provide a short circuit path between the field plate contact F2 and the gate contact G2. In some embodiments, a second tunable circuit may be located in region 412 .

電晶體440位於區域413之中，並具有一閘極接觸端G3、一汲極接觸端D3、一源極接觸端S3、一基極接觸端B3以及一場板接觸端F3。電晶體440根據閘極接觸端G3、汲極接觸端D3以及源極接觸端S3的電位而動作。在一些實施例中，基極接觸端B3可能電性連接源極接觸端S3。在本實施例中，一第三可調電路(未顯示)於場板接觸端F3和閘極接觸端G3之間設置一短路路徑。因此，場板接觸端F3電性連接閘極接觸端G3。在此例中，電晶體440的導通電阻及閘極電荷值相似於電晶體420的導通電阻及閘極電荷值。在一可能實施例中，電晶體440的導通電阻小於電晶體430的導通電阻。因此，電晶體440的功耗低於電晶體430。在其它實施例中，第三可調電路可能在場板接觸端F3與源極接觸端S3之間設置一短路路徑。在一些實施例中，第三可調電路可能位於區域413之中。The transistor 440 is located in the region 413 and has a gate contact G3 , a drain contact D3 , a source contact S3 , a base contact B3 and a field plate contact F3 . The transistor 440 operates according to the potentials of the gate terminal G3 , the drain terminal D3 and the source terminal S3 . In some embodiments, the base contact terminal B3 may be electrically connected to the source contact terminal S3. In this embodiment, a third adjustable circuit (not shown) provides a short-circuit path between the field plate contact F3 and the gate contact G3. Therefore, the field plate contact F3 is electrically connected to the gate contact G3. In this example, the on-resistance and gate charge values of transistor 440 are similar to the on-resistance and gate charge values of transistor 420 . In a possible embodiment, the on-resistance of the transistor 440 is smaller than the on-resistance of the transistor 430 . Therefore, the power consumption of transistor 440 is lower than that of transistor 430 . In other embodiments, the third adjustable circuit may provide a short circuit path between the field plate contact F3 and the source contact S3. In some embodiments, a third tunable circuit may be located in region 413 .

電晶體450位於區域414之中，並具有一閘極接觸端G4、一汲極接觸端D4、一源極接觸端S4、一基極接觸端B4以及一場板接觸端F4。電晶體450根據閘極接觸端G4、汲極接觸端D4以及源極接觸端S4的電位而動作。在一些實施例中，基極接觸端B4可能電性連接源極接觸端S4。在本實施例中，一第四可調電路(未顯示)於場板接觸端F4和源極接觸端S4之間設置一短路路徑。因此，場板接觸端F4電性連接源極接觸端S4。在此例中，電晶體450的導通電阻及閘極電荷值相似於電晶體430的導通電阻及閘極電荷值。另外，電晶體450的閘極電荷值小於電晶體420及440的閘極電荷值。在其它實施例中，第四可調電路可能在場板接觸端F4與閘極接觸端G4之間設置一短路路徑。第四可調電路可能位於區域414之中。The transistor 450 is located in the area 414 and has a gate contact G4 , a drain contact D4 , a source contact S4 , a base contact B4 and a field plate contact F4 . The transistor 450 operates according to the potentials of the gate terminal G4 , the drain terminal D4 and the source terminal S4 . In some embodiments, the base contact terminal B4 may be electrically connected to the source contact terminal S4. In this embodiment, a fourth adjustable circuit (not shown) provides a short-circuit path between the field plate contact F4 and the source contact S4. Therefore, the field plate contact F4 is electrically connected to the source contact S4. In this example, the on-resistance and gate charge values of transistor 450 are similar to the on-resistance and gate charge values of transistor 430 . In addition, the gate charge of the transistor 450 is smaller than the gate charges of the transistors 420 and 440 . In other embodiments, the fourth adjustable circuit may provide a short circuit path between the field plate contact F4 and the gate contact G4. A fourth tunable circuit may be located in region 414 .

在第4圖中，由於基板410被切分成區域411~414，並且區域411及413的電晶體的場板接觸端電性連接至閘極接觸端，故在基板410中，大約有50%的電晶體係屬於金屬至閘極(metal to gate；MTG)架構。另外，由於區域412及414的電晶體的場板接觸端電性連接至源極接觸端，故在基板410中，大約有50%的電晶體係屬於金屬至源極(metal to source；MTS)架構。In FIG. 4, since the substrate 410 is divided into regions 411-414, and the field plate contacts of the transistors in the regions 411 and 413 are electrically connected to the gate contacts, in the substrate 410, about 50% The transistor system belongs to the metal to gate (MTG) architecture. In addition, since the field plate contacts of the transistors in the regions 412 and 414 are electrically connected to the source contacts, about 50% of the transistors in the substrate 410 are metal to source (MTS) architecture.

由於金屬至閘極(MTG)架構的電晶體具有較低的導通電阻，故金屬至閘極架構的電晶體的功耗較低。金屬至源極(MTS)架構的電晶體具有較低的閘極電荷值，故金屬至源極架構的電晶體的切換速度較快。由於品質因素(figure of merit；FOM)正比於導通電阻及閘極電荷值的乘積，故基板410具有較佳的品質因素。Metal-to-gate (MTG) transistors consume less power because they have lower on-resistance. The metal-to-source (MTS) transistor has a lower gate charge value, so the switching speed of the metal-to-source transistor is faster. Since the figure of merit (FOM) is proportional to the product of the on-resistance and the gate charge value, the substrate 410 has a better figure of merit.

在其它實施例中，可能只有單一區域的電晶體的場板接觸端電性連接至閘極接觸端。在此例中，具有MTG架構的電晶體的數量約為所有電晶體的25%。在另一可能實施例中，如果有三區域的電晶體的場板接觸端電性連接至閘極接觸端，則具有MTG架構的電晶體的數量約為所有電晶體的75%。如果所有區域(如411~414)的電晶體的場板接觸端電性連接至閘極接觸端，則具有MTG架構的電晶體的數量約為所有電晶體的100%。然而，如果區域411~414的電晶體的場板接觸端均未電性連接至閘極接觸端，則具有MTG架構的電晶體的數量約為所有電晶體的0%。因此，使用者可依照實際應用，可調整MTG及MTS架構的電晶體數量，進而優化品質因素，使得元件具有較高的效率。In other embodiments, only a single region of the transistor may have the field plate contact electrically connected to the gate contact. In this example, the number of transistors with MTG architecture is about 25% of all transistors. In another possible embodiment, if the field plate contacts of the transistors with three regions are electrically connected to the gate contacts, the number of transistors with MTG structure is about 75% of all transistors. If the field plate contacts of the transistors in all areas (such as 411-414) are electrically connected to the gate contacts, the number of transistors with MTG structure is about 100% of all transistors. However, if the field plate contacts of the transistors in regions 411-414 are not electrically connected to the gate contacts, the number of transistors with MTG structure is approximately 0% of all transistors. Therefore, the user can adjust the number of transistors in the MTG and MTS structures according to the actual application, and then optimize the quality factor, so that the device has higher efficiency.

本發明並不限定MTG架構的電晶體的所在區域。如果具有MTG架構的電晶體的數量被限制在50%時，則可藉由調整前述之控制信號SIG，使得在區域411~414之任兩區域中具有MTG架構的電晶體。在本實施例中，由於區域411及413的可調電路(未顯示)根據控制信號SIG，導通場板接觸端F1與閘極接觸端G1之間的短路路徑以及場板接觸端F3與閘極接觸端G3之間的短路路徑，故區域411及413具有MTG架構的電晶體。在其它實施例中，如果區域411及412的可調電路(未顯示)根據控制信號SIG，導通場板接觸端F1與閘極接觸端G1之間的短路路徑以及場板接觸端F2與閘極接觸端G2之間的短路路徑，則區域411及412具有MTG架構的電晶體。同樣地，如果區域411及414可調電路(未顯示)根據控制信號SIG，導通場板接觸端F1與閘極接觸端G1之間的短路路徑以及場板接觸端F4與閘極接觸端G4之間的短路路徑，則區域411及414具有MTG架構的電晶體。換言之，MTG架構或MTS架構可隨相對應的可調電路的控制信號SIG不同而做動態調整。 The present invention does not limit the area where the transistors of the MTG structure are located. If the number of transistors with MTG structure is limited to 50%, the aforementioned control signal SIG can be adjusted so that any two regions of regions 411-414 have transistors with MTG structure. In this embodiment, since the adjustable circuit (not shown) in the regions 411 and 413 is based on the control signal SIG, the short circuit path between the field plate contact terminal F1 and the gate contact terminal G1 and the field plate contact terminal F3 and the gate electrode are turned on. There is a short path between the contacts G3, so the regions 411 and 413 have transistors with MTG structure. In other embodiments, if the adjustable circuits (not shown) in the regions 411 and 412 turn on the short path between the field plate contact F1 and the gate G1 and the field plate contact F2 and the gate G1 according to the control signal SIG. With a short path between the contacts G2, the regions 411 and 412 have transistors with an MTG structure. Similarly, if the adjustable circuit (not shown) in regions 411 and 414 conducts the short-circuit path between the field plate contact terminal F1 and the gate contact terminal G1 and the connection between the field plate contact terminal F4 and the gate contact terminal G4 according to the control signal SIG If there is a short-circuit path between them, the regions 411 and 414 have transistors of MTG structure. In other words, the MTG architecture or the MTS architecture can be dynamically adjusted according to the control signal SIG of the corresponding adjustable circuit.

在一些實施例中，每一區域裡的短路路徑並非固定不變。舉例而言，當MTG架構的電晶體的數量被限制在50%時，則區域411及413的可調電路(未顯示)根據控制信號SIG，導通場板接觸端F1與閘極接觸端G1之間的短路路徑以及場板接觸端F3與閘極接觸端G3之間的短路路徑。然而，當MTG架構的電晶體的數量被改變限制在25%時，則區域411及413之一者的可調電路根據控制信號SIG，導通場板接觸端與閘極接觸端之間的短路路徑。在此例中，區域411及413的另一者的可調電路可能根據控制信號SIG，導通場板接觸端與源極接觸端之間的短路路徑。在一些實施例中，區域411及413的另一者的可調電路可能不導通場板接觸端與源極接觸端之間的短路路徑以及場板接觸端與閘極接觸端之間的短路路徑。 In some embodiments, the short-circuit paths in each region are not fixed. For example, when the number of transistors in the MTG structure is limited to 50%, the adjustable circuits (not shown) in regions 411 and 413 turn on the connection between the field plate contact terminal F1 and the gate contact terminal G1 according to the control signal SIG. The short circuit path between and the short circuit path between the field plate contact F3 and the gate contact G3. However, when the number of transistors in the MTG structure is limited to 25%, the adjustable circuit in one of the regions 411 and 413 conducts the short-circuit path between the field plate contact and the gate contact according to the control signal SIG . In this example, the adjustable circuit of the other one of the regions 411 and 413 may turn on the short path between the field plate contact and the source contact according to the control signal SIG. In some embodiments, the adjustable circuitry of the other of regions 411 and 413 may not conduct the short path between the field plate contact and the source contact and the short path between the field plate contact and the gate contact .

除非另作定義，在此所有詞彙(包含技術與科學詞彙)均屬本發明所屬技術領域中具有通常知識者之一般理解。此外，除非明白表示，詞彙於一般字典中之定義應解釋為與其相關技術領域之文章中意義一致，而不應解釋為理想狀態或過分正式之語態。雖然“第一”、“第二”等術語可用於描述各種元件，但這些元件不應受這些術語的限制。這些術語只是用以區分一個元件和另一個元件。 Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be understood by those of ordinary skill in the art to which this invention belongs. In addition, unless expressly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in its related technical field, and should not be interpreted as an ideal state or an overly formal voice. Although terms such as 'first' and 'second' may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾。舉例來說，本發明實施例所述之系統、裝置或是方法可以硬體、軟體或硬體以及軟體的組合的實體實施例加以實現。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, device or method described in the embodiments of the present invention can be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

100、400：半導體結構 101、410：基板 111、112：井區 121~123：摻雜區 140：閘極結構 150、170：絕緣層 160：場板 131、132：溝槽隔離物 141：閘極介電層 142：閘極電極層 GP：間隙 102、420、430、440、450：電晶體 190：線路層 191：可調電路 L1~L4：內連線 E1~E5：電極 181~185：貫孔 210：接觸墊 220：控制電路 SIG：控制信號 SW1、SW2：開關電路 GND：接地電壓 T1~T4：開關 IV1、IV2：反相器 SV1、SV2：反相信號 VP：高操作電壓 411~414：區域 F1~F4：場板接觸端 S1~S4：源極接觸端 G1~G4：閘極接觸端 D1~D4：汲極接觸端 B1~B4：基極接觸端 100, 400: Semiconductor structure 101, 410: Substrate 111, 112: well area 121~123: doped area 140: Gate structure 150, 170: insulation layer 160: field plate 131, 132: Trench spacers 141: gate dielectric layer 142: Gate electrode layer GP: Gap 102, 420, 430, 440, 450: Transistor 190: Line layer 191: Adjustable circuit L1~L4: Inner connection E1~E5: electrodes 181~185: through hole 210: contact pad 220: control circuit SIG: control signal SW1, SW2: switch circuit GND: ground voltage T1~T4: switch IV1, IV2: Inverters SV1, SV2: Inversion signal VP: high operating voltage 411~414: area F1~F4: field plate contact terminal S1~S4: Source contacts G1~G4: gate contact terminal D1~D4: Drain contact terminal B1~B4: Base contacts

第1圖為本發明之半導體結構的示意圖。 第2圖為本發明之半導體結構的等效電路示意圖。 第3圖為本發明之可調電路的一可能實施例。 第4圖為本發明之半導體結構的另一示意圖。 FIG. 1 is a schematic diagram of a semiconductor structure of the present invention. Fig. 2 is a schematic diagram of an equivalent circuit of the semiconductor structure of the present invention. Fig. 3 is a possible embodiment of the adjustable circuit of the present invention. FIG. 4 is another schematic diagram of the semiconductor structure of the present invention.

102：電晶體 191：可調電路 210：接觸墊 220：控制電路 SIG：控制信號 SW1、SW2：開關電路 GND：接地電壓 E1~E5：電極 102: Transistor 191: Adjustable circuit 210: contact pad 220: control circuit SIG: control signal SW1, SW2: switch circuit GND: ground voltage E1~E5: electrodes

Claims (12)

一種半導體結構，包括：一基板，具有一第一導電型；一第一井區，形成於該基板之中，並具有該第一導電型；一第二井區，形成於該基板之中，並具有一第二導電型，該第二導電型與該第一導電型互補；一第一摻雜區，形成於該第一井區之中，並具有該第二導電型；一第二摻雜區，形成於該第二井區之中，並具有該第二導電型；一閘極電極層，位於該基板之上，其中該閘極電極層、該第一摻雜區及該第二摻雜區構成一電晶體；一閘極介電層，位於該基板與該閘極電極層之間；一場板，重疊該絕緣層及該閘極電極層；一可調電路，耦接該場板、該閘極電極層及該第一摻雜區，提供可選之一第一短路路徑或一第二短路路徑，其中該第一短路路徑位在該場板與該閘極電極層之間，該第二短路路徑位在該場板與該第一摻雜區之間；以及一絕緣層，位於該閘極電極層之上，並位於該閘極電極層與該場板之間。 A semiconductor structure, comprising: a substrate having a first conductivity type; a first well region formed in the substrate and having the first conductivity type; a second well region formed in the substrate, And has a second conductivity type, the second conductivity type is complementary to the first conductivity type; a first doped region, formed in the first well region, and has the second conductivity type; a second doped region impurity region, formed in the second well region, and has the second conductivity type; a gate electrode layer, located on the substrate, wherein the gate electrode layer, the first doped region and the second The doped region constitutes a transistor; a gate dielectric layer is located between the substrate and the gate electrode layer; a field plate overlaps the insulating layer and the gate electrode layer; an adjustable circuit is coupled to the field plate, the gate electrode layer and the first doped region, providing an optional first short circuit path or a second short circuit path, wherein the first short circuit path is located between the field plate and the gate electrode layer , the second short-circuit path is located between the field plate and the first doped region; and an insulating layer is located on the gate electrode layer and between the gate electrode layer and the field plate. 如請求項1之半導體結構，其中該可調電路包括：一第一開關電路，耦接於該場板與該閘極電極層之間；以及一第二開關電路，耦接於該場板與該第一摻雜區之間。 The semiconductor structure of claim 1, wherein the adjustable circuit includes: a first switch circuit coupled between the field plate and the gate electrode layer; and a second switch circuit coupled between the field plate and the gate electrode layer between the first doped regions. 如請求項2之半導體結構，其中該第一開關電路包括： 一第一反相器，反相一控制信號，用以產生一第一反相信號；一第一開關，耦接於該場板與該閘極電極層之間，並接收該第一反相信號；以及一第二開關，耦接於該場板與該閘極電極層之間，並接收該控制信號。 The semiconductor structure according to claim 2, wherein the first switch circuit comprises: A first inverter, inverting a control signal, for generating a first inversion signal; a first switch, coupled between the field plate and the gate electrode layer, and receiving the first inversion signal; and a second switch, coupled between the field plate and the gate electrode layer, and receiving the control signal. 如請求項3之半導體結構，其中該第二開關電路包括：一第二反相器，反相該控制信號，用以產生一第二反相信號；一第三開關，耦接於該場板與該第一摻雜區之間，並接收該控制信號；以及一第四開關，耦接於該場板與該第一摻雜區之間，並接收該第二反相信號。 The semiconductor structure according to claim 3, wherein the second switch circuit includes: a second inverter for inverting the control signal to generate a second inversion signal; a third switch coupled to the field plate and the first doped region, and receive the control signal; and a fourth switch, coupled between the field plate and the first doped region, and receive the second inversion signal. 如請求項4之半導體結構，其中該第一及第三開關均為N型電晶體，該第二及第四開關均為P型電晶體。 The semiconductor structure according to claim 4, wherein the first and third switches are both N-type transistors, and the second and fourth switches are both P-type transistors. 如請求項1之半導體結構，其中該電晶體係為一橫向擴散金屬氧化物半導體電晶體。 The semiconductor structure according to claim 1, wherein the transistor system is a laterally diffused metal oxide semiconductor transistor. 一種操作電路，包括：一第一電晶體，形成於一基板的一第一區域之中，並包括一第一場板接觸端、一第一閘極接觸端、一第一源極接觸端；一第一可調電路，在該第一場板接觸端與該第一閘極接觸端之間形成一第一短路路徑，或是在該第一場板接觸端與該第一源極接觸端之間形成一第二短路路徑；一第二電晶體，形成於該基板的一第二區域之中，並包括一第 二場板接觸端、一第二閘極接觸端、一第二源極接觸端；以及一第二可調電路，在該第二場板接觸端與該第二閘極接觸端之間形成一第三短路路徑，或是在該第二場板接觸端與該第二源極接觸端之間形成一第四短路路徑。 An operating circuit, comprising: a first transistor formed in a first region of a substrate, and including a first field plate contact, a first gate contact, and a first source contact; A first adjustable circuit, forming a first short-circuit path between the first field plate contact and the first gate contact, or between the first field plate contact and the first source contact A second short-circuit path is formed between them; a second transistor is formed in a second region of the substrate and includes a first Two field plate contact terminals, a second gate electrode contact terminal, a second source electrode contact terminal; and a second adjustable circuit, forming a circuit between the second field plate contact terminal and the second gate electrode contact terminal The third short circuit path, or a fourth short circuit path is formed between the second field plate contact end and the second source electrode contact end. 如請求項7之操作電路，其中該第一可調電路包括：一第一開關電路，耦接於該第一場板接觸端與該第一閘極接觸端之間；以及一第二開關電路，耦接於該第一場板接觸端與該第一源極接觸端之間。 The operating circuit of claim 7, wherein the first adjustable circuit includes: a first switch circuit coupled between the first field plate contact terminal and the first gate contact terminal; and a second switch circuit , coupled between the first field plate contact and the first source contact. 如請求項8之操作電路，其中該第一開關電路包括：一第一反相器，反相一控制信號，用以產生一第一反相信號；一第一開關，耦接於該第一場板接觸端與該第一閘極接觸端之間，並接收該第一反相信號；以及一第二開關，耦接於該第一場板接觸端與該第一閘極接觸端之間，並接收該控制信號。 The operating circuit of claim 8, wherein the first switch circuit includes: a first inverter, which inverts a control signal to generate a first inverted signal; a first switch, coupled to the first between the field plate contact end and the first gate electrode contact end, and receiving the first inverted signal; and a second switch, coupled between the first field plate contact end and the first gate electrode contact end , and receive the control signal. 如請求項9之操作電路，其中該第二開關電路包括：一第二反相器，反相該控制信號，用以產生一第二反相信號；一第三開關，耦接於該第一場板接觸端與該第一源極接觸端之間，並接收該控制信號；以及一第四開關，耦接於該第一場板接觸端與該第一源極接觸端之 間，並接收該第二反相信號。 The operation circuit of claim item 9, wherein the second switch circuit includes: a second inverter for inverting the control signal to generate a second inverted signal; a third switch coupled to the first between the field plate contact and the first source contact, and receiving the control signal; and a fourth switch, coupled between the first field plate contact and the first source contact , and receive the second inverted signal. 如請求項10之操作電路，其中該第一及第三開關均為N型電晶體，該第二及第四開關均為P型電晶體。 The operating circuit of claim 10, wherein the first and third switches are both N-type transistors, and the second and fourth switches are both P-type transistors. 如請求項7之操作電路，其中該第一及第二電晶體係為矽電晶體或高電子遷移率電晶體。 The operating circuit according to claim 7, wherein the first and second transistor systems are silicon transistors or high electron mobility transistors.
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TWI600160B (en) * 2014-06-20 2017-09-21 英特爾股份有限公司 Monolithic integration of high voltage transistors & low voltage non-planar transistors
TWI693717B (en) * 2015-02-17 2020-05-11 南韓商Ｓｋ海力士系統集成電路有限公司 Power integrated devices, electronic devices including the same, and electronic systems including the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8253197B2 (en) * 2004-01-29 2012-08-28 Enpirion, Inc. Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same
US8847310B1 (en) * 2012-07-31 2014-09-30 Azure Silicon LLC Power device integration on a common substrate
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