TWI782860B - 半導體結構及其製造方法 - Google Patents
半導體結構及其製造方法 Download PDFInfo
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- TWI782860B TWI782860B TW111102699A TW111102699A TWI782860B TW I782860 B TWI782860 B TW I782860B TW 111102699 A TW111102699 A TW 111102699A TW 111102699 A TW111102699 A TW 111102699A TW I782860 B TWI782860 B TW I782860B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 147
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000002955 isolation Methods 0.000 claims abstract description 84
- 230000017525 heat dissipation Effects 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 239000000463 material Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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Abstract
一種半導體結構,包括基底與深溝渠隔離結構。深溝渠隔離結構設置在基底中,且不電性連接至任何元件。深溝渠隔離結構包括散熱層與介電襯層。散熱層設置在基底中。介電襯層設置在散熱層與基底之間。
Description
本發明是有關於一種半導體結構及其製造方法,且特別是有關於一種具有深溝渠隔離結構(deep trench isolation,DTI)的半導體結構及其製造方法。
在目前的半導體結構中,半導體元件之間常會使用深溝渠隔離結構來進行隔離。由於深溝渠隔離結構的材料的導熱係數低,因此會阻礙散熱。此外,在半導體元件(如,電晶體元件)的操作頻率及/或元件密度越來越高的情況下,半導體元件在操作時的溫度也越來越高。因此,如果深溝渠隔離結構阻礙半導體元件進行散熱(heat dissipation),將會降低半導體元件的效能與壽命。
本發明提供一種半導體結構及其製造方法,其有助於半導體元件進行散熱。
本發明提出一種半導體結構,包括基底與深溝渠隔離結
構。深溝渠隔離結構設置在基底中,且不電性連接至任何元件。深溝渠隔離結構包括散熱層與介電襯層。散熱層設置在基底中。介電襯層設置在散熱層與基底之間。
依照本發明的一實施例所述,在上述半導體結構中,深溝渠隔離結構不貫穿所述基底。
依照本發明的一實施例所述,在上述半導體結構中,散熱層的導熱係數(thermal conductivity)可大於二氧化矽的導熱係數。
依照本發明的一實施例所述,在上述半導體結構中,散熱層的導熱係數可大於矽的導熱係數。
依照本發明的一實施例所述,在上述半導體結構中,散熱層的材料例如是金屬。
依照本發明的一實施例所述,在上述半導體結構中,介電襯層的剖面形狀可為U形。
依照本發明的一實施例所述,在上述半導體結構中,更可包括半導體元件。半導體元件位在基底上或基底中,或者位在基底上與基底中。
依照本發明的一實施例所述,在上述半導體結構中,半導體元件可為主動元件。
依照本發明的一實施例所述,在上述半導體結構中,主動元件可為電晶體元件。
依照本發明的一實施例所述,在上述半導體結構中,深
溝渠隔離結構可為圍繞半導體元件的連續結構。
依照本發明的一實施例所述,在上述半導體結構中,更可包括淺溝渠隔離結構。淺溝渠隔離結構設置在基底中。淺溝渠隔離結構可圍繞半導體元件。
依照本發明的一實施例所述,在上述半導體結構中,深溝渠隔離結構可圍繞淺溝渠隔離結構。
依照本發明的一實施例所述,在上述半導體結構中,更可包括介電層。介電層覆蓋半導體元件。
依照本發明的一實施例所述,在上述半導體結構中,深溝渠隔離結構可延伸至介電層中。
依照本發明的一實施例所述,在上述半導體結構中,深溝渠隔離結構可貫穿介電層。
依照本發明的一實施例所述,在上述半導體結構中,介電襯層更可設置在散熱層與介電層之間。
依照本發明的一實施例所述,在上述半導體結構中,更可包括散熱器(heat sink)與內連線結構。散熱器設置在散熱層上。內連線結構設置在散熱器與散熱層之間。
依照本發明的一實施例所述,在上述半導體結構中,內連線結構可直接接觸散熱器與散熱層。
本發明提出一種半導體結構的製造方法,用以形成上述半導體結構,且包括以下步驟。形成半導體元件。半導體元件位在基底上或基底中,或者位在基底上與基底中。在形成半導體元
件之後,在基底中形成深溝渠隔離結構。
依照本發明的一實施例所述,在上述半導體結構的製造方法中,深溝渠隔離結構的形成方法可包括以下步驟。形成覆蓋半導體元件的介電層。在介電層與基底中形成深溝渠隔離結構。
基於上述,在本發明所提出的半導體結構中,深溝渠隔離結構包括散熱層與介電襯層,且散熱層具有高導熱係數。因此,本發明所述的深溝渠隔離結構可以減少對半導體元件的散熱路徑的阻礙,且有助於半導體元件進行散熱。如此一來,在本發明所提出的半導體結構中,深溝渠隔離結構可兼具隔離功能與散熱功能,藉此可提升半導體元件的效能與壽命。此外,在本發明所提出的半導體結構的製造方法中,由於先形成半導體元件,再形成深溝渠隔離結構,因此可降低製程複雜度。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
10,20:半導體結構
100:基底
102:深溝渠隔離結構
104:散熱層
106:介電襯層
108:半導體元件
110:集極
110a,110b,110c:摻雜區
112:基極
112a,112b:導電層
114:射極
116:隔離層
118:淺溝渠隔離結構
120,122,204:介電層
124,126,128,202:內連線結構
200:散熱器
D1,D2:散熱方向
圖1為根據本發明的一些實施例的半導體結構的剖面圖。
圖2為圖1的半導體結構的局部上視圖。
圖3為根據本發明的另一些實施例的半導體結構的剖面圖。
下文列舉實施例並配合附圖來進行詳細地說明,但所提供的實施例並非用以限制本發明所涵蓋的範圍。為了方便理解,在下述說明中相同的構件將以相同的符號標示來說明。此外,附圖僅以說明為目的,並未依照原尺寸作圖。另外,上視圖中的特徵與剖面圖中的特徵並非按相同比例繪製。事實上,為論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1為根據本發明的一些實施例的半導體結構的剖面圖。圖2為圖1的半導體結構的局部上視圖。在本實施例的上視圖中,省略剖面圖中的部分構件,以清楚說明上視圖中的各構件之間的位置關係。
請參照圖1與圖2,半導體結構10包括基底100與深溝渠隔離結構102。基底100可為半導體基底,如矽基底,但本發明並不以此為限。深溝渠隔離結構102設置在基底100中,且不電性連接至任何元件。亦即,在本實施例中,深溝渠隔離結構102的功能並非用以進行電性連接。
深溝渠隔離結構102包括散熱層104與介電襯層106。在一些實施例中,深溝渠隔離結構102不貫穿所述基底100。散熱層104設置在基底100中。在一些實施例中,散熱層104的導熱係數可大於二氧化矽的導熱係數。在一些實施例中,散熱層104的導熱係數可大於矽的導熱係數。散熱層104的材料不限於金屬或非金屬。在一些實施例中,散熱層104可為金屬(如,銅),但本發明並不以此為限。
介電襯層106設置在散熱層104與基底100之間。介電襯層106可設置在散熱層104的側壁與基底100之間以及散熱層104的底面與基底100之間。在一些實施例中,介電襯層106的剖面形狀可為U形。介電襯層106的材料例如是氧化矽。
半導體結構10更可包括半導體元件108。半導體元件108位在基底100上或基底100中,或者位在基底100上與基底100中。在本實施例中,半導體元件108是以位在基底100上與基底100中為例,但本發明並不以此為限。在一些實施例中,半導體元件108可為主動元件。在一些實施例中,主動元件可為電晶體元件。在本實施例中,半導體元件108是以SiGe異質接面雙極性電晶體(heterojunction bipolar transistor,HBT)為例,但本發明並不以此為限。
在本實施例中,半導體元件108可包括集極110、基極112與射極114。集極110與射極114可具有第一導電型(如,N型),且基極112可具有第二導電型(如,P型)。以下,第一導電型與第二導電型可分別為N型導電型與P型導電型中的一者與另一者。在本實施例中,第一導電型是以N型導電型為例,且第二導電型是以P型導電型為例,但本發明並不以此為限。在另一些實施例中,第一導電型可為P型導電型,且第二導電型可為N型導電型。
集極110設置基底100中。在一些實施例中,集極110可包括摻雜區110a、摻雜區110b與摻雜區110c。摻雜區110a、摻雜區110b與摻雜區110c可具有第一導電型(如,N型)。在一些
實施例中,摻雜區110a可為選擇性植入集極(selectively implanted collector,SIC)。摻雜區110a與摻雜區110b分離設置在基底100中。摻雜區110c連接至摻雜區110a與摻雜區110b。
基極112設置在基底100上。在一些實施例中,基極112可包括導電層112a與導電層112b。導電層112a與導電層112b可具有第二導電型(如,P型)。導電層112a設置在基底100上,且可連接至集極110的摻雜區110a。導電層112a的材料例如是矽鍺(SiGe)。導電層112b設置在導電層112a上。導電層112b的材料例如是摻雜多晶矽。
射極114設置在基極112上。射極114可連接至基極112的導電層112a。部分射極114可設置在部分導電層112b上。在一些實施例中,基極112的導電層112b可圍繞射極114(圖2)。射極114的材料例如是摻雜多晶矽。此外,半導體結構10更可包括隔離層116。隔離層116設置在射極114與導電層112b之間。隔離層116的材料例如是氮化矽。
在本實施例中,深溝渠隔離結構102可為圍繞半導體元件108的連續結構,亦即深溝渠隔離結構102的上視形狀可包括環狀(圖2),但本發明並不以此為限。深溝渠隔離結構102的上視形狀可依據產品需求來進行調整。舉例來說,在另一些實施例中,深溝渠隔離結構102的上視形狀可為片狀或柱狀。
半導體結構10更可包括淺溝渠隔離結構118。淺溝渠隔離結構118設置在基底100中。淺溝渠隔離結構118可圍繞半導
體元件108(圖2)。深溝渠隔離結構102可圍繞淺溝渠隔離結構118(圖2)。淺溝渠隔離結構118的材料例如是氧化矽。
半導體結構10更可包括介電層120。介電層120覆蓋半導體元件108。深溝渠隔離結構102可延伸至介電層120中。深溝渠隔離結構102可貫穿介電層120。介電襯層106更可設置在散熱層104與介電層120之間。介電層120的材料例如是氧化矽。
半導體結構10更可包括介電層122。介電層122設置在介電層120與深溝渠隔離結構102上。介電層122的材料例如是氧化矽。
半導體結構10更可包括內連線結構124、內連線結構126與內連線結構128。內連線結構124、內連線結構126與內連線結構128可設置在介電層120與介電層122中。內連線結構124的頂部、內連線結構126的頂部與內連線結構128的頂部分別可為接墊(pad)。內連線結構124可電性連接至集極110。內連線結構126可電性連接至基極112。內連線結構128可電性連接至射極114。在本實施例中,內連線結構124、內連線結構126與內連線結構128分別可包括接觸窗(contact),但本發明並不以此為限。在另一些實施例中,內連線結構124、內連線結構126與內連線結構128分別可包括接觸窗、導線、通孔(via)或其組合。內連線結構124、內連線結構126與內連線結構128的材料例如是金屬,如鎢、鋁、銅或其組合,但本發明並不以此為限。
在一些實施例中,半導體結構10的製造方法可包括以下
步驟。形成半導體元件108。半導體元件108位在基底100上或基底100中,或者位在基底100上與基底100中。在本實施例中,半導體元件108是以位在基底100上與基底100中為例,但本發明並不以此為限。在形成半導體元件108之後,在基底100中形成深溝渠隔離結構102。在一些實施例中,深溝渠隔離結構102的形成方法可包括以下步驟。首先,形成覆蓋半導體元件108的介電層120。接著,在介電層120與基底100中形成深溝渠隔離結構102。深溝渠隔離結構102可貫穿介電層120。舉例來說,散熱層104與介電襯層106可包括以下步驟。首先,可在介電層120與基底100中形成溝渠(未示出)。接著,可依序形成填入溝渠的介電襯材料層(未示出)與散熱材料層(未示出)。散熱材料層的形成方法例如是電化學沉積(electrochemical deposition)法,但本發明並不以此為限。然後,可藉由化學機械研磨法移除位在溝渠外部的散熱材料層與介電襯材料層,而形成散熱層104與介電襯層106。此外,半導體結構10中的其他構件的形成方法為所屬技術領域具有通常知識者所週知,於此省略其說明。
基於上述實施例可知,在半導體結構10中,深溝渠隔離結構102包括散熱層104與介電襯層106,且散熱層104具有高導熱係數。因此,本發明所述的深溝渠隔離結構102可以減少對半導體元件108的散熱路徑的阻礙,且有助於半導體元件108進行散熱。舉例來說,如圖1所示,半導體元件108可沿著散熱方向D1經由基底100與深溝渠隔離結構102進行橫向散熱(lateral heat
dissipation)。如此一來,在半導體結構10中,深溝渠隔離結構102可兼具隔離功能與散熱功能,藉此可提升半導體元件108的效能與壽命。此外,在上述實施例的半導體結構10的製造方法中,由於先形成半導體元件108,再形成深溝渠隔離結構102,因此可降低製程複雜度。
圖3為根據本發明的另一些實施例的半導體結構的剖面圖。
請參照圖1與圖3,圖3的半導體結構20與圖1的半導體結構10的差異如下。在圖3中,半導體結構20更可包括散熱器200與內連線結構202。散熱器200設置在散熱層104上。散熱器200的材料例如是金屬,但本發明並不以此為限。內連線結構202設置在散熱器200與散熱層104之間。內連線結構202可直接接觸散熱器200與散熱層104。內連線結構202設置在介電層122中。在本實施例中,內連線結構202、內連線結構124、內連線結構126與內連線結構128分別可包括接觸窗、導線、通孔或其組合。內連線結構202的材料例如是金屬,如鎢、鋁、銅或其組合,但本發明並不以此為限。
此外,半導體結構20更可包括介電層204。介電層204設置在散熱器200與介電層122之間。內連線結構202可穿過介電層204而連接至散熱器200。在一些實施例中,在介電層204中可具有封裝結構所需的構件(未示出),於此省略其說明。
另外,半導體結構20與半導體結構10中相同的構件使
用相同的符號表示,且半導體結構20與半導體結構10中相同或相似的內容,可參考上述實施例對半導體結構10的說明,於此不再說明。
基於上述實施例可知,在半導體結構20中,由於散熱層104可藉由內連線結構202來連接至散熱器200,因此半導體元件108可藉由散熱器200進行散熱。舉例來說,如圖2所示,半導體元件108可沿著散熱方向D2經由散熱層104、內連線結構202與散熱器200進行垂直散熱(vertical heat dissipation),藉此可進一步地提升半導體結構20的散熱能力。亦即,在半導體結構20中,半導體元件108可沿著散熱方向D1進行橫向散熱且可沿著散熱方向D2進行垂直散熱。如此一來,在半導體結構20中,深溝渠隔離結構102可兼具隔離功能與散熱功能,藉此可提升半導體元件108的效能與壽命。此外,在上述實施例的半導體結構20的製造方法中,由於先形成半導體元件108,再形成深溝渠隔離結構102,因此可降低製程複雜度。
綜上所述,在上述實施例的半導體結構中,深溝渠隔離結構包括散熱層與介電襯層,且散熱層具有高導熱係數。因此,本發明所述的深溝渠隔離結構可以減少對半導體元件的散熱路徑的阻礙,且有助於半導體元件進行散熱。如此一來,在上述實施例的半導體結構中,深溝渠隔離結構可兼具隔離功能與散熱功能,藉此可提升半導體元件的效能與壽命。此外,在上述實施例的半導體結構的製造方法中,由於先形成半導體元件,再形成深
溝渠隔離結構,因此可降低製程複雜度。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10:半導體結構
100:基底
102:深溝渠隔離結構
104:散熱層
106:介電襯層
108:半導體元件
110:集極
110a,110b,110c:摻雜區
112:基極
112a,112b:導電層
114:射極
116:隔離層
118:淺溝渠隔離結構
120,122:介電層
124,126,128:內連線結構
D1:散熱方向
Claims (19)
- 一種半導體結構,包括:基底;深溝渠隔離結構,設置在所述基底中,且不電性連接至任何元件,其中所述深溝渠隔離結構包括:散熱層,設置在所述基底中;以及介電襯層,設置在所述散熱層與所述基底之間;散熱器,設置在所述散熱層上;以及內連線結構,設置在所述散熱器與所述散熱層之間。
- 如請求項1所述的半導體結構,其中所述深溝渠隔離結構不貫穿所述基底。
- 如請求項1所述的半導體結構,其中所述散熱層的導熱係數大於二氧化矽的導熱係數。
- 如請求項1所述的半導體結構,其中所述散熱層的導熱係數大於矽的導熱係數。
- 如請求項1所述的半導體結構,其中所述散熱層的材料包括金屬。
- 如請求項1所述的半導體結構,其中所述介電襯層的剖面形狀包括U形。
- 如請求項1所述的半導體結構,更包括:半導體元件,位在所述基底上或所述基底中,或者位在所述基底上與所述基底中。
- 如請求項7所述的半導體結構,其中所述半導體元件包括主動元件。
- 如請求項8所述的半導體結構,其中所述主動元件包括電晶體元件。
- 如請求項7所述的半導體結構,其中所述深溝渠隔離結構為圍繞所述半導體元件的連續結構。
- 如請求項7所述的半導體結構,更包括:淺溝渠隔離結構,設置在所述基底中,且圍繞所述半導體元件。
- 如請求項11所述的半導體結構,其中所述深溝渠隔離結構圍繞所述淺溝渠隔離結構。
- 如請求項7所述的半導體結構,更包括:介電層,覆蓋所述半導體元件。
- 如請求項13所述的半導體結構,其中所述深溝渠隔離結構延伸至所述介電層中。
- 如請求項13所述的半導體結構,其中所述深溝渠隔離結構貫穿所述介電層。
- 如請求項13所述的半導體結構,其中介電襯層更設置在所述散熱層與所述介電層之間。
- 如請求項1所述的半導體結構,其中所述內連線結構直接接觸所述散熱器與所述散熱層。
- 一種半導體結構的製造方法,用以形成如請求項1所述的半導體結構,且包括:形成半導體元件,其中所述半導體元件位在所述基底上或所述基底中,或者位在所述基底上與所述基底中;以及在形成所述半導體元件之後,在所述基底中形成所述深溝渠隔離結構。
- 如請求項18所述的半導體結構的製造方法,其中所述深溝渠隔離結構的形成方法包括:形成覆蓋所述半導體元件的介電層;以及在所述介電層與所述基底中形成所述深溝渠隔離結構。
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GB0022329D0 (en) * | 2000-09-12 | 2000-10-25 | Mitel Semiconductor Ltd | Semiconductor device |
US8735262B2 (en) * | 2011-10-24 | 2014-05-27 | Infineon Technologies Ag | Semiconductor device having a through contact and a manufacturing method therefor |
US9625186B2 (en) | 2013-08-29 | 2017-04-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cooling system for 3D IC |
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2022
- 2022-01-21 TW TW111102699A patent/TWI782860B/zh active
- 2022-02-07 CN CN202210120215.1A patent/CN116504727A/zh active Pending
- 2022-03-06 US US17/687,663 patent/US11915969B2/en active Active
Patent Citations (2)
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US20150056777A1 (en) * | 2010-12-14 | 2015-02-26 | International Business Machines Corporation | Device isolation with improved thermal conductivity |
US20210043534A1 (en) * | 2018-09-21 | 2021-02-11 | United Microelectronics Corp. | High resistivity wafer with heat dissipation structure and method of making the same |
Also Published As
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US20230238270A1 (en) | 2023-07-27 |
CN116504727A (zh) | 2023-07-28 |
TW202331960A (zh) | 2023-08-01 |
US11915969B2 (en) | 2024-02-27 |
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