TWI782585B - Display device - Google Patents
Display device Download PDFInfo
- Publication number
- TWI782585B TWI782585B TW110122478A TW110122478A TWI782585B TW I782585 B TWI782585 B TW I782585B TW 110122478 A TW110122478 A TW 110122478A TW 110122478 A TW110122478 A TW 110122478A TW I782585 B TWI782585 B TW I782585B
- Authority
- TW
- Taiwan
- Prior art keywords
- transistor
- circuit
- display device
- signal
- driving
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
- Vehicle Body Suspensions (AREA)
- Diaphragms For Electromechanical Transducers (AREA)
- Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
Abstract
Description
本案涉及一種電子裝置。詳細而言,本案涉及一種顯示裝置。This case involves an electronic device. Specifically, this case relates to a display device.
於現有顯示裝置中,顯示裝置的驅動控制電路採用直接開關的方式。此種設計導致訊號之推力會逐漸下降,進而使面板內部的發光電路產生相位偏移。因此,訊號的些微相位偏移使得顯示裝置產生明顯的顯示瑕疵(mura)。In the existing display device, the driving control circuit of the display device adopts a direct switch mode. This design causes the thrust of the signal to gradually decrease, which in turn causes the phase shift of the light-emitting circuit inside the panel. Therefore, the slight phase shift of the signal causes obvious display artifacts (mura) in the display device.
因此,上述技術尚存諸多缺陷,而有待本領域從業人員研發出其餘適合的電路設計。Therefore, the above-mentioned technology still has many defects, and it is waiting for practitioners in the field to develop other suitable circuit designs.
本案的一面向涉及一種顯示裝置包含驅動電晶體、控制電路、移位暫存器電路。控制電路耦接於驅動電晶體,並用以控制驅動電晶體。移位暫存器電路耦接於控制電路,並用以根據複數個訊號輸出掃頻訊號至控制電路。移位暫存器電路藉由掃頻訊號以調整控制電路之節點之電壓準位。控制電路根據節點之電壓準位控制驅動電晶體。One aspect of the present application relates to a display device including a driving transistor, a control circuit, and a shift register circuit. The control circuit is coupled to the driving transistor and used for controlling the driving transistor. The shift register circuit is coupled to the control circuit, and is used for outputting a frequency sweep signal to the control circuit according to a plurality of signals. The shift register circuit adjusts the voltage levels of the nodes of the control circuit through the frequency sweep signal. The control circuit controls the driving transistor according to the voltage level of the node.
以下將以圖式及詳細敘述清楚說明本案之精神,任何所屬技術領域中具有通常知識者在瞭解本案之實施例後,當可由本案所教示之技術,加以改變及修飾,其並不脫離本案之精神與範圍。The following will clearly illustrate the spirit of this case with diagrams and detailed descriptions. Anyone with ordinary knowledge in the technical field can change and modify the technology taught in this case after understanding the embodiment of this case. It does not depart from the spirit of this case. Spirit and scope.
本文之用語只為描述特定實施例,而無意為本案之限制。單數形式如“一”、“這”、“此”、“本”以及“該”,如本文所用,同樣也包含複數形式。The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the present case. Singular forms such as "a", "the", "the", "this" and "the", as used herein, also include plural forms.
關於本文中所使用之『包含』、『包括』、『具有』、『含有』等等,均為開放性的用語,即意指包含但不限於。"Includes", "including", "has", "containing" and so on used in this article are all open terms, meaning including but not limited to.
關於本文中所使用之用詞(terms),除有特別註明外,通常具有每個用詞使用在此領域中、在本案之內容中與特殊內容中的平常意義。某些用以描述本案之用詞將於下或在此說明書的別處討論,以提供本領域技術人員在有關本案之描述上額外的引導。Regarding the terms (terms) used in this article, unless otherwise specified, generally have the ordinary meaning of each term used in this field, in the content of this case and in the special content. Certain terms used to describe the subject matter are discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance in describing the subject matter.
第1圖為根據本案一些實施例繪示的顯示裝置之電路方塊示意圖。在一些實施例中,請參閱第1圖,顯示裝置100包含驅動電晶體DT1、控制電路110、移位暫存器電路120、第一電晶體T1、第二電晶體T2及發光元件L。在一些實施例中,顯示裝置100採用閘極驅動電路基板(Gate Driver on Array, GOA)技術。在一些實施例中,顯示裝置100採用逐行掃描(progressive scan)的方式以驅動顯示裝置100的面板內部的畫素電路。FIG. 1 is a schematic circuit block diagram of a display device according to some embodiments of the present invention. In some embodiments, please refer to FIG. 1 , the
在一些實施例中,請以圖式中元件之上端及右端起算為第一端,驅動電晶體DT1包含第一端、第二端及控制端。驅動電晶體DT1之第一端耦接於第一電晶體T1。驅動電晶體DT1之第二端耦接於第二電晶體T2。驅動電晶體DT1之控制端耦接於控制電路110。In some embodiments, please count as the first end from the upper end and the right end of the device in the drawing, and the driving transistor DT1 includes the first end, the second end and the control end. The first end of the driving transistor DT1 is coupled to the first transistor T1. The second end of the driving transistor DT1 is coupled to the second transistor T2. The control terminal of the driving transistor DT1 is coupled to the
在一些實施例中,第一電晶體T1包含第一端、第二端及控制端。第一電晶體T1之第一端接收電源供應電壓VDD。第一電晶體T1之第二端耦接於驅動電晶體DT1之第一端。第一電晶體T1之控制端接收驅動訊號EM1[n]。In some embodiments, the first transistor T1 includes a first terminal, a second terminal and a control terminal. The first terminal of the first transistor T1 receives the power supply voltage VDD. The second end of the first transistor T1 is coupled to the first end of the driving transistor DT1. The control terminal of the first transistor T1 receives the driving signal EM1[n].
在一些實施例中,第二電晶體T2包含第一端、第二端及控制端。第二電晶體T2之第一端耦接於驅動電晶體DT1之第二端。第二電晶體T2之第二端耦接於發光元件L。在一些實施例中,發光元件L包含第一端及第二端。發光元件L之第一端耦接於第二電晶體T2之第二端。發光元件L之第二端接收電源供應電壓VSS。須說明的是,本案顯示裝置100之發光路徑為電源供應電壓VDD與電源供應電壓VSS之間的最短路經。本案顯示裝置100之發光路徑係經由第一電晶體T1、驅動電晶體DT1及第二電晶體T2。由第一電晶體T1、驅動電晶體DT1及第二電晶體T2控制發光元件L。In some embodiments, the second transistor T2 includes a first terminal, a second terminal and a control terminal. The first terminal of the second transistor T2 is coupled to the second terminal of the driving transistor DT1. The second end of the second transistor T2 is coupled to the light emitting element L. In some embodiments, the light emitting element L includes a first end and a second end. The first end of the light emitting element L is coupled to the second end of the second transistor T2. The second end of the light emitting element L receives the power supply voltage VSS. It should be noted that the light-emitting path of the
在一些實施例中,控制電路110耦接於驅動電晶體DT1,並用以控制驅動電晶體DT1。移位暫存器電路120耦接於控制電路110,並用以根據複數個訊號(例如:掃頻時脈訊號SW_CLK、掃頻高準位SW_H及掃頻低準位SW_L)輸出掃頻訊號SWEEP[n]至控制電路110。移位暫存器電路120藉由掃頻訊號SWEEP[n]調整控制電路110之節點N2之電壓準位。在一些實施例中,移位暫存器電路120藉由掃頻訊號SWEEP[n]以抬升或降低控制電路110之節點N2之電壓準位。In some embodiments, the
在一些實施例中,控制電路110包含電晶體T3、電晶體T4、電晶體T5、電晶體T6、脈衝寬度調變電晶體PT1、電容C1、節點N1及節點N2。在一些實施例中,電晶體T3包含第一端、第二端及控制端。電晶體T3之第一端接收截止訊號PPO。電晶體T3之控制端接收第一驅動訊號EM[n]。脈衝寬度調變電晶體PT1包含第一端、第二端及控制端。脈衝寬度調變電晶體PT1之第一端耦接於節點N2。脈衝寬度調變電晶體PT1之第二端耦接於電晶體T3之第二端。脈衝寬度調變電晶體PT1之控制端耦接於節點N1。In some embodiments, the
在一些實施例中,電晶體T4包含第一端、第二端及控制端。電晶體T4之第一端耦接於節點N2。電晶體T4之第二端耦接於節點N1。電晶體T4之控制端接收閘極訊號Gate[n]。電晶體T5包含第一端、第二端及控制端。電晶體T5之第一端接收直流訊號RES_DC。電晶體T5之第二端耦接於節點N1。電晶體T5之控制端接收重置訊號R[n]。電晶體T6包含第一端、第二端及控制端。電晶體T6之第一端耦接於脈衝寬度調變電晶體PT1之第二端及電晶體T3之第二端。電晶體T6之第二端接收輸入訊號Input。電晶體T6之控制端接收閘極訊號Gate[n]。電容C1包含第一端及第二端。電容C1之第一端耦接於節點N1。電容C1之第二端耦接於控制電路110的輸入端(即掃描電阻電容端111),並接收掃頻訊號SWEEP[n]。In some embodiments, the transistor T4 includes a first terminal, a second terminal and a control terminal. The first end of the transistor T4 is coupled to the node N2. The second end of the transistor T4 is coupled to the node N1. The control terminal of the transistor T4 receives the gate signal Gate[n]. The transistor T5 includes a first terminal, a second terminal and a control terminal. The first end of the transistor T5 receives the DC signal RES_DC. The second end of the transistor T5 is coupled to the node N1. The control terminal of the transistor T5 receives the reset signal R[n]. The transistor T6 includes a first terminal, a second terminal and a control terminal. The first end of the transistor T6 is coupled to the second end of the pulse width modulation transistor PT1 and the second end of the transistor T3. The second end of the transistor T6 receives the input signal Input. The control terminal of the transistor T6 receives the gate signal Gate[n]. The capacitor C1 includes a first terminal and a second terminal. A first end of the capacitor C1 is coupled to the node N1. The second terminal of the capacitor C1 is coupled to the input terminal of the control circuit 110 (ie, the scanning resistor-capacitor terminal 111 ), and receives the sweep signal SWEEP[n].
在一些實施例中,移位暫存器電路120包含選擇電晶體ST1、電容C2、輸出電路121及掃頻電壓驅動電路122。在一些實施例中,輸出電路121耦接於選擇電晶體ST1及電容C2。在一些實施例中,掃頻電壓驅動電路122耦接於輸出電路121。In some embodiments, the
在一些實施例中,選擇電晶體ST1根據驅動訊號輸出掃頻訊號SWEEP[n]至控制電路110之輸出入端(即掃描電阻電容端111)。電容C2用以穩定掃頻訊號SWEEP[n]之電壓。In some embodiments, the selection transistor ST1 outputs the sweep signal SWEEP[n] to the I/O terminal of the control circuit 110 (ie, the scanning resistor and capacitor terminal 111 ) according to the driving signal. The capacitor C2 is used to stabilize the voltage of the sweep signal SWEEP[n].
在一些實施例中,電容C2包含第一端及第二端。電容C2之第一端耦接於輸出電路121。電容C2之第二端係為控制電路110之輸入端(即掃描電阻電容端111)。選擇電晶體ST1包含第一端、第二端及控制端。選擇電晶體ST1之第一端耦接於控制電路110之輸入端(即掃描電阻電容端111)。選擇電晶體ST1之第二端根據輸出電路121接收到的驅動訊號EM[n]及斜率訊號SW_slope[P]輸出掃頻訊號SWEEP[n]。In some embodiments, the capacitor C2 includes a first terminal and a second terminal. The first end of the capacitor C2 is coupled to the
在一些實施例中,驅動電晶體DT1、第一電晶體T1、第二電晶體T2、電晶體T3、電晶體T4、電晶體T5、電晶體T6、脈衝寬度調變電晶體PT1及選擇電晶體ST1均為P型金屬氧化物半導體場效電晶體PMOS(p type Metal Oxide Semiconductor, PMOS)。雖然本案之實施例採用PMOS,但不以圖式實施例為限。詳細而言,若電晶體T7至電晶體T15採用N型金屬氧化物半導體場效電晶體(N type Metal Oxide Semiconductor, NMOS)。本案之顯示裝置100之電性操作會相反。In some embodiments, the driving transistor DT1, the first transistor T1, the second transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the pulse width modulation transistor PT1 and the selection transistor ST1 is a P-type metal oxide semiconductor field effect transistor PMOS (p type Metal Oxide Semiconductor, PMOS). Although the embodiment of this case adopts PMOS, it is not limited to the embodiment in the drawing. In detail, if the transistors T7 to T15 are N type metal oxide semiconductor field effect transistors (N type Metal Oxide Semiconductor, NMOS). The electrical operation of the
在一些實施例中,顯示裝置100更包含驅動移位暫存器電路910、第一掃描移位暫存器電路930以及第二掃描移位暫存器電路950。在一些實施例中,驅動移位暫存器電路910、第一掃描移位暫存器電路930以及第二掃描移位暫存器電路950均由顯示裝置100之系統端(圖中未示)所控制。In some embodiments, the
在一些實施例中,驅動移位暫存器電路910用以接收驅動時脈訊號EM_CLK、第一串列輸入訊號S1及閘極驅動訊號GOA,藉以輸出驅動訊號EM1[n]至第一電晶體T1以及移位暫存器電路120之輸出電路121或輸出驅動訊號EM2[n]至第二電晶體T2。In some embodiments, the driving
在一些實施例中,第一掃描移位暫存器電路930用以接收第一掃描時脈訊號SC_CLK1及第二串列輸入訊號S2[N],藉以輸出閘極訊號Gate[n]或多級閘極訊號。在一些實施例中,第一掃描移位暫存器電路930輸出閘極訊號Gate[n]或多級閘極訊號至控制電路110或移位暫存器電路120。In some embodiments, the first scan
在一些實施例中,第二掃描移位暫存器電路950用以接收第二掃描時脈訊號SC_CLK2及次級第二串列輸入訊號S2[N+1],藉以輸出閘極訊號Gate[n]或多級閘極訊號。在一些實施例中,第二掃描移位暫存器電路950輸出閘極訊號Gate[n]或多級閘極訊號至控制電路110或移位暫存器電路120。In some embodiments, the second scan
在一些實施例中,為使第1圖之顯示裝置100的操作易於理解,請一併參閱第2圖,第2圖為根據本案一些實施例繪示的顯示裝置之驅動訊號時序示意圖。在一些實施例中,移位暫存器電路120用以根據複數個訊號輸出掃頻訊號SWEEP[n]至控制電路110。移位暫存器電路120藉由掃頻訊號SWEEP[n]以調整控制電路110之節點N2之電壓準位。控制電路110根據節點N2之電壓準位控制驅動電晶體DT1。須說明的是,階段I11至階段I17為顯示裝置100的一個驅動週期。In some embodiments, in order to make the operation of the
在一些實施例中,第一電晶體T1、驅動電晶體DT1及第二電晶體T2控制發光元件L。第一電晶體T1之控制端響應驅動訊號EM1[n]導通。第二電晶體T2之控制端響應驅動訊號EM2[n]導通。驅動電晶體DT1響應控制電路110之節點N2之電壓準位導通,藉以與第一電晶體T1及第二電晶體T2共同控制發光元件L。In some embodiments, the first transistor T1 , the driving transistor DT1 and the second transistor T2 control the light emitting element L. Referring to FIG. The control terminal of the first transistor T1 is turned on in response to the driving signal EM1[n]. The control terminal of the second transistor T2 is turned on in response to the driving signal EM2[n]. The driving transistor DT1 is turned on in response to the voltage level of the node N2 of the
在一些實施例中,驅動訊號EM1[n]之工作週期P1大於驅動訊號EM2[n]之工作週期P2。須說明的是,R[n]為重置訊號,控制電路110用以根據重置訊號R[n]進行重置。訊號PAM[n]為控制電路110之節點N2之電壓準位變化。訊號PAM[n]響應掃頻訊號SWEEP[n]變化,並與移位暫存器電路120內部操作密切相關。為了更佳地理解移位暫存器電路120內部操作,其詳細步驟將於下面段落中解釋之。In some embodiments, the duty cycle P1 of the driving signal EM1[n] is greater than the duty cycle P2 of the driving signal EM2[n]. It should be noted that R[n] is a reset signal, and the
實質上,驅動訊號EM1[n]之工作週期P1為顯示裝置100的控制階段。驅動訊號EM2[n]之工作週期P2為發光元件L的發光階段。調整工作週期P2的時間長短,以達成類似脈衝寬度調變的驅動方式。In essence, the duty cycle P1 of the driving signal EM1 [n] is a control phase of the
在一些實施例中,為使移位暫存器電路120內部操作易於理解,請一併參閱第3圖及第4圖。第3圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路120之電路方塊示意圖。在一些實施例中,第3圖為第1圖中顯示裝置100之移位暫存器電路120之內部結構的展開圖。第4圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路120之驅動訊號時序示意圖。在一些實施例中,請參閱第3圖及第4圖,輸出電路121用以根據驅動訊號EM[n]控制選擇電晶體ST1。掃頻電壓驅動電路122用以根據選擇訊號PHG[n]透過輸出電路121控制選擇電晶體ST1。由輸出電路121及掃頻電壓驅動電路12控制的選擇電晶體ST1根據驅動訊號EM[n]仿製斜率訊號SW_slope[P],藉以輸出掃頻訊號SWEEP[n]。In some embodiments, in order to understand the internal operation of the
須說明的是,電壓準位VGH及VGL均為直流準位。掃頻高準位SW_H及掃頻低準位SW_L均為直流準位。階段I21至至階段I24為顯示裝置100之移位暫存器電路120的一個驅動週期。It should be noted that the voltage levels VGH and VGL are both DC levels. Both the sweep high level SW_H and the sweep low level SW_L are DC levels. The phase I21 to the phase I24 are one driving cycle of the
在一些實施例中,移位暫存器電路120包含輸出電路121及掃頻電壓驅動電路122。在一些實施例中,輸出電路121包含電晶體T9、電晶體T11及電晶體T12。在一些實施例中,掃頻電壓驅動電路122包含電晶體T7、電晶體T8、電晶體T10、電晶體T13、電晶體T14、電晶體T15、電容C3及電容C4。In some embodiments, the
在一些實施例中,電晶體T7至電晶體T15均為P型金屬氧化物半導體場效電晶體PMOS(p type Metal Oxide Semiconductor, PMOS)。雖然本案之實施例採用PMOS,但不以圖式實施例為限。詳細而言,若電晶體T7至電晶體T15採用N型通道金屬氧化物半導體場效電晶體NMOS(N type Metal Oxide Semiconductor, NMOS)。本案之顯示裝置100之電性操作會相反。In some embodiments, the transistors T7 to T15 are all PMOS (p type Metal Oxide Semiconductor, PMOS) transistors. Although the embodiment of this case adopts PMOS, it is not limited to the embodiment in the drawing. In detail, if the transistors T7 to T15 are N type metal oxide semiconductor field effect transistors NMOS (N type Metal Oxide Semiconductor, NMOS). The electrical operation of the
第5圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路120之狀態示意圖。在一些實施例中,請參閱第4圖及第5圖,於階段I21中,移位暫存器電路120之掃頻電壓驅動電路122接收掃頻時脈訊號SW_CLK。掃頻時脈訊號SW_CLK用以穩壓掃頻電壓驅動電路122之內部電壓。此時,驅動電壓EM[n]為高準位,電晶體T7、電晶體T8及電晶體T9導通,藉以將從移位暫存器電路120之輸出端Output輸入的電流引導至掃頻低準位SW_L。須說明的是,於階段I21中,斜率訊號SW_slope[P]將被先行輸入至選擇電晶體ST1之第一端。FIG. 5 is a schematic diagram of the state of the
第6圖為根據本案一些實施例繪示的顯示裝置之控制電路120之狀態示意圖。在一些實施例中,請參閱第2圖及第6圖,於階段I12中,閘極訊號Gate[n]為低準位,電晶體T6及電晶體T4響應閘極訊號Gate[n]導通。此時,輸入訊號Input透過電晶體T6之第二端輸入,並經由脈衝寬度調變電晶體PT1、節點N2、電晶體T4、節點N1及電容C1將電壓準位輸入至上述移位暫存器電路120之輸出端Output,藉以進行補償。須說明的是,第2圖之階段I12大致上對應至第4圖之階段I21。FIG. 6 is a schematic diagram of the state of the
在一些實施例中,請參閱第2圖,於階段I11中,重置電位R[n]為低準位,電晶體T5導通,以將節點N1或節點N2之電位重置到直流訊號RES_DC。In some embodiments, please refer to FIG. 2 , in the phase I11 , the reset potential R[n] is at a low level, and the transistor T5 is turned on to reset the potential of the node N1 or the node N2 to the DC signal RES_DC.
第7圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路120之狀態示意圖。在一些實施例中,請參閱第4圖及第7圖,於階段I22中,選擇訊號PHG[n]為低準位,電晶體T15之控制端響應選擇訊號PHG[n]導通,電晶體T10之控制端及電晶體T14之控制端響應電壓準位VGL導通。此時,電晶體T7、電晶體T8及電晶體T9關閉。掃頻高準位SW_H透過電晶體T10開始輸出高準位至移位暫存器電路120之輸出端Output,進而輸出高準位至上述控制電路110。FIG. 7 is a schematic diagram of the state of the
第8圖為根據本案一些實施例繪示的顯示裝置之控制電路120之狀態示意圖。在一些實施例中,請參閱第2圖及第8圖,於階段I13中,掃頻訊號SWEEP[n]為高準位。從移位暫存器電路120之輸出端Output輸出的掃頻訊號SWEEP[n]抬升節點N1的電壓準位,進而產生一股高推力藉以間接抬升節點N2的電壓準位。FIG. 8 is a schematic diagram of the state of the
第9圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路120之狀態示意圖。在一些實施例中,請參閱第4圖及第9圖,於階段I22中,選擇訊號PHG[n]從低準位轉為高準位,電晶體T15之控制端響應選擇訊號PHG[n]關閉。此時,電晶體T10之控制端及電晶體T14之控制端維持低準位,掃頻高準位SW_H透過電晶體T10持續輸出高準位至移位暫存器電路120之輸出端Output,進而輸出高準位至上述控制電路110。須說明的是,第2圖之階段I13大致上對應至第4圖之階段I22。FIG. 9 is a schematic diagram of the state of the
第10圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路120之狀態示意圖。在一些實施例中,請參閱第4圖及第10圖,於階段I23中,驅動訊號EM[n]為低準位,電晶體T11、電晶體T12、電晶體T13及選擇電晶體ST1響應驅動訊號EM[n]導通,電晶體T10之控制端及電晶體T14之控制端響應電壓準位VGH關閉。斜率訊號SW_slope[P]透過選擇電晶體ST1輸出至移位暫存器電路120之輸出端Output。選擇電晶體ST1開始仿製斜率訊號SW_slope[P]之下降緣,以輸出逐漸下降的斜率訊號至上述控制電路110。FIG. 10 is a schematic diagram of the state of the
第11圖為根據本案一些實施例繪示的顯示裝置之控制電路120之狀態示意圖。在一些實施例中,請參閱第2圖及第11圖,於階段I14、階段I15及階段I16中,由於掃頻訊號SWEEP[n]逐漸下降,節點N2的電壓變化(即訊號PAM[n])響應節點N1而逐漸下降,驅動訊號EM[n]為低準位,截止訊號PPO透過電晶體T3及脈衝寬度調變電晶體PT1寫入節點N2。驅動電經體DT1之控制端響應節點N2截止,並與第一電晶體T1及電晶體T2輸出電流至發光元件L,以達成脈衝振幅調變的驅動方式。須說明的是,第2圖之階段I14、階段I15及階段I16大致上對應至第4圖之階段I23。FIG. 11 is a schematic diagram of the state of the
第12圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路120之狀態示意圖。在一些實施例中,請參閱第4圖及第12圖,於階段I24中,驅動電壓EM[n]為高準位,電晶體T7、電晶體T8及電晶體T9導通,藉以將從移位暫存器電路120之輸出端Output輸入的電流引導至掃頻低準位SW_L。須說明的是,第2圖之階段I17大致上對應至第4圖之階段I24。FIG. 12 is a schematic diagram of a state of a
第13圖為根據本案一些實施例繪示的顯示裝置100A之電路方塊示意圖。在一些實施例中,相較於第1圖之顯示裝置100,第13圖之實施例於控制電路110A中增加兩顆電晶體(例如:電晶體T16及電晶體T17),以及增加一個設定移位暫存器電路970A及驅動電晶體DT2。設定移位暫存器電路970A耦接於電晶體T17之控制端。須說明的是,藉由增加第13圖之電路結構,以同時控制驅動電晶體DT1及驅動電晶體DT2,藉以減少顯示裝置的顯示缺陷(mura)。FIG. 13 is a schematic circuit block diagram of a
依據前述實施例,本案提供一種顯示裝置,藉由本案之電路架構產生一股掃頻訊號之持續推力,以減少顯示裝置的相位偏移而產生的顯示瑕疵(mura)。According to the foregoing embodiments, the present application provides a display device, which uses the circuit structure of the present application to generate a continuous thrust of a sweeping signal to reduce display muras caused by phase shift of the display device.
雖然本案以詳細之實施例揭露如上,然而本案並不排除其他可行之實施態樣。因此,本案之保護範圍當視後附之申請專利範圍所界定者為準,而非受於前述實施例之限制。Although this case discloses the above with detailed embodiments, this case does not exclude other feasible implementation forms. Therefore, the scope of protection of this case should be defined by the scope of the appended patent application, rather than being limited by the foregoing embodiments.
對本領域技術人員而言,在不脫離本案之精神和範圍內,當可對本案作各種之更動與潤飾。基於前述實施例,所有對本案所作的更動與潤飾,亦涵蓋於本案之保護範圍內。For those skilled in the art, without departing from the spirit and scope of this document, various changes and modifications can be made to this document. Based on the foregoing embodiments, all changes and modifications made to this case are also covered within the scope of protection of this case.
100, 100A:顯示裝置 110, 110A:控制電路 111, 111A:掃描電阻電容端 120, 120A:移位暫存器電路 121, 121A:輸出電路 122, 122A:掃頻電壓驅動電路 910, 910A:驅動移位暫存器電路 930, 930A:第一掃描移位暫存器電路 950, 950A:第二掃描移位暫存器電路 970A:設定移位暫存器電路 T1~T17:電晶體 DT1, DT2:驅動電晶體 ST1:選擇電晶體 PT1:脈衝寬度調變電晶體 C1~C4:電容 N1~N2:節點 L:發光元件 R[n]:重置訊號 EM[n], EM1[n], EM[n]:驅動訊號 VDD, VSS:電源供應電壓 Gate[n], Gate[n+1]:閘極訊號 EM_CLK:驅動時脈訊號 S1:第一串列輸入訊號 GOA:閘極驅動訊號 SC_CLK1:第一掃描時脈訊號 S2[N]:第二串列輸入訊號 SC_CLK2:第二掃描時脈訊號 S2[N+1]:次級第二串列輸入訊號 SW_CLK:掃頻時脈訊號 SW_H:掃頻高準位 SW_L:掃頻低準位 SW_slope[P]:斜率訊號 RES_DC:直流訊號 SWEEP[n]:掃頻訊號 PAM[n]:訊號 P1~P3:工作週期 I11~I17:階段 I21~I24:階段 VGL, VGH:電壓準位 PHG[n]:選擇訊號 Input:輸入訊號 Output:輸出端 PWD_DC:直流訊號 SET[n]:設定訊號 SET_CLK:時脈訊號 100, 100A: display device 110, 110A: control circuit 111, 111A: scanning resistance and capacitance terminals 120, 120A: shift register circuit 121, 121A: output circuit 122, 122A: frequency sweep voltage drive circuit 910, 910A: drive shift register circuit 930, 930A: the first scan shift register circuit 950, 950A: the second scan shift register circuit 970A: Set shift register circuit T1~T17: Transistor DT1, DT2: drive transistor ST1: select transistor PT1: pulse width modulation transistor C1~C4: capacitance N1~N2: Node L: light emitting element R[n]: reset signal EM[n], EM1[n], EM[n]: drive signal VDD, VSS: power supply voltage Gate[n], Gate[n+1]: gate signal EM_CLK: drive clock signal S1: The first serial input signal GOA: gate drive signal SC_CLK1: first scan clock signal S2[N]: The second serial input signal SC_CLK2: Second scan clock signal S2[N+1]: secondary second serial input signal SW_CLK: frequency sweep clock signal SW_H: Frequency sweep high level SW_L: Sweep low level SW_slope[P]: slope signal RES_DC: DC signal SWEEP[n]: frequency sweep signal PAM[n]: signal P1~P3: work cycle I11~I17: stage I21~I24: stage VGL, VGH: voltage level PHG[n]: select signal Input: input signal Output: output terminal PWD_DC: DC signal SET[n]: set signal SET_CLK: clock signal
參照後續段落中的實施方式以及下列圖式,當可更佳地理解本案的內容: 第1圖為根據本案一些實施例繪示的顯示裝置之電路方塊示意圖; 第2圖為根據本案一些實施例繪示的顯示裝置之驅動訊號時序示意圖; 第3圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路之電路方塊示意圖; 第4圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路之驅動訊號時序示意圖; 第5圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路之狀態示意圖; 第6圖為根據本案一些實施例繪示的顯示裝置之控制電路之狀態示意圖; 第7圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路之狀態示意圖; 第8圖為根據本案一些實施例繪示的顯示裝置之控制電路之狀態示意圖; 第9圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路之狀態示意圖; 第10圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路之狀態示意圖; 第11圖為根據本案一些實施例繪示的顯示裝置之控制電路之狀態示意圖; 第12圖為根據本案一些實施例繪示的顯示裝置之移位暫存器電路之狀態示意圖;以及 第13圖為根據本案一些實施例繪示的顯示裝置之電路方塊示意圖。 The content of this case can be better understood with reference to the implementation manner in the following paragraphs and the following drawings: Figure 1 is a schematic circuit block diagram of a display device according to some embodiments of the present invention; FIG. 2 is a schematic diagram of a timing sequence of driving signals of a display device according to some embodiments of the present invention; FIG. 3 is a schematic circuit block diagram of a shift register circuit of a display device according to some embodiments of the present invention; FIG. 4 is a schematic diagram of a timing sequence of driving signals of a shift register circuit of a display device according to some embodiments of the present invention; FIG. 5 is a schematic diagram of the state of the shift register circuit of the display device according to some embodiments of the present invention; FIG. 6 is a schematic diagram of the state of the control circuit of the display device according to some embodiments of the present invention; FIG. 7 is a schematic diagram of a state of a shift register circuit of a display device according to some embodiments of the present invention; FIG. 8 is a schematic diagram of the state of the control circuit of the display device according to some embodiments of the present invention; FIG. 9 is a schematic diagram of the state of the shift register circuit of the display device according to some embodiments of the present invention; FIG. 10 is a schematic diagram of the state of the shift register circuit of the display device according to some embodiments of the present invention; FIG. 11 is a schematic diagram of the state of the control circuit of the display device according to some embodiments of the present invention; FIG. 12 is a schematic diagram of a state of a shift register circuit of a display device according to some embodiments of the present invention; and FIG. 13 is a schematic circuit block diagram of a display device according to some embodiments of the present invention.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none
120:移位暫存器電路 120: Shift register circuit
121:輸出電路 121: output circuit
122:掃頻電壓驅動電路 122: frequency sweep voltage drive circuit
910:驅動移位暫存器電路 910: Driving shift register circuit
930:第一掃描移位暫存器電路 930: first scanning shift register circuit
950:第二掃描移位暫存器電路 950: The second scan shift register circuit
T7~T15:電晶體 T7~T15: Transistor
C2~C4:電容 C2~C4: capacitance
ST1:選擇電晶體 ST1: select transistor
EM_CLK:驅動時脈訊號 EM_CLK: drive clock signal
S1:第一串列輸入訊號 S1: The first serial input signal
GOA:閘極驅動訊號 GOA: gate drive signal
SC_CLK1:第一掃描時脈訊號 SC_CLK1: first scan clock signal
S2[N]:第二串列輸入訊號 S2[N]: The second serial input signal
SC_CLK2:第二掃描時脈訊號 SC_CLK2: Second scan clock signal
S2[N+1]:次級第二串列輸入訊號 S2[N+1]: secondary second serial input signal
SW_CLK:掃頻時脈訊號 SW_CLK: frequency sweep clock signal
SW_H:掃頻高準位 SW_H: Frequency sweep high level
SW_L:掃頻低準位 SW_L: Sweep low level
SW_slope[P]:斜率訊號 SW_slope[P]: slope signal
VGL,VGH:電壓準位 VGL, VGH: voltage level
PHG[n]:選擇訊號 PHG[n]: select signal
Output:輸出端 Output: output terminal
EM[n]:驅動訊號 EM[n]: drive signal
SWEEP[n]:掃頻訊號 SWEEP[n]: frequency sweep signal
Claims (10)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW110122478A TWI782585B (en) | 2021-06-18 | 2021-06-18 | Display device |
CN202111474668.6A CN114120879B (en) | 2021-06-18 | 2021-12-03 | Display apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW110122478A TWI782585B (en) | 2021-06-18 | 2021-06-18 | Display device |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI782585B true TWI782585B (en) | 2022-11-01 |
TW202301308A TW202301308A (en) | 2023-01-01 |
Family
ID=80366695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110122478A TWI782585B (en) | 2021-06-18 | 2021-06-18 | Display device |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN114120879B (en) |
TW (1) | TWI782585B (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201503080A (en) * | 2013-07-01 | 2015-01-16 | Au Optronics Corp | Organic light-emitting diode display panel |
US20170256209A1 (en) * | 2016-03-02 | 2017-09-07 | Samsung Electronics Co., Ltd. | Image display apparatus and method of driving the same |
TW201737231A (en) * | 2016-01-26 | 2017-10-16 | Japan Display Inc | Display device |
CN108399895A (en) * | 2018-05-31 | 2018-08-14 | 京东方科技集团股份有限公司 | Display panel and its driving method, display device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0682754A (en) * | 1992-07-16 | 1994-03-25 | Toshiba Corp | Active matrix type display device |
JP4514852B2 (en) * | 1999-07-16 | 2010-07-28 | 三菱電機株式会社 | Image transmission apparatus and image transmission system |
EP3389039A1 (en) * | 2017-04-13 | 2018-10-17 | Samsung Electronics Co., Ltd. | Display panel and driving method of display panel |
KR102664219B1 (en) * | 2017-04-13 | 2024-05-09 | 삼성전자주식회사 | Display panel and driving method of the display panel |
-
2021
- 2021-06-18 TW TW110122478A patent/TWI782585B/en active
- 2021-12-03 CN CN202111474668.6A patent/CN114120879B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201503080A (en) * | 2013-07-01 | 2015-01-16 | Au Optronics Corp | Organic light-emitting diode display panel |
TW201737231A (en) * | 2016-01-26 | 2017-10-16 | Japan Display Inc | Display device |
US20170256209A1 (en) * | 2016-03-02 | 2017-09-07 | Samsung Electronics Co., Ltd. | Image display apparatus and method of driving the same |
CN108399895A (en) * | 2018-05-31 | 2018-08-14 | 京东方科技集团股份有限公司 | Display panel and its driving method, display device |
Also Published As
Publication number | Publication date |
---|---|
TW202301308A (en) | 2023-01-01 |
CN114120879A (en) | 2022-03-01 |
CN114120879B (en) | 2024-03-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5232956B2 (en) | Liquid crystal display | |
JP4993544B2 (en) | Shift register circuit | |
US11355070B2 (en) | Shift register unit, gate driving circuit and control method thereof and display apparatus | |
JP5079301B2 (en) | Shift register circuit and image display apparatus including the same | |
US7233308B2 (en) | Shift register | |
US7289594B2 (en) | Shift registrer and driving method thereof | |
KR101022173B1 (en) | Shift Register and Organic Light Emitting Display Device Using the Same | |
WO2018040711A1 (en) | Shift register and driving method thereof, gate driving circuit and display device | |
WO2017016190A1 (en) | Shift register, display device, and shift register driving method | |
KR102015396B1 (en) | Shift register and method for driving the same | |
WO2009104307A1 (en) | Shift register circuit, display device, and method for driving shift register circuit | |
JP2006106320A (en) | Driving circuit of liquid crystal display device | |
WO2019154122A1 (en) | Shift register and method for driving same, and gate driving circuit and display apparatus | |
KR20050096568A (en) | Shift register | |
TWI417859B (en) | Gate driver and operating method thereof | |
US20110234565A1 (en) | Shift register circuit, display device, and method for driving shift register circuit | |
WO2019015267A1 (en) | Shift register unit and driving method therefor, gate drive circuit | |
JP2008251094A (en) | Shift register circuit and image display apparatus with the same | |
WO2018126687A1 (en) | Shift register circuit, driving method therefor, gate drive circuit and display device | |
CN111326096A (en) | GOA circuit and display panel | |
WO2022110924A1 (en) | Shift register and display panel | |
KR101027827B1 (en) | Shift register and method for driving the same | |
CN111326097B (en) | GOA circuit and display panel | |
CN113643659A (en) | Organic light emitting diode display device | |
TWI782585B (en) | Display device |