TWI781836B - Semiconductor memory device - Google Patents

Abstract

本發明提出一種半導體記憶裝置，其主要包括一記憶體陣列(1)、複數個控制電路(2)、複數個預充電電路(3)、一待機啟動電路(4)、複數個高電壓位準控制電路(5)、複數個讀取用字元線控制電路(6)、以及複數個寫入驅動電路(7)。本發明於SRAM晶胞中設置一耦合元件控制器，連接於寫入用字元線(WWL)、寫入用位元線(WBL)與儲存節點(A)之間，該耦合元件控制器因應該寫入用字元線(WWL)、該寫入用位元線(WBL)與該儲存節點(A)之邏輯狀態而提供不同的耦合電容，其中當該寫入用字元線(WWL)及該寫入用位元線(WBL)均為高邏輯狀態且該儲存節點(A)所儲存之邏輯狀態為邏輯0時提供最大的耦合電容，亦即僅當SRAM晶胞被選定且該儲存節點(A)由邏輯0寫入邏輯1時，才於該寫入用字元線(WWL)及該儲存節點(A)之間提供最大的耦合電容，藉此，可於有效提高寫入邏輯1之速度的同時，亦避免無謂的半選定干擾(half-selected disturbance)。 The present invention proposes a semiconductor memory device, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of pre-charging circuits (3), a standby startup circuit (4), and a plurality of high voltage levels A control circuit (5), a plurality of read word line control circuits (6), and a plurality of write drive circuits (7). In the present invention, a coupling element controller is arranged in the SRAM unit cell, which is connected between the word line (WWL) for writing, the bit line (WBL) for writing and the storage node (A). Different coupling capacitors should be provided for the logic states of the write word line (WWL), the write bit line (WBL) and the storage node (A), wherein when the write word line (WWL) And the write bit line (WBL) is in a high logic state and the logic state stored in the storage node (A) is logic 0 to provide the maximum coupling capacitance, that is, only when the SRAM unit cell is selected and the storage node (A) When the node (A) is written from logic 0 to logic 1, the maximum coupling capacitance is provided between the word line (WWL) for writing and the storage node (A), thereby effectively improving the write logic 1 while avoiding unnecessary half-selected disturbance.

Description

半導體記憶裝置 semiconductor memory device

本發明係有關於一種具高讀取/寫入速度之雙埠(dual port)靜態隨機存取記憶體(Static Random Access Memory，簡稱SRAM)，尤指一種有效提高7T SRAM待機效能，並能有效提高讀取速度與寫入速度，且能有效降低漏電流(leakage current)、降低讀取時之半選定晶胞干擾以及避免無謂的功率耗損之SRAM。 The present invention relates to a dual port (dual port) static random access memory (SRAM for short) with high read/write speed, especially a kind of effectively improving the standby performance of 7T SRAM, and can effectively The SRAM improves the reading speed and writing speed, and can effectively reduce the leakage current, reduce the interference of the semi-selected cell when reading, and avoid unnecessary power consumption.

習知之單埠靜態隨機存取記憶體(SRAM)如第1a圖所示，其主要包括一記憶體陣列(memory array)，該記憶體陣列係由複數個記憶體區塊(memory block，MB₁、MB₂等)所組成，每一記憶體區塊更由複數列記憶體晶胞(a plurality of rows of memory cells)與複數行記憶體晶胞(a plurality of columns of memory cells)所組成，每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體晶胞；複數條字元線(word line，WL₁、WL₂等)，每一字元線對應至複數列記憶體晶胞中之一列；以及複數位元線對(bit line pairs，BL₁、BLB₁...BL_m、BLB_m等)，每一位元線對係對應至複數行記憶體晶胞中之一行，且每一位元線對係由一位元線(BL₁...BL_m)及一互補位元線(BLB₁...BLB_m)所組成。 The conventional static random access memory (SRAM), as shown in Figure 1a, mainly includes a memory array (memory array), which is composed of a plurality of memory blocks (memory block, MB ₁ , MB ₂ , etc.), and each memory block is composed of a plurality of rows of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL ₁ , WL ₂ , etc.), each word line corresponds to a plurality of columns of memory One column in the bulk unit cell; and complex bit line pairs (bit line pairs, BL ₁ , BLB ₁ ... BL _m , BLB _m , etc.), each bit line pair corresponds to a plurality of rows of memory unit cells Each bit line pair is composed of a bit line (BL ₁ ... BL _m ) and a complementary bit line (BLB ₁ ... BLB _m ).

第1b圖所示即是6T單埠靜態隨機存取記憶體(SRAM)晶胞 之電路示意圖，其中，PMOS電晶體(P1)和(P2)稱為負載電晶體(load transistor)，NMOS電晶體(M1)和(M2)稱為驅動電晶體(driving transistor)，NMOS電晶體(M3)和(M4)稱為存取電晶體(access transistor)，WL為字元線(word line)，而BL及BLB分別為位元線(bit line)及互補位元線(complementary bit line)，由於該單埠SRAM晶胞需要6個電晶體，且於讀取邏輯0時，為了避免讀取操作初始瞬間(initial instant)另一驅動電晶體導通，節點A之讀取初始瞬間電壓(V_AR)必須滿足方程式(1)： Figure 1b is a schematic circuit diagram of a 6T static random access memory (SRAM) unit cell, where PMOS transistors (P1) and (P2) are called load transistors, and NMOS transistors (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is a word line, and BL and BLB are the bit line and the complementary bit line respectively, since the port SRAM unit cell requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial instant) Another driving transistor is turned on, and the initial instantaneous voltage (V _AR ) of node A must satisfy equation (1):

V_AR=V_DD×(R_M1)/(R_M1+R_M3)<V_TM2 (1)以防止讀取時之半選定晶胞干擾(half-selected cell disturbance)，其中，V_AR表示節點A之讀取初始瞬間電壓，R_M1與R_M3分別表示該NMOS電晶體(M1)與該NMOS電晶體(M3)之導通電阻，而V_DD與V_TM2分別表示電源供應電壓與該NMOS電晶體(M2)之臨界電壓，此導致驅動電晶體與存取電晶體之間的電流驅動能力比(即單元比率，cell ratio)通常設定在2.2至3.5之間(請參考98年10月20日第US76060B2號專利說明書第2欄第8-10行)。 V _AR =V _DD ×(R _M1 )/(R _M1 +R _M3 )<V _TM2 (1) to prevent half-selected cell disturbance when reading, where V _AR represents node A R _M1 and R _M3 represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3) respectively, and V _DD and V _TM2 represent the power supply voltage and the NMOS transistor ( M2) critical voltage, which causes the current drive capability ratio (i.e. cell ratio, cell ratio) between the drive transistor and the access transistor to be usually set between 2.2 and 3.5 (please refer to US76060B2 on October 20, 1998 No. 2 patent specification column 8-10 lines).

第1b圖所示6T單埠靜態隨機存取記憶體晶胞於寫入操作時之HSPICE暫態分析模擬結果，如第2圖所示，其係使用TSMC 90奈米CMOS製程參數加以模擬。 Figure 1b shows the HSPICE transient analysis simulation results of the 6T port SRAM unit cell during the write operation, as shown in Figure 2, which is simulated using TSMC 90nm CMOS process parameters.

用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之一種方式係揭露於第3圖中。第3圖顯示一種僅具單一位元線之5T單埠靜態隨機存取記憶體晶胞之電路示意圖，與第1b圖之6T單埠靜態隨機存取記憶體晶胞相比，此種5T靜態隨機存取記憶體晶胞比6T靜態隨機存取記憶體晶胞少一個電晶體及少一條位元線，惟該5T單埠靜態隨機存取記憶體晶胞 在不變更PMOS電晶體P1和P2以及NMOS電晶體M1、M2和M3的通道寬長比的情況下存在寫入邏輯1相當困難之問題。茲考慮記憶體晶胞左側節點A原本儲存邏輯0的情況，由於節點A之電荷僅單獨自位元線(BL)傳送，因此在將節點A中先前寫入的邏輯0蓋寫成邏輯1之寫入初始瞬間電壓(V_AW)等於方程式(2)： One way to reduce the number of transistors in a 6T SRAM cell is disclosed in FIG. 3 . Figure 3 shows a schematic circuit diagram of a 5T port SRAM unit cell with only a single bit line. Compared with the 6T port SRAM unit cell in Figure 1b, this 5T SRAM unit cell The random access memory unit cell has one less transistor and one bit line less than the 6T SRAM unit cell, but the 5T SRAM unit cell does not change the PMOS transistors P1 and P2 And in the case of the channel width-to-length ratio of the NMOS transistors M1, M2, and M3, there is a problem that it is quite difficult to write a logic 1. Considering the case where the node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the bit line (BL) alone, the logic 0 previously written in node A is overwritten with logic 1. Entering the initial instantaneous voltage (V _AW ) is equal to equation (2):

V_AW=V_DD×(R_M1)/(R_M1+R_M3) (2)其中，V_AW表示節點A之寫入初始瞬間電壓，R_M1與R_M3分別表示NMOS電晶體(M1)與NMOS電晶體(M3)之導通電阻，比較方程式(1)與方程式(2)可知，寫入初始瞬間電壓(V_AW)小於NMOS電晶體(M2)之臨界電壓(V_TM2)，因而無法完成寫入邏輯1之操作。第3圖所示5T靜態隨機存取記憶體晶胞，於寫入操作時之HSPICE暫態分析模擬結果，如第4圖所示，其係使用TSMC 90奈米CMOS製程參數加以模擬，由該模擬結果可証實，具單一位元線之5T靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。 V _AW =V _DD ×(R _M1 )/(R _M1 +R _M3 ) (2) Among them, V _AW represents the initial writing voltage of node A, R _M1 and R _M3 represent NMOS transistor (M1) and NMOS The on-resistance of the transistor (M3), comparing equation (1) and equation (2), shows that the initial instant voltage of writing (V _AW ) is lower than the critical voltage (V _TM2 ) of the NMOS transistor (M2), so the writing cannot be completed Operation of logic 1. Figure 3 shows the 5T SRAM unit cell, the HSPICE transient analysis simulation results during the write operation, as shown in Figure 4, it is simulated using TSMC 90nm CMOS process parameters, by the The simulation results can confirm that it is very difficult to write a logic 1 in a 5T SRAM cell with a single bit line.

接下來討論靜態隨機存取記憶體(SRAM)之單埠及雙埠架構，第1b圖之6T靜態隨機存取記憶體(SRAM)晶胞即是單埠靜態隨機存取記憶體(SRAM)晶胞之一例，其係使用兩條位元線BL及BLB做讀寫的動作，也就是讀與寫均是經由同樣的一對位元線來達成，是以在同一時間內只能進行讀或寫的動作，因此，當欲設計具有同時讀寫能力之雙埠靜態隨機存取記憶體時，便需要多加入兩顆存取電晶體以及另一對位元線，這使得記憶體晶胞的面積大大地增加，如果我們能夠簡化記憶體晶胞的架構，使得一條位元線負責讀取的動作，而另一條位元線負責寫入的動作，則雙埠靜態隨機存取記憶體晶胞的面積便會減小許多，傳統的雙埠靜態隨機存取記 憶體晶胞之所以不採用這種方法，是因為如前所述存在寫入邏輯1相當困難之問題。 Next, discuss the port and dual-port architecture of static random access memory (SRAM). The 6T static random access memory (SRAM) unit cell in Figure 1b is the port static random access memory (SRAM) chip An example of a cell, which uses two bit lines BL and BLB for reading and writing, that is, reading and writing are achieved through the same pair of bit lines, so only reading or writing can be performed at the same time Therefore, when it is desired to design a dual-port SRAM with simultaneous read and write capabilities, it is necessary to add two more access transistors and another pair of bit lines, which makes the memory cell The area is greatly increased. If we can simplify the structure of the memory unit cell so that one bit line is responsible for the reading action, while the other bit line is responsible for the writing action, then the dual-port static random access memory unit cell The area will be reduced a lot, the traditional dual-port SRAM The reason why memory cells do not use this method is because of the difficulty of writing a logic 1 as mentioned earlier.

迄今，有許多具單一讀取位元線之雙埠靜態隨機存取記憶體晶胞之技術被提出，例如專利文獻所提出之「半導體記憶體裝置」(TW I733624B，110年7月11日授予修平科技大學)，其指定代表圖如第5圖所示，惟該專利文獻於寫入操作時仍有下列缺失，該專利文獻為了提高寫入速度，設計有寫入用字元線控制電路(6)，該寫入用字元線控制電路(6)於寫入用字元線(WWL)致能的第一階段，將寫入用字元線(WWL)設定成較電源供應電壓(V_DD)還高之第二高電源供應電壓(V_DDH2)，其雖可有效加速寫入邏輯1之速度，惟由於此時該寫入用字元線(WWL)設定成較電源供應電壓(V_DD)還高之第二高電源供應電壓(V_DDH2)，其亦會造成半選定SRAM晶胞之寫入干擾，因此仍有改進空間。 So far, many technologies of dual-port static random access memory cells with a single read bit line have been proposed, such as the "semiconductor memory device" proposed in the patent literature (TW I733624B, granted on July 11, 110 Xiuping University of Science and Technology), its designated representative figure is shown in Figure 5, but the patent document still has the following deficiencies during the writing operation. In order to improve the writing speed, the patent document is designed with a word line control circuit for writing ( 6), the write word line control circuit (6) sets the write word line (WWL) to a voltage higher than the power supply voltage (V _DD ) is still higher than the second highest power supply voltage (V _DDH2 ), which can effectively speed up the speed of writing logic 1, but because the word line (WWL) for writing is set to be higher than the power supply voltage (V _DD ) is also higher than the second highest power supply voltage (V _DDH2 ), which will also cause write disturbance to half-selected SRAM cells, so there is still room for improvement.

有鑑於此，本發明之目的係提出一種半導體記憶裝置，其能藉由於SRAM晶胞中設置一耦合元件控制器，連接於寫入用字元線(WWL)、寫入用位元線(WBL)與儲存節點(A)之間，其中，該寫入用字元線(WWL)致能之電壓位準為電源供應電壓(V_DD)，而非如前述專利文獻所載較該電源供應電壓(V_DD)還高之該第二高電源供應電壓(V_DDH2)，該耦合元件控制器因應該寫入用字元線(WWL)、該寫入用位元線(WBL)與該儲存節點(A)之邏輯狀態而提供不同的耦合電容，其中當該寫入用字元線(WWL)及該寫入用位元線(WBL)均為高邏輯狀態且該儲存節點(A)所儲存之邏輯狀態為邏輯0時提供最大的耦合電容，亦即僅當SRAM晶胞被選定且該儲存節點(A)由邏輯0寫入邏輯1時，才於該寫入用字元線(WWL)及該儲 存節點(A)之間提供最大的耦合電容，藉此，可於有效提高寫入邏輯1之速度的同時，亦避免無謂的半選定干擾(half-selected disturbance)。 In view of this, the purpose of the present invention is to propose a semiconductor memory device, which can be connected to the word line (WWL) for writing and the bit line (WBL) for writing by setting a coupling element controller in the SRAM unit cell. ) and the storage node (A), wherein the voltage level for enabling the word line for writing (WWL) is the power supply voltage (V _DD ), rather than comparing the power supply voltage as stated in the aforementioned patent documents (V _DD ) higher than the second high power supply voltage (V _DDH2 ), the coupling element controller responds to the write word line (WWL), the write bit line (WBL) and the storage node Different coupling capacitances are provided for the logic state of (A), wherein when the write word line (WWL) and the write bit line (WBL) are both in a high logic state and the storage node (A) stores The maximum coupling capacitance is provided when the logic state is logic 0, that is, only when the SRAM unit cell is selected and the storage node (A) is written from logic 0 to logic 1, the word line (WWL) for writing The maximum coupling capacitance is provided between the storage node (A) and the storage node (A), thereby effectively increasing the writing speed of logic 1 and avoiding unnecessary half-selected disturbance.

本發明提出一種半導體記憶裝置，其主要包括一記憶體陣列(1)、複數個控制電路(2)、複數個預充電電路(3)、一待機啟動電路(4)、複數個高電壓位準控制電路(5)、複數個讀取用字元線控制電路(6)、以及複數個寫入驅動電路(7)。本發明於SRAM晶胞中設置一耦合元件控制器，連接於寫入用字元線(WWL)、寫入用位元線(WBL)與儲存節點(A)之間，該耦合元件控制器因應該寫入用字元線(WWL)、該寫入用位元線(WBL)與該儲存節點(A)之邏輯狀態而提供不同的耦合電容，其中當該寫入用字元線(WWL)及該寫入用位元線(WBL)均為高邏輯狀態且該儲存節點(A)所儲存之邏輯狀態為邏輯0時提供最大的耦合電容，亦即僅當SRAM晶胞被選定且該儲存節點(A)由邏輯0寫入邏輯1時，才於該寫入用字元線(WWL)及該儲存節點(A)之間提供最大的耦合電容，藉此，可於有效提高寫入邏輯1之速度的同時，亦避免無謂的半選定干擾(half-selected disturbance)。 The present invention proposes a semiconductor memory device, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of pre-charging circuits (3), a standby startup circuit (4), and a plurality of high voltage levels A control circuit (5), a plurality of read word line control circuits (6), and a plurality of write drive circuits (7). In the present invention, a coupling element controller is arranged in the SRAM unit cell, which is connected between the word line (WWL) for writing, the bit line (WBL) for writing and the storage node (A). Different coupling capacitors should be provided for the logic states of the write word line (WWL), the write bit line (WBL) and the storage node (A), wherein when the write word line (WWL) And the write bit line (WBL) is in a high logic state and the logic state stored in the storage node (A) is logic 0 to provide the maximum coupling capacitance, that is, only when the SRAM unit cell is selected and the storage node (A) When the node (A) is written from logic 0 to logic 1, the maximum coupling capacitance is provided between the word line (WWL) for writing and the storage node (A), thereby effectively improving the write logic 1 while avoiding unnecessary half-selected disturbance.

1:SRAM晶胞 1: SRAM unit cell

2:控制電路 2: Control circuit

3:預充電電路 3: Precharge circuit

4:待機啟動電路 4: Standby startup circuit

5:高電壓位準控制電路 5: High voltage level control circuit

6:讀取用字元線控制電路 6: Read word line control circuit

7:寫入驅動電路 7: Write drive circuit

SW:開關 SW: switch

P11:第一PMOS電晶體 P11: The first PMOS transistor

P12:第二PMOS電晶體 P12: The second PMOS transistor

M11:第一NMOS電晶體 M11: The first NMOS transistor

M12:第二NMOS電晶體 M12: The second NMOS transistor

M13:第三NMOS電晶體 M13: The third NMOS transistor

A:儲存節點 A: storage node

B:反相儲存節點 B: Inversion storage node

CE:耦合元件 CE: coupling element

M14:第一讀取用電晶體 M14: The first read transistor

M15:第二讀取用電晶體 M15: Second reading transistor

WBL:寫入用位元線 WBL: bit line for writing

WWL:寫入用字元線 WWL: word line for writing

RBL:讀取用位元線 RBL: read bit line

RWL:讀取用字元線 RWL: word line for reading

RWLC:讀取用字元線控制信號 RWLC: word line control signal for reading

C:節點 C: node

S:待機模式控制信號 S: Standby mode control signal

/S:反相待機模式控制信號 /S: reverse phase standby mode control signal

VL1:第一低電壓節點 VL1: the first low voltage node

VL2:第二低電壓節點 VL2: second low voltage node

M21:第四NMOS電晶體 M21: The fourth NMOS transistor

M22:第五NMOS電晶體 M22: Fifth NMOS transistor

M23:第六NMOS電晶體 M23: The sixth NMOS transistor

M24:第七NMOS電晶體 M24: The seventh NMOS transistor

M25:第八NMOS電晶體 M25: Eighth NMOS transistor

M26:第九NMOS電晶體 M26: Ninth NMOS transistor

M27:第十NMOS電晶體 M27: Tenth NMOS transistor

P21:第三PMOS電晶體 P21: The third PMOS transistor

RC:讀取控制信號 RC: read control signal

RGND:加速讀取電壓 RGND: Accelerated reading voltage

INV3:第三反相器 INV3: The third inverter

D1:第一延遲電路 D1: The first delay circuit

WC:寫入控制信號 WC: write control signal

P31:第四PMOS電晶體 P31: The fourth PMOS transistor

P:預充電信號 P: Precharge signal

M41:第十一NMOS電晶體 M41: Eleventh NMOS transistor

P41:第五PMOS電晶體 P41: Fifth PMOS transistor

D2:第二延遲電路 D2: Second delay circuit

V_DD:電源供應電壓 V _DD : power supply voltage

V_DDH1:第一高電源供應電壓 V _DDH1 : first high power supply voltage

V_DDH2:第二高電源供應電壓 V _DDH2 : The second highest power supply voltage

P51:第六PMOS電晶體 P51: The sixth PMOS transistor

P52:第七PMOS電晶體 P52: The seventh PMOS transistor

INV4:第四反相器 INV4: Fourth inverter

VH:高電壓節點 VH: high voltage node

P61:第八PMOS電晶體 P61: Eighth PMOS transistor

P62:第九PMOS電晶體 P62: Ninth PMOS transistor

P63:第十PMOS電晶體 P63: Tenth PMOS transistor

M61:第十二NMOS電晶體 M61: Twelfth NMOS transistor

INV5:第五反相器 INV5: fifth inverter

INV6:第六反相器 INV6: sixth inverter

P71:第十一PMOS電晶體 P71: Eleventh PMOS transistor

M71:第十三NMOS電晶體 M71: Thirteenth NMOS transistor

M72:第十四NMOS電晶體 M72: Fourteenth NMOS transistor

M73:第十五NMOS電晶體 M73: Fifteenth NMOS transistor

INV7:第七反相器 INV7: seventh inverter

INV8:第八反相器 INV8: eighth inverter

D3:第三延遲電路 D3: The third delay circuit

D4:第四延遲電路 D4: The fourth delay circuit

V_DDH3:第三高電源供應電壓 V _DDH3 : The third highest power supply voltage

Y:行解碼器輸出信號 Y: line decoder output signal

Cap:電容器 Cap: Capacitor

Din:輸入資料 Din: input data

BLB:互補位元線 BLB: complementary bit line

BLB₁…BLB_m:互補位元線 BLB ₁ …BLB _m : complementary bit lines

MB₁…MB_k:記憶體區塊 MB ₁ …MB _k : memory block

WL₁…WL_n:字元線 WL ₁ …WL _n : word line

BL₁…BL_m:位元線 BL ₁ …BL _m : bit lines

M1…M4:NMOS電晶體 M1…M4: NMOS transistors

P1…P2:PMOS電晶體 P1…P2: PMOS transistors

第1a圖 係顯示習知之靜態隨機存取記憶體； Figure 1a shows a conventional static random access memory;

第1b圖 係顯示習知6T靜態隨機存取記憶體晶胞之電路示意圖； Figure 1b is a schematic circuit diagram showing a conventional 6T SRAM unit cell;

第2圖 係顯示習知6T靜態隨機存取記憶體晶胞之寫入動作時序圖； Figure 2 is a timing diagram showing the writing action of a conventional 6T SRAM unit cell;

第3圖 係顯示習知5T靜態隨機存取記憶體晶胞之電路示意圖； Figure 3 is a circuit diagram showing a conventional 5T SRAM unit cell;

第4圖 係顯示習知5T靜態隨機存取記憶體晶胞之寫入動作時序圖； Figure 4 is a timing diagram showing the writing action of a conventional 5T SRAM unit cell;

第5圖 係顯示習知TW I733624B之指定代表圖； Figure 5 is a designated representative figure showing the conventional TW I733624B;

第6圖 係顯示本發明較佳實施例所提出之電路示意圖； Fig. 6 shows a schematic circuit diagram of a preferred embodiment of the present invention;

第7a圖 係顯示第6圖於寫入邏輯0期間之簡化電路圖； Figure 7a is a simplified circuit diagram showing the period of writing logic 0 in Figure 6;

第7b圖 係顯示第6圖於寫入邏輯1期間之簡化電路圖； Figure 7b shows a simplified circuit diagram of Figure 6 during writing logic 1;

第8圖 係顯示第6圖於讀取期間之簡化電路圖。 Figure 8 is a simplified circuit diagram showing Figure 6 during reading.

根據上述之目的，本發明提出一種半導體記憶裝置，其主要包括一記憶體陣列，該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成，每一列記憶體晶胞與每一行記憶體晶胞均包括有複數個記憶體晶胞(1)；複數個控制電路(2)，每一列記憶體晶胞設置一個控制電路(2)；複數個預充電電路(3)，每一行記憶體晶胞設置一個預充電電路(3)；一待機啟動電路(4)，該待機啟動電路(4)係促使雙埠SRAM快速進入待機模式，以有效提高雙埠SRAM之待機效能；複數個高電壓位準控制電路(5)，每一列記憶體晶胞設置一個高電壓位準控制電路(5)，以在讀取邏輯0時減少讀取路徑之電阻從而提高讀取速度；複數個讀取用字元線控制電路(6)，每一列記憶體晶胞設置一個讀取用字元線控制電路(6)，以在讀取邏輯0時，於對應讀取用用字元線(RWL)致能的第一階段，將對應讀取用字元線控制信號(RWLC)設定成較電源供應電壓(V_DD)還高之第二高電源供應電壓(V_DDH2)，以進一步減少讀取路徑之電阻，並加速讀取用位元線(RWL)上之電荷的放電，從而有效提高讀取速度；以及複數個寫入驅動電路(7)，每一行記憶體晶胞設置一個寫入驅動電路(7)，以在寫入邏輯0之第一階段將低於接地電壓之電壓位準施加至寫入用位元線(WBL)， 以加速寫入邏輯0之速度，而於寫入邏輯1時則將高於電源供應電壓(V_DD)之第三高電源供應電壓(V_DDH3)的位準加至該寫入用位元線(WBL)，以加速寫入邏輯1之速度。 According to the above-mentioned purpose, the present invention proposes a semiconductor memory device, which mainly includes a memory array, which is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and a plurality of rows of memory cells Each row of memory cells includes a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of pre-charging circuits (3), Each row of memory unit cells is provided with a pre-charging circuit (3); a standby start-up circuit (4), the standby start-up circuit (4) prompts the dual-port SRAM to quickly enter the standby mode to effectively improve the standby performance of the dual-port SRAM; A plurality of high-voltage level control circuits (5), one high-voltage level control circuit (5) is provided for each row of memory cells, so as to reduce the resistance of the read path when reading logic 0 and thus increase the read speed; A word line control circuit (6) for reading, each row of memory cells is provided with a word line control circuit (6) for reading, so that when reading logic 0, the corresponding word line for reading In the first stage of enabling (RWL), the corresponding read word line control signal (RWLC) is set to the second highest power supply voltage (V _DDH2 ) higher than the power supply voltage (V _DD ) to further reduce Read the resistance of the path, and accelerate the discharge of the charge on the read bit line (RWL), thereby effectively improving the read speed; and a plurality of write drive circuits (7), each row of memory cells is provided with a write In the drive circuit (7), in order to apply a voltage level lower than the ground voltage to the bit line (WBL) for writing in the first stage of writing logic 0, so as to speed up the speed of writing logic 0, while writing When entering logic 1, the level of the third highest power supply voltage (V _DDH3 ) higher than the power supply voltage (V _DD ) is added to the writing bit line (WBL) to speed up the speed of writing logic 1 .

為了便於說明起見，第6圖所示之半導體記憶裝置僅以一個記憶體晶胞(1)、一條寫入用字元線(WWL)、一條寫入用位元線(WBL)、一條讀取用字元線(RWL)、一條讀取用位元線(RBL)、一控制電路(2)、一預充電電路(3)、一待機啟動電路(4)、一高電壓位準控制電路(5)、一讀取用字元線控制電路(6)以及一寫入驅動電路(7)做為實施例來說明。該記憶體晶胞(1)係包括一第一反相器(由一第一PMOS電晶體P11與一第一NMOS電晶體M11所組成)、一第二反相器(由一第二PMOS電晶體P12與一第二NMOS電晶體M12所組成)、一第三NMOS電晶體(M13)、一第一讀取用電晶體(M14)、一第二讀取用電晶體(M15)以及一耦合元件控制器，其中，該第一反相器及該第二反相器係呈交互耦合連接，亦即該第一反相器之輸出(即節點A)係連接該第二反相器之輸入，而該第二反相器之輸出(即節點B)則連接該第一反相器之輸入，並且該第一反相器之輸出(節點A)係用於儲存SRAM晶胞之資料，而該第二反相器之輸出(節點B)則用於儲存SRAM晶胞之反相資料。 For the sake of illustration, the semiconductor memory device shown in Figure 6 only uses a memory cell (1), a word line (WWL) for writing, a bit line (WBL) for writing, and a A read word line (RWL), a read bit line (RBL), a control circuit (2), a pre-charge circuit (3), a standby startup circuit (4), a high voltage level control circuit (5), a read word line control circuit (6) and a write drive circuit (7) are described as embodiments. The memory unit cell (1) includes a first inverter (made up of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (made up of a second PMOS transistor crystal P12 and a second NMOS transistor M12), a third NMOS transistor (M13), a first read transistor (M14), a second read transistor (M15) and a coupling A device controller, wherein the first inverter and the second inverter are cross-coupled, that is, the output of the first inverter (i.e. node A) is connected to the input of the second inverter , and the output of the second inverter (i.e. node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM unit cell, and The output (node B) of the second inverter is used to store the inverted data of the SRAM cell.

該記憶體晶胞(1)之該第一反相器(由該第一PMOS電晶體P11與該第一NMOS電晶體M11所組成)係連接在一電源供應電壓(V_DD)與一第一低電壓節點(VL1)之間，該第二反相器(由該第二PMOS電晶體P12與該第二NMOS電晶體M12所組成)係連接在一高電壓節點(VH)與一第二低電壓節點(VL2)之間，該第一讀取用電晶體(M14)之源極、閘極 與汲極係分別連接至該第二讀取用電晶體(M15)之汲極、該讀取用字元線(RWL)與該讀取用位元線(RBL)，而該第二讀取用電晶體(M15)之源極、閘極與汲極則分別連接至該第二低電壓節點(VL2)、該第二反相器之輸出(即節點B)與該第一讀取用電晶體(M14)之源極。 The first inverter of the memory cell (1) (composed of the first PMOS transistor P11 and the first NMOS transistor M11) is connected to a power supply voltage (V _DD ) and a first Between the low voltage node (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected between a high voltage node (VH) and a second low voltage node. Between the voltage nodes (VL2), the source, gate and drain of the first read transistor (M14) are respectively connected to the drain of the second read transistor (M15), the read The word line (RWL) and the read bit line (RBL), and the source, gate and drain of the second read transistor (M15) are respectively connected to the second low voltage node (VL2), the output of the second inverter (ie node B) and the source of the first read transistor (M14).

該耦合元件控制器係由一開關(SW)及一耦合元件(CE)所組成，其中該開關係由一NMOS電晶體所組成，該NMOS電晶體之閘極連接該寫入用位元線(WBL)，該NMOS電晶體之汲極連接該寫入用字元線(WWL)，而該NMOS電晶體之源極連接該耦合元件(CE)之一端；該耦合元件(CE)亦係由一NMOS電晶體所組成，其閘極連接該開關之該NMOS電晶體的源極，其源極與汲極連接在一起並連接至該節點(A)。其中，該寫入用字元線(WWL)致能之電壓位準為該電源供應電壓(V_DD)，當該寫入用字元線(WWL)及該寫入用位元線(WBL)均為高邏輯狀態且該節點(A)所儲存之邏輯狀態為邏輯0時提供最大的耦合電容，亦即僅當SRAM晶胞被選定且該節點(A)由邏輯0寫入邏輯1時，才於該寫入用字元線(WWL)及該節點(A)之間提供最大的耦合電容，藉此，可於有效提高寫入邏輯1之速度的同時，亦避免無謂的半選定干擾(half-selected disturbance)。 The coupling element controller is composed of a switch (SW) and a coupling element (CE), wherein the switch is composed of an NMOS transistor, and the gate of the NMOS transistor is connected to the bit line for writing ( WBL), the drain of the NMOS transistor is connected to the write word line (WWL), and the source of the NMOS transistor is connected to one end of the coupling element (CE); the coupling element (CE) is also composed of a Composed of NMOS transistors, the gate of which is connected to the source of the NMOS transistor of the switch, and the source and drain of which are connected together and connected to the node (A). Wherein, the enabling voltage level of the writing word line (WWL) is the power supply voltage (V _DD ), when the writing word line (WWL) and the writing bit line (WBL) When both are in a high logic state and the logic state stored in the node (A) is logic 0, the maximum coupling capacitance is provided, that is, only when the SRAM cell is selected and the node (A) is written from a logic 0 to a logic 1, The largest coupling capacitance is provided between the word line (WWL) for writing and the node (A), thereby effectively increasing the speed of writing logic 1 and avoiding unnecessary half-selected interference ( half-selected disturbance).

請再參考第6圖，該控制電路(2)係由一第四NMOS電晶體(M21)、一第五NMOS電晶體(M22)、一第六NMOS電晶體(M23)、一第七NMOS電晶體(M24)、一第八NMOS電晶體(M25)、一第九NMOS電晶體(M26)、一第十NMOS電晶體(M27)、一第三PMOS電晶體(P21)、一讀取控制信號(RC)、一第三反相器(INV3)、一第一延遲電路(D1)、一加速讀取電壓(RGND)、一寫入控制信號(WC)、一待機模式控制信 號(S)以及一反相待機模式控制信號(/S)所組成。該第四NMOS電晶體(M21)之源極、閘極與汲極係分別連接至接地電壓、該反相待機模式控制信號(/S)與該第二低電壓節點(VL2)；該第五NMOS電晶體(M22)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該待機模式控制信號(S)與該第二低電壓節點(VL2)；該第六NMOS電晶體(M23)之源極係連接至接地電壓，而閘極與汲極連接在一起並連接至該第一低電壓節點(VL1)；該第七NMOS電晶體(M24)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(M25)之汲極、該讀取控制信號(RC)與該第二低電壓節點(VL2)；該第八NMOS電晶體(M25)之源極、閘極與汲極係分別連接至該加速讀取電壓(RGND)、該第一延遲電路(D1)之輸出與該第七NMOS電晶體(M24)之源極；該第一延遲電路(D1)係連接在該第三反相器(INV3)之輸出與該第八NMOS電晶體(M25)之該閘極之間；該第三反相器(INV3)之輸入係供接收該讀取控制信號(RC)，而輸出則連接至該第一延遲電路(D1)之輸入；該第九NMOS電晶體(M26)之源極、閘極與汲極係分別連接至接地電壓、該第十NMOS電晶體(M27)之汲極與該第一低電壓節點(VL1)；該第十NMOS電晶體(M27)之源極、閘極與汲極係分別連接至該待機模式控制信號(S)、該寫入控制信號(WC)與該第九NMOS電晶體(M26)之閘極；而該第三PMOS電晶體(P21)之源極、閘極與汲極係分別連接至該反相待機模式控制信號(/S)、該寫入控制信號(WC)與該第十NMOS電晶體(M27)之汲極。其中，該反相待機模式控制信號(/S)係由該待機模式控制信號(S)經一反相器而獲得。 Please refer to Fig. 6 again, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV3), a first delay circuit (D1), an acceleration read voltage (RGND), a write control signal (WC), a standby mode control signal Signal (S) and an inverted standby mode control signal (/S). The source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to the ground voltage, the inverting standby mode control signal (/S) and the second low voltage node (VL2); the fifth The source, gate and drain of the NMOS transistor (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2); the second low voltage node (VL2); The sources of the six NMOS transistors (M23) are connected to the ground voltage, and the gate and the drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistors (M24) , the gate and the drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); the eighth NMOS transistor (M25 ) source, gate and drain are respectively connected to the acceleration read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first The delay circuit (D1) is connected between the output of the third inverter (INV3) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV3) is for receiving The read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the source, gate and drain of the ninth NMOS transistor (M26) are respectively connected to the ground voltage, The drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the source, gate and drain of the tenth NMOS transistor (M27) are respectively connected to the standby mode control signal (S), the write control signal (WC) and the gate of the ninth NMOS transistor (M26); and the source, gate and drain of the third PMOS transistor (P21) are respectively connected to the Invert the standby mode control signal (/S), the write control signal (WC) and the drain of the tenth NMOS transistor (M27). Wherein, the inverted standby mode control signal (/S) is obtained from the standby mode control signal (S) via an inverter.

其中，該第三PMOS電晶體(P21)之汲極、該第十NMOS 電晶體(M27)之汲極及該第九NMOS電晶體(M26)之閘極係連接在一起並形成一節點(C)，當該寫入控制信號(WC)為邏輯低位準時，該節點(C)之電壓位準係為該反相待機模式控制信號(/S)之邏輯位準，而當該寫入控制信號(WC)為邏輯高位準時，該節點(C)之電壓位準係為該待機模式控制信號(S)之邏輯位準，藉此以有效地防止待機模式下因非預期因素而發生的誤寫入。 Among them, the drain of the third PMOS transistor (P21), the tenth NMOS The drain of the transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together to form a node (C), when the write control signal (WC) is a logic low level, the node ( The voltage level of C) is the logic level of the inverted standby mode control signal (/S), and when the write control signal (WC) is logic high level, the voltage level of the node (C) is The logic level of the standby mode control signal (S) is used to effectively prevent erroneous writing due to unexpected factors in the standby mode.

該控制電路(2)係設計成可因應不同操作模式而控制該第一低電壓節點(VL1)與該第二低電壓節點(VL2)之電壓位準，於寫入模式時，將選定晶胞中較接近該寫入用位元線(WBL)之驅動電晶體(即該第一NMOS電晶體M11)的源極電壓(即該第一低電壓節點VL1)設定成較接地電壓為高之一預定電壓(即該第六NMOS電晶體(M23)之閘源極電壓V_GS(M23))且將選定晶胞中另一驅動電晶體(即該第二NMOS電晶體M12)的源極電壓(即該第二低電壓節點VL2)設定成接地電壓，以便防止寫入邏輯1困難之問題。 The control circuit (2) is designed to control the voltage levels of the first low voltage node (VL1) and the second low voltage node (VL2) in response to different operating modes. In the writing mode, the selected unit cell The source voltage (ie, the first low voltage node VL1) of the drive transistor (ie, the first NMOS transistor M11) closer to the write bit line (WBL) is set to one higher than the ground voltage. Predetermined voltage (i.e. the gate source voltage V _{GS(M23) of the sixth NMOS transistor (M23)} ) and the source voltage (i.e. That is, the second low voltage node VL2) is set to the ground voltage, so as to prevent the difficulty of writing logic 1.

於讀取模式之第一階段時，將選定晶胞中較接近讀取用位元線(RBL)之驅動電晶體(即該第二NMOS電晶體M12)的源極電壓(即該第二低電壓節點VL2)設定成呈較接地電壓為低之電壓，該較接地電壓為低之該第二低電壓節點(VL2)可有效提高讀取速度，而於讀取模式之第二階段時，將選定晶胞中較接近讀取用位元線(RBL)之驅動電晶體(即該第二NMOS電晶體M12)的源極電壓設定回接地電壓，以便減少無謂的功率消耗，其中該讀取模式之該第二階段與該第一階段相隔之時間，係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算，並至該第八NMOS 電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間，其值可藉由該第三反相器(INV3)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。 In the first stage of the read mode, the source voltage (ie, the second lowest NMOS transistor M12) of the drive transistor (ie, the second NMOS transistor M12) closer to the read bit line (RBL) in the selected unit cell is set. The voltage node VL2) is set to be a voltage lower than the ground voltage, the second low voltage node (VL2) which is lower than the ground voltage can effectively improve the read speed, and in the second stage of the read mode, the The source voltage of the drive transistor (that is, the second NMOS transistor M12) closer to the read bit line (RBL) in the selected unit cell is set back to the ground voltage, so as to reduce unnecessary power consumption, wherein the read mode The time between the second stage and the first stage is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level, and until the eighth NMOS The time until the gate voltage of the transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), its value can be determined by the falling delay time of the third inverter (INV3) and the first delay circuit (D1 ) to adjust the delay time provided.

於待機模式時，將所有記憶體晶胞中之驅動電晶體的源極電壓設定成較接地電壓為高之該預定電壓，以便降低漏電流；而於保持模式時則將記憶體晶胞中之驅動電晶體的源極電壓設定成接地電壓，以便維持原來之保持特性，該第一低電壓節點(VL1)及該第二低電壓節點VL2於寫入模式、讀取模式、待機模式與保持模式之詳細工作電壓位準如下述表1所示。 In the standby mode, the source voltage of the driving transistors in all memory cells is set to the predetermined voltage higher than the ground voltage, so as to reduce the leakage current; The source voltage of the driving transistor is set to the ground voltage in order to maintain the original holding characteristic. The first low voltage node (VL1) and the second low voltage node VL2 are in the writing mode, reading mode, standby mode and holding mode The detailed working voltage levels are shown in Table 1 below.

表1中之該寫入控制信號(WC)為一寫入致能信號(Write Enable，簡稱WE)與對應之寫入用字元線(WWL)信號的及閘(AND gate)運算結果，此時僅於該寫入致能信號(WE)與該對應之寫入用字元線(WWL)信號均為邏輯高位準時，該寫入控制信號(WC)方為邏輯高位準；該讀取控制信號(RC)為一讀取致能信號(Read Enable，簡稱RE)與對應之 讀取用字元線(RWL)信號的及閘運算結果。在此值得注意的是，對於非選定字元線及非選定位元線係設定為浮接(floating)狀態，而對於非讀取模式期間之該讀取控制信號(RC)係設定為該加速讀取電壓(RGND)之位準，以防止該第七NMOS電晶體(M24)之漏電流。 The write control signal (WC) in Table 1 is the AND gate operation result of a write enable signal (Write Enable, WE for short) and a corresponding write word line (WWL) signal. Only when the write enable signal (WE) and the corresponding write word line (WWL) signal are both logic high, the write control signal (WC) is logic high; the read control The signal (RC) is a read enable signal (Read Enable, referred to as RE) and the corresponding Read the AND operation result of the word line (RWL) signal. It is worth noting here that the non-selected word lines and non-selected bit lines are set to the floating state, while the read control signal (RC) is set to the accelerated state during the non-read mode. The level of the read voltage (RGND) is used to prevent the leakage current of the seventh NMOS transistor (M24).

請參考第6圖，該預充電電路(3)係由一第四PMOS電晶體(P31)以及一預充電信號(P)所組成，該第四PMOS電晶體(P31)之源極、閘極與汲極係分別連接至該電源供應電壓(V_DD)、該預充電信號(P)與相對應之讀取用位元線(RBL)，以便於預充電期間，藉由邏輯低位準之該預充電信號(P)，以將相對應之讀取用位元線(RBL)預充電至該電源供應電壓(V_DD)之位準。 Please refer to Figure 6, the precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P), the source and gate of the fourth PMOS transistor (P31) The drain and the drain are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding read bit line (RBL), so that during precharge, by the logic low level of the The precharge signal (P) is used to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V _DD ).

請再參考第6圖，該待機啟動電路(4)係由一第五PMOS電晶體(P41)、一第十一NMOS電晶體(M41)、一第二延遲電路(D2)以及該反相待機模式控制信號(/S)所組成。該第五PMOS電晶體(P41)之源極、閘極與汲極係分別連接至該電源供應電壓(V_DD)、該反相待機模式控制信號(/S)與該第十一NMOS電晶體(M41)之汲極；該第十一NMOS電晶體(M41)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該第二延遲電路(D2)之輸出與該第五PMOS電晶體(P41)之汲極；該第二延遲電路(D2)之輸入連接至該反相待機模式控制信號(/S)，而該第二延遲電路(D2)之輸出則連接至該第十一NMOS電晶體(M41)之閘極。 Please refer to the 6th figure again, this standby startup circuit (4) is made up of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2) and the inverting standby Mode control signal (/S) composed. The source, gate and drain of the fifth PMOS transistor (P41) are respectively connected to the power supply voltage (V _DD ), the inverting standby mode control signal (/S) and the eleventh NMOS transistor The drain of (M41); the source, gate and drain of the eleventh NMOS transistor (M41) are respectively connected to the first low voltage node (VL1), the output of the second delay circuit (D2) and the drain of the fifth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and the output of the second delay circuit (D2) is connected to the gate of the eleventh NMOS transistor (M41).

請再參考第6圖，該高電壓位準控制電路(5)係由一第六PMOS電晶體(P51)、一第七PMOS電晶體(P52)以及一第四反相器(INV4)所組成，其中該第六PMOS電晶體(P51)之源極、閘極與汲極係分別連接 至該電源供應電壓(V_DD)、該讀取控制信號(RC)與該高電壓節點(VH)，該第七PMOS電晶體(P52)之源極、閘極與汲極係分別連接至一第一高電源供應電壓(V_DDH1)、該第四反相器(INV4)之輸出與該高電壓節點(VH)，而該第四反相器(INV4)之輸入係供接收該讀取控制信號(RC)，而輸出則連接至該第七PMOS電晶體(P52)之汲極。在此值得注意的是，該第一反相器係連接在該電源供應電壓(V_DD)與該第一低電壓節點(VL1)之間，而該第二反相器則連接在該高電壓節點(VH)與該第二低電壓節點(VL2)之間。 Please refer to Figure 6 again, the high voltage level control circuit (5) is composed of a sixth PMOS transistor (P51), a seventh PMOS transistor (P52) and a fourth inverter (INV4) , wherein the source, gate and drain of the sixth PMOS transistor (P51) are respectively connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH), The source, gate and drain of the seventh PMOS transistor (P52) are respectively connected to a first high power supply voltage (V _DDH1 ), the output of the fourth inverter (INV4) and the high voltage node (VH), and the input of the fourth inverter (INV4) is for receiving the read control signal (RC), and the output is connected to the drain of the seventh PMOS transistor (P52). It is worth noting here that the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node ( VL1 ), while the second inverter is connected at the high voltage node (VH) and the second low voltage node (VL2).

請再參考第6圖，該讀取用字元線控制電路(6)係由一第八PMOS電晶體(P61)、一第九PMOS電晶體(P62)、一第十PMOS電晶體(P63)、一第十二NMOS電晶體(M61)、一第五反相器(INV5)、一第六反相器(INV6)、該第二高電源供應電壓(V_DDH2)、一讀取用字元線(RWL)以及一讀取用字元線控制信號(RWLC)所組成。該第八PMOS電晶體(P61)之源極、閘極與汲極係分別連接至該第二高電源供應電壓(V_DDH2)、該第五反相器(INV5)之輸出與該第九PMOS電晶體(P62)之源極；該第九PMOS電晶體(P62)之源極、閘極與汲極係分別連接至該該第八PMOS電晶體(P61)之汲極、該第六反相器(INV6)之輸出與該讀取用字元線控制信號(RWLC)；第十PMOS電晶體(P63)之源極、閘極與汲極係分別連接至該電源供應電壓(V_DD)、第五反相器(INV5)之輸出與該讀取用字元線控制信號(RWLC)；該第十二NMOS電晶體(M61)之源極、閘極與汲極係分別連接至該接地電壓、該第五反相器(INV5)之輸出與該讀取用字元線控制信號(RWLC)；該第五反相器(INV5)之輸入係供接收該讀取用 字元線(RWL)，而該第六反相器(INV6)之輸入則與該第五反相器(INV5)之輸出連接。 Please refer to the 6th figure again, the word line control circuit (6) is composed of an eighth PMOS transistor (P61), a ninth PMOS transistor (P62), and a tenth PMOS transistor (P63) for reading. , a twelfth NMOS transistor (M61), a fifth inverter (INV5), a sixth inverter (INV6), the second high power supply voltage (V _DDH2 ), a character for reading Line (RWL) and a read word line control signal (RWLC). The source, gate and drain of the eighth PMOS transistor (P61) are respectively connected to the second high power supply voltage (V _DDH2 ), the output of the fifth inverter (INV5) and the ninth PMOS The source of the transistor (P62); the source, gate and drain of the ninth PMOS transistor (P62) are respectively connected to the drain of the eighth PMOS transistor (P61), the sixth inversion The output of the device (INV6) and the read word line control signal (RWLC); the source, gate and drain of the tenth PMOS transistor (P63) are respectively connected to the power supply voltage (V _DD ), The output of the fifth inverter (INV5) and the read word line control signal (RWLC); the source, gate and drain of the twelfth NMOS transistor (M61) are respectively connected to the ground voltage , the output of the fifth inverter (INV5) and the read word line control signal (RWLC); the input of the fifth inverter (INV5) is for receiving the read word line (RWL) , and the input of the sixth inverter (INV6) is connected to the output of the fifth inverter (INV5).

該讀取用字元線控制電路(6)於致能時係採用二階段操作，於該讀取用字元線(RWL)致能的第一階段，將該讀取用字元線控制信號(RWLC)設定成較該電源供應電壓(V_DD)還高之該第二高電源供應電壓(V_DDH2)，以有效提高讀取速度，而於該第一階段後之第二階段時，則將該讀取用字元線控制信號(RWLC)拉低回該電源供應電壓(V_DD)，以減緩讀取擾入；其中，該讀取用字元線控制電路(6)之該第二階段與該第一階段相隔之時間，係等於該第五反相器(INV5)之輸出足以導通該第八PMOS電晶體(P61)之時間起算，並至該第六反相器(INV6)之輸出足以關閉該第九PMOS電晶體(P62)為止之時間，其值可藉由該第六反相器(INV6)之上升延遲時間來調整。 The read word line control circuit (6) adopts a two-stage operation when it is enabled. In the first stage when the read word line (RWL) is enabled, the read word line control signal (RWLC) is set to the second high power supply voltage (V _DDH2 ) which is higher than the power supply voltage (V _DD ), so as to effectively increase the reading speed, and in the second stage after the first stage, then Pulling down the read word line control signal (RWLC) back to the power supply voltage (V _DD ) to slow down read interference; wherein, the second read word line control circuit (6) The time interval between the stage and the first stage is equal to the time when the output of the fifth inverter (INV5) is sufficient to turn on the eighth PMOS transistor (P61), and ends at the time when the output of the sixth inverter (INV6) The time until the output is sufficient to turn off the ninth PMOS transistor (P62) can be adjusted by the rising delay time of the sixth inverter (INV6).

請再參考第6圖，該寫入驅動電路(7)係由一第十一PMOS電晶體(P71)、一第十三NMOS電晶體(M71)、一第十四NMOS電晶體(M72)、一第十五NMOS電晶體(M73)、一第七反相器(INV7)、一第八反相器(INV8)、一電容器(Cap)、一輸入資料(Din)、一行解碼器輸出信號(Y)、一第三延遲電路(D3)、一第四延遲電路(D4)以及一第三高電源供應電壓(V_DDH3)所組成，其中該第十一PMOS電晶體(P71)之源極、閘極與汲極係分別連接至該第三高電源供應電壓(V_DDH3)、該第七反相器(INV7)之輸出與該第十三NMOS電晶體(M71)之汲極，該第十三NMOS電晶體(M71)之源極、閘極與汲極係分別連接至該第十五NMOS電晶體(M73)之汲極、該第七反相器(INV7)之輸出與該第十一PMOS 電晶體(P71)之汲極，該第十四NMOS電晶體(M72)之源極、閘極與汲極係分別連接至該接地電壓、該第三延遲電路(D3)之輸出與該第十一PMOS電晶體(P71)之汲極，該第十五NMOS電晶體(M73)之源極、閘極與汲極係分別連接至該接地電壓、該第八反相器(INV8)之輸出與該第十三NMOS電晶體(M71)之源極，該第七反相器(INV7)之輸入係供接收該輸入資料(Din)，而輸出則連接至該第十一PMOS電晶體(P71)之閘極、該第十三NMOS電晶體(M71)之閘極以及該第三延遲電路(D3)之輸入，該第八反相器(INV8)之輸入係供接收該行解碼器輸出信號(Y)，而輸出則連接至該第四延遲電路(D4)之輸入以及該第十五NMOS電晶體(M73)之閘極，該電容器(Cap)之一端係連接至該第四延遲電路(D4)之輸出，而該電容器(Cap)之另一端則連接至該第十三NMOS電晶體(M71)之源極以及該第十五NMOS電晶體(M73)之汲極，其中，該第十一PMOS電晶體(P71)之汲極、該第十三NMOS電晶體(M71)之汲極與該第十四NMOS電晶體(M72)之汲極係共同連接至該寫入用位元線(WBL)，該寫入用位元線(WBL)於寫入邏輯0之第一階段係設計成低於於該接地電壓之電壓位準，以加速寫入邏輯0之速度，而於寫入邏輯1時則設計成高於該電源供應電壓(V_DD)之該第三高電源供應電壓(V_DDH3)的位準，以加速寫入邏輯1之速度。 Please refer to the 6th figure again, the writing drive circuit (7) is composed of an eleventh PMOS transistor (P71), a thirteenth NMOS transistor (M71), a fourteenth NMOS transistor (M72), One fifteenth NMOS transistor (M73), one seventh inverter (INV7), one eighth inverter (INV8), one capacitor (Cap), one input data (Din), one line of decoder output signal ( Y), a third delay circuit (D3), a fourth delay circuit (D4) and a third high power supply voltage (V _DDH3 ), wherein the source of the eleventh PMOS transistor (P71), The gate and the drain are respectively connected to the third high power supply voltage (V _DDH3 ), the output of the seventh inverter (INV7) and the drain of the thirteenth NMOS transistor (M71), the tenth The source, gate and drain of the three NMOS transistors (M71) are respectively connected to the drain of the fifteenth NMOS transistor (M73), the output of the seventh inverter (INV7) and the eleventh inverter (INV7). The drain of the PMOS transistor (P71), the source, the gate and the drain of the fourteenth NMOS transistor (M72) are respectively connected to the ground voltage, the output of the third delay circuit (D3) and the first The drain of the eleventh PMOS transistor (P71), the source, the gate and the drain of the fifteenth NMOS transistor (M73) are respectively connected to the ground voltage, the output of the eighth inverter (INV8) With the source of the thirteenth NMOS transistor (M71), the input of the seventh inverter (INV7) is for receiving the input data (Din), and the output is connected to the eleventh PMOS transistor (P71 ), the gate of the thirteenth NMOS transistor (M71) and the input of the third delay circuit (D3), the input of the eighth inverter (INV8) is for receiving the row decoder output signal (Y), and the output is connected to the input of the fourth delay circuit (D4) and the gate of the fifteenth NMOS transistor (M73), and one end of the capacitor (Cap) is connected to the fourth delay circuit ( D4), and the other end of the capacitor (Cap) is connected to the source of the thirteenth NMOS transistor (M71) and the drain of the fifteenth NMOS transistor (M73), wherein the tenth The drain of a PMOS transistor (P71), the drain of the thirteenth NMOS transistor (M71) and the drain of the fourteenth NMOS transistor (M72) are commonly connected to the write bit line ( WBL), the write bit line (WBL) is designed to be lower than the voltage level of the ground voltage in the first stage of writing logic 0 to speed up the speed of writing logic 0, while writing logic 0 When 1, it is designed to be higher than the third high power supply voltage (V _DDH3 ) level of the power supply voltage (V _DD ), so as to speed up the writing speed of logic 1.

該寫入驅動電路(7)致能與否係由該行解碼器輸出信號(Y)之邏輯位準決定，當該行解碼器輸出信號(Y)為邏輯低位準時，該寫入驅動電路(7)為非致能狀態，而當該行解碼器輸出信號(Y)為邏輯高位準時，該寫入驅動電路(7)處於致能狀態。當該行解碼器輸出信號(Y)為 邏輯低位準時，該第八反相器(INV8)之輸出為邏輯高位準，一方面導通該第十五NMOS電晶體(M73)，另一方面經過該第四延遲電路(D4)所提供之延遲時間後對該電容器(Cap)之一端充電，由於導通的該第十五NMOS電晶體(M73)，使得該電容器(Cap)之另一端為該接地電壓，而該電容器(Cap)之一端則會因電容器(Cap)的充電而保持該電源供應電壓(V_DD)之電壓位準。 Whether the writing drive circuit (7) is enabled or not is determined by the logic level of the row decoder output signal (Y). When the row decoder output signal (Y) is at a logic low level, the write drive circuit ( 7) is in a non-enabled state, and when the output signal (Y) of the row decoder is at a logic high level, the writing drive circuit (7) is in an enabled state. When the row decoder output signal (Y) is at a logic low level, the output of the eighth inverter (INV8) is at a logic high level, which turns on the fifteenth NMOS transistor (M73) on the one hand and passes through the After the delay time provided by the fourth delay circuit (D4), one end of the capacitor (Cap) is charged, and the other end of the capacitor (Cap) is at the ground voltage due to the turned-on fifteenth NMOS transistor (M73). , and one end of the capacitor (Cap) will maintain the voltage level of the power supply voltage (V _DD ) due to the charging of the capacitor (Cap).

該寫入驅動電路(7)於寫入邏輯0之致能狀態時係採用二階段操作，於該寫入驅動電路(7)致能的第一階段，邏輯高位準之該行解碼器輸出信號(Y)，使得該第八反相器(INV8)之輸出為邏輯低位準，一方面使該第十五NMOS電晶體(M73)為截止(OFF)狀態，另一方面經過該第四延遲電路(D4)所提供之延遲時間後對該電容器(Cap)之一端快速放電至該接地電壓，由於此時該輸入資料(Din)為邏輯低位準，使得該第七反相器(INV7)之輸出為邏輯高位準，於是導通該第十三NMOS電晶體(M71)，並使該第十一PMOS電晶體(P71)為截止(OFF)狀態，因此該寫入用位元線(WBL)之電壓位準於該寫入驅動電路(7)寫入邏輯0之第一階段時滿足方程式(3)： The writing drive circuit (7) adopts a two-stage operation when writing into the enable state of logic 0, and in the first stage when the write drive circuit (7) is enabled, the row decoder output signal of logic high level (Y), so that the output of the eighth inverter (INV8) is a logic low level, on the one hand, the fifteenth NMOS transistor (M73) is turned off (OFF), and on the other hand, it passes through the fourth delay circuit (D4) After the delay time provided by (D4), one end of the capacitor (Cap) is quickly discharged to the ground voltage, because the input data (Din) is at a logic low level at this time, making the output of the seventh inverter (INV7) It is a logic high level, so the thirteenth NMOS transistor (M71) is turned on, and the eleventh PMOS transistor (P71) is turned off (OFF), so the voltage of the write bit line (WBL) The level satisfies the equation (3) when the write drive circuit (7) writes the first stage of logic 0:

V_WBL1=-V_DD×Cap/(Cap+C_WBL) (3) V _WBL1 =-V _DD ×Cap/(Cap+C _WBL ) (3)

其中，V_WBL1表示該寫入用位元線(WBL)於寫入邏輯0之第一階段的電壓位準，V_WBL1的絕對值設計為小於該第三NMOS電晶體(M13)之臨界電壓，例如可設計為-100mV、-150mV或-200mV，V_DD為該電源供應電壓(V_DD)之電壓位準，而Cap與C_WBL分別表示該該電容器(Cap)之電容值與該寫入用位元線(WBL)之寄生電容值。 Wherein, V _WBL1 represents the voltage level of the writing bit line (WBL) in the first stage of writing logic 0, and the absolute value of V _WBL1 is designed to be smaller than the threshold voltage of the third NMOS transistor (M13), For example, it can be designed as -100mV, -150mV or -200mV, V _DD is the voltage level of the power supply voltage (V _DD ), and Cap and C _WBL respectively represent the capacitance value of the capacitor (Cap) and the write-in The parasitic capacitance value of the bit line (WBL).

當邏輯低位準之該輸入資料(Din)經過該該第七反相器(INV7)以及該第三延遲電路(D3)所提供之延遲時間後，該寫入驅動電路(7)進入致能的第二階段，此時由於該第十四NMOS電晶體(M72)為導通狀態，使得該寫入用位元線(WBL)之電壓位準於該寫入驅動電路(7)寫入邏輯0之第二階段時滿足方程式(4)： When the input data (Din) of the logic low level passes through the delay time provided by the seventh inverter (INV7) and the third delay circuit (D3), the write drive circuit (7) enters the enabled state In the second stage, at this time, since the fourteenth NMOS transistor (M72) is in the conduction state, the voltage level of the write-in bit line (WBL) is at the point where the write-in drive circuit (7) writes logic 0 Equation (4) is satisfied in the second stage:

V_WBL2=0 (4) V _WBL2 =0 (4)

茲說明第6圖之本發明較佳實施例的工作原理如下： Hereby explain the working principle of the preferred embodiment of the present invention of the 6th figure as follows:

(I)寫入模式(write mode) (I) Write mode (write mode)

於寫入操作開始前，該待機模式控制信號(S)與該寫入控制信號(WC)均為邏輯低位準，使得該第三PMOS電晶體(P21)導通(ON)，並使得該第十NMOS電晶體(M27)截止(OFF)，於是該第三PMOS電晶體(P21)之汲極呈邏輯高位準，該邏輯高位準之該第三PMOS電晶體(P21)之汲極會導通該第九NMOS電晶體(M26)，並使得該第一低電壓節點(VL1)呈接地電壓。 Before the write operation starts, both the standby mode control signal (S) and the write control signal (WC) are logic low level, so that the third PMOS transistor (P21) is turned on (ON), and the tenth PMOS transistor (P21) is turned on. The NMOS transistor (M27) cuts off (OFF), so the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) at the logic high level will turn on the third PMOS transistor (P21). nine NMOS transistors (M26), and make the first low voltage node (VL1) be at ground voltage.

而於寫入操作期間內，該寫入控制信號(WC)為邏輯高位準，使得該第三PMOS電晶體(P21)截止，該第十NMOS電晶體(M27)導通，並使得該第三PMOS電晶體(P21)之汲極呈邏輯低位準，該邏輯低位準之該第三PMOS電晶體(P21)之汲極會使得該第九NMOS電晶體(M26)截止，並使得該第一低電壓節點(VL1)等於該第六NMOS電晶體(M23)之閘源極電壓V_GS(M26)，藉此得以有效防止寫入邏輯1困難之問題。第7a圖所示為第6圖之本發明較佳實施例於寫入邏輯0期間之簡化電路圖，而第7b 圖所示則為寫入邏輯1期間之簡化電路圖。 During the write operation, the write control signal (WC) is at a logic high level, so that the third PMOS transistor (P21) is turned off, the tenth NMOS transistor (M27) is turned on, and the third PMOS transistor (M27) is turned on. The drain of the transistor (P21) is at a logic low level, and the drain of the third PMOS transistor (P21) of the logic low level will make the ninth NMOS transistor (M26) cut off, and make the first low voltage The node ( VL1 ) is equal to the gate-source voltage V _{GS ( M26 )} of the sixth NMOS transistor ( M23 ), thereby effectively preventing the difficulty of writing logic 1. Figure 7a shows a simplified circuit diagram of the preferred embodiment of the present invention in Figure 6 during writing logic 0, and Figure 7b shows a simplified circuit diagram during writing logic 1.

接下來依4種寫入狀態來說明第7a圖與第7b圖之本發明較佳實施例如何完成寫入邏輯0與寫入邏輯1動作。 Next, according to the four writing states, how the preferred embodiment of the present invention in Fig. 7a and Fig. 7b completes the operations of writing logic 0 and writing logic 1 will be described.

(一)節點A原本儲存邏輯0，而現在欲寫入邏輯0： (1) Node A originally stored logic 0, but now wants to write logic 0:

在寫入動作發生前(該寫入用字元線WWL為接地電壓)，該第一NMOS電晶體(M11)為導通(ON)。因為該第一NMOS電晶體(M11)為ON，所以當寫入動作開始時，該寫入用字元線(WWL)由Low(接地電壓)轉High(電源供應電壓V_DD)。當該寫入用字元線(WWL)的電壓大於該第三NMOS電晶體(M13)(即存取電晶體)的臨界電壓時，該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON)，此時因為該寫入用位元線(WBL)於寫入邏輯0之第一階段係設計成低於於該接地電壓之電壓位準，而於寫入邏輯0之第二階段則拉回至該接地電壓，所以會將該節點A先放電後再拉回至該接地電壓，而完成邏輯0的寫入動作，直到寫入週期結束。 Before the write operation occurs (the write word line WWL is at the ground voltage), the first NMOS transistor ( M11 ) is turned on (ON). Because the first NMOS transistor (M11) is ON, when the write operation starts, the write word line (WWL) changes from Low (ground voltage) to High (power supply voltage V _DD ). When the voltage of the word line (WWL) for writing is greater than the threshold voltage of the third NMOS transistor (M13) (that is, the access transistor), the third NMOS transistor (M13) is turned off (OFF) It is turned on (ON). At this time, because the writing bit line (WBL) is designed to be lower than the voltage level of the ground voltage in the first stage of writing logic 0, and in the first stage of writing logic 0 In the second stage, it is pulled back to the ground voltage, so the node A will be discharged first and then pulled back to the ground voltage to complete the write operation of logic 0 until the end of the write cycle.

(二)節點A原本儲存邏輯0，而現在欲寫入邏輯1： (2) Node A originally stored logic 0, but now wants to write logic 1:

為了便於說明，先僅考慮控制電路(2)對於提高寫入邏輯1之功效，然後，再考慮耦合元件控制器對於提高寫入邏輯1之功效。 For the convenience of explanation, first only consider the effect of the control circuit (2) on improving writing logic 1, and then consider the effect of the coupling element controller on improving writing logic 1.

首先，僅考慮控制電路(2)，在寫入動作發生前(該寫入用字元線WWL為接地電壓)，該第一NMOS電晶體(M11)為導通(ON)。在此值得注意的是，因為該第一NMOS電晶體(M11)為ON，所以當寫入動作開始時，該寫入用字元線(WWL)由Low(接地電壓)轉High，當該 寫入用字元線(WWL)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時，該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON)，此時因為該寫入用位元線(WBL)為該第三高電源供應電壓(V_DDH3)之電壓位準，並且因為該第一NMOS電晶體(M11)仍為ON且該節點B仍處於電壓位準為接近於該電源供應電壓(V_DD)之電壓位準的初始狀態，所以該第一PMOS電晶體(P11)仍為截止(OFF)，而該節點A之寫入初始瞬間電壓(V_AWI)滿足方程式(5)： First, considering only the control circuit (2), the first NMOS transistor (M11) is turned on (ON) before the write operation occurs (the write word line WWL is at the ground voltage). It is worth noting here that because the first NMOS transistor (M11) is ON, when the write operation starts, the write word line (WWL) turns from Low (ground voltage) to High, and when the write When the voltage of the input word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from cut-off (OFF) to conduction (ON). The write bit line (WBL) is at the voltage level of the third high power supply voltage (V _DDH3 ), and because the first NMOS transistor (M11) is still ON and the node B is still at the voltage level of The initial state of the voltage level close to the power supply voltage (V _DD ), so the first PMOS transistor (P11) is still off (OFF), and the writing initial instantaneous voltage (V _AWI ) of the node A satisfies Equation (5):

V_AWI1=V_DDH3×(R_M11+R_M23)/(R_M13+R_M11+R_M23)>V_TM12 (5)其中，V_AWI1表示節點A寫入邏輯1之寫入初始瞬間電壓，R_M13表示該第三NMOS電晶體(M13)之導通電阻，R_M11表示該第一NMOS電晶體(M11)之導通電阻，R_M23表示該第六NMOS電晶體(M23)之導通電阻，而V_DDH3與V_TM12分別表示該第三高電源供應電壓之電壓位準與該第二NMOS電晶體(M12)之臨界電壓。由於在該第一低電壓節點(VL1)處提供一等於該第六NMOS電晶體(M23)之閘-源極電壓V_GS(M23)之電壓位準，因此可輕易地將節點A之電壓位準設定成比第4圖之習知5T靜態隨機存取記憶體晶胞之該節點A之電壓位準還要高許多。該還要高許多之分壓電壓位準係足以使該第二NMOS電晶體(M12)導通，於是使得節點B放電至一較低電壓位準，該節點B之較低電壓位準會使得該第一NMOS電晶體(M11)之導通等效電阻(R_M11)呈現較高的電阻值，該第一NMOS電晶體(M11)之該較高的電阻值會於該節點A獲得較高電壓位準，該節點A之較高電壓位準又會經由該第二反相器(由第二PMOS電晶體P12與第二NMOS電晶體M12所組成)，而使得該節點B呈現更低電壓位準，該節點B之更低電壓位準又會經由該第一 反相器(由第一PMOS電晶體P11與第一NMOS電晶體M11所組成)，而使得該節點A獲得更高電壓位準，依此循環，即可將該節點A充電至該電源供應電壓(V_DD)，而完成邏輯1的寫入動作。 V _AWI1 =V _DDH3 ×(R _M11 +R _M23 )/(R _M13 +R _M11 +R _M23 )>V _TM12 (5) Among them, V _AWI1 represents the initial instant voltage for writing logic 1 at node A, and R _M13 Represents the conduction resistance of the third NMOS transistor (M13), R _M11 represents the conduction resistance of the first NMOS transistor (M11), R _M23 represents the conduction resistance of the sixth NMOS transistor (M23), and V _DDH3 and V _TM12 respectively represents the voltage level of the third high power supply voltage and the threshold voltage of the second NMOS transistor ( M12 ). Since a voltage level equal to the gate-source voltage V _{GS (M23)} of the sixth NMOS transistor (M23) is provided at the first low voltage node (VL1), the voltage level of node A can be easily set to The standard setting is much higher than the voltage level of the node A of the conventional 5T SRAM unit cell in FIG. 4 . The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), thereby discharging node B to a lower voltage level which causes the The conduction equivalent resistance (R _M11 ) of the first NMOS transistor (M11) presents a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A Standard, the higher voltage level of the node A will pass through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B presents a lower voltage level , the lower voltage level of the node B will pass through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level, In this cycle, the node A can be charged to the power supply voltage (V _DD ), and the write operation of logic 1 is completed.

其中，該第一低電壓節點(VL1)於節點A原本儲存邏輯0，而在寫入邏輯1之期間，係具有等於該第六NMOS電晶體(M23)之閘源極電壓V_GS(M23)的電壓位準，而於寫入邏輯1後，又會因經由該第九NMOS電晶體(M26)放電而為接地電壓之位準。 Wherein, the first low-voltage node (VL1) originally stores logic 0 at node A, but during writing logic 1, it has a gate-source voltage V _{GS (M23) equal to the sixth NMOS transistor (M23)} After the logic 1 is written, it will be the level of the ground voltage due to discharge through the ninth NMOS transistor (M26).

接著，僅考慮耦合元件控制器對於提高寫入邏輯1之功效，該耦合元件控制器係由該開關(SW)及該耦合元件(CE)所組成，其中該開關(SW)及該耦合元件(CE)均為NMOS電晶體，在寫入動作發生前(該寫入用位元線WBL為高於該電源供應電壓V_DD之該第三高電源供應電壓V_DDH3的位準)，該開關(SW)導通。當寫入動作開始時，該寫入用字元線(WWL)由Low(接地電壓)轉High(V_DD)後，該耦合元件(CE)於該寫入用字元線(WWL)及該節點(A)之間提供最大的耦合電容，於是可更進一步提高方程式(5)之寫入初始瞬間電壓(V_AWI)，從而有效地提高寫入邏輯1之速度。在此值得注意的是，該寫入用字元線(WWL)致能之電壓位準為該電源供應電壓(V_DD)，藉此，可於有效提高寫入邏輯1之速度的同時，亦避免無謂的半選定干擾(half-selected disturbance)。 Then, only consider the effect of the coupling element controller for improving writing logic 1, the coupling element controller is composed of the switch (SW) and the coupling element (CE), wherein the switch (SW) and the coupling element ( CE) are all NMOS transistors, before the writing action occurs (the bit line WBL for writing is at the level of the third high power supply voltage V _DDH3 higher than the power supply voltage V _DD ), the switch ( SW) is turned on. When the writing operation starts, after the writing word line (WWL) changes from Low (ground voltage) to High (V _DD ), the coupling element (CE) is connected between the writing word line (WWL) and the writing word line (WWL). The maximum coupling capacitance is provided between the nodes (A), so that the instantaneous writing initial voltage (V _AWI ) of equation (5) can be further increased, thereby effectively increasing the writing speed of logic 1. It is worth noting here that the enabling voltage level of the word line for writing (WWL) is the power supply voltage (V _DD ), thereby effectively increasing the writing speed of logic 1 and simultaneously Avoid unnecessary half-selected disturbance.

(三)節點A原本儲存邏輯1，而現在欲寫入邏輯1： (3) Node A originally stored logic 1, but now wants to write logic 1:

在寫入動作發生前(該寫入用字元線WWL為接地電壓)，該第一PMOS電晶體(P11)為導通(ON)。當該寫入用字元線(WWL)由Low(接地 電壓)轉High，由於該節點A為該電源供應電壓(V_DD)之電壓位準，且該寫入用位元線(WBL)為該第三高電源供應電壓(V_DDH3)之電壓位準，因此當該第二高電源供應電壓(V_DDH2)設定為高於該電源供應電壓(V_DD)但低於該電源供應電壓(V_DD)與該第三NMOS電晶體(M13)臨界電壓之V_TM13的總和時，亦即 Before the write operation occurs (the write word line WWL is at the ground voltage), the first PMOS transistor ( P11 ) is turned on (ON). When the word line for writing (WWL) turns from Low (ground voltage) to High, since the node A is at the voltage level of the power supply voltage (V _DD ), and the bit line for writing (WBL) is The voltage level of the third high power supply voltage (V _DDH3 ), so when the second high power supply voltage (V _DDH2 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the sum of V _TM13 of the threshold voltage of the third NMOS transistor (M13), that is

V_DD<V_DDH2<V_DD+V_TM13 (6)會使該第三NMOS電晶體(M13)繼續保持截止(OFF)狀態；此時因為該第一PMOS電晶體(P11)仍為ON，所以該節點A的電壓會維持於該電源供應電壓(V_DD)之電壓位準，直到寫入週期結束。 V _DD <V _DDH2 <V _DD +V _TM13 (6) will keep the third NMOS transistor (M13) in OFF state; at this time, because the first PMOS transistor (P11) is still ON, so The voltage of the node A will be maintained at the voltage level of the power supply voltage (V _DD ) until the writing cycle ends.

(四)節點A原本儲存邏輯1，而現在欲寫入邏輯0： (4) Node A originally stored logic 1, but now wants to write logic 0:

在寫入動作發生前(該寫入用字元線WWL為接地電壓)，該第一PMOS電晶體(P11)為導通(ON)。當該寫入用字元線(WWL)由Low(接地電壓)轉High，且該寫入用字元線(WWL)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時，該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON)，此時因為該寫入用位元線(WBL)為滿足方程式(3)的電壓位準(V_WBL1)，其小於0V，並且因為該第一PMOS電晶體(P11)仍為ON且該節點B處於電壓位準為接近於該接地電壓之電壓位準的初始狀態，所以該第一NMOS電晶體(M11)仍為截止，而該節點A之寫入初始瞬間電壓(V_AWI0)滿足方程式(7)： Before the write operation occurs (the write word line WWL is at the ground voltage), the first PMOS transistor ( P11 ) is turned on (ON). When the writing word line (WWL) turns from Low (ground voltage) to High, and the voltage of the writing word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13), the first The three NMOS transistors (M13) are turned from cutoff (OFF) to conduction (ON). At this time, because the write bit line (WBL) is a voltage level (V _WBL1 ) that satisfies the equation (3), it is less than 0V , and because the first PMOS transistor (P11) is still ON and the node B is in an initial state where the voltage level is close to the ground voltage, the first NMOS transistor (M11) is still off , and the writing initial instantaneous voltage (V _AWI0 ) of the node A satisfies equation (7):

V_AWI0=V_WBL1×R_P11/(R_M13+R_P11)+V_DD×R_M13/(R_M13+R_P11) (7) V _AWI0 =V _WBL1 ×R _P11 /(R _M13 +R _P11 )+V _DD ×R _M13 /(R _M13 +R _P11 ) (7)

V_AWI0表示節點A由邏輯1寫入邏輯0之寫入初始瞬間電壓，R_M13與R_P11 分別表示該第主NMOS電晶體(M13)與該第一PMOS電晶體(P11)之導通電阻，而V_WBL1與V_DD分別表示該寫入用位元線(WBL)於寫入邏輯0之第一階段的電壓位準與該電源供應電壓(V_DD)之電壓位準，由於由邏輯1寫入邏輯0時，該第三NMOS電晶體(M13)係工作於飽和區，飽和區之電流係與其閘-源極電壓V_GS(M13)之電壓位準扣減其臨界電壓後之平方成正比例，因此藉由該寫入用位元線(WBL)於寫入邏輯0之第一階段的電壓位準(V_WBL1)小於0V以及藉由將該寫入用字元線(WWL)設定成較該電源供應電壓(V_DD)還高之該第二高電源供應電壓(V_DDH2)的設計方式，可有效加速由邏輯1寫入邏輯0之速度。 V _AWI0 represents the initial instant voltage of node A written from logic 1 to logic 0, R _M13 and R _P11 respectively represent the on-resistance of the first NMOS transistor (M13) and the first PMOS transistor (P11), and V _WBL1 and V _DD represent the voltage level of the writing bit line (WBL) in the first stage of writing logic 0 and the voltage level of the power supply voltage (V _DD ), respectively. When the logic is 0, the third NMOS transistor (M13) works in the saturation region, and the current in the saturation region is proportional to the square of the gate-source voltage V _{GS (M13)} minus its critical voltage, Therefore, the voltage level (V _WBL1 ) of the first phase of writing logic 0 by the write bit line (WBL) is less than 0V and by setting the write word line (WWL) to be lower than the The design method of the second high power supply voltage (V _DDH2 ) whose power supply voltage (V _DD ) is even higher can effectively speed up the speed of writing logic 0 from logic 1.

在此值得注意的是，節點A由邏輯1寫入邏輯0時，該第三NMOS電晶體(M13)係工作於飽和區，飽和區之電流係與其閘-源極電壓V_GS(M13)之電壓位準扣減其臨界電壓後之平方成正比例，因此於節點A由邏輯1寫入邏輯0時，可藉由前述方程式(3)於由邏輯1寫入邏輯0之初期提供低於該接地電壓之電壓位準(V_WBL1)給該寫入用位元線(WBL)，其中，V_WBL1的絕對值限定為小於該第三NMOS電晶體(M13)之臨界電壓，例如可設計為-100mV、-150mV或-200mV，藉此可藉由進一步加大工作於飽和區之該第三NMOS電晶體(M13)的閘-源極電壓V_GS(M13)，以有效地提高節點A由邏輯1寫入邏輯0之寫入速度。 It is worth noting here that when node A is written from logic 1 to logic 0, the third NMOS transistor (M13) works in the saturation region, and the current in the saturation region is equal to its gate-source voltage V _{GS (M13)} . The square of the voltage level minus its threshold voltage is proportional. Therefore, when node A is written into logic 0 by logic 1, the above-mentioned equation (3) can be used to provide a voltage lower than the ground at the initial stage of writing logic 0 by logic 1. The voltage level (V _WBL1 ) of the voltage is given to the bit line (WBL) for writing, wherein the absolute value of V _WBL1 is limited to be less than the critical voltage of the third NMOS transistor (M13), for example, it can be designed as -100mV , -150mV or -200mV, by further increasing the gate-source voltage V _GS(M13) of the third NMOS transistor (M13) operating in the saturation region, to effectively increase the node A by logic 1 Write speed for writing logic 0.

(II)讀取模式(read mode) (II) Read mode (read mode)

於讀取操作開始前，該讀取控制信號(RC)、該寫入控制信號(WC)及該待機模式控制信號(S)均為邏輯低位準，使得該第三PMOS電晶體(P21)導 通，並使得該第十NMOS電晶體(M27)截止，於是該第三PMOS電晶體(P21)之汲極呈邏輯高位準，邏輯高位準之該第三PMOS電晶體(P21)之汲極會導通第九NMOS電晶體(M26)，並使得該第一低電壓節點(VL1)呈接地電壓。另一方面，由於該讀取控制信號(RC)為邏輯低位準，使得該第七NMOS電晶體(M24)截止(OFF)，並使得該第八NMOS電晶體(M25)導通(ON)。 Before the read operation starts, the read control signal (RC), the write control signal (WC) and the standby mode control signal (S) are logic low level, so that the third PMOS transistor (P21) conducts and make the tenth NMOS transistor (M27) cut off, so the drain of the third PMOS transistor (P21) is logic high level, and the drain of the third PMOS transistor (P21) of logic high level will be The ninth NMOS transistor ( M26 ) is turned on, and the first low voltage node ( VL1 ) is grounded. On the other hand, since the read control signal (RC) is logic low level, the seventh NMOS transistor ( M24 ) is turned off (OFF), and the eighth NMOS transistor ( M25 ) is turned on (ON).

在此值得注意的是，於讀取操作開始前之預充電期間，該預充電信號(P)係為邏輯低位準，藉此以將相對應之讀取用位元線(RBL)預充電至該電源供應電壓(V_DD)之位準，惟由於例如10奈米以下製程技術之操作電壓將降為0.9伏特以下時將造成讀取速度降低而無法滿足規範之問題，因此，本發明提出二階段的讀取控制以於提高讀取速度並滿足規範的同時，亦避免無謂的功率耗損。 It is worth noting here that during the precharge period before the start of the read operation, the precharge signal (P) is at a logic low level, thereby precharging the corresponding read bit line (RBL) to The level of the power supply voltage (V _DD ), but because the operating voltage of the process technology below 10 nanometers will be reduced to below 0.9 volts, the reading speed will be reduced and cannot meet the specification. Therefore, the present invention proposes two The reading control in stages is used to increase the reading speed and meet the specifications while avoiding unnecessary power consumption.

第6圖所示之本發明較佳實施例係藉由二階段的讀取控制以於提高讀取速度的同時，亦避免無謂的功率耗損，於讀取操作之第一階段，該讀取控制信號(RC)為邏輯高位準，使得該第七NMOS電晶體(M24)導通，由於此時該第八NMOS電晶體(M25)仍導通，於是該第二低電壓節點(VL2)大約呈較接地電壓為低之該加速讀取電壓(RGND)，該較接地電壓為低之該加速讀取電壓(RGND)可有效提高讀取速度。 The preferred embodiment of the present invention shown in Fig. 6 uses a two-stage read control to increase the read speed while avoiding unnecessary power consumption. In the first stage of the read operation, the read control The signal (RC) is logic high level, so that the seventh NMOS transistor (M24) is turned on, because the eighth NMOS transistor (M25) is still turned on at this time, so the second low voltage node (VL2) is approximately grounded The accelerated read voltage (RGND) with a lower voltage than the ground voltage can effectively increase the read speed.

而於讀取操作之第二階段，雖然該讀取控制信號(RC)仍為邏輯高位準，使得該第七NMOS電晶體(M24)仍為導通，惟由於此時該第八NMOS電晶體(M25)截止，於是該第二低電壓節點(VL2)會經由導通的該第四NMOS電晶體(M21)而呈接地電壓(由於讀取操作期間該反相待機模式控制信號(/S)為邏輯高位準)，藉此可有效減少無謂的功率消耗。在此值 得注意的是，該讀取操作之該第二階段與該第一階段相隔之時間，係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算，並至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間，其值可藉由該第三反相器(INV3)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。再者，無論於讀取操作之第一階段抑是第二階段，該第四NMOS電晶體(M21)均呈導通狀態(由於讀取操作期間該反相待機模式控制信號(/S)為邏輯高位準)。第8圖所示為第6圖之本發明較佳實施例於讀取期間之簡化電路圖。 In the second stage of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but because the eighth NMOS transistor ( M25) is turned off, so the second low voltage node (VL2) will be at the ground voltage through the turned-on fourth NMOS transistor (M21) (because the inverted standby mode control signal (/S) is logic during the read operation High level), thereby effectively reducing unnecessary power consumption. at this value It should be noted that the time between the second phase of the read operation and the first phase is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level, and until the eighth NMOS The time until the gate voltage of the transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), its value can be determined by the falling delay time of the third inverter (INV3) and the first delay circuit (D1 ) to adjust the delay time provided. Moreover, no matter in the first stage or the second stage of the read operation, the fourth NMOS transistor (M21) is in the conduction state (because the inverted standby mode control signal (/S) is a logic state during the read operation high level). FIG. 8 shows a simplified circuit diagram of the preferred embodiment of the present invention of FIG. 6 during readout.

接下來依2種讀取狀態來說明第8圖之本發明較佳實施例如何藉由控制電路(2)、該高電壓位準控制電路(5)以及讀取用字元線控制電路(6)以於提高讀取速度的同時，亦避免無謂的功率耗損。 Next, how the preferred embodiment of the present invention in Fig. 8 uses the control circuit (2), the high voltage level control circuit (5) and the word line control circuit (6) for reading is described according to two read states. ) to avoid unnecessary power consumption while increasing the reading speed.

(一)讀取邏輯1(節點A儲存邏輯1)： (1) Read logic 1 (node A stores logic 1):

在讀取動作發生前，該第一NMOS電晶體(M11)為截止(OFF)且該第二NMOS電晶體(M12)為導通(ON)，該節點A與該節點B分別為該電源供應電壓(V_DD)與接地電壓，而該讀取用位元線(RBL)則因該預充電電路(3)而等於該電源供應電壓(V_DD)。於讀取期間，由於節點B為接地電壓，因此該第二讀取用電晶體(M15)截止(OFF)，藉此可有效保持該讀取用位元線(RBL)為該電源供應電壓(V_DD)直到讀取週期結束而順利完成讀取邏輯1之操作。在此值得注意的是，於讀取操作之該第一階段，該第二低電壓節點(VL2)於讀取邏輯1時之讀取初始瞬間電壓(V_RVL2I)必須滿足方程式(8)： Before the read operation occurs, the first NMOS transistor (M11) is turned off (OFF) and the second NMOS transistor (M12) is turned on (ON), and the node A and the node B are respectively the power supply voltage (V _DD ) and ground voltage, and the read bit line (RBL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During reading, since the node B is at the ground voltage, the second read transistor (M15) is turned off (OFF), thereby effectively maintaining the read bit line (RBL) at the power supply voltage ( V _DD ) until the end of the read cycle to successfully complete the operation of reading logic 1. It is worth noting here that, in the first stage of the read operation, the read initial transient voltage (V _RVL2I ) of the second low voltage node (VL2) when reading logic 1 must satisfy equation (8):

V_RVL2I=RGND×R_M21/(R_M21+R_M24+R_M25)>-V_TM12 (8) 以有效地防止讀取時之半選定干擾，其中，V_RVL2I表示該第二低電壓節點(VL2)於讀取邏輯1時之讀取初始瞬間電壓，RGND表示該加速讀取電壓，R_M21表示該第四NMOS電晶體(M21)之導通電阻，R_M24表示該第七NMOS電晶體(M24)之導通電阻，R_M25表示該第八NMOS電晶體(M25)之導通電阻，而V_TM12表示該第二NMOS電晶體(M12)之臨界電壓；而於該讀取操作之該第二階段，該第二低電壓節點(VL2)之電壓(V_RVL2)可由方程式(9)表示 V _RVL2I =RGND×R _M21 /(R _M21 +R _M24 +R _M25 )>-V _TM12 (8) to effectively prevent half-selected interference during reading, where V _RVL2I represents the second low voltage node (VL2 ) reads the initial instantaneous voltage when reading logic 1, RGND represents the accelerated reading voltage, R _M21 represents the on-resistance of the fourth NMOS transistor (M21), and R _M24 represents the seventh NMOS transistor (M24) R _M25 represents the conduction resistance of the eighth NMOS transistor (M25), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12); and in the second phase of the read operation, the The voltage (V _RVL2 ) of the second low voltage node (VL2) can be expressed by equation (9)

V_RVL2=接地電壓 (9)藉此，可有效地減少無謂的功率消耗。再者，為了有效降低讀取時之半選定晶胞干擾與有效降低漏電流，必須將較接地電壓為低之該加速讀取電壓(RGND)設定為使該第二低電壓節點(VL2)之電壓位準小於該第二NMOS電晶體(M12)之臨界電壓(V_TM12)，同時可更嚴謹地將較接地電壓為低之該加速讀取電壓(RGND)之絕對值|RGND|設定為低於該第二NMOS電晶體(M12)之臨界電壓(V_TM12)，亦即 V _RVL2 = ground voltage (9) In this way, unnecessary power consumption can be effectively reduced. Moreover, in order to effectively reduce the interference of the half-selected cell during reading and effectively reduce the leakage current, the accelerated reading voltage (RGND) must be set to be lower than the ground voltage so that the second low voltage node (VL2) The voltage level is lower than the threshold voltage (V _TM12 ) of the second NMOS transistor (M12), and at the same time, the absolute value |RGND| At the threshold voltage (V _TM12 ) of the second NMOS transistor (M12), that is

|RGND|<V_TM12 (10)其中，|RGND|與V_TM12分別表示該加速讀取電壓之絕對值與該第二NMOS電晶體(M12)之臨界電壓。 |RGND|<V _TM12 (10) Wherein, |RGND| and V _TM12 represent the absolute value of the accelerated reading voltage and the threshold voltage of the second NMOS transistor ( M12 ), respectively.

(二)讀取邏輯0(節點A儲存邏輯0)： (2) Read logic 0 (node A stores logic 0):

在讀取動作發生前，該第一NMOS電晶體(M11)為導通(ON)且該第二NMOS電晶體(M12)為截止(OFF)，該節點A與該節點B分別為接地電壓與該電源供應電壓(V_DD)，而該讀取用位元線(RBL)則因該預充電電路(3)而等於該電源供應電壓(V_DD)。於讀取期間，由於節點B為該 第一高電源供應電壓(V_DDH1)，且該第二低電壓節點(VL2)呈較接地電壓為低之電壓，本發明將該第一高電源供應電壓(V_DDH1)設定為高於該電源供應電壓(V_DD)但低於該電源供應電壓(V_DD)與該第二PMOS電晶體(P12)臨界電壓之絕對值|V_TP12|的總和，亦即 Before the read operation occurs, the first NMOS transistor (M11) is turned on (ON) and the second NMOS transistor (M12) is turned off (OFF), the node A and the node B are respectively the ground voltage and the power supply voltage (V _DD ), and the read bit line (RBL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During reading, since the node B is the first high power supply voltage (V _DDH1 ), and the second low voltage node (VL2) is at a voltage lower than the ground voltage, the present invention uses the first high power supply voltage (V _DDH1 ) is set to be higher than the power supply voltage (V _DD ) but lower than the sum of the power supply voltage (V _DD ) and the absolute value |V _TP12 | which is

V_DD<V_DDH1<V_DD+|V_TP12| (11) V _DD <V _DDH1 <V _DD +|V _TP12 | (11)

其中，|V_TP12|表示該第二PMOS電晶體(P12)臨界電壓之絕對值，因此，可藉由增加該第二讀取用電晶體(M15)之導通程度，以提高讀取邏輯0之速度，同時配合較接地電壓為低之該第二低電壓節點(VL2)以進一步提高讀取速度。 Wherein, |V _TP12 | represents the absolute value of the threshold voltage of the second PMOS transistor (P12), therefore, by increasing the conduction degree of the second read transistor (M15), the read logic 0 can be improved. speed, while cooperating with the second low voltage node (VL2) which is lower than the ground voltage to further increase the reading speed.

再者，於讀取期間，藉由該讀取用字元線控制電路(6)以於該讀取用字元線(RWL)致能的第一階段，將該讀取用字元線控制信號(RWLC)設定成較該電源供應電壓(V_DD)還高之該第二高電源供應電壓(V_DDH2)，以進一步減少讀取路徑之電阻，並加速該讀取用位元線(RWL)上之電荷的放電從而再進一步提高讀取速度，而於該第一階段後之第二階段時，則將該讀取用字元線控制信號(RWLC)拉低回該電源供應電壓(V_DD)，以減緩讀取干擾。在此值得注意的是，該第二高電源供應電壓(V_DDH2)設定為高於該電源供應電壓(V_DD)但低於該電源供應電壓(V_DD)與該第一讀取用電晶體(M14)臨界電壓之V_TM14的總和時，亦即 Furthermore, during the read period, the read word line is controlled by the read word line control circuit (6) in the first stage of enabling the read word line (RWL). signal (RWLC) is set to the second high power supply voltage (V _DDH2 ) higher than the power supply voltage (V _DD ) to further reduce the resistance of the read path and speed up the read bit line (RWL ) to further increase the reading speed, and in the second phase after the first phase, the word line control signal (RWLC) for reading is pulled back to the power supply voltage (V _DD ) to mitigate read disturb. It is worth noting here that the second high power supply voltage (V _DDH2 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the first read transistor (M14) The sum of the threshold voltage V _TM14 , that is

V_DD<V_DDH2<V_DD+V_TM14 (12)比較方程式(6)與方程式(12)可知，該第二高電源供應電壓(V_DDH2)必須滿足該電源供應電壓(V_DD)與該第一讀取用電晶體(M14)臨界電壓之V_TM14的總和(V_DD+V_TM14)以及該電源供應電壓(V_DD)與該第三NMOS電晶體 (M13)臨界電壓之V_TM13的總和(V_DD+V_TM13)兩者中之較小者。 V _DD <V _DDH2 <V _DD +V _TM14 (12) Comparing Equation (6) with Equation (12), we can see that the second highest power supply voltage (V _DDH2 ) must satisfy the power supply voltage (V _DD ) and the first The sum of V _TM14 of the threshold voltage of a read transistor (M14) (V _DD +V _TM14 ) and the sum of the power supply voltage (V _DD ) and V _TM13 of the threshold voltage of the third NMOS transistor (M13) ( V _DD +V _TM13 ) whichever is smaller.

再者，為了簡化電路設計，可將該第一高電源供應電壓(V_DDH1)、該第二高電源供應電壓(V_DDH2)與該第三高電源供應電壓(V_DDH3)設計成相同，其值為大於該電源供應電壓(V_DD)但小於等於滿足該電源供應電壓(V_DD)與該第一讀取用電晶體(M14)臨界電壓之V_TM14的總和(V_DD+V_TM14)、該電源供應電壓(V_DD)與該第三NMOS電晶體(M13)臨界電壓之V_TM13的總和(V_DD+V_TM13)以及該電源供應電壓(V_DD)與該第二PMOS電晶體(P12)臨界電壓之絕對值|V_TP12|總和(V_DD+|V_TP12|)三者中之較小者(該值可由方程式(6)、方程式(11)與方程式(12)推知)。 Moreover, in order to simplify the circuit design, the first high power supply voltage (V _DDH1 ), the second high power supply voltage (V _DDH2 ) and the third high power supply voltage (V _DDH3 ) can be designed to be the same, which The value is greater than the power supply voltage (V _DD ) but less than or equal to the sum (V _DD +V _TM14 ) of the power supply voltage (V _DD ) and the critical voltage V _TM14 of the first reading transistor ( M14 ), The sum of the power supply voltage (V _DD ) and the threshold voltage V _TM13 of the third NMOS transistor (M13) (V _DD +V _TM13 ) and the sum of the power supply voltage (V _DD ) and the second PMOS transistor (P12 ) the absolute value of the threshold voltage |V _TP12 | sum (V _DD + |V _TP12 |) the smaller of the three (this value can be deduced from equation (6), equation (11) and equation (12)).

1:SRAM晶胞 1: SRAM unit cell

2:控制電路 2: Control circuit

3:預充電電路 3: Precharge circuit

4:待機啟動電路 4: Standby startup circuit

5:高電壓位準控制電路 5: High voltage level control circuit

6:讀取用字元線控制電路 6: Read word line control circuit

7:寫入驅動電路 7: Write drive circuit

SW:開關 SW: switch

P11:第一PMOS電晶體 P11: The first PMOS transistor

P12:第二PMOS電晶體 P12: The second PMOS transistor

M11:第一NMOS電晶體 M11: The first NMOS transistor

M12:第二NMOS電晶體 M12: The second NMOS transistor

M13:第三NMOS電晶體 M13: The third NMOS transistor

A:儲存節點 A: storage node

B:反相儲存節點 B: Inversion storage node

CE:耦合元件 CE: coupling element

M14:第一讀取用電晶體 M14: The first read transistor

M15:第二讀取用電晶體 M15: Second reading transistor

WBL:寫入用位元線 WBL: bit line for writing

WWL:寫入用字元線 WWL: word line for writing

RBL:讀取用位元線 RBL: read bit line

RWL:讀取用字元線 RWL: word line for reading

RWLC:讀取用字元線控制信號 RWLC: word line control signal for reading

C:節點 C: node

S:待機模式控制信號 S: Standby mode control signal

/S:反相待機模式控制信號 /S: reverse phase standby mode control signal

VL1:第一低電壓節點 VL1: the first low voltage node

VL2:第二低電壓節點 VL2: second low voltage node

M21:第四NMOS電晶體 M21: The fourth NMOS transistor

M22:第五NMOS電晶體 M22: Fifth NMOS transistor

M23:第六NMOS電晶體 M23: The sixth NMOS transistor

M24:第七NMOS電晶體 M24: The seventh NMOS transistor

M25:第八NMOS電晶體 M25: Eighth NMOS transistor

M26:第九NMOS電晶體 M26: Ninth NMOS transistor

M27:第十NMOS電晶體 M27: Tenth NMOS transistor

P21:第三PMOS電晶體 P21: The third PMOS transistor

RC:讀取控制信號 RC: read control signal

RGND:加速讀取電壓 RGND: Accelerated reading voltage

INV3:第三反相器 INV3: The third inverter

D1:第一延遲電路 D1: The first delay circuit

WC:寫入控制信號 WC: write control signal

P31:第四PMOS電晶體 P31: The fourth PMOS transistor

P:預充電信號 P: Precharge signal

M41:第十一NMOS電晶體 M41: Eleventh NMOS transistor

P41:第五PMOS電晶體 P41: Fifth PMOS transistor

D2:第二延遲電路 D2: Second delay circuit

V_DD:電源供應電壓 V _DD : power supply voltage

V_DDH1:第一高電源供應電壓 V _DDH1 : first high power supply voltage

V_DDH2:第二高電源供應電壓 V _DDH2 : The second highest power supply voltage

P51:第六PMOS電晶體 P51: The sixth PMOS transistor

P52:第七PMOS電晶體 P52: The seventh PMOS transistor

INV4:第四反相器 INV4: Fourth inverter

VH:高電壓節點 VH: high voltage node

P61:第八PMOS電晶體 P61: Eighth PMOS transistor

P62:第九PMOS電晶體 P62: Ninth PMOS transistor

P63:第十PMOS電晶體 P63: Tenth PMOS transistor

M61:第十二NMOS電晶體 M61: Twelfth NMOS transistor

INV5:第五反相器 INV5: fifth inverter

INV6:第六反相器 INV6: sixth inverter

P71:第十一PMOS電晶體 P71: Eleventh PMOS transistor

M71:第十三NMOS電晶體 M71: Thirteenth NMOS transistor

M72:第十四NMOS電晶體 M72: Fourteenth NMOS transistor

M73:第十五NMOS電晶體 M73: Fifteenth NMOS transistor

INV7:第七反相器 INV7: seventh inverter

INV8:第八反相器 INV8: eighth inverter

D3:第三延遲電路 D3: The third delay circuit

D4:第四延遲電路 D4: The fourth delay circuit

V_DDH3:第三高電源供應電壓 V _DDH3 : The third highest power supply voltage

Y:行解碼器輸出信號 Y: line decoder output signal

Cap:電容器 Cap: Capacitor

Din:輸入資料 Din: input data

Claims (10)

一種半導體記憶裝置，包括： A semiconductor memory device, comprising: 一記憶體陣列，該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成，每一列記憶體晶胞與每一行記憶體晶胞均包含有複數個記憶體晶胞(1)； A memory array, the memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and each row of memory cells includes a plurality of memory cells ( 1); 複數個控制電路(2)，每一列記憶體晶胞設置一個控制電路(2)； A plurality of control circuits (2), one control circuit (2) is provided for each row of memory cells; 複數個預充電電路(3)，每一行記憶體晶胞設置一個預充電電路(3)；一待機啟動電路(4)，該待機啟動電路(4)係促使該半導體記憶裝置快速進入待機模式，以有效提高該半導體記憶裝置之待機效能； A plurality of pre-charging circuits (3), each row of memory cells is provided with a pre-charging circuit (3); a standby startup circuit (4), the standby startup circuit (4) prompts the semiconductor memory device to quickly enter the standby mode, To effectively improve the standby performance of the semiconductor memory device; 複數個讀取用字元線控制電路(6)，每一列記憶體晶胞設置一個讀取用字元線控制電路(6)，以有效提高讀取速度；以及 A plurality of word line control circuits (6) for reading, one word line control circuit (6) for reading is provided for each row of memory cells, so as to effectively improve the reading speed; and 複數個寫入驅動電路(7)，每一行記憶體晶胞設置一個寫入驅動電路(7)，以於寫入模式時有效提高由邏輯1寫入邏輯0之寫入速度； A plurality of write drive circuits (7), one write drive circuit (7) is provided for each row of memory unit cells, so as to effectively increase the write speed of writing logic 0 from logic 1 to logic 0 in the write mode; 其中，每一記憶體晶胞(1)更包含： Wherein, each memory cell (1) further includes: 一第一反相器，係由一第一PMOS電晶體(P11)與一第一NMOS電晶體(M11)所組成，該第一反相器係連接在一電源供應電壓(V_DD)與一第一低電壓節點(VL1)之間； A first inverter is composed of a first PMOS transistor (P11) and a first NMOS transistor (M11), the first inverter is connected between a power supply voltage (V _DD ) and a between the first low voltage nodes (VL1); 一第二反相器，係由一第二PMOS電晶體(P12)與一第二NMOS電晶體(M12)所組成，該第二反相器係連接在一高電壓節點(VH)與一第二低電壓節點(VL2)之間； A second inverter is composed of a second PMOS transistor (P12) and a second NMOS transistor (M12), the second inverter is connected between a high voltage node (VH) and a first Between two low voltage nodes (VL2); 一儲存節點(A)，係由該第一反相器之輸出端所形成； a storage node (A) formed by the output of the first inverter; 一反相儲存節點(B)，係由該第二反相器之輸出端所形成； an inverted storage node (B) formed by the output of the second inverter; 一第三NMOS電晶體(M13)，係連接在該儲存節點(A)與一寫入用位元線(WBL)之間，且閘極連接至一寫入用字元線(WWL)； A third NMOS transistor (M13) is connected between the storage node (A) and a write bit line (WBL), and the gate is connected to a write word line (WWL); 一第一讀取用電晶體(M14)，該第一讀取用電晶體(M14)之源極、閘極與汲極係分別連接至一第二讀取用電晶體(M15)之汲極、一讀取用字元線控制信號(RWLC)與一讀取用位元線(RBL)； A first read transistor (M14), the source, gate and drain of the first read transistor (M14) are respectively connected to the drain of a second read transistor (M15) 1. A read word line control signal (RWLC) and a read bit line (RBL); 該第二讀取用電晶體(M15)，該第二讀取用電晶體(M15)之源極、閘極與汲極係分別連接至該第二低電壓節點(VL2)、該反相儲存節點(B)與該第一讀取用電晶體(M14)之源極；以及 The second read transistor (M15), the source, gate and drain of the second read transistor (M15) are respectively connected to the second low voltage node (VL2), the inverting storage node (B) and the source of the first read transistor (M14); and 一耦合元件控制器，該耦合元件控制器連接於該寫入用字元線(WWL)、該寫入用位元線(WBL)與該儲存節點(A)之間，並因應該寫入用字元線(WWL)、該寫入用位元線(WBL)與該儲存節點(A)之邏輯狀態而提供不同的耦合電容，其中當該寫入用字元線(WWL)及該寫入用位元線(WBL)均為高邏輯狀態且該儲存節點(A)所儲存之邏輯狀態為該邏輯0時提供最大的耦合電容，亦即，僅當該記憶體晶胞(1)被選定且該儲存節點(A)由該邏輯0寫入該邏輯1時，才於該寫入用字元線(WWL)及該儲存節點(A)之間提供最大的耦合電容； A coupling element controller, the coupling element controller is connected between the word line (WWL) for writing, the bit line (WBL) for writing and the storage node (A), and responds to the word line (WWL), the write bit line (WBL) and the logic state of the storage node (A) to provide different coupling capacitance, wherein when the write word line (WWL) and the write Maximum coupling capacitance is provided when both bit lines (WBL) are in a high logic state and the stored logic state of the storage node (A) is the logic 0, i.e., only when the memory cell (1) is selected And when the storage node (A) is written into the logic 1 by the logic 0, the maximum coupling capacitance is provided between the word line for writing (WWL) and the storage node (A); 其中，該第一反相器和該第二反相器係呈交互耦合連接，亦即該第一反相器之輸出端(即該儲存節點A)係連接至該第二反相器之輸入端，而該第二反相器之輸出端(即該反相儲存節點B)則連接至該第一反相器之輸入端； Wherein, the first inverter and the second inverter are connected in cross-coupling, that is, the output end of the first inverter (that is, the storage node A) is connected to the input of the second inverter terminal, and the output terminal of the second inverter (that is, the inverting storage node B) is connected to the input terminal of the first inverter; 而每一控制電路(2)更包含：一第四NMOS電晶體(M21)、一第五NMOS電晶體(M22)、一第六NMOS電晶體(M23)、一第七NMOS電晶體(M24)、一第八NMOS電晶體(M25)、一第九NMOS電晶體(M26)、一第十NMOS電晶體(M27)、一第三PMOS電晶體(P21)、一讀取控制信號(RC)、一第三反相器(INV3)、一第一延遲電路(D1)、一加速讀取電壓(RGND)、一寫入控制信號(WC)、一待機模式控制信號(S)以及一反相待機模式控制信號(/S)； And each control circuit (2) further includes: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24) , an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), A third inverter (INV3), a first delay circuit (D1), an acceleration read voltage (RGND), a write control signal (WC), a standby mode control signal (S) and an inverted standby Mode control signal (/S); 其中，該第四NMOS電晶體(M21)之源極、閘極與汲極係分別連接至一接地電壓、該反相待機模式控制信號(/S)與該第二低電壓節點(VL2)； Wherein, the source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the inverting standby mode control signal (/S) and the second low voltage node (VL2); 該第五NMOS電晶體(M22)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該待機模式控制信號(S)與該第二低電壓節點(VL2)； The source, gate and drain of the fifth NMOS transistor (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2) ; 該第六NMOS電晶體(M23)之源極係連接至該接地電壓，而閘極與汲極連接在一起並連接至該第一低電壓節點(VL1)； The source of the sixth NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1); 該第七NMOS電晶體(M24)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(M25)之汲極、該讀取控制信號(RC)與該第二低電壓節點(VL2)； The source, gate and drain of the seventh NMOS transistor (M24) are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); 該第八NMOS電晶體(M25)之源極、閘極與汲極係分別連接至該加速讀取電壓(RGND)、該第一延遲電路(D1)之輸出與該第七NMOS電晶體(M24)之源極； The source, gate and drain of the eighth NMOS transistor (M25) are respectively connected to the accelerated reading voltage (RGND), the output of the first delay circuit (D1) and the seventh NMOS transistor (M24 ) source; 該第一延遲電路(D1)係連接在該第三反相器(INV3)之輸出與該第八NMOS電晶體(M25)之該閘極之間； The first delay circuit (D1) is connected between the output of the third inverter (INV3) and the gate of the eighth NMOS transistor (M25); 該第三反相器(INV3)之輸入係供接收該讀取控制信號(RC)，而輸出則連接至該第一延遲電路(D1)之輸入； The input of the third inverter (INV3) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); 該第九NMOS電晶體(M26)之源極、閘極與汲極係分別連接至該接地電壓、該第十NMOS電晶體(M27)之汲極與該第一低電壓節點(VL1)； The source, gate and drain of the ninth NMOS transistor (M26) are respectively connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); 該第十NMOS電晶體(M27)之源極、閘極與汲極係分別連接至該待機模式控制信號(S)、該寫入控制信號(WC)與該第九NMOS電晶體(M26)之閘極； The source, gate and drain of the tenth NMOS transistor (M27) are respectively connected to the standby mode control signal (S), the write control signal (WC) and the ninth NMOS transistor (M26). Gate; 該第三PMOS電晶體(P21)之源極、閘極與汲極係分別連接至該反相待機模式控制信號(/S)、該寫入控制信號(WC)與該第十NMOS電晶體(M27)之汲極； The source, gate and drain of the third PMOS transistor (P21) are respectively connected to the inverting standby mode control signal (/S), the write control signal (WC) and the tenth NMOS transistor ( M27) drain pole; 其中，對於非讀取模式期間之該讀取控制信號(RC)係設定為該加速讀取電壓(RGND)之位準，以防止該第七NMOS電晶體(M24)於非讀取模式期間之漏電流； Wherein, the reading control signal (RC) during the non-reading mode is set to the level of the accelerated reading voltage (RGND) to prevent the seventh NMOS transistor (M24) from being damaged during the non-reading mode. leakage current; 再者，該待機啟動電路(4)係設計成於進入待機模式之一初始期間內，對該第一低電壓節點(VL1)處之寄生電容快速充電至該第六NMOS電晶體(M23)之臨界電壓(V_TM23)的電壓位準； Furthermore, the standby startup circuit (4) is designed to quickly charge the parasitic capacitance at the first low voltage node (VL1) to the sixth NMOS transistor (M23) during an initial period of entering the standby mode the voltage level of the threshold voltage (V _TM23 ); 其中，每一寫入驅動電路(7)更包含：一第十一PMOS電晶體(P71)、一第十三NMOS電晶體(M71)、一第十四NMOS電晶體(M72)、一第十五NMOS電晶體(M73)、一第七反相器(INV7)、一第八反相器(INV8)、一電容器(Cap)、一輸入資料(Din)、一行解碼器輸出信號(Y)、一第三延遲電路(D3)、一第四延遲電路(D4)以及一第三高電源供應電壓(V_DDH3)； Wherein, each writing drive circuit (7) further includes: an eleventh PMOS transistor (P71), a thirteenth NMOS transistor (M71), a fourteenth NMOS transistor (M72), a tenth Five NMOS transistors (M73), one seventh inverter (INV7), one eighth inverter (INV8), one capacitor (Cap), one input data (Din), one line of decoder output signal (Y), a third delay circuit (D3), a fourth delay circuit (D4) and a third high power supply voltage (V _DDH3 ); 其中，該第十一PMOS電晶體(P71)之源極、閘極與汲極係分別連接至該第三高電源供應電壓(V_DDH3)、該第七反相器(INV7)之輸出與該第十三NMOS電晶體(M71)之汲極； Wherein, the source, gate and drain of the eleventh PMOS transistor (P71) are respectively connected to the third high power supply voltage (V _DDH3 ), the output of the seventh inverter (INV7) and the The drain of the thirteenth NMOS transistor (M71); 該第十三NMOS電晶體(M71)之源極、閘極與汲極係分別連接至該第十五NMOS電晶體(M73)之汲極、該第七反相器(INV7)之輸出與該第十一PMOS電晶體(P71)之汲極； The source, gate and drain of the thirteenth NMOS transistor (M71) are respectively connected to the drain of the fifteenth NMOS transistor (M73), the output of the seventh inverter (INV7) and the The drain of the eleventh PMOS transistor (P71); 該第十四NMOS電晶體(M72)之源極、閘極與汲極係分別連接至該接地電壓、該第三延遲電路(D3)之輸出與該第十一PMOS電晶體(P71)之汲極； The source, gate and drain of the fourteenth NMOS transistor (M72) are respectively connected to the ground voltage, the output of the third delay circuit (D3) and the drain of the eleventh PMOS transistor (P71). pole; 該第十五NMOS電晶體(M73)之源極、閘極與汲極係分別連接至該接地電壓、該第八反相器(INV8)之輸出與該第十三NMOS電晶體(M71)之源極； The source, gate and drain of the fifteenth NMOS transistor (M73) are respectively connected to the ground voltage, the output of the eighth inverter (INV8) and the thirteenth NMOS transistor (M71). source; 該第七反相器(INV7)之輸入係供接收該輸入資料(Din)，而輸出則連接至該第十一PMOS電晶體(P71)之閘極、該第十三NMOS電晶體(M71)之閘極以及該第三延遲電路(D3)之輸入； The input of the seventh inverter (INV7) is for receiving the input data (Din), and the output is connected to the gate of the eleventh PMOS transistor (P71), the thirteenth NMOS transistor (M71) and the input of the third delay circuit (D3); 該第八反相器(INV8)之輸入係供接收該行解碼器輸出信號(Y)，而輸出則連接至該第四延遲電路(D4)之輸入以及該第十五NMOS電晶體(M73)之閘極； The input of the eighth inverter (INV8) is for receiving the row decoder output signal (Y), and the output is connected to the input of the fourth delay circuit (D4) and the fifteenth NMOS transistor (M73) gate of 該電容器(Cap)之一端係連接至該第四延遲電路(D4)之輸出，而該電容器(Cap)之另一端則連接至該第十三NMOS電晶體(M71)之源極以及該第十五NMOS電晶體(M73)之汲極； One end of the capacitor (Cap) is connected to the output of the fourth delay circuit (D4), and the other end of the capacitor (Cap) is connected to the source of the thirteenth NMOS transistor (M71) and the tenth NMOS transistor (M71). 5 drains of NMOS transistors (M73); 其中，該第十一PMOS電晶體(P71)之汲極、該第十三NMOS電晶體(M71)之汲極與該第十四NMOS電晶體(M72)之汲極係共同連接至該寫入用位元線(WBL)，該寫入用位元線(WBL)於寫入該邏輯0之第一階段係設計成低於於該接地電壓之電壓位準，以加速寫入該邏輯0之速度，而於寫入邏輯0之第二階段，則拉回至該接地電壓，以減緩寫入該邏輯0時的干擾；而於寫入該邏輯1時，該寫入用位元線(WBL)設計成高於該電源供應電壓(V_DD)之該第三高電源供應電壓(V_DDH3)的位準，以加速寫入該邏輯1之速度； Wherein, the drain of the eleventh PMOS transistor (P71), the drain of the thirteenth NMOS transistor (M71) and the drain of the fourteenth NMOS transistor (M72) are commonly connected to the writing Using the bit line (WBL), the write bit line (WBL) is designed to be lower than the ground voltage in the first stage of writing the logic 0, so as to speed up the writing of the logic 0 speed, and in the second stage of writing logic 0, it is pulled back to the ground voltage to slow down the interference when writing the logic 0; and when writing the logic 1, the write bit line (WBL ) is designed to be higher than the level of the third high power supply voltage (V _DDH3 ) of the power supply voltage (V _DD ), so as to speed up writing the logic 1; 其中，該每一寫入驅動電路(7)於寫入該邏輯0之該第一階段滿足下列方程式： Wherein, each writing drive circuit (7) satisfies the following equation in the first stage of writing the logic 0: V_WBL1=-V_DD×Cap/(Cap+C_WBL) V _WBL1 =-V _DD ×Cap/(Cap+C _WBL ) 其中，V_WBL1表示該寫入用位元線(WBL)於寫入該邏輯0之該第一階段 的電壓位準，V_WBL1的絕對值設計為小於該第三NMOS電晶體(M13)之臨界電壓，V_DD為該電源供應電壓(V_DD)之電壓位準，而Cap與C_WBL分別表示該電容器(Cap)之電容值與該寫入用位元線(WBL)之寄生電容值。 Wherein, V _WBL1 represents the voltage level of the writing bit line (WBL) in the first stage of writing the logic 0, and the absolute value of V _WBL1 is designed to be smaller than the threshold of the third NMOS transistor (M13) Voltage, V _DD is the voltage level of the power supply voltage (V _DD ), and Cap and C _WBL respectively represent the capacitance of the capacitor (Cap) and the parasitic capacitance of the bit line for writing (WBL). 如申請專利範圍第1項所述之半導體記憶裝置，其中，更包括複數個高電壓位準控制電路(5)，每一列記憶體晶胞設置一個高電壓位準控制電路(5)，以在讀取邏輯0時提高讀取速度，每一高電壓位準控制電路(5)更包含：一第六PMOS電晶體(P51)、一第七PMOS電晶體(P52)以及一第四反相器(INV4)； The semiconductor memory device as described in Item 1 of the scope of the patent application, which further includes a plurality of high-voltage level control circuits (5), and each row of memory cells is provided with a high-voltage level control circuit (5), so as to To improve the reading speed when reading logic 0, each high voltage level control circuit (5) further includes: a sixth PMOS transistor (P51), a seventh PMOS transistor (P52) and a fourth inverter (INV4); 其中，該第六PMOS電晶體(P51)之源極、閘極與汲極係分別連接至該電源供應電壓(V_DD)、該讀取控制信號(RC)與該高電壓節點(VH)； Wherein, the source, gate and drain of the sixth PMOS transistor (P51) are respectively connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH); 該第七PMOS電晶體(P52)之源極、閘極與汲極係分別連接至一第一高電源供應電壓(V_DDH1)、該第四反相器(INV4)之輸出與該高電壓節點(VH)； The source, gate and drain of the seventh PMOS transistor (P52) are respectively connected to a first high power supply voltage (V _DDH1 ), the output of the fourth inverter (INV4) and the high voltage node (VH); 該第四反相器(I63)之輸入係供接收該讀取控制信號(RC)，而該輸出則連接至該第七PMOS電晶體(P52)之閘極。 The input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to the gate of the seventh PMOS transistor (P52). 如申請專利範圍第2項所述之半導體記憶裝置，其中，每一讀取用字元線控制電路(6)更包含：一第八PMOS電晶體(P61)、一第九PMOS電晶體(P62)、一第十PMOS電晶體(P63)、一第十二NMOS電晶體(M61)、一第五反相器(INV5)、一第六反相器(INV6)、該第二高電源供應電壓(V_DDH2)、該讀取用字元線(RWL)以及該讀取用字元線控制信號(RWLC)； The semiconductor memory device as described in item 2 of the scope of the patent application, wherein each word line control circuit (6) for reading further includes: an eighth PMOS transistor (P61), a ninth PMOS transistor (P62 ), a tenth PMOS transistor (P63), a twelfth NMOS transistor (M61), a fifth inverter (INV5), a sixth inverter (INV6), the second high power supply voltage (V _DDH2 ), the read word line (RWL) and the read word line control signal (RWLC); 其中，該第八PMOS電晶體(P61)之源極、閘極與汲極係分別連接至該第二高電源供應電壓(V_DDH2)、該第五反相器(INV5)之輸出與該第九PMOS電晶體(P62)之源極； Wherein, the source, gate and drain of the eighth PMOS transistor (P61) are respectively connected to the second high power supply voltage (V _DDH2 ), the output of the fifth inverter (INV5) and the first Nine PMOS transistor (P62) source; 該第九PMOS電晶體(P62)之源極、閘極與汲極係分別連接至該第八PMOS電晶體(P61)之汲極、該第六反相器(INV6)之輸出與該讀取用字元線控制信號(RWLC)； The source, gate and drain of the ninth PMOS transistor (P62) are respectively connected to the drain of the eighth PMOS transistor (P61), the output of the sixth inverter (INV6) and the readout Use the word line control signal (RWLC); 第十PMOS電晶體(P63)之源極、閘極與汲極係分別連接至該電源供應電壓(V_DD)、該第五反相器(INV5)之輸出與該讀取用字元線控制 信號(RWLC)； The source, gate and drain of the tenth PMOS transistor (P63) are respectively connected to the power supply voltage (V _DD ), the output of the fifth inverter (INV5) and the word line control for reading signal(RWLC); 該第十二NMOS電晶體(M61)之源極、閘極與汲極係分別連接至該接地電壓、該第五反相器(INV5)之輸出與該讀取用字元線控制信號(RWLC)； The source, gate and drain of the twelfth NMOS transistor (M61) are respectively connected to the ground voltage, the output of the fifth inverter (INV5) and the read word line control signal (RWLC ); 該第五反相器(INV5)之輸入係供接收該讀取用字元線(RWL)，而該第六反相器(INV6)之輸入則與該第五反相器(INV5)之輸出連接。 The input of the fifth inverter (INV5) is for receiving the read word line (RWL), and the input of the sixth inverter (INV6) is connected to the output of the fifth inverter (INV5). connect. 如申請專利範圍第3項所述之半導體記憶裝置，其中，每一預充電電路(3)係由一第四PMOS電晶體(P31)以及一預充電信號(P)所組成； The semiconductor memory device as described in item 3 of the scope of the patent application, wherein each pre-charging circuit (3) is composed of a fourth PMOS transistor (P31) and a pre-charging signal (P); 其中，該第四PMOS電晶體(P31)之源極、閘極與汲極係分別連接至該電源供應電壓(V_DD)、該預充電信號(P)與該讀取用位元線(RBL)，以便於一預充電期間，藉由邏輯低位準之該預充電信號(P)，以將該讀取用位元線(RBL)預充電至該電源供應電壓(V_DD)之位準； Wherein, the source, gate and drain of the fourth PMOS transistor (P31) are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the read bit line (RBL ), so that during a precharge period, the read bit line (RBL) is precharged to the level of the power supply voltage (V _DD ) by the precharge signal (P) of logic low level; 該待機啟動電路(4)係由一第五PMOS電晶體(P41)、一第十一NMOS電晶體(M41)、一第二延遲電路(D2)以及該反相待機模式控制信號(/S)所組成； This standby startup circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2) and the inverted standby mode control signal (/S) composed of; 其中，該第五PMOS電晶體(P41)之源極、閘極與汲極係分別連接至該電源供應電壓(V_DD)、該反相待機模式控制信號(/S)與該第十一NMOS電晶體(M41)之汲極； Wherein, the source, gate and drain of the fifth PMOS transistor (P41) are connected to the power supply voltage (V _DD ), the inverting standby mode control signal (/S) and the eleventh NMOS transistor respectively. The drain of the transistor (M41); 該第十一NMOS電晶體(M41)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該第二延遲電路(D2)之輸出與該第五PMOS電晶體(P41)之該汲極； The source, gate and drain of the eleventh NMOS transistor (M41) are respectively connected to the first low voltage node (VL1), the output of the second delay circuit (D2) and the fifth PMOS transistor (P41) the drain; 該第二延遲電路(D2)之輸入連接至該反相待機模式控制信號(/S)，而該第二延遲電路(D2)之輸出則連接至該第十一NMOS電晶體(M41)之閘極。 The input of the second delay circuit (D2) is connected to the inverting standby mode control signal (/S), and the output of the second delay circuit (D2) is connected to the gate of the eleventh NMOS transistor (M41) pole. 如申請專利範圍第4項所述之半導體記憶裝置，其中，該儲存節點(A)於原本儲存該邏輯0，而在寫入該邏輯1之寫入初始瞬間電壓(V_AWI1)滿足下列方程式： The semiconductor memory device as described in item 4 of the scope of the patent application, wherein the storage node (A) originally stores the logic 0, and the write initial instant voltage (V _AWI1 ) when writing the logic 1 satisfies the following equation: V_AWI1=V_DDH3×(R_M11+R_M23)/(R_M13+R_M11+R_M23)>V_TM12 V _AWI1 =V _DDH3 ×(R _M11 +R _M23 )/(R _M13 +R _M11 +R _M23 )>V _TM12 其中，V_AWI1表示該儲存節點(A)由儲存該邏輯0而寫入該邏輯1之該寫入初始瞬間電壓，R_M11、R_M13與R_M23分別表示該第一NMOS電晶體 (M11)、該第三NMOS電晶體(M13)與該第六NMOS電晶體(M23)之導通電阻，而V_DDH3與V_TM12分別表示該第三高電源供應電壓之電壓位準與該第二NMOS電晶體(M12)之臨界電壓； Wherein, V _AWI1 represents the initial writing instant voltage of the storage node (A) which stores the logic 0 and writes the logic 1, and R _M11 , R _M13 and R _M23 respectively represent the first NMOS transistor ( M11 ), The on-resistance of the third NMOS transistor (M13) and the sixth NMOS transistor (M23), and V _DDH3 and V _TM12 respectively represent the voltage level of the third high power supply voltage and the second NMOS transistor ( M12) critical voltage; 且該儲存節點(A)於原本儲存該邏輯1，而在寫入該邏輯0之寫入初始瞬間電壓(V_AWI0)滿足下列方程式： In addition, the storage node (A) originally stores the logic 1, and the initial instant voltage (V _AWI0 ) of writing the logic 0 satisfies the following equation: V_AWI0=V_WBL1×R_P11/(R_M13+R_P11)+V_DD×R_M13/(R_M13+R_P11) V _AWI0 =V _WBL1 ×R _P11 /(R _M13 +R _P11 )+V _DD ×R _M13 /(R _M13 +R _P11 ) 其中，V_AWI0表示節點A由該邏輯1寫入該邏輯0之寫入初始瞬間電壓，R_M13與R_P11分別表示該第三NMOS電晶體(M13)與該第一PMOS電晶體(P11)之導通電阻，而V_WBL1與V_DD分別表示該寫入用位元線(WBL)於寫入該邏輯0之該第一階段的電壓位準與該電源供應電壓(V_DD)之電壓位準。 Among them, _VAWI0 represents the initial instant voltage of node A written into the logic 0 by the logic 1, and R _M13 and R _P11 respectively represent the voltage between the third NMOS transistor (M13) and the first PMOS transistor (P11). On-resistance, and V _WBL1 and V _DD respectively represent the voltage level of the writing bit line (WBL) in the first stage of writing the logic 0 and the voltage level of the power supply voltage (V _DD ). 如申請專利範圍第5項所述之半導體記憶裝置，其中，該第二高電源供應電壓(V_DDH2)係設定為滿足該電源供應電壓(V_DD)與該第一讀取用電晶體(M14)之臨界電壓(V_TM14)的總和(即V_DD+V_TM14)以及該電源供應電壓(V_DD)與該第三NMOS電晶體(M13)之臨界電壓(V_TM13)的總和(即V_DD+V_TM13)兩者中之較小者。 The semiconductor memory device as described in item 5 of the scope of the patent application, wherein the second high power supply voltage (V _DDH2 ) is set to satisfy the power supply voltage (V _DD ) and the first reading transistor (M14 ) of the threshold voltage (V _TM14 ) (that is, V _DD +V _TM14 ) and the sum of the power supply voltage (V _DD ) and the threshold voltage (V _TM13 ) of the third NMOS transistor (M13) (that is, V _DD +V _TM13 ) the smaller of the two. 如申請專利範圍第6項所述之半導體記憶裝置，其中，讀取操作係可再細分成二個階段，於該讀取操作之一第一階段係藉由將該第二低電壓節點(VL2)設定成較該接地電壓為低之電壓以有效提高讀取速度，而於該讀取操作之一第二階段則藉由將該第二低電壓節點(VL2)設定回該接地電壓，以便減少無謂的功率消耗；於該讀取操作之該第一階段，該第二低電壓節點(VL2)於讀取邏輯1時之讀取初始瞬間電壓(V_RVL2I)必須滿足下列方程式： For the semiconductor memory device described in item 6 of the scope of the patent application, wherein the read operation can be subdivided into two stages, and in the first stage of the read operation, the second low voltage node (VL2 ) is set to a voltage lower than the ground voltage to effectively increase the read speed, and in a second stage of the read operation by setting the second low voltage node (VL2) back to the ground voltage, in order to reduce Unnecessary power consumption; in the first phase of the read operation, the read initial transient voltage (V _RVL2I ) of the second low voltage node (VL2) when reading logic 1 must satisfy the following equation: V_RVL2I=RGND×R_M21/(R_M21+R_M24+R_M25)>-V_TM12 V _RVL2I =RGND×R _M21 /(R _M21 +R _M24 +R _M25 )>-V _TM12 以有效地防止讀取時之半選定晶胞干擾，其中，V_RVL2I表示該第二低電壓節點(VL2)於讀取邏輯1時之該讀取初始瞬間電壓，RGND表示該加速讀取電壓，R_M21表示該第四NMOS電晶體(M21)之導通電阻，R_M24表示該第七NMOS電晶體(M24)之導通電阻，R_M25表示該第八NMOS 電晶體(M25)之導通電阻，而V_TM12表示該第二NMOS電晶體(M12)之臨界電壓。 To effectively prevent half-selected cell interference during reading, wherein, _VRVL2I represents the initial instantaneous voltage of the second low voltage node (VL2) when reading logic 1, and RGND represents the accelerated reading voltage, RM21 represents the conduction resistance of the fourth NMOS transistor ( _M21 ), RM24 represents the conduction resistance of the seventh NMOS transistor ( _M24 ), RM25 represents the conduction resistance of the eighth NMOS transistor ( _M25 ), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12). 如申請專利範圍第7項所述之半導體記憶裝置，其中，該第一高電源供應電壓(V_DDH1)係設定為高於該電源供應電壓(V_DD)但低於該電源供應電壓(V_DD)與該第二PMOS電晶體(P12)臨界電壓之絕對值|V_TP12|的總和，亦即 The semiconductor memory device as described in item 7 of the scope of the patent application, wherein the first high power supply voltage (V _DDH1 ) is set to be higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the absolute value |V _TP12 | of the threshold voltage of the second PMOS transistor (P12), that is V_DD<V_DDH1<V_DD+|V_TP12|。 V _DD < V _DDH1 < V _DD + |V _TP12 |. 如申請專利範圍第8項所述之半導體記憶裝置，其中，該第一高電源供應電壓(V_DDH1)、該第二高電源供應電壓(V_DDH2)與該第三高電源供應電壓(V_DDH3)設定成相同，其值為大於該電源供應電壓(V_DD)但小於等於該電源供應電壓(V_DD)與該第一讀取用電晶體(M14)臨界電壓(V_TM14)的總和(V_DD+V_TM14)、該電源供應電壓(V_DD)與該第三NMOS電晶體M13)臨界電壓(V_TM13)的總和(V_DD+V_TM13)以及該電源供應電壓(V_DD)與該第二PMOS電晶體(P12)臨界電壓之絕對值(|V_TP12|)的總和(V_DD+|V_TP12|)三者中之較小者。 The semiconductor memory device as described in item 8 of the scope of the patent application, wherein the first high power supply voltage (V _DDH1 ), the second high power supply voltage (V _DDH2 ) and the third high power supply voltage (V _DDH3 ) is set to be the same, and its value is greater than the power supply voltage ( _{V DD} ) but less than or equal _to the sum (V _DD +V _TM14 ), the sum of the power supply voltage (V _DD ) and the third NMOS transistor M13) threshold voltage (V _TM13 ) (V _DD +V _TM13 ), and the power supply voltage (V _DD ) and the first The smaller of the sum (V _DD + |V _TP12 |) of the absolute value of the threshold voltage (|V _TP12 |) of the two PMOS transistors (P12). 如申請專利範圍第1項所述之半導體記憶裝置，其中，該耦合元件控制器係由一開關(SW)及一耦合元件(CE)所組成，其中該開關係由一NMOS電晶體所組成，該NMOS電晶體之閘極連接該寫入用位元線(WBL)，該NMOS電晶體之汲極連接該寫入用字元線(WWL)，而該NMOS電晶體之源極連接該耦合元件(CE)之一端；該耦合元件(CE)係由另一NMOS電晶體所組成，其閘極連接該開關之該NMOS電晶體的源極，其源極與汲極連接在一起並連接至該儲存節點(A)，其中，該寫入用字元線(WWL)致能之電壓位準為該電源供應電壓(V_DD)。 The semiconductor memory device as described in item 1 of the scope of the patent application, wherein the coupling element controller is composed of a switch (SW) and a coupling element (CE), wherein the switch is composed of an NMOS transistor, The gate of the NMOS transistor is connected to the write bit line (WBL), the drain of the NMOS transistor is connected to the write word line (WWL), and the source of the NMOS transistor is connected to the coupling element One end of (CE); the coupling element (CE) is composed of another NMOS transistor, its gate is connected to the source of the NMOS transistor of the switch, and its source and drain are connected together and connected to the A storage node (A), wherein the voltage level for enabling the word line for writing (WWL) is the power supply voltage (V _DD ).

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