TWI716162B - Dual port static random access memory - Google Patents

Dual port static random access memory Download PDF

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TWI716162B
TWI716162B TW108138325A TW108138325A TWI716162B TW I716162 B TWI716162 B TW I716162B TW 108138325 A TW108138325 A TW 108138325A TW 108138325 A TW108138325 A TW 108138325A TW I716162 B TWI716162 B TW I716162B
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nmos transistor
inverter
writing
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TW202117726A (en
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黃淳德
蕭明椿
陳盈宏
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修平學校財團法人修平科技大學
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Abstract

本發明提出一種雙埠靜態隨機存取記憶體，其主要包括一記憶體陣列(1)、複數個控制電路(2)、複數個預充電電路(3)、一待機啟動電路(4)、複數個高電壓位準控制電路(5)、複數個寫入用字元線控制電路(6)、複數個讀取用字元線控制電路(7)、以及一個寫入驅動電路(8)。藉此，於寫入模式時，可藉由該複數個控制電路(2)、該複數個寫入用字元線控制電路(6)以及該複數個寫入驅動電路(8)的組合以防止寫入邏輯1困難之同時，亦有效提高寫入速度，而於讀取模式時，則藉由該複數個控制電路(2)、該複數個高電壓位準控制電路(5)以及該複數個讀取用字元線控制電路(7)的組合以於提高讀取速度的同時，亦避免無謂的功率耗損。 The present invention provides a dual-port static random access memory, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), a standby activation circuit (4), a plurality of A high-voltage level control circuit (5), a plurality of writing word line control circuits (6), a plurality of reading word line control circuits (7), and a writing drive circuit (8). Therefore, in the writing mode, the combination of the plurality of control circuits (2), the plurality of writing word line control circuits (6), and the plurality of write drive circuits (8) can prevent While writing logic 1 is difficult, it also effectively improves the writing speed. In the read mode, the plurality of control circuits (2), the plurality of high voltage level control circuits (5) and the plurality of The combination of the word line control circuit (7) for reading can improve the reading speed while avoiding unnecessary power consumption.

Description

雙埠靜態隨機存取記憶體 Dual-port static random access memory

本發明係有關於一種具高讀取/寫入速度之雙埠(dual port)靜態隨機存取記憶體(Static Random Access Memory，簡稱SRAM)，尤指一種有效提高7T SRAM待機效能，並能有效提高讀取速度與寫入速度，且能有效降低漏電流(leakage current)、降低讀取時之半選定晶胞干擾以及避免無謂的功率耗損之SRAM。 The present invention relates to a dual port static random access memory (SRAM) with high read/write speed, in particular to a kind of 7T SRAM that effectively improves the standby performance of 7T SRAM and can effectively Improve read speed and write speed, and can effectively reduce leakage current (leakage current), reduce half-selected cell interference during read, and avoid unnecessary power consumption of SRAM.

習知之單埠靜態隨機存取記憶體(SRAM)如第1a圖所示，其主要包括一記憶體陣列(memory array)，該記憶體陣列係由複數個記憶體區塊(memory block，MB1、MB2等)所組成，每一記憶體區塊更由複數列記憶體晶胞(a plurality of rows of memory cells)與複數行記憶體晶胞(a plurality of columns of memory cells)所組成，每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體晶胞；複數條字元線(word line，WL1、WL2等)，每一字元線對應至複數列記憶體晶胞中之一列；以及複數位元線對(bit line pairs，BL1、BLB1...BLm、BLBm等)，每一位元線對係對應至複數行記憶體晶胞中之一行，且每一位元線對係由一位元線(BL1...BLm)及一互補位元線(BLB1...BLBm)所組成。 The conventional single-port static random access memory (SRAM) is shown in Figure 1a. It mainly includes a memory array. The memory array is composed of a plurality of memory blocks (MB 1). , MB 2, etc.), each memory block is composed of a plurality of rows of memory cells (a plurality of rows of memory cells) and a plurality of rows of memory cells (a plurality of columns of memory cells). Each row of memory cell and each row of memory cell includes a plurality of memory cells; a plurality of word lines (WL 1 , WL 2, etc.), each word line corresponds to a plurality of rows of memory A column in the body cell; and multiple bit line pairs (BL 1 , BLB 1 ... BL m , BLB m, etc.), each bit line pair corresponds to the plural row memory cell One row, and each bit line pair is composed of a bit line (BL 1 ... BL m ) and a complementary bit line (BLB 1 ... BLB m ).

第1b圖所示即是6T單埠靜態隨機存取記憶體(SRAM)晶胞 之電路示意圖，其中，PMOS電晶體(P1)和(P2)稱為負載電晶體(load transistor)，NMOS電晶體(M1)和(M2)稱為驅動電晶體(driving transistor)，NMOS電晶體(M3)和(M4)稱為存取電晶體(access transistor)，WL為字元線(word line)，而BL及BLB分別為位元線(bit line)及互補位元線(complementary bit line)，由於該單埠SRAM晶胞需要6個電晶體，且於讀取邏輯0時，為了避免讀取操作初始瞬間(initial instant)另一驅動電晶體導通，節點A之讀取初始瞬間電壓(VAR)必須滿足方程式(1)： Figure 1b shows the circuit diagram of the 6T single-port static random access memory (SRAM) unit cell. Among them, PMOS transistors (P1) and (P2) are called load transistors and NMOS transistors (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is a word line, and BL And BLB are bit lines and complementary bit lines respectively. Because the single-port SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial instant) Another driving transistor is turned on, and the read initial instant voltage (V AR ) of node A must satisfy equation (1):

VAR=VDD×(RM1)/(RM1+RM3)<VTM2 (1)以防止讀取時之半選定晶胞干擾(half-selected cell disturbance)，其中，VAR表示節點A之讀取初始瞬間電壓，RM1與RM3分別表示該NMOS電晶體(M1)與該NMOS電晶體(M3)之導通電阻，而VDD與VTM2分別表示電源供應電壓與該NMOS電晶體(M2)之臨界電壓，此導致驅動電晶體與存取電晶體之間的電流驅動能力比(即單元比率，cell ratio)通常設定在2.2至3.5之間(請參考98年10月20日第US76060B2號專利說明書第2欄第8-10行)。 V AR =V DD ×(R M1 )/(R M1 +R M3 )<V TM2 (1) to prevent half-selected cell disturbance during reading, where V AR represents node A R M1 and R M3 respectively represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3), and V DD and V TM2 represent the power supply voltage and the NMOS transistor ( M2) the threshold voltage, which results in the current drive capability ratio (ie cell ratio) between the drive transistor and the access transistor is usually set between 2.2 and 3.5 (please refer to US76060B2 dated October 20, 1998) Patent No. 2, column 2, lines 8-10).

第1b圖所示6T單埠靜態隨機存取記憶體晶胞於寫入操作時之HSPICE暫態分析模擬結果，如第2圖所示，其係使用TSMC 90奈米CMOS製程參數加以模擬。 Figure 1b shows the HSPICE transient analysis simulation results of the 6T single-port static random access memory cell during the write operation. As shown in Figure 2, it was simulated using TSMC 90nm CMOS process parameters.

用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之一種方式係揭露於第3圖中。第3圖顯示一種僅具單一位元線之5T單埠靜態隨機存取記憶體晶胞之電路示意圖，與第1b圖之6T單埠靜態隨機存取記憶體晶胞相比，此種5T靜態隨機存取記憶體晶胞比6T靜態隨機存取記憶體晶胞少一個電晶體及少一條位元線，惟該5T單埠靜態隨機存取記憶體晶胞 在不變更PMOS電晶體P1和P2以及NMOS電晶體M1、M2和M3的通道寬長比的情況下存在寫入邏輯1相當困難之問題。茲考慮記憶體晶胞左側節點A原本儲存邏輯0的情況，由於節點A之電荷僅單獨自位元線(BL)傳送，因此在將節點A中先前寫入的邏輯0蓋寫成邏輯1之寫入初始瞬間電壓(VAW)等於方程式(2)： One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a schematic circuit diagram of a 5T single-port static random access memory cell with only a single bit line. Compared with the 6T single-port static random access memory cell in Figure 1b, this 5T static The random access memory cell is one less transistor and one bit line less than the 6T static random access memory cell, but the 5T single port static random access memory cell does not change the PMOS transistors P1 and P2 And in the case of the channel width-to-length ratio of NMOS transistors M1, M2, and M3, there is a problem that writing logic 1 is quite difficult. Consider the situation that the node A on the left side of the memory cell originally stores logic 0. Since the charge of node A is only transferred from the bit line (BL) alone, the logic 0 written in node A is overwritten with logic 1 Enter the initial instantaneous voltage (V AW ) equal to equation (2):

VAW=VDD×(RM1)/(RM1+RM3) (2)其中，VAW表示節點A之寫入初始瞬間電壓，RM1與RM3分別表示NMOS電晶體(M1)與NMOS電晶體(M3)之導通電阻，比較方程式(1)與方程式(2)可知，寫入初始瞬間電壓(VAW)小於NMOS電晶體(M2)之臨界電壓(VTM2)，因而無法完成寫入邏輯1之操作。第3圖所示5T靜態隨機存取記憶體晶胞，於寫入操作時之HSPICE暫態分析模擬結果，如第4圖所示，其係使用TSMC 90奈米CMOS製程參數加以模擬，由該模擬結果可証實，具單一位元線之5T靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。 V AW =V DD ×(R M1 )/(R M1 +R M3 ) (2) Among them, V AW represents the initial instantaneous voltage of node A, and R M1 and R M3 represent NMOS transistors (M1) and NMOS respectively The on-resistance of the transistor (M3), comparing equation (1) and equation (2) shows that the initial instantaneous voltage (V AW ) of writing is less than the critical voltage (V TM2 ) of the NMOS transistor (M2), so writing cannot be completed Operation of logic 1. Figure 3 shows the HSPICE transient analysis simulation results of the 5T static random access memory cell during the write operation. As shown in Figure 4, it is simulated using TSMC 90nm CMOS process parameters. The simulation results can confirm that the 5T static random access memory cell with a single bit line has the problem that it is quite difficult to write logic 1.

接下來討論靜態隨機存取記憶體(SRAM)之單埠及雙埠架構，第1b圖之6T靜態隨機存取記憶體(SRAM)晶胞即是單埠靜態隨機存取記憶體(SRAM)晶胞之一例，其係使用兩條位元線BL及BLB做讀寫的動作，也就是讀與寫均是經由同樣的一對位元線來達成，是以在同一時間內只能進行讀或寫的動作，因此，當欲設計具有同時讀寫能力之雙埠靜態隨機存取記憶體時，便需要多加入兩顆存取電晶體以及另一對位元線(請參考第5圖所示電路，其中WBL及WBLB為寫入用位元線對、RBL及RBLB為讀取用位元線對、WWL為寫入用字元線、RWL為讀取用字元線)，這使得記憶體晶胞的面積大大地增加，如果我們能夠簡化記憶體晶胞的架構，使得一條 位元線負責讀取的動作，而另一條位元線負責寫入的動作，則在設計雙埠靜態隨機存取記憶體時，記憶體晶胞便不需要多加入兩顆電晶體及一對位元線，這樣記憶體晶胞的面積便會減小許多，傳統的雙埠靜態隨機存取記憶體晶胞之所以不採用這種方法，是因為如前所述存在寫入邏輯1相當困難之問題。 Next, we discuss the single-port and dual-port architecture of static random access memory (SRAM). The 6T static random access memory (SRAM) cell in Figure 1b is the single-port static random access memory (SRAM) crystal. An example of a cell, which uses two bit lines BL and BLB for reading and writing, that is, reading and writing are achieved through the same pair of bit lines, so only read or Therefore, when you want to design a dual-port static random access memory with simultaneous read and write capabilities, you need to add two more access transistors and another pair of bit lines (please refer to Figure 5 A circuit, where WBL and WBLB are bit line pairs for writing, RBL and RBLB are bit line pairs for reading, WWL is a word line for writing, and RWL is a word line for reading), which makes the memory The area of the unit cell is greatly increased. If we can simplify the structure of the memory unit cell, The bit line is responsible for reading, and the other bit line is responsible for writing. When designing a dual-port static random access memory, the memory cell does not need to add two more transistors and a pair Bit line, so the area of the memory cell will be much reduced. The reason why the traditional dual-port static random access memory cell does not use this method is because it is quite difficult to write logic 1 as mentioned above The problem.

迄今，有許多具單一讀取位元線之雙埠靜態隨機存取記憶體晶胞之技術被提出，例如專利文獻1所提出之「Dual write wordline memory cell」(第US9336863B2號，105年5月10日授予Qualcomm Corporation)，其係藉由二階段之寫入操作以避免由於使用單一寫入位元線所導致寫入邏輯1困難之問題，於寫入操作之第一階段預先寫入邏輯1，而於寫入操作之第二階段，則視實際寫入資料而決定是否將該預先寫入之邏輯1放電至邏輯0；專利文獻2所提出之「Method of writing to and reading data from a three-dimensional two port register file」(第US 9275724B2號，105年3月1日授予TSMC Corporation)，其係使用二個專用的讀取NMOS電晶體以達成單一讀取位元線之SRAM晶胞的讀取操作，而於寫入操作時由於使用二個存取電晶體與需要互補寫入位元線，導致SRAM晶胞電晶體數量較多之缺失；專利文獻3所提出之「雙埠靜態隨機存取記憶體」(第TW I605551B，106年11月11日授予修平科技大學)，其係藉由控制電路與高電壓位準控制電路的組合設計，於讀取操作之第一階段，利用控制電路將原本的接地電壓節點的電位拉低至小於接地電壓，並配合高電壓位準控制電路以減少讀取路徑之電阻，而加速單一讀取位元線之電荷的放電從而提高SRAM之讀取速度，而於讀取操作之第二階段，則將原本比接地電壓低的電壓改回接地電壓，以避 免無謂的功率消耗。該等專利雖可有效解決使用單一寫入位元線所導致寫入邏輯1困難之問題，惟該等專利均未考慮到SRAM操作電壓將降為0.9伏特以下，此時易因製程-電壓-溫度(PVT)變化而造成可能無法在規範的時間內完成寫入操作，因此仍有改進空間。 So far, many technologies for dual-port static random access memory cells with a single read bit line have been proposed, such as the "Dual write wordline memory cell" proposed in Patent Document 1 (No. US9336863B2, May 105 Granted to Qualcomm Corporation on the 10th), which uses a two-stage write operation to avoid the difficulty of writing logic 1 due to the use of a single write bit line, and write logic 1 in advance in the first stage of the write operation , And in the second stage of the write operation, it is determined whether to discharge the pre-written logic 1 to logic 0 according to the actual written data; Patent Document 2 proposes "Method of writing to and reading data from a three -dimensional two port register file" (No. US 9275724B2, granted to TSMC Corporation on March 1, 105), which uses two dedicated read NMOS transistors to achieve a single read bit line SRAM cell read During the write operation, the use of two access transistors and the need for complementary write bit lines lead to the lack of a large number of SRAM cell transistors; the "Dual Port Static Random Memory" proposed in Patent Document 3 Access memory" (No. TW I605551B, awarded to Shuhei University of Technology on November 11, 106), which is designed by the combination of a control circuit and a high-voltage level control circuit. The control circuit is used in the first stage of the read operation Pull down the potential of the original ground voltage node to less than the ground voltage, and cooperate with the high voltage level control circuit to reduce the resistance of the read path, and accelerate the discharge of the charge of a single read bit line to increase the read speed of SRAM , And in the second stage of the read operation, the voltage that was originally lower than the ground voltage is changed back to the ground voltage to avoid Avoid unnecessary power consumption. Although these patents can effectively solve the problem of difficulty in writing logic 1 caused by the use of a single write bit line, none of these patents consider that the SRAM operating voltage will drop below 0.9 volts. At this time, it is easy to cause process-voltage- The temperature (PVT) changes may not complete the write operation within the specified time, so there is still room for improvement.

有鑑於此，本發明之主要目的係提出一種雙埠靜態隨機存取記憶體，其能藉由複數個控制電路(2)、複數個寫入用字元線控制電路(6)以及複數個寫入驅動電路(8)的組合以有效提高寫入速度，尤其是提高由邏輯1寫入邏輯0之速度，且能有效解決10奈米以下SRAM操作電壓降為0.9V以下時易造成寫入時間無法滿足規範之問題。 In view of this, the main purpose of the present invention is to provide a dual-port static random access memory, which can be controlled by a plurality of control circuits (2), a plurality of writing word line control circuits (6) and a plurality of writing The combination of input drive circuit (8) can effectively improve the writing speed, especially the speed of writing logic 0 from logic 1, and can effectively solve the problem of writing time when the operating voltage of SRAM below 10nm drops below 0.9V. The problem of failing to meet the specifications

本發明之次要目的係提出一種雙埠靜態隨機存取記憶體，其能藉由複數個控制電路(2)、複數個高電壓位準控制電路(5)以及複數個讀取用字元線控制電路(7)的組合以於提高讀取速度的同時，亦避免無謂的功率耗損。 The secondary objective of the present invention is to provide a dual-port static random access memory, which can be controlled by a plurality of control circuits (2), a plurality of high voltage level control circuits (5) and a plurality of read word lines The combination of the control circuit (7) can improve the reading speed while avoiding unnecessary power loss.

本發明提出一種雙埠靜態隨機存取記憶體，其主要包括一記憶體陣列(1)、複數個控制電路(2)、複數個預充電電路(3)、一待機啟動電路(4)、複數個高電壓位準控制電路(5)、複數個寫入用字元線控制電路(6)、複數個讀取用字元線控制電路(7)、以及一個寫入驅動電路(8)。藉此，於寫入模式時，可藉由該複數個控制電路(2)、該複數個寫入用字元線控制電路(6)以及該複數個寫入驅動電路(8)的組合以防止寫入邏輯1困難之同時，亦有效提高寫入速度，而於讀取模式時，則藉由該複數個控制電路(2)、該複數個高電壓位準控制電路(5)以及該複 數個讀取用字元線控制電路(7)的組合以於提高讀取速度的同時，亦避免無謂的功率耗損。 The present invention provides a dual-port static random access memory, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), a standby activation circuit (4), a plurality of A high-voltage level control circuit (5), a plurality of writing word line control circuits (6), a plurality of reading word line control circuits (7), and a writing drive circuit (8). Therefore, in the writing mode, the combination of the plurality of control circuits (2), the plurality of writing word line control circuits (6), and the plurality of write drive circuits (8) can prevent While writing logic 1 is difficult, it also effectively increases the writing speed. In the read mode, the plurality of control circuits (2), the plurality of high voltage level control circuits (5) and the complex The combination of several word line control circuits (7) for reading can improve the reading speed while avoiding unnecessary power consumption.

1‧‧‧SRAM晶胞 1‧‧‧SRAM cell

2‧‧‧控制電路 2‧‧‧Control circuit

3‧‧‧預充電電路 3‧‧‧Pre-charge circuit

4‧‧‧待機啟動電路 4‧‧‧Standby start circuit

5‧‧‧高電壓位準控制電路 5‧‧‧High voltage level control circuit

6‧‧‧寫入用字元線控制電路 6‧‧‧Word line control circuit for writing

7‧‧‧讀取用字元線控制電路 7‧‧‧Character line control circuit for reading

8‧‧‧寫入驅動電路 8‧‧‧Write drive circuit

P11‧‧‧第一PMOS電晶體 P11‧‧‧First PMOS transistor

P12‧‧‧第二PMOS電晶體 P12‧‧‧Second PMOS Transistor

M11‧‧‧第一NMOS電晶體 M11‧‧‧First NMOS transistor

M12‧‧‧第二NMOS電晶體 M12‧‧‧Second NMOS Transistor

M13‧‧‧第三NMOS電晶體 M13‧‧‧The third NMOS transistor

A‧‧‧儲存節點 A‧‧‧Storage Node

B‧‧‧反相儲存節點 B‧‧‧Inverted storage node

C‧‧‧節點 C‧‧‧node

M14‧‧‧第一讀取用電晶體 M14‧‧‧First reading transistor

M15‧‧‧第二讀取用電晶體 M15‧‧‧Second reading transistor

WBL‧‧‧寫入用位元線 WBL‧‧‧Bit line for writing

WWL‧‧‧寫入用字元線 WWL‧‧‧Character line for writing

RBL‧‧‧讀取用位元線 RBL‧‧‧Bit line for reading

RWL‧‧‧讀取用字元線 RWL‧‧‧Character line for reading

WWLC‧‧‧寫入用字元線控制信號 WWLC‧‧‧Character line control signal for writing

RWLC‧‧‧讀取用字元線控制信號 RWLC‧‧‧Character line control signal for reading

S‧‧‧待機模式控制信號 S‧‧‧Standby mode control signal

/S‧‧‧反相待機模式控制信號 /S‧‧‧Inverted standby mode control signal

VL1‧‧‧第一低電壓節點 VL1‧‧‧The first low voltage node

VL2‧‧‧第二低電壓節點 VL2‧‧‧The second low voltage node

M21‧‧‧第四NMOS電晶體 M21‧‧‧Fourth NMOS Transistor

M22‧‧‧第五NMOS電晶體 M22‧‧‧Fifth NMOS Transistor

M23‧‧‧第六NMOS電晶體 M23‧‧‧The sixth NMOS transistor

M24‧‧‧第七NMOS電晶體 M24‧‧‧The seventh NMOS transistor

M25‧‧‧第八NMOS電晶體 M25‧‧‧Eighth NMOS Transistor

M26‧‧‧第九NMOS電晶體 M26‧‧‧Ninth NMOS Transistor

M27‧‧‧第十NMOS電晶體 M27‧‧‧Tenth NMOS Transistor

P21‧‧‧第三PMOS電晶體 P21‧‧‧The third PMOS transistor

RC‧‧‧讀取控制信號 RC‧‧‧Read control signal

RGND‧‧‧加速讀取電壓 RGND‧‧‧Accelerated reading voltage

INV3‧‧‧第三反相器 INV3‧‧‧Third inverter

D1‧‧‧第一延遲電路 D1‧‧‧First delay circuit

WC‧‧‧寫入控制信號 WC‧‧‧Write control signal

P31‧‧‧第四PMOS電晶體 P31‧‧‧Fourth PMOS Transistor

P‧‧‧預充電信號 P‧‧‧Precharge signal

M41‧‧‧第十一NMOS電晶體 M41‧‧‧Eleventh NMOS Transistor

P41‧‧‧第五PMOS電晶體 P41‧‧‧Fifth PMOS Transistor

D2‧‧‧第二延遲電路 D2‧‧‧Second delay circuit

VDD‧‧‧電源供應電壓 V DD ‧‧‧Power supply voltage

VDDH1‧‧‧第一高電源供應電壓 V DDH1 ‧‧‧The highest power supply voltage

VDDH2‧‧‧第二高電源供應電壓 V DDH2 ‧‧‧The second highest power supply voltage

P51‧‧‧第六PMOS電晶體 P51‧‧‧Sixth PMOS Transistor

P52‧‧‧第七PMOS電晶體 P52‧‧‧The seventh PMOS transistor

INV4‧‧‧第四反相器 INV4‧‧‧Fourth inverter

VH‧‧‧高電壓節點 VH‧‧‧High Voltage Node

P61‧‧‧第八PMOS電晶體 P61‧‧‧Eighth PMOS Transistor

P62‧‧‧第九PMOS電晶體 P62‧‧‧Ninth PMOS Transistor

P63‧‧‧第十PMOS電晶體 P63‧‧‧Tenth PMOS Transistor

M61‧‧‧第十二NMOS電晶體 M61‧‧‧Twelfth NMOS Transistor

INV5‧‧‧第五反相器 INV5‧‧‧Fifth inverter

INV6‧‧‧第六反相器 INV6‧‧‧Sixth inverter

P71‧‧‧第十一PMOS電晶體 P71‧‧‧Eleventh PMOS Transistor

P72‧‧‧第十二PMOS電晶體 P72‧‧‧Twelfth PMOS Transistor

P73‧‧‧第十三PMOS電晶體 P73‧‧‧Thirteenth PMOS Transistor

M71‧‧‧第十三NMOS電晶體 M71‧‧‧The thirteenth NMOS transistor

INV7‧‧‧第七反相器 INV7‧‧‧Seventh inverter

INV8‧‧‧第八反相器 INV8‧‧‧Eighth inverter

P81‧‧‧第十四PMOS電晶體 P81‧‧‧14th PMOS Transistor

M81‧‧‧第十四NMOS電晶體 M81‧‧‧14th NMOS Transistor

M82‧‧‧第十五NMOS電晶體 M82‧‧‧Fifteenth NMOS Transistor

M83‧‧‧第十六NMOS電晶體 M83‧‧‧Sixteenth NMOS Transistor

INV9‧‧‧第九反相器 INV9‧‧‧Ninth inverter

INV10‧‧‧第十反相器 INV10‧‧‧Tenth inverter

D3‧‧‧第三延遲電路 D3‧‧‧The third delay circuit

D4‧‧‧第四延遲電路 D4‧‧‧Fourth delay circuit

VDDH3‧‧‧第三高電源供應電壓 V DDH3 ‧‧‧The third highest power supply voltage

Y‧‧‧行解碼器輸出信號 Y‧‧‧Line decoder output signal

Cap‧‧‧電容器 Cap‧‧‧Capacitor

Din‧‧‧輸入資料 Din‧‧‧Enter data

BLB‧‧‧互補位元線 BLB‧‧‧Complementary bit line

BLB1…BLBm‧‧‧互補位元線 BLB 1 …BLB m ‧‧‧Complementary bit line

MB1…MBk‧‧‧記憶體區塊 MB 1 …MB k ‧‧‧Memory block

WL1…WLn‧‧‧字元線 WL 1 …WL n ‧‧‧Character line

BL1…BLm‧‧‧位元線 BL 1 …BL m ‧‧‧Bit line

M1…M4‧‧‧NMOS電晶體 M1…M4‧‧‧NMOS transistor

P1…P2‧‧‧PMOS電晶體 P1…P2‧‧‧PMOS Transistor

第1a圖 係顯示習知之靜態隨機存取記憶體； Figure 1a shows the conventional static random access memory;

第1b圖 係顯示習知6T靜態隨機存取記憶體晶胞之電路示意圖； Figure 1b is a schematic diagram showing the circuit of a conventional 6T static random access memory cell;

第2圖 係顯示習知6T靜態隨機存取記憶體晶胞之寫入動作時序圖； Figure 2 is a timing diagram showing the write operation of the conventional 6T static random access memory cell;

第3圖 係顯示習知5T靜態隨機存取記憶體晶胞之電路示意圖； Figure 3 is a schematic diagram showing the circuit of a conventional 5T static random access memory cell;

第4圖 係顯示習知5T靜態隨機存取記憶體晶胞之寫入動作時序圖； Figure 4 is a timing diagram showing the write operation of the conventional 5T static random access memory cell;

第5圖 係顯示習知8T雙埠靜態隨機存取記憶體晶胞之電路示意圖； Figure 5 is a schematic diagram showing the circuit of a conventional 8T dual-port static random access memory cell;

第6圖 係顯示本發明較佳實施例所提出之電路示意圖； Figure 6 is a schematic diagram showing the circuit proposed by the preferred embodiment of the present invention;

第7a圖 係顯示第6圖於寫入邏輯0期間之簡化電路圖； Figure 7a shows the simplified circuit diagram of Figure 6 during the writing of logic 0;

第7b圖 係顯示第6圖於寫入邏輯1期間之簡化電路圖； Figure 7b shows the simplified circuit diagram of Figure 6 during the writing of logic 1;

第8圖 係顯示第6圖於讀取期間之簡化電路圖。 Figure 8 shows the simplified circuit diagram of Figure 6 during the read period.

根據上述之主要目的，本發明提出一種雙埠靜態隨機存取記憶體，其主要包括一記憶體陣列，該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成，每一列記憶體晶胞與每一行記憶體晶胞均包括有複數個記憶體晶胞(1)；複數個控制電路(2)，每一列記憶體晶胞設置一個控制電路(2)；複數個預充電電路(3)，每一行記憶體晶胞設置一個預充電電路(3)；一待機啟動電路(4)，該待機啟動電路(4)係促使雙埠SRAM快速進入待機模式，以有效提高雙埠SRAM之待機效能；複數 個高電壓位準控制電路(5)，每一列記憶體晶胞設置一個高電壓位準控制電路(5)，以在讀取邏輯0時減少讀取路徑之電阻從而提高讀取速度；複數個寫入用字元線控制電路(6)，每一列記憶體晶胞設置一個寫入用字元線控制電路(6)，以在由邏輯0寫入邏輯1或由邏輯1寫入邏輯0時，於對應寫入用字元線(WWL)致能的第一階段，將對應寫入用字元線控制信號(WWLC)設定成較電源供應電壓(VDD)還高之第二高電源供應電壓(VDDH2)，以有效提高寫入速度；複數個讀取用字元線控制電路(7)，每一列記憶體晶胞設置一個讀取用字元線控制電路(7)，以在讀取邏輯0時，於對應讀取用用字元線(RWL)致能的第一階段，將對應讀取用字元線控制信號(RWLC)設定成較電源供應電壓(VDD)還高之第二高電源供應電壓(VDDH2)，以進一步減少讀取路徑之電阻，並加速讀取用位元線(RWL)上之電荷的放電，從而有效提高讀取速度；以及複數個寫入驅動電路(8)，每一行記憶體晶胞設置一個寫入驅動電路(8)，以在寫入邏輯0之第一階段將低於接地電壓之電壓位準施加至寫入用位元線(WBL)，以加速寫入邏輯0之速度，而於寫入邏輯1時則將高於電源供應電壓(VDD)之第三高電源供應電壓(VDDH3)的位準加至該寫入用位元線(WBL)，以加速寫入邏輯1之速度。 According to the above-mentioned main purpose, the present invention proposes a dual-port static random access memory, which mainly includes a memory array composed of a plurality of rows of memory cell and a plurality of rows of memory cell, each A row of memory cell and each row of memory cell includes a plurality of memory cell (1); a plurality of control circuits (2), each column of memory cell is provided with a control circuit (2); a plurality of presets Charge circuit (3), each row of memory cell is equipped with a pre-charge circuit (3); a standby startup circuit (4), the standby startup circuit (4) is to prompt the dual-port SRAM to quickly enter the standby mode to effectively improve the dual Standby performance of port SRAM; multiple high-voltage level control circuits (5), each row of memory cell is equipped with a high-voltage level control circuit (5) to reduce the resistance of the read path when reading logic 0 Improve the reading speed; a plurality of word line control circuits for writing (6), each column of memory cell is provided with a word line control circuit (6) for writing, in order to write logic 1 or logic 0 When logic 1 is written to logic 0, in the first phase of enabling the corresponding write word line (WWL), set the corresponding write word line control signal (WWLC) to be lower than the power supply voltage (V DD ) The second highest power supply voltage (V DDH2 ) to effectively increase the writing speed; multiple read word line control circuits (7), each row of memory cell sets a read word line control circuit (7) When reading logic 0, set the corresponding read word line control signal (RWLC) to be higher than the power supply voltage in the first phase of enabling the corresponding read word line (RWL) (V DD ) The second highest power supply voltage (V DDH2 ) is also high to further reduce the resistance of the read path and accelerate the discharge of the charge on the read bit line (RWL), thereby effectively increasing the read speed ; And a plurality of write drive circuits (8), each row of memory cell is provided with a write drive circuit (8) to apply a voltage level lower than the ground voltage to the write during the first stage of writing logic 0 Use bit line (WBL) to accelerate the speed of writing logic 0, and when writing logic 1, it will be higher than the third highest power supply voltage (V DDH3 ) level of the power supply voltage (V DD ) Add to the write bit line (WBL) to speed up the write logic 1 speed.

為了便於說明起見，第6圖所示之雙埠靜態隨機存取記憶體僅以一個記憶體晶胞(1)、一條寫入用字元線(WWL)、一條寫入用位元線(WBL)、一條讀取用字元線(RWL)、一條讀取用位元線(RBL)、一控制電路(2)、一預充電電路(3)、一待機啟動電路(4)、一高電壓位準控制電路(5)、一寫入用字元線控制電路(6)、一讀取用字元線控制電 路(7)以及一寫入驅動電路(8)做為實施例來說明。該記憶體晶胞(1)係包括一第一反相器(由一第一PMOS電晶體P11與一第一NMOS電晶體M11所組成)、一第二反相器(由一第二PMOS電晶體P12與一第二NMOS電晶體M12所組成)、一第三NMOS電晶體(M13)、一第一讀取用電晶體(M14)以及一第二讀取用電晶體(M15)，其中，該第一反相器及該第二反相器係呈交互耦合連接，亦即該第一反相器之輸出(即節點A)係連接該第二反相器之輸入，而該第二反相器之輸出(即節點B)則連接該第一反相器之輸入，並且該第一反相器之輸出(節點A)係用於儲存SRAM晶胞之資料，而該第二反相器之輸出(節點B)則用於儲存SRAM晶胞之反相資料。 For ease of description, the dual-port static random access memory shown in Figure 6 only uses one memory cell (1), one write word line (WWL), and one write bit line ( WBL), a word line for reading (RWL), a bit line for reading (RBL), a control circuit (2), a precharge circuit (3), a standby startup circuit (4), a high Voltage level control circuit (5), a word line control circuit for writing (6), a word line control circuit for reading The circuit (7) and a write drive circuit (8) are described as embodiments. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor) (P12 and a second NMOS transistor M12), a third NMOS transistor (M13), a first reading transistor (M14) and a second reading transistor (M15), among which, The first inverter and the second inverter are mutually coupled, that is, the output of the first inverter (ie node A) is connected to the input of the second inverter, and the second inverter The output of the phaser (ie node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, and the second inverter The output (node B) is used to store the inverted data of the SRAM cell.

該記憶體晶胞(1)之該第一反相器(由該第一PMOS電晶體P11與該第一NMOS電晶體M11所組成)係連接在一電源供應電壓(VDD)與一第一低電壓節點(VL1)之間，該第二反相器(由該第二PMOS電晶體P12與該第二NMOS電晶體M12所組成)係連接在一高電壓節點(VH)與一第二低電壓節點(VL2)之間，該第一讀取用電晶體(M14)之源極、閘極與汲極係分別連接至該第二讀取用電晶體(M15)之汲極、該讀取用字元線(RWL)與該讀取用位元線(RBL)，而該第二讀取用電晶體(M15)之源極、閘極與汲極則分別連接至該第二低電壓節點(VL2)、該第二反相器之輸出(即節點B)與該第一讀取用電晶體(M14)之源極。 The first inverter of the memory cell (1) (composed of the first PMOS transistor P11 and the first NMOS transistor M11) is connected to a power supply voltage (V DD ) and a first Between the low voltage node (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected to a high voltage node (VH) and a second low Between the voltage node (VL2), the source, gate, and drain of the first read transistor (M14) are connected to the drain and drain of the second read transistor (M15). Use the word line (RWL) and the read bit line (RBL), and the source, gate and drain of the second read transistor (M15) are respectively connected to the second low voltage node (VL2), the output of the second inverter (ie node B) and the source of the first read transistor (M14).

請再參考第6圖，該控制電路(2)係由一第四NMOS電晶體(M21)、一第五NMOS電晶體(M22)、一第六NMOS電晶體(M23)、一第七NMOS電晶體(M24)、一第八NMOS電晶體(M25)、一第九NMOS電晶體(M26)、一第十NMOS電晶體(M27)、一第三PMOS電晶體(P21)、 一讀取控制信號(RC)、一第三反相器(INV3)、一第一延遲電路(D1)、一加速讀取電壓(RGND)、一寫入控制信號(WC)、一待機模式控制信號(S)以及一反相待機模式控制信號(/S)所組成。該第四NMOS電晶體(M21)之源極、閘極與汲極係分別連接至接地電壓、該反相待機模式控制信號(/S)與該第二低電壓節點(VL2)；該第五NMOS電晶體(M22)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該待機模式控制信號(S)與該第二低電壓節點(VL2)；該第六NMOS電晶體(M23)之源極係連接至接地電壓，而閘極與汲極連接在一起並連接至該第一低電壓節點(VL1)；該第七NMOS電晶體(M24)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(M25)之汲極、該讀取控制信號(RC)與該第二低電壓節點(VL2)；該第八NMOS電晶體(M25)之源極、閘極與汲極係分別連接至該加速讀取電壓(RGND)、該第一延遲電路(D1)之輸出與該第七NMOS電晶體(M24)之源極；該第一延遲電路(D1)係連接在該第三反相器(INV3)之輸出與該第八NMOS電晶體(M25)之該閘極之間；該第三反相器(INV3)之輸入係供接收該讀取控制信號(RC)，而輸出則連接至該第一延遲電路(D1)之輸入；該第九NMOS電晶體(M26)之源極、閘極與汲極係分別連接至接地電壓、該第十NMOS電晶體(M27)之汲極與該第一低電壓節點(VL1)；該第十NMOS電晶體(M27)之源極、閘極與汲極係分別連接至該接地電壓、該寫入控制信號(WC)與該第九NMOS電晶體(M26)之閘極；而該第三PMOS電晶體(P21)之源極、閘極與汲極係分別連接至該反相待機模式控制信號(/S)、該寫入控制信號(WC)與該第十NMOS電晶體(M27)之汲極。其中，該反相待機模式控 制信號(/S)係由該待機模式控制信號(S)經一反相器而獲得。 Please refer to Figure 6 again. The control circuit (2) consists of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), A read control signal (RC), a third inverter (INV3), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), a standby mode control Signal (S) and an inverted standby mode control signal (/S). The source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to the ground voltage, the inverted standby mode control signal (/S) and the second low voltage node (VL2); the fifth The source, gate and drain of the NMOS transistor (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2); The source of the six NMOS transistor (M23) is connected to the ground voltage, while the gate and drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) , The gate and the drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); the eighth NMOS transistor (M25) The source, gate and drain of) are respectively connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first The delay circuit (D1) is connected between the output of the third inverter (INV3) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV3) is for receiving The read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the source, gate and drain of the ninth NMOS transistor (M26) are connected to ground voltage, The drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the source, gate and drain of the tenth NMOS transistor (M27) are connected to the ground voltage and the Write control signal (WC) and the gate of the ninth NMOS transistor (M26); and the source, gate, and drain of the third PMOS transistor (P21) are respectively connected to the inverted standby mode control Signal (/S), the write control signal (WC) and the drain of the tenth NMOS transistor (M27). Among them, the inverted standby mode control The control signal (/S) is obtained from the standby mode control signal (S) through an inverter.

其中，該第三PMOS電晶體(P21)之汲極、該第十NMOS電晶體(M27)之汲極及該第九NMOS電晶體(M26)之閘極係連接在一起並形成一節點(C)，當該寫入控制信號(WC)為邏輯低位準時，該節點(C)之電壓位準係為該反相待機模式控制信號(/S)之邏輯電壓位準，而當該寫入控制信號(WC)為邏輯高位準時，該節點(C)之電壓位準係為該接地電壓，藉此以穩定地完成寫入操作(由於寫入操作期間該節點C之電壓位準恆為該接地電壓)。 Wherein, the drain of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together to form a node (C ), when the write control signal (WC) is at a logic low level, the voltage level of the node (C) is the logic voltage level of the inverted standby mode control signal (/S), and when the write control When the signal (WC) is at a logic high level, the voltage level of the node (C) is the ground voltage, thereby stably completing the write operation (because the voltage level of the node C during the write operation is always the ground voltage Voltage).

該控制電路(2)係設計成可因應不同操作模式而控制該第一低電壓節點(VL1)與該第二低電壓節點(VL2)之電壓位準，於寫入模式時，將選定晶胞中較接近該寫入用位元線(WBL)之驅動電晶體(即該第一NMOS電晶體M11)的源極電壓(即該第一低電壓節點VL1)設定成較接地電壓為高之一預定電壓(即該第六NMOS電晶體(M23)之閘源極電壓VGS(M23))且將選定晶胞中另一驅動電晶體(即該第二NMOS電晶體M12)的源極電壓(即該第二低電壓節點VL2)設定成接地電壓，以便防止寫入邏輯1困難之問題。 The control circuit (2) is designed to control the voltage levels of the first low voltage node (VL1) and the second low voltage node (VL2) in response to different operating modes. In the write mode, the unit cell is selected The source voltage (that is, the first low voltage node VL1) of the driving transistor (that is, the first NMOS transistor M11) closer to the write bit line (WBL) is set to be one higher than the ground voltage A predetermined voltage (i.e. the gate-source voltage V GS(M23) of the sixth NMOS transistor (M23)) and the source voltage (i.e. the second NMOS transistor M12) of another driving transistor in the unit cell ( That is, the second low voltage node VL2) is set to a ground voltage to prevent the problem of difficulty in writing logic 1.

於讀取模式之第一階段時，將選定晶胞中較接近讀取用位元線(RBL)之驅動電晶體(即該第二NMOS電晶體M12)的源極電壓(即該第二低電壓節點VL2)設定成呈較接地電壓為低之電壓，該較接地電壓為低之該第二低電壓節點(VL2)可有效提高讀取速度，而於讀取模式之第二階段時，將選定晶胞中較接近讀取用位元線(RBL)之驅動電晶體(即該第二NMOS電晶體M12)的源極電壓設定回接地電壓，以便減少無謂的功率消 耗，其中該讀取模式之該第二階段與該第一階段相隔之時間，係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算，並至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間，其值可藉由該第三反相器(INV3)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。 In the first stage of the read mode, select the source voltage (ie, the second low) of the drive transistor (ie the second NMOS transistor M12) that is closer to the read bit line (RBL) in the selected cell The voltage node VL2) is set to have a lower voltage than the ground voltage. The second low voltage node (VL2), which is lower than the ground voltage, can effectively increase the reading speed. In the second stage of the reading mode, the The source voltage of the driving transistor (that is, the second NMOS transistor M12) closer to the read bit line (RBL) in the selected unit cell is set back to the ground voltage in order to reduce unnecessary power consumption. The time between the second phase and the first phase of the read mode is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level and reaches the eighth NMOS transistor The time until the gate voltage of (M25) is sufficient to turn off the eighth NMOS transistor (M25), its value can be determined by the falling delay time of the third inverter (INV3) and the first delay circuit (D1) Provide the delay time to adjust.

於待機模式時，將所有記憶體晶胞中之驅動電晶體的源極電壓設定成較接地電壓為高之該預定電壓，以便降低漏電流；而於保持模式時則將記憶體晶胞中之驅動電晶體的源極電壓設定成接地電壓，以便維持原來之保持特性，該第一低電壓節點(VL1)及該第二低電壓節點VL2於寫入模式、讀取模式、待機模式與保持模式之詳細工作電壓位準如下述表1所示。 In the standby mode, the source voltage of the driving transistors in all the memory cells is set to a predetermined voltage higher than the ground voltage in order to reduce the leakage current; and in the hold mode, the source voltage of the driving transistors in the memory cell The source voltage of the driving transistor is set to the ground voltage to maintain the original retention characteristics. The first low voltage node (VL1) and the second low voltage node VL2 are in write mode, read mode, standby mode and hold mode The detailed operating voltage levels are shown in Table 1 below.

Figure 108138325-A0101-12-0011-1
Figure 108138325-A0101-12-0011-1

表1中之該寫入控制信號(WC)為一寫入致能信號(Write Enable，簡稱WE)與對應之寫入用字元線(WWL)信號的及閘(AND gate) 運算結果，此時僅於該寫入致能信號(WE)與該對應之寫入用字元線(WWL)信號均為邏輯高位準時，該寫入控制信號(WC)方為邏輯高位準；該讀取控制信號(RC)為一讀取致能信號(Read Enable，簡稱RE)與對應之讀取用字元線(RWL)信號的及閘運算結果。在此值得注意的是，對於非選定字元線及非選定位元線係設定為浮接(floating)狀態，而對於非讀取模式期間之該讀取控制信號(RC)係設定為該加速讀取電壓(RGND)之位準，以防止該第七NMOS電晶體(M24)之漏電流。 The write control signal (WC) in Table 1 is an AND gate of a write enable signal (Write Enable, WE for short) and the corresponding write word line (WWL) signal As a result of the operation, at this time, only when the write enable signal (WE) and the corresponding write word line (WWL) signal are both at a high logic level, the write control signal (WC) is at a high logic level; The read control signal (RC) is a sum operation result of a read enable signal (Read Enable, RE for short) and a corresponding read word line (RWL) signal. It is worth noting here that the non-selected character line and the non-selected positioning element line are set to the floating state, and the read control signal (RC) during the non-read mode is set to the acceleration Read the voltage (RGND) level to prevent leakage current of the seventh NMOS transistor (M24).

請參考第6圖，該預充電電路(3)係由一第四PMOS電晶體(P31)以及一預充電信號(P)所組成，該第四PMOS電晶體(P31)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該預充電信號(P)與相對應之讀取用位元線(RBL)，以便於預充電期間，藉由邏輯低位準之該預充電信號(P)，以將相對應之讀取用位元線(RBL)預充電至該電源供應電壓(VDD)之位準。 Please refer to Figure 6, the precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P). The source and gate of the fourth PMOS transistor (P31) And the drain are respectively connected to the power supply voltage (V DD ), the precharge signal (P) and the corresponding read bit line (RBL), so that during the precharge period, the logic low level of the The precharge signal (P) is used to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V DD ).

請再參考第6圖，該待機啟動電路(4)係由一第五PMOS電晶體(P41)、一第十一NMOS電晶體(M41)、一第二延遲電路(D2)以及該反相待機模式控制信號(/S)所組成。該第五PMOS電晶體(P41)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該反相待機模式控制信號(/S)與該第十一NMOS電晶體(M41)之汲極；該第十一NMOS電晶體(M41)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該第二延遲電路(D2)之輸出與該第五PMOS電晶體(P41)之汲極；該第二延遲電路(D2)之輸入連接至該反相待機模式控制信號(/S)，而該第二延遲電路(D2)之輸出則連接至該第十一NMOS電晶體(M41)之閘極。 Please refer to Figure 6 again, the standby startup circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2) and the inverting standby circuit Mode control signal (/S) composed. The source, gate, and drain of the fifth PMOS transistor (P41) are connected to the power supply voltage (V DD ), the inverted standby mode control signal (/S) and the eleventh NMOS transistor, respectively The drain of (M41); the source, gate and drain of the eleventh NMOS transistor (M41) are respectively connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) And the drain of the fifth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and the output of the second delay circuit (D2) is Connect to the gate of the eleventh NMOS transistor (M41).

請再參考第6圖，該高電壓位準控制電路(5)係由一第六PMOS電晶體(P51)、一第七PMOS電晶體(P52)以及一第四反相器(INV4)所組成，其中該第六PMOS電晶體(P51)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該讀取控制信號(RC)與該高電壓節點(VH)，該第七PMOS電晶體(P52)之源極、閘極與汲極係分別連接至一第一高電源供應電壓(VDDH1)、該第四反相器(INV4)之輸出與該高電壓節點(VH)，而該第四反相器(INV4)之輸入係供接收該讀取控制信號(RC)，而輸出則連接至該第七PMOS電晶體(P52)之汲極。在此值得注意的是，該第一反相器係連接在該電源供應電壓(VDD)與該第一低電壓節點(VL1)之間，而該第二反相器則連接在該高電壓節點(VH)與該第二低電壓節點(VL2)之間。 Please refer to Figure 6 again, the high voltage level control circuit (5) is composed of a sixth PMOS transistor (P51), a seventh PMOS transistor (P52) and a fourth inverter (INV4) , Wherein the source, gate and drain of the sixth PMOS transistor (P51) are respectively connected to the power supply voltage (V DD ), the read control signal (RC) and the high voltage node (VH), The source, gate, and drain of the seventh PMOS transistor (P52) are respectively connected to a first high power supply voltage (V DDH1 ), the output of the fourth inverter (INV4), and the high voltage node (VH), and the input of the fourth inverter (INV4) is for receiving the read control signal (RC), and the output is connected to the drain of the seventh PMOS transistor (P52). It is worth noting here that the first inverter is connected between the power supply voltage (V DD ) and the first low voltage node (VL1), and the second inverter is connected to the high voltage Between the node (VH) and the second low voltage node (VL2).

請再參考第6圖，該寫入用字元線控制電路(6)係由一第八PMOS電晶體(P61)、一第九PMOS電晶體(P62)、一第十PMOS電晶體(P63)、一第十二NMOS電晶體(M61)、一第五反相器(INV5)、一第六反相器(INV6)、一第二高電源供應電壓(VDDH2)、一寫入用字元線(WWL)以及一寫入用字元線控制信號(WWLC)所組成。該第八PMOS電晶體(P61)之源極、閘極與汲極係分別連接至該第二高電源供應電壓(VDDH2)、該第五反相器(INV5)之輸出與該第九PMOS電晶體(P62)之源極；該第九PMOS電晶體(P62)之源極、閘極與汲極係分別連接至該第八PMOS電晶體(P61)之汲極、該第六反相器(INV6)之輸出與該寫入用字元線控制信號(WWLC)；該第十PMOS電晶體(P63)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該第五反相器(INV5)之輸出與該寫入用字 元線控制信號(WWLC)；該第十二NMOS電晶體(M61)之源極、閘極與汲極係分別連接至該接地電壓、該第五反相器(INV5)之輸出與該寫入用字元線控制信號(WWLC)；該第五反相器(INV5)之輸入係供接收該寫入用字元線(WWL)，而該第六反相器(INV6)之輸入則與該第五反相器(INV5)之輸出連接。 Please refer to Figure 6 again, the word line control circuit for writing (6) consists of an eighth PMOS transistor (P61), a ninth PMOS transistor (P62), and a tenth PMOS transistor (P63) , A twelfth NMOS transistor (M61), a fifth inverter (INV5), a sixth inverter (INV6), a second high power supply voltage (V DDH2 ), a writing character Line (WWL) and a word line control signal (WWLC) for writing. The source, gate and drain of the eighth PMOS transistor (P61) are respectively connected to the second high power supply voltage (V DDH2 ), the output of the fifth inverter (INV5) and the ninth PMOS The source of the transistor (P62); the source, gate and drain of the ninth PMOS transistor (P62) are respectively connected to the drain of the eighth PMOS transistor (P61) and the sixth inverter The output of (INV6) and the word line control signal (WWLC) for writing; the source, gate and drain of the tenth PMOS transistor (P63) are respectively connected to the power supply voltage (V DD ), The output of the fifth inverter (INV5) and the word line control signal (WWLC) for writing; the source, gate and drain of the twelfth NMOS transistor (M61) are respectively connected to the ground Voltage, the output of the fifth inverter (INV5) and the word line control signal (WWLC) for writing; the input of the fifth inverter (INV5) is for receiving the word line for writing (WWL) ), and the input of the sixth inverter (INV6) is connected to the output of the fifth inverter (INV5).

該寫入用字元線控制電路(6)於致能時係採用二階段操作以有效解決10奈米以下SRAM操作電壓降為0.9以下時易造成寫入時間無法滿足規範之問題，於該寫入用字元線(WWL)致能的第一階段，將該寫入用字元線控制信號(WWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2)，以有效提高寫入速度，而於該第一階段後之第二階段時，則將該寫入用字元線控制信號(WWLC)拉低回該電源供應電壓(VDD)，以減緩寫干擾入；其中，該寫入用字元線控制電路(6)之該第二階段與該第一階段相隔之時間，係等於該第五反相器(INV5)之輸出足以導通該第八PMOS電晶體(P61)之時間起算，並至該第六反相器(INV6)之輸出足以關閉該第九PMOS電晶體(P62)為止之時間，其值可藉由該第六反相器(INV6)之上升延遲時間來調整。 The word line control circuit (6) for writing uses a two-stage operation when enabled to effectively solve the problem that the writing time cannot meet the specification when the operating voltage of SRAM below 10nm drops below 0.9. In the first stage of enabling the word line (WWL) for writing, the word line control signal for writing (WWLC) is set to the second high power supply voltage (V DD ) higher than the power supply voltage (V DD ) V DDH2 ), in order to effectively increase the writing speed, and in the second stage after the first stage, the word line control signal (WWLC) for writing is pulled down back to the power supply voltage (V DD ), In order to slow down the write interference; wherein, the time between the second stage and the first stage of the word line control circuit (6) for writing is equal to the output of the fifth inverter (INV5) enough to turn on the Calculated from the time of the eighth PMOS transistor (P61) and the time until the output of the sixth inverter (INV6) is enough to turn off the ninth PMOS transistor (P62), its value can be determined by the sixth inverter The rise delay time of the inverter (INV6) is adjusted.

請再參考第6圖，該讀取用字元線控制電路(7)係由一第十一PMOS電晶體(P71)、一第十二PMOS電晶體(P72)、一第十三PMOS電晶體(P73)、一第十三NMOS電晶體(M71)、一第七反相器(INV7)、一第八反相器(INV8)、該第二高電源供應電壓(VDDH2)、一讀取用字元線(RWL)以及一讀取用字元線控制信號(RWLC)所組成。該第十一PMOS電晶體(P71)之源極、閘極與汲極係分別連接至該第二高電源供應電壓 (VDDH2)、該第七反相器(INV7)之輸出與該第十二PMOS電晶體(P72)之源極；該第十二PMOS電晶體(P72)之源極、閘極與汲極係分別連接至該該第十一PMOS電晶體(P71)之汲極、該第八反相器(INV8)之輸出與該讀取用字元線控制信號(RWLC)；第十三PMOS電晶體(P73)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該第七反相器(INV7)之輸出與該讀取用字元線控制信號(RWLC)；該第十三NMOS電晶體(M71)之源極、閘極與汲極係分別連接至該接地電壓、該第七反相器(INV7)之輸出與該讀取用字元線控制信號(RWLC)；該第七反相器(INV7)之輸入係供接收該讀取用字元線(RWL)，而該第八反相器(INV8)之輸入則與該第七反相器(INV7)之輸出連接。 Please refer to Figure 6 again, the read word line control circuit (7) is composed of an eleventh PMOS transistor (P71), a twelfth PMOS transistor (P72), and a thirteenth PMOS transistor (P73), a thirteenth NMOS transistor (M71), a seventh inverter (INV7), an eighth inverter (INV8), the second high power supply voltage (V DDH2 ), a read It is composed of a word line (RWL) and a word line control signal (RWLC) for reading. The source, gate and drain of the eleventh PMOS transistor (P71) are respectively connected to the second high power supply voltage (V DDH2 ), the output of the seventh inverter (INV7) and the tenth The source of two PMOS transistors (P72); the source, gate and drain of the twelfth PMOS transistor (P72) are connected to the drain, the drain of the eleventh PMOS transistor (P71), respectively The output of the eighth inverter (INV8) and the read word line control signal (RWLC); the source, gate and drain of the thirteenth PMOS transistor (P73) are respectively connected to the power supply voltage (V DD ), the output of the seventh inverter (INV7) and the word line control signal (RWLC) for reading; the source, gate and drain system of the thirteenth NMOS transistor (M71) Connected to the ground voltage, the output of the seventh inverter (INV7) and the word line control signal (RWLC) for reading respectively; the input of the seventh inverter (INV7) is for receiving the reading Word line (RWL), and the input of the eighth inverter (INV8) is connected to the output of the seventh inverter (INV7).

該讀取用字元線控制電路(7)於致能時係採用二階段操作，於該讀取用字元線(RWL)致能的第一階段，將該讀取用字元線控制信號(RWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2)，以有效提高讀取速度，而於該第一階段後之第二階段時，則將該讀取用字元線控制信號(RWLC)拉低回該電源供應電壓(VDD)，以減緩讀取擾入；其中，該讀取用字元線控制電路(7)之該第二階段與該第一階段相隔之時間，係等於該第七反相器(INV7)之輸出足以導通該第十一PMOS電晶體(P71)之時間起算，並至該第八反相器(INV8)之輸出足以關閉該第十二PMOS電晶體(P72)為止之時間，其值可藉由該第八反相器(INV8)之上升延遲時間來調整。 The read word line control circuit (7) adopts a two-stage operation when it is enabled. In the first stage when the read word line (RWL) is enabled, the read word line control signal (RWLC) is set to the second high power supply voltage (V DDH2 ) higher than the power supply voltage (V DD ) to effectively increase the reading speed, and in the second stage after the first stage, The read word line control signal (RWLC) is pulled back to the power supply voltage (V DD ) to slow the read disturbance; wherein, the second read word line control circuit (7) The time between the phase and the first phase is equal to the time required for the output of the seventh inverter (INV7) to turn on the eleventh PMOS transistor (P71), and to the eighth inverter (INV8) The time until the output is sufficient to turn off the twelfth PMOS transistor (P72), its value can be adjusted by the rise delay time of the eighth inverter (INV8).

請再參考第6圖，該寫入驅動電路(8)係由一第十四PMOS電晶體(P81)、一第十四NMOS電晶體(M81)、一第十五NMOS電晶體 (M82)、一第十六NMOS電晶體(M83)、一第九反相器(INV9)、一第十反相器(INV10)、一電容器(Cap)、一輸入資料(Din)、一行解碼器輸出信號(Y)、一第三延遲電路(D3)、一第四延遲電路(D4)以及一第三高電源供應電壓(VDDH3)所組成，其中該第十四PMOS電晶體(P81)之源極、閘極與汲極係分別連接至該第三高電源供應電壓(VDDH3)、該第九反相器(INV9)之輸出與該第十四NMOS電晶體(M81)之汲極，該第十四NMOS電晶體(M81)之源極、閘極與汲極係分別連接至該第十六NMOS電晶體(M83)之汲極、該第九反相器(INV9)之輸出與該第十四PMOS電晶體(P81)之汲極，該第十五NMOS電晶體(M82)之源極、閘極與汲極係分別連接至該接地電壓、該第三延遲電路(D3)之輸出與該第十四PMOS電晶體(P81)之汲極，該第十六NMOS電晶體(M83)之源極、閘極與汲極係分別連接至該接地電壓、該第十反相器(INV10)之輸出與該第十四NMOS電晶體(M81)之源極，該第九反相器(INV9)之輸入係供接收該輸入資料(Din)，而輸出則連接至該第十四PMOS電晶體(P81)之閘極、該第十四NMOS電晶體(M81)之閘極以及該第三延遲電路(D3)之輸入，該第十反相器(INV10)之輸入係供接收該行解碼器輸出信號(Y)，而輸出則連接至該第四延遲電路(D4)之輸入以及該第十六NMOS電晶體(M83)之閘極，該電容器(Cap)之一端係連接至該第四延遲電路(D4)之輸出，而該電容器(Cap)之另一端則連接至該第十四NMOS電晶體(M81)之源極以及該第十六NMOS電晶體(M83)之汲極，其中，該第十四PMOS電晶體(P81)之汲極、該第十四NMOS電晶體(M81)之汲極與該第十五NMOS電晶體(M82)之汲極係共同連接至該寫入用位元線(WBL)，該寫入用位元 線(WBL)於寫入邏輯0之第一階段係設計成低於於該接地電壓之電壓位準，以加速寫入邏輯0之速度，而於寫入邏輯1時則設計成高於該電源供應電壓(VDD)之該第三高電源供應電壓(VDDH3)的位準，以加速寫入邏輯1之速度。 Please refer to Figure 6 again. The write drive circuit (8) consists of a fourteenth PMOS transistor (P81), a fourteenth NMOS transistor (M81), a fifteenth NMOS transistor (M82), A sixteenth NMOS transistor (M83), a ninth inverter (INV9), a tenth inverter (INV10), a capacitor (Cap), an input data (Din), a row of decoder output signals ( Y), a third delay circuit (D3), a fourth delay circuit (D4), and a third high power supply voltage (V DDH3 ), wherein the source of the fourteenth PMOS transistor (P81), The gate and drain are respectively connected to the third high power supply voltage (V DDH3 ), the output of the ninth inverter (INV9) and the drain of the fourteenth NMOS transistor (M81), the tenth The source, gate and drain of the four NMOS transistors (M81) are respectively connected to the drain of the sixteenth NMOS transistor (M83), the output of the ninth inverter (INV9) and the fourteenth The drain of the PMOS transistor (P81), the source, gate and drain of the fifteenth NMOS transistor (M82) are respectively connected to the ground voltage, the output of the third delay circuit (D3) and the first The drain of the fourteenth PMOS transistor (P81), the source, gate and drain of the sixteenth NMOS transistor (M83) are connected to the ground voltage and the output of the tenth inverter (INV10) respectively With the source of the fourteenth NMOS transistor (M81), the input of the ninth inverter (INV9) is for receiving the input data (Din), and the output is connected to the fourteenth PMOS transistor (P81) ), the gate of the fourteenth NMOS transistor (M81) and the input of the third delay circuit (D3). The input of the tenth inverter (INV10) is for receiving the output signal of the row decoder (Y), and the output is connected to the input of the fourth delay circuit (D4) and the gate of the sixteenth NMOS transistor (M83). One end of the capacitor (Cap) is connected to the fourth delay circuit ( D4), and the other end of the capacitor (Cap) is connected to the source of the fourteenth NMOS transistor (M81) and the drain of the sixteenth NMOS transistor (M83), where the tenth The drain of the four PMOS transistors (P81), the drain of the fourteenth NMOS transistor (M81), and the drain of the fifteenth NMOS transistor (M82) are connected to the write bit line ( WBL), the write bit line (WBL) in the first stage of writing logic 0 is designed to be lower than the voltage level of the ground voltage to accelerate the speed of writing logic 0, and in writing logic When 1, it is designed to be higher than the third highest power supply voltage (V DDH3 ) of the power supply voltage (V DD ) to accelerate the writing speed of logic 1.

該寫入驅動電路(8)致能與否係由該行解碼器輸出信號(Y)之邏輯位準決定，當該行解碼器輸出信號(Y)為邏輯低位準時，該寫入驅動電路(8)為非致能狀態，而當該行解碼器輸出信號(Y)為邏輯高位準時，該寫入驅動電路(8)處於致能狀態。當該行解碼器輸出信號(Y)為邏輯低位準時，該第十反相器(INV10)之輸出為邏輯高位準，一方面導通該第十六NMOS電晶體(M83)，另一方面經過該第四延遲電路(D4)所提供之延遲時間後對該電容器(Cap)之一端充電，由於導通的該第十六NMOS電晶體(M83)，使得該電容器(Cap)之另一端為該接地電壓，而該電容器(Cap)之一端則會因電容器(Cap)的充電而保持該電源供應電壓(VDD)之電壓位準。 Whether the write drive circuit (8) is enabled or not is determined by the logic level of the row decoder output signal (Y). When the row decoder output signal (Y) is at a logic low level, the write drive circuit ( 8) is in the disabled state, and when the row decoder output signal (Y) is at a logic high level, the write drive circuit (8) is in the enabled state. When the row decoder output signal (Y) is at a logic low level, the output of the tenth inverter (INV10) is at a logic high level. On the one hand, the sixteenth NMOS transistor (M83) is turned on, and on the other hand, it passes through the After the delay time provided by the fourth delay circuit (D4), one end of the capacitor (Cap) is charged. Because the 16th NMOS transistor (M83) is turned on, the other end of the capacitor (Cap) is the ground voltage , And one end of the capacitor (Cap) will maintain the voltage level of the power supply voltage (V DD ) due to the charging of the capacitor (Cap).

該寫入驅動電路(8)於寫入邏輯0之致能狀態時係採用二階段操作，於該寫入驅動電路(8)致能的第一階段，邏輯高位準之該行解碼器輸出信號(Y)，使得該第十反相器(INV10)之輸出為邏輯低位準，一方面使該第十六NMOS電晶體(M83)為截止(OFF)狀態，另一方面經過該第四延遲電路(D4)所提供之延遲時間後對該電容器(Cap)之一端快速放電至該接地電壓，由於此時該輸入資料(Din)為邏輯低位準，使得該第九反相器(INV9)之輸出為邏輯高位準，於是導通該第十四NMOS電晶體(M81)，並使該第十四PMOS電晶體(P81)為截止(OFF)狀態，因此該寫 入用位元線(WBL)之電壓位準於該寫入驅動電路(8)寫入邏輯0之第一階段時滿足方程式(3)： The write drive circuit (8) adopts a two-stage operation when writing the enable state of logic 0. In the first stage of the write drive circuit (8) is enabled, the row decoder output signal at a logic high level (Y), making the output of the tenth inverter (INV10) a logic low level, on the one hand, making the sixteenth NMOS transistor (M83) in an OFF state, on the other hand, passing through the fourth delay circuit After the delay time provided by (D4), one end of the capacitor (Cap) is quickly discharged to the ground voltage. Because the input data (Din) is at a logic low level at this time, the output of the ninth inverter (INV9) Is a logic high level, so the fourteenth NMOS transistor (M81) is turned on, and the fourteenth PMOS transistor (P81) is turned off (OFF), so the write The voltage level of the input bit line (WBL) satisfies the equation (3) when the write drive circuit (8) writes the first stage of logic 0:

VWBL1=-VDD×Cap/(Cap+CWBL) (3) V WBL1 =-V DD ×Cap/(Cap+C WBL ) (3)

其中，VWBL1表示該寫入用位元線(WBL)於寫入邏輯0之第一階段的電壓位準，VWBL1的絕對值設計為小於該第三NMOS電晶體(M13)之臨界電壓，例如可設計為-100mV、-150mV或-200mV，VDD為該電源供應電壓(VDD)之電壓位準，而Cap與CWBL分別表示該該電容器(Cap)之電容值與該寫入用位元線(WBL)之寄生電容值。 Wherein, V WBL1 represents the voltage level of the writing bit line (WBL) in the first stage of writing logic 0, and the absolute value of V WBL1 is designed to be smaller than the threshold voltage of the third NMOS transistor (M13), For example, it can be designed to be -100mV, -150mV or -200mV, V DD is the voltage level of the power supply voltage (V DD ), and Cap and C WBL represent the capacitance value of the capacitor (Cap) and the writing The parasitic capacitance value of the bit line (WBL).

當邏輯低位準之該輸入資料(Din)經過該該第九反相器(INV9)以及該第三延遲電路(D3)所提供之延遲時間後，該寫入驅動電路(8)進入致能的第二階段，此時由於該第十五NMOS電晶體(M82)為導通狀態，使得該寫入用位元線(WBL)之電壓位準於該寫入驅動電路(8)寫入邏輯0之第二階段時滿足方程式(4)： When the input data (Din) at the logic low level has passed the delay time provided by the ninth inverter (INV9) and the third delay circuit (D3), the write drive circuit (8) enters the enabling In the second stage, at this time, since the fifteenth NMOS transistor (M82) is turned on, the voltage level of the write bit line (WBL) is equal to that of the write logic 0 of the write drive circuit (8). In the second stage, equation (4) is satisfied:

VWBL2=0 (4) V WBL2 =0 (4)

茲說明第6圖之本發明較佳實施例的工作原理如下： The working principle of the preferred embodiment of the present invention shown in Figure 6 is described as follows:

(I)寫入模式(write mode) (I) write mode

於寫入操作開始前，該待機模式控制信號(S)與該寫入控制信號(WC)均為邏輯低位準，使得該第三PMOS電晶體(P21)導通(ON)，並使得該第十NMOS電晶體(M27)截止(OFF)，於是該第三PMOS電晶體(P21)之汲極呈邏輯高位準，該邏輯高位準之該第三PMOS電晶體(P21)之汲極會導通該第九NMOS電晶體(M26)，並使得該第一低電壓節點(VL1)呈 接地電壓。 Before the start of the write operation, the standby mode control signal (S) and the write control signal (WC) are both logic low levels, so that the third PMOS transistor (P21) is turned on (ON), and the tenth The NMOS transistor (M27) is turned off (OFF), so the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) at the logic high level will turn on the second Nine NMOS transistors (M26), and make the first low voltage node (VL1) present Ground voltage.

而於寫入操作期間內，該寫入控制信號(WC)為邏輯高位準，使得該第三PMOS電晶體(P21)截止，該第十NMOS電晶體(M27)導通，並使得該第三PMOS電晶體(P21)之汲極呈邏輯低位準，該邏輯低位準之該第三PMOS電晶體(P21)之汲極會使得該第九NMOS電晶體(M26)截止，並使得該第一低電壓節點(VL1)等於該第六NMOS電晶體(M23)之閘源極電壓VGS(M26)，藉此得以有效防止寫入邏輯1困難之問題。第7a圖所示為第6圖之本發明較佳實施例於寫入邏輯0期間之簡化電路圖，而第7b圖所示則為寫入邏輯1期間之簡化電路圖。 During the write operation period, the write control signal (WC) is at a logic high level, so that the third PMOS transistor (P21) is turned off, the tenth NMOS transistor (M27) is turned on, and the third PMOS transistor is turned on. The drain of the transistor (P21) is at a logic low level. The drain of the third PMOS transistor (P21) at the logic low level will turn off the ninth NMOS transistor (M26) and make the first low voltage The node (VL1) is equal to the gate-source voltage V GS (M26 ) of the sixth NMOS transistor (M23 ) , thereby effectively preventing the problem of difficulty in writing logic 1. FIG. 7a shows the simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during the logic 0 writing period, and FIG. 7b shows the simplified circuit diagram during the logic 1 writing period.

接下來依4種寫入狀態來說明第7a圖與第7b圖之本發明較佳實施例如何完成寫入邏輯0與寫入邏輯1動作。 Next, according to four write states, how the preferred embodiment of the present invention shown in FIG. 7a and FIG. 7b completes the write logic 0 and write logic 1 actions.

(一)節點A原本儲存邏輯0，而現在欲寫入邏輯0： (1) Node A originally stored logic 0, but now wants to write logic 0:

在寫入動作發生前(該寫入用字元線控制信號WWLC為接地電壓)，該第一NMOS電晶體(M11)為導通(ON)。因為該第一NMOS電晶體(M11)為ON，所以當寫入動作開始時，該寫入用字元線(WWL)由Low(接地電壓)轉High(電源供應電壓VDD)。當該寫入用字元線控制信號(WWLC)的電壓大於該第三NMOS電晶體(M13)(即存取電晶體)的臨界電壓時，該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON)，此時因為該寫入用位元線(WBL)於寫入邏輯0之第一階段係設計成低於於該接地電壓之電壓位準，而於寫入邏輯0之第二階段則拉回至該接地電壓，所以會將該節點A放電，而完成邏輯0的寫入動作，直到寫入週期結束。 Before the writing operation occurs (the word line control signal WWLC for writing is the ground voltage), the first NMOS transistor (M11) is turned on (ON). Because the first NMOS transistor (M11) is ON, when the writing operation starts, the writing word line (WWL) changes from Low (ground voltage) to High (power supply voltage V DD ). When the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, access transistor), the third NMOS transistor (M13) is turned off (OFF) ) Turns on (ON). At this time, because the writing bit line (WBL) is designed to be lower than the ground voltage in the first stage of writing logic 0, and writing logic 0 In the second stage, it is pulled back to the ground voltage, so the node A will be discharged to complete the logic 0 write operation until the write cycle ends.

(二)節點A原本儲存邏輯0，而現在欲寫入邏輯1： (2) Node A originally stored logic 0, but now it wants to write logic 1:

在寫入動作發生前(該寫入用字元線控制信號WWLC為接地電壓)，該第一NMOS電晶體(M11)為導通(ON)。在此值得注意的是，因為該第一NMOS電晶體(M11)為ON，所以當寫入動作開始時，該寫入用字元線控制信號(WWLC)由Low(接地電壓)轉High，該節點A的電壓會由於寄生電容耦合效應而跟隨該寫入用字元線控制信號(WWLC)的電壓呈現些微上升。當該寫入用字元線控制信號(WWLC)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時，該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON)，此時因為該寫入用位元線(WBL)為該第三高電源供應電壓(VDDH3)之電壓位準，並且因為該第一NMOS電晶體(M11)仍為ON且該節點B仍處於電壓位準為接近於該電源供應電壓(VDD)之電壓位準的初始狀態，所以該第一PMOS電晶體(P11)仍為截止(OFF)，而該節點A之寫入初始瞬間電壓(VAWI)滿足方程式(5)： Before the writing operation occurs (the word line control signal WWLC for writing is the ground voltage), the first NMOS transistor (M11) is turned on (ON). It is worth noting here that because the first NMOS transistor (M11) is ON, when the writing operation starts, the writing word line control signal (WWLC) turns from Low (ground voltage) to High. Due to the parasitic capacitive coupling effect, the voltage of the node A will follow the voltage of the word line control signal (WWLC) for writing to show a slight increase. When the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from off (OFF) to on (ON) , At this time, because the writing bit line (WBL) is the voltage level of the third high power supply voltage (V DDH3 ), and because the first NMOS transistor (M11) is still ON and the node B is still In the initial state where the voltage level is close to the voltage level of the power supply voltage (V DD ), the first PMOS transistor (P11) is still OFF, and the node A writes the initial instantaneous voltage (V AWI ) satisfies equation (5):

VAWI1=VDDH3×(RM11+RM23)/(RM13+RM11+RM23)>VTM12 (5)其中，VAWI1表示節點A寫入邏輯1之寫入初始瞬間電壓，RM13表示該第三NMOS電晶體(M13)之導通電阻，RM11表示該第一NMOS電晶體(M11)之導通電阻，RM23表示該第六NMOS電晶體(M23)之導通電阻，而VDDH3與VTM12分別表示該第三高電源供應電壓之電壓位準與該第二NMOS電晶體(M12)之臨界電壓。由於在該第一低電壓節點(VL1)處提供一等於該第六NMOS電晶體(M23)之閘-源極電壓VGS(M23)之電壓位準，因此可輕易地將節點A之電壓位準設定成比第4圖之習知5T靜態隨機存取記憶體晶胞之該 節點A之電壓位準還要高許多。該還要高許多之分壓電壓位準係足以使該第二NMOS電晶體(M12)導通，於是使得節點B放電至一較低電壓位準，該節點B之較低電壓位準會使得該第一NMOS電晶體(M11)之導通等效電阻(RM11)呈現較高的電阻值，該第一NMOS電晶體(M11)之該較高的電阻值會於該節點A獲得較高電壓位準，該節點A之較高電壓位準又會經由該第二反相器(由第二PMOS電晶體P12與第二NMOS電晶體M12所組成)，而使得該節點B呈現更低電壓位準，該節點B之更低電壓位準又會經由該第一反相器(由第一PMOS電晶體P11與第一NMOS電晶體M11所組成)，而使得該節點A獲得更高電壓位準，依此循環，即可將該節點A充電至該電源供應電壓(VDD)，而完成邏輯1的寫入動作。 V AWI1 =V DDH3 ×(R M11 +R M23 )/(R M13 +R M11 +R M23 )>V TM12 (5) Where, V AWI1 represents the initial instantaneous voltage of writing logic 1 to node A, R M13 Represents the on-resistance of the third NMOS transistor (M13), R M11 represents the on-resistance of the first NMOS transistor (M11), R M23 represents the on-resistance of the sixth NMOS transistor (M23), and V DDH3 and V TM12 respectively represents the voltage level of the third high power supply voltage and the threshold voltage of the second NMOS transistor (M12). Since a voltage level equal to the gate-source voltage V GS (M23) of the sixth NMOS transistor (M23) is provided at the first low voltage node (VL1), the voltage level of node A can be easily changed The standard is set to be much higher than the voltage level of the node A of the conventional 5T static random access memory cell in Fig. 4. The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), so that node B is discharged to a lower voltage level. The lower voltage level of node B will cause the The on-resistance (R M11 ) of the first NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A The higher voltage level of the node A will pass through the second inverter (consisting of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B presents a lower voltage level , The lower voltage level of the node B will pass through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level, According to this cycle, the node A can be charged to the power supply voltage (V DD ) to complete the logic 1 write operation.

其中，該第一低電壓節點(VL1)於節點A原本儲存邏輯0，而在寫入邏輯1之期間，係具有等於該第六NMOS電晶體(M23)之閘源極電壓VGS(M23)的電壓位準，而於寫入邏輯1後，又會因經由該第九NMOS電晶體(M26)放電而為接地電壓之位準。 Wherein, the first low voltage node (VL1) originally stores logic 0 at node A, and during the writing of logic 1, it has the gate-source voltage V GS (M23) of the sixth NMOS transistor (M23) After the logic 1 is written, it will be the ground voltage level due to the discharge through the ninth NMOS transistor (M26).

在此值得注意的是，本發明係藉由二階段的寫入用字元線控制電路(6)以有效解決10奈米以下SRAM操作電壓降為0.9V以下時易造成寫入時間無法滿足規範之問題，該寫入用字元線控制電路(6)於該寫入用字元線(WWL)致能的第一階段，將該寫入用字元線控制信號(WWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2)，由於在節點A原本儲存邏輯0而在寫入邏輯1初期，該第三NMOS電晶體(M13)係工作於飽和區，飽和區之電流係與閘-源極電壓VGS(M13)之電壓位準扣減其臨界電壓VTM13後之平方成正比例，因此將該寫入用字元線控制信 號(WWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2)的該第一階段期間，可有效加速寫入邏輯1之速度；此外，為了減緩寫入期間對於半選定晶胞的干擾現象，於該第一階段後之第二階段期間，則將該寫入用字元線控制信號(WWLC)拉低回該電源供應電壓(VDD)之電壓位準，其中，該寫入用字元線控制電路(6)之該第二階段與該第一階段相隔之時間，係等於該第五反相器(INV5)之輸出足以導通該第八PMOS電晶體(P61)之時間起算，並至該第六反相器(INV6)之輸出足以關閉該第九PMOS電晶體(P62)為止之時間，其值可藉由該第六反相器(INV6)之上升延遲時間來調整。 It is worth noting here that the present invention uses a two-stage writing word line control circuit (6) to effectively solve the problem that when the operating voltage of SRAM below 10nm drops below 0.9V, the writing time cannot meet the specification. The problem is that the writing word line control circuit (6) sets the writing word line control signal (WWLC) to be lower than the first stage of enabling the writing word line (WWL) The power supply voltage (V DD ) is still higher than the second highest power supply voltage (V DDH2 ). Since the node A originally stores logic 0 and in the initial stage of writing logic 1, the third NMOS transistor (M13) works at In the saturation area, the current in the saturation area is proportional to the square of the gate-source voltage V GS (M13) minus its threshold voltage V TM13 , so the word line control signal (WWLC) for writing The first stage period of the second high power supply voltage (V DDH2 ) set to be higher than the power supply voltage (V DD ) can effectively accelerate the speed of writing logic 1; in addition, in order to slow down the writing period For the interference phenomenon of the half-selected cell, during the second stage after the first stage, the writing word line control signal (WWLC) is pulled down back to the voltage level of the power supply voltage (V DD ), Wherein, the time between the second stage and the first stage of the writing word line control circuit (6) is equal to the output of the fifth inverter (INV5) enough to turn on the eighth PMOS transistor ( Calculated from the time of P61) and until the output of the sixth inverter (INV6) is enough to turn off the ninth PMOS transistor (P62), its value can be determined by the rise of the sixth inverter (INV6) Delay time to adjust.

(三)節點A原本儲存邏輯1，而現在欲寫入邏輯1： (3) Node A originally stored logic 1, but now wants to write logic 1:

在寫入動作發生前(該寫入用字元線控制信號WWLC為接地電壓)，該第一PMOS電晶體(P11)為導通(ON)。當該寫入用字元線控制信號(WWLC)由Low(接地電壓)轉High，由於該節點A為該電源供應電壓(VDD)之電壓位準，且該寫入用位元線(WBL)為該第三高電源供應電壓(VDDH3)之電壓位準，因此當該第二高電源供應電壓(VDDH2)設定為高於該電源供應電壓(VDD)但低於該電源供應電壓(VDD)與該第三NMOS電晶體(M13)臨界電壓之VTM13的總和時，亦即 Before the writing operation occurs (the word line control signal WWLC for writing is the ground voltage), the first PMOS transistor (P11) is turned on (ON). When the writing word line control signal (WWLC) turns from Low (ground voltage) to High, the node A is the voltage level of the power supply voltage (V DD ), and the writing bit line (WBL ) Is the voltage level of the third highest power supply voltage (V DDH3 ), so when the second highest power supply voltage (V DDH2 ) is set higher than the power supply voltage (V DD ) but lower than the power supply voltage (V DD ) and the sum of the threshold voltage of the third NMOS transistor (M13) V TM13 , that is

VDD<VDDH2<VDD+VTM13 (6)會使該第三NMOS電晶體(M13)繼續保持截止(OFF)狀態；此時因為該第一PMOS電晶體(P11)仍為ON，所以該節點A的電壓會維持於該電源供應電壓(VDD)之電壓位準，直到寫入週期結束。 V DD <V DDH2 <V DD +V TM13 (6) will make the third NMOS transistor (M13) continue to maintain the OFF state; at this time, because the first PMOS transistor (P11) is still ON, so The voltage of the node A will be maintained at the voltage level of the power supply voltage (V DD ) until the end of the writing period.

(四)節點A原本儲存邏輯1，而現在欲寫入邏輯0： (4) Node A originally stored logic 1, but now wants to write logic 0:

在寫入動作發生前(該寫入用字元線控制信號WWLC為接地電壓)，該第一PMOS電晶體(P11)為導通(ON)。當該寫入用字元線控制信號(WWLC)由Low(接地電壓)轉High，且該寫入用字元線控制信號(WWLC)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時，該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON)，此時因為該寫入用位元線(WBL)為滿足方程式(3)的電壓位準(VWBL1)，其小於0V，並且因為該第一PMOS電晶體(P11)仍為ON且該節點B處於電壓位準為接近於該接地電壓之電壓位準的初始狀態，所以該第一NMOS電晶體(M11)仍為截止，而該節點A之寫入初始瞬間電壓(VAWI0)滿足方程式(7)： Before the writing operation occurs (the word line control signal WWLC for writing is the ground voltage), the first PMOS transistor (P11) is turned on (ON). When the writing word line control signal (WWLC) turns from Low (ground voltage) to High, and the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13) At this time, the third NMOS transistor (M13) changes from off (OFF) to on (ON), because the write bit line (WBL) is the voltage level (V WBL1 ) that satisfies the equation (3) , Which is less than 0V, and because the first PMOS transistor (P11) is still ON and the node B is in the initial state where the voltage level is close to the voltage level of the ground voltage, the first NMOS transistor (M11) ) Is still off, and the initial instantaneous voltage (V AWI0 ) of the node A writes satisfies equation (7):

VAWI0=VWBL1×RP11/(RM13+RP11)+VDD×RM13/(RM13+RP11) (7) V AWI0 =V WBL1 ×R P11 /(R M13 +R P11 )+V DD ×R M13 /(R M13 +R P11 ) (7)

VAWI0表示節點A由邏輯1寫入邏輯0之寫入初始瞬間電壓，RM13與RP11分別表示該第三NMOS電晶體(M13)與該第一PMOS電晶體(P11)之導通電阻，而VWBL1與VDD分別表示該寫入用位元線(WBL)於寫入邏輯0之第一階段的電壓位準與該電源供應電壓(VDD)之電壓位準，由於由邏輯1寫入邏輯0時，該第三NMOS電晶體(M13)係工作於飽和區，飽和區之電流係與其閘-源極電壓VGS(M13)之電壓位準扣減其臨界電壓後之平方成正比例，因此藉由該寫入用位元線(WBL)於寫入邏輯0之第一階段的電壓位準(VWBL1)小於0V以及藉由將該寫入用字元線控制信號(WWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2)的設計方式，可有效加速由邏輯1寫入邏輯0之速度。 V AWI0 represents the initial instantaneous voltage at which node A is written to logic 0 from logic 1, R M13 and R P11 represent the on-resistance of the third NMOS transistor (M13) and the first PMOS transistor (P11), and V WBL1 and V DD respectively represent the voltage level of the writing bit line (WBL) in the first stage of writing logic 0 and the voltage level of the power supply voltage (V DD ), since it is written by logic 1 At logic 0, the third NMOS transistor (M13) works in the saturation region, and the current in the saturation region is proportional to the square of its gate-source voltage V GS (M13) minus its threshold voltage. Therefore, the voltage level (V WBL1 ) in the first stage of writing logic 0 by the writing bit line (WBL) is less than 0V and by setting the writing word line control signal (WWLC) to The design of the second highest power supply voltage (V DDH2 ) which is higher than the power supply voltage (V DD ) can effectively accelerate the speed of writing logic 0 from logic 1 to logic 1.

在此值得注意的是，節點A由邏輯0寫入邏輯1以及由邏輯1寫入邏輯0時，該第三NMOS電晶體(M13)係工作於飽和區，飽和區之電流係與其閘-源極電壓VGS(M13)之電壓位準扣減其臨界電壓後之平方成正比例，因此藉由二階段的該寫入用字元線控制電路(6)而於該寫入用字元線(WWL)致能的第一階段，將該寫入用字元線控制信號(WWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2)，可有效加速節點A由邏輯0寫入邏輯1以及由邏輯1寫入邏輯0之寫入速度；再者，於節點A由邏輯1寫入邏輯0時，可藉由前述方程式(3)於由邏輯1寫入邏輯0之初期提供低於該接地電壓之電壓位準(VWBL1)給該寫入用位元線(WBL)，其中，VWBL1的絕對值限定為小於該第三NMOS電晶體(M13)之臨界電壓，例如可設計為-100mV、-150mV或-200mV，藉此可藉由進一步加大工作於飽和區之該第三NMOS電晶體(M13)的閘-源極電壓VGS(M13)，以有效地提高節點A由邏輯1寫入邏輯0之寫入速度。 It is worth noting here that when node A is written from logic 0 to logic 1 and from logic 1 to logic 0, the third NMOS transistor (M13) works in the saturation region, and the current in the saturation region is connected to its gate-source The voltage level of the pole voltage V GS (M13) minus the threshold voltage is proportional to the square of the threshold voltage. Therefore, the two-stage writing word line control circuit (6) is used in the writing word line ( In the first stage of WWL) enabling, setting the writing word line control signal (WWLC) to the second high power supply voltage (V DDH2 ) higher than the power supply voltage (V DD ) can be effective Accelerate the write speed of node A from logic 0 to logic 1 and from logic 1 to logic 0; furthermore, when node A is from logic 1 to logic 0, the above equation (3) can be used to change from logic 1 In the initial stage of writing logic 0, a voltage level (V WBL1 ) lower than the ground voltage is provided to the writing bit line (WBL), wherein the absolute value of V WBL1 is limited to be smaller than the third NMOS transistor (M13 ) Threshold voltage, for example, can be designed as -100mV, -150mV or -200mV, which can further increase the gate-source voltage V GS (M13 ) of the third NMOS transistor (M13) operating in the saturation region ) To effectively increase the write speed of node A from logic 1 to logic 0.

(II)讀取模式(read mode) (II) Read mode

於讀取操作開始前，該讀取控制信號(RC)、該寫入控制信號(WC)及該待機模式控制信號(S)均為邏輯低位準，使得該第三PMOS電晶體(P21)導通，並使得該第十NMOS電晶體(M27)截止，於是該第三PMOS電晶體(P21)之汲極呈邏輯高位準，邏輯高位準之該第三PMOS電晶體(P21)之汲極會導通第九NMOS電晶體(M26)，並使得該第一低電壓節點(VL1)呈接地電壓。另一方面，由於該讀取控制信號(RC)為邏輯低位準，使得該第七NMOS電晶體(M24)截止(OFF)，並使得該第八NMOS電晶體(M25)導通(ON)。 Before the read operation starts, the read control signal (RC), the write control signal (WC) and the standby mode control signal (S) are all logic low levels, so that the third PMOS transistor (P21) is turned on , And turn off the tenth NMOS transistor (M27), so the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) at a logic high level is turned on The ninth NMOS transistor (M26) makes the first low voltage node (VL1) present a ground voltage. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned on (ON).

在此值得注意的是，於讀取操作開始前之預充電期間，該預充電信號(P)係為邏輯低位準，藉此以將相對應之讀取用位元線(RBL)預充電至該電源供應電壓(VDD)之位準，惟由於例如10奈米以下製程技術之操作電壓將降為0.9伏特以下時將造成讀取速度降低而無法滿足規範之問題，因此，本發明提出二階段的讀取控制以於提高讀取速度並滿足規範的同時，亦避免無謂的功率耗損。 It is worth noting here that during the precharge period before the start of the read operation, the precharge signal (P) is at a logic low level, so as to precharge the corresponding read bit line (RBL) to The level of the power supply voltage (V DD ), but because the operating voltage of the process technology below 10 nanometers will drop below 0.9 volts, the reading speed will be reduced and the specification cannot be met. Therefore, the present invention proposes two The read control of the stage can improve the read speed and meet the specifications while avoiding unnecessary power consumption.

第6圖所示之本發明較佳實施例係藉由二階段的讀取控制以於提高讀取速度的同時，亦避免無謂的功率耗損，於讀取操作之第一階段，該讀取控制信號(RC)為邏輯高位準，使得該第七NMOS電晶體(M24)導通，由於此時該第八NMOS電晶體(M25)仍導通，於是該第二低電壓節點(VL2)大約呈較接地電壓為低之該加速讀取電壓(RGND)，該較接地電壓為低之該加速讀取電壓(RGND)可有效提高讀取速度。 The preferred embodiment of the present invention shown in Figure 6 uses a two-stage read control to increase the read speed while avoiding unnecessary power consumption. In the first stage of the read operation, the read control The signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the second low voltage node (VL2) is approximately grounded. The accelerated reading voltage (RGND) whose voltage is low, and the accelerated reading voltage (RGND) whose voltage is lower than the ground voltage can effectively increase the reading speed.

而於讀取操作之第二階段，雖然該讀取控制信號(RC)仍為邏輯高位準，使得該第七NMOS電晶體(M24)仍為導通，惟由於此時該第八NMOS電晶體(M25)截止，於是該第二低電壓節點(VL2)會經由導通的該第四NMOS電晶體(M21)而呈接地電壓(由於讀取操作期間該反相待機模式控制信號(/S)為邏輯高位準)，藉此可有效減少無謂的功率消耗。在此值得注意的是，該讀取操作之該第二階段與該第一階段相隔之時間，係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算，並至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間，其值可藉由該第三反相器(INV3)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。再者，無論於讀取操作之第一階段抑 是第二階段，該第四NMOS電晶體(M21)均呈導通狀態(由於讀取操作期間該反相待機模式控制信號(/S)為邏輯高位準)。第8圖所示為第6圖之本發明較佳實施例於讀取期間之簡化電路圖。 In the second stage of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but because the eighth NMOS transistor ( M25) is turned off, so the second low voltage node (VL2) will be at the ground voltage via the turned-on fourth NMOS transistor (M21) (because the inverted standby mode control signal (/S) is a logic during the read operation) High level), which can effectively reduce unnecessary power consumption. It is worth noting here that the time between the second stage and the first stage of the read operation is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level, and reaches the first stage. The time until the gate voltage of the eight NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25) can be determined by the fall delay time of the third inverter (INV3) and the first delay circuit (D1) Adjust the delay time provided. Furthermore, whether in the first stage of the read operation or not In the second stage, the fourth NMOS transistors (M21) are all turned on (because the inverted standby mode control signal (/S) is at a logic high level during the read operation). FIG. 8 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during the read period.

接下來依2種讀取狀態來說明第8圖之本發明較佳實施例如何藉由控制電路(2)、該高電壓位準控制電路(5)以及讀取用字元線控制電路(7)以於提高讀取速度的同時，亦避免無謂的功率耗損。 Next, according to two reading states, how the preferred embodiment of the present invention in Figure 8 uses the control circuit (2), the high voltage level control circuit (5), and the word line control circuit for reading (7). ) In order to improve the reading speed, it also avoids unnecessary power consumption.

(一)讀取邏輯1(節點A儲存邏輯1)： (1) Read logic 1 (node A stores logic 1):

在讀取動作發生前，該第一NMOS電晶體(M11)為截止(OFF)且該第二NMOS電晶體(M12)為導通(ON)，該節點A與該節點B分別為該電源供應電壓(VDD)與接地電壓，而該讀取用位元線(RBL)則因該預充電電路(3)而等於該電源供應電壓(VDD)。於讀取期間，由於節點B為接地電壓，因此該第二讀取用電晶體(M15)截止(OFF)，藉此可有效保持該讀取用位元線(RBL)為該電源供應電壓(VDD)直到讀取週期結束而順利完成讀取邏輯1之操作。在此值得注意的是，於讀取操作之該第一階段，該第二低電壓節點(VL2)於讀取邏輯1時之讀取初始瞬間電壓(VRVL2I)必須滿足方程式(8)： Before the read operation occurs, the first NMOS transistor (M11) is turned off (OFF) and the second NMOS transistor (M12) is turned on (ON), and the node A and the node B are respectively the power supply voltage (V DD ) and the ground voltage, and the read bit line (RBL) is equal to the power supply voltage (V DD ) due to the precharge circuit (3). During the reading period, since node B is at the ground voltage, the second reading transistor (M15) is turned off (OFF), thereby effectively keeping the reading bit line (RBL) as the power supply voltage ( V DD ) The operation of reading logic 1 is successfully completed until the end of the reading cycle. It is worth noting here that in the first stage of the read operation, the read initial instantaneous voltage (V RVL2I ) of the second low voltage node (VL2) when reading logic 1 must satisfy the equation (8):

VRVL2I=RGND×RM21/(RM21+RM24+RM25)>-VTM12 (8)以有效地防止讀取時之半選定晶胞干擾，其中，VRVL2I表示該第二低電壓節點(VL2)於讀取邏輯1時之讀取初始瞬間電壓，RGND表示該加速讀取電壓，RM21表示該第四NMOS電晶體(M21)之導通電阻，RM24表示該第七NMOS電晶體(M24)之導通電阻，RM25表示該第八NMOS電晶體(M25)之導通電阻，而VTM12表示該第二NMOS電晶體(M12)之臨界電壓；而於 該讀取操作之該第二階段，該第二低電壓節點(VL2)之電壓(VRVL2)可由方程式(9)表示 V RVL2I =RGND×R M21 /(R M21 +R M24 +R M25 )>-V TM12 (8) to effectively prevent the half-selected cell interference during reading, where V RVL2I represents the second low voltage node (VL2) Read the initial instantaneous voltage when reading logic 1, RGND represents the accelerated reading voltage, R M21 represents the on-resistance of the fourth NMOS transistor (M21), and R M24 represents the seventh NMOS transistor ( M24) on-resistance, R M25 represents the on-resistance of the eighth NMOS transistor (M25), and V TM12 represents the threshold voltage of the second NMOS transistor (M12); and in the second stage of the read operation , The voltage (V RVL2 ) of the second low voltage node (VL2) can be expressed by equation (9)

VRVL2=接地電壓 (9)藉此，可有效地減少無謂的功率消耗。再者，為了有效降低讀取時之半選定晶胞干擾與有效降低漏電流，必須將較接地電壓為低之該加速讀取電壓(RGND)設定為使該第二低電壓節點(VL2)之電壓位準小於該第二NMOS電晶體(M12)之臨界電壓(VTM12)，同時可更嚴謹地將較接地電壓為低之該加速讀取電壓(RGND)之絕對值|RGND|設定為低於該第二NMOS電晶體(M12)之臨界電壓(VTM12)，亦即 V RVL2 = ground voltage (9) This can effectively reduce unnecessary power consumption. Furthermore, in order to effectively reduce the half-selected cell interference during reading and effectively reduce the leakage current, the accelerated reading voltage (RGND) that is lower than the ground voltage must be set to make the second low voltage node (VL2) The voltage level is smaller than the threshold voltage (V TM12 ) of the second NMOS transistor (M12), and at the same time, the absolute value of the accelerated reading voltage (RGND), which is lower than the ground voltage, can be set to low |RGND| The threshold voltage (V TM12 ) of the second NMOS transistor (M12), which is

|RGND|<VTM12 (10)其中，|RGND|與VTM12分別表示該加速讀取電壓之絕對值與該第二NMOS電晶體(M12)之臨界電壓。 |RGND|<V TM12 (10) where |RGND| and V TM12 respectively represent the absolute value of the accelerating read voltage and the threshold voltage of the second NMOS transistor (M12).

(二)讀取邏輯0(節點A儲存邏輯0)： (2) Read logic 0 (node A stores logic 0):

在讀取動作發生前，該第一NMOS電晶體(M11)為導通(ON)且該第二NMOS電晶體(M12)為截止(OFF)，該節點A與該節點B分別為接地電壓與該電源供應電壓(VDD)，而該讀取用位元線(RBL)則因該預充電電路(3)而等於該電源供應電壓(VDD)。於讀取期間，由於節點B為該第一高電源供應電壓(VDDH1)，且該第二低電壓節點(VL2)呈較接地電壓為低之電壓，本發明將該第一高電源供應電壓(VDDH1)設定為高於該電源供應電壓(VDD)但低於該電源供應電壓(VDD)與該第二PMOS電晶體(P12)臨界電壓之絕對值|VTP12|的總和，亦即 Before the read operation occurs, the first NMOS transistor (M11) is turned on (ON) and the second NMOS transistor (M12) is turned off (OFF), the node A and the node B are ground voltage and the The power supply voltage (V DD ), and the read bit line (RBL) is equal to the power supply voltage (V DD ) due to the precharge circuit (3). During the reading period, since node B is the first high power supply voltage (V DDH1 ) and the second low voltage node (VL2) is a voltage lower than the ground voltage, the present invention provides the first high power supply voltage (V DDH1 ) is set to be higher than the power supply voltage (V DD ) but lower than the sum of the absolute value of the power supply voltage (V DD ) and the second PMOS transistor (P12) threshold voltage |V TP12 |, also which is

VDD<VDDH1<VDD+|VTP12| (11) V DD <V DDH1 <V DD +|V TP12 | (11)

其中，|VTP12|表示該第二PMOS電晶體(P12)臨界電壓之絕對值，因此，可藉由增加該第二讀取用電晶體(M15)之導通程度，以提高讀取邏輯0之速度，同時配合較接地電壓為低之該第二低電壓節點(VL2)以進一步提高讀取速度。 Where |V TP12 | represents the absolute value of the threshold voltage of the second PMOS transistor (P12). Therefore, the conduction degree of the second read transistor (M15) can be increased to improve the read logic 0 At the same time, the second low voltage node (VL2), which is lower than the ground voltage, can be used to further increase the reading speed.

再者，於讀取期間，藉由該讀取用字元線控制電路(7)以於該讀取用字元線(RWL)致能的第一階段，將該讀取用字元線控制信號(RWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2)，以進一步減少讀取路徑之電阻，並加速該讀取用位元線(RWL)上之電荷的放電從而再進一步提高讀取速度，而於該第一階段後之第二階段時，則將該讀取用字元線控制信號(RWLC)拉低回該電源供應電壓(VDD)，以減緩讀取干擾。在此值得注意的是，該第二高電源供應電壓(VDDH2)設定為高於該電源供應電壓(VDD)但低於該電源供應電壓(VDD)與該第一讀取用電晶體(M14)臨界電壓之VTM14的總和時，亦即 Furthermore, during the reading period, the reading word line control circuit (7) is used to control the reading word line in the first stage of enabling the reading word line (RWL) The signal (RWLC) is set to the second highest power supply voltage (V DDH2 ) higher than the power supply voltage (V DD ) to further reduce the resistance of the read path and speed up the read bit line (RWL) ) To further increase the reading speed. In the second stage after the first stage, the word line control signal (RWLC) for reading is pulled down back to the power supply voltage (V DD ) to slow down read interference. It is worth noting here that the second high power supply voltage (V DDH2 ) is set higher than the power supply voltage (V DD ) but lower than the power supply voltage (V DD ) and the first read transistor (M14) When the threshold voltage is the sum of V TM14 , that is

VDD<VDDH2<VDD+VTM14 (12)比較方程式(6)與方程式(12)可知，該第二高電源供應電壓(VDDH2)必須滿足該電源供應電壓(VDD)與該第一讀取用電晶體(M14)臨界電壓之VTM14的總和(VDD+VTM14)以及該電源供應電壓(VDD)與該第三NMOS電晶體(M13)臨界電壓之VTM13的總和(VDD+VTM13)兩者中之較小者。 V DD <V DDH2 <V DD +V TM14 (12) Comparing equation (6) with equation (12) shows that the second highest power supply voltage (V DDH2 ) must satisfy the power supply voltage (V DD ) and the first The sum of V TM14 (V DD +V TM14 ) of the threshold voltage of a reading transistor (M14) and the sum of the power supply voltage (V DD ) and the threshold voltage of the third NMOS transistor (M13) V TM13 ( V DD +V TM13 ) The smaller of the two.

再者，為了簡化電路設計，可將該第一高電源供應電壓(VDDH1)、該第二高電源供應電壓(VDDH2)與該第三高電源供應電壓(VDDH3)設計成相同，其值為大於該電源供應電壓(VDD)但小於等於滿足該電源供應電壓(VDD)與該第一讀取用電晶體(M14)臨界電壓之VTM14的總和(VDD+ VTM14)、該電源供應電壓(VDD)與該第三NMOS電晶體(M13)臨界電壓之VTM13的總和(VDD+VTM13)以及該電源供應電壓(VDD)與該第二PMOS電晶體(P12)臨界電壓之絕對值|VTP12|總和(VDD+|VTP12|)三者中之較小者(該值可由方程式(6)、方程式(11)與方程式(12)推知)。 Furthermore, in order to simplify the circuit design, the first high power supply voltage (V DDH1 ), the second high power supply voltage (V DDH2 ) and the third high power supply voltage (V DDH3 ) can be designed to be the same. The value is greater than the power supply voltage (V DD ) but less than or equal to the sum of V TM14 (V DD + V TM14 ) that satisfies the power supply voltage (V DD ) and the threshold voltage of the first read transistor (M14), The sum of the power supply voltage (V DD ) and the threshold voltage of the third NMOS transistor (M13) V TM13 (V DD +V TM13 ) and the power supply voltage (V DD ) and the second PMOS transistor (P12 ) The absolute value of the critical voltage |V TP12 | (V DD +|V TP12 |) is the smaller of the three (the value can be inferred from equation (6), equation (11) and equation (12)).

1‧‧‧SRAM晶胞 1‧‧‧SRAM cell

2‧‧‧控制電路 2‧‧‧Control circuit

3‧‧‧預充電電路 3‧‧‧Pre-charge circuit

4‧‧‧待機啟動電路 4‧‧‧Standby start circuit

5‧‧‧高電壓位準控制電路 5‧‧‧High voltage level control circuit

6‧‧‧寫入用字元線控制電路 6‧‧‧Word line control circuit for writing

7‧‧‧讀取用字元線控制電路 7‧‧‧Character line control circuit for reading

8‧‧‧寫入驅動電路 8‧‧‧Write drive circuit

P11‧‧‧第一PMOS電晶體 P11‧‧‧First PMOS transistor

P12‧‧‧第二PMOS電晶體 P12‧‧‧Second PMOS Transistor

M11‧‧‧第一NMOS電晶體 M11‧‧‧First NMOS transistor

M12‧‧‧第二NMOS電晶體 M12‧‧‧Second NMOS Transistor

M13‧‧‧第三NMOS電晶體 M13‧‧‧The third NMOS transistor

A‧‧‧儲存節點 A‧‧‧Storage Node

B‧‧‧反相儲存節點 B‧‧‧Inverted storage node

C‧‧‧節點 C‧‧‧node

M14‧‧‧第一讀取用電晶體 M14‧‧‧First reading transistor

M15‧‧‧第二讀取用電晶體 M15‧‧‧Second reading transistor

WBL‧‧‧寫入用位元線 WBL‧‧‧Bit line for writing

WWL‧‧‧寫入用字元線 WWL‧‧‧Character line for writing

RBL‧‧‧讀取用位元線 RBL‧‧‧Bit line for reading

RWL‧‧‧讀取用字元線 RWL‧‧‧Character line for reading

WWLC‧‧‧寫入用字元線控制信號 WWLC‧‧‧Character line control signal for writing

RWLC‧‧‧讀取用字元線控制信號 RWLC‧‧‧Character line control signal for reading

S‧‧‧待機模式控制信號 S‧‧‧Standby mode control signal

/S‧‧‧反相待機模式控制信號 /S‧‧‧Inverted standby mode control signal

VL1‧‧‧第一低電壓節點 VL1‧‧‧The first low voltage node

VL2‧‧‧第二低電壓節點 VL2‧‧‧The second low voltage node

M21‧‧‧第四NMOS電晶體 M21‧‧‧Fourth NMOS Transistor

M22‧‧‧第五NMOS電晶體 M22‧‧‧Fifth NMOS Transistor

M23‧‧‧第六NMOS電晶體 M23‧‧‧The sixth NMOS transistor

M24‧‧‧第七NMOS電晶體 M24‧‧‧The seventh NMOS transistor

M25‧‧‧第八NMOS電晶體 M25‧‧‧Eighth NMOS Transistor

M26‧‧‧第九NMOS電晶體 M26‧‧‧Ninth NMOS Transistor

M27‧‧‧第十NMOS電晶體 M27‧‧‧Tenth NMOS Transistor

P21‧‧‧第三PMOS電晶體 P21‧‧‧The third PMOS transistor

RC‧‧‧讀取控制信號 RC‧‧‧Read control signal

RGND‧‧‧加速讀取電壓 RGND‧‧‧Accelerated reading voltage

INV3‧‧‧第三反相器 INV3‧‧‧Third inverter

D1‧‧‧第一延遲電路 D1‧‧‧First delay circuit

WC‧‧‧寫入控制信號 WC‧‧‧Write control signal

P31‧‧‧第四PMOS電晶體 P31‧‧‧Fourth PMOS Transistor

P‧‧‧預充電信號 P‧‧‧Precharge signal

M41‧‧‧第十一NMOS電晶體 M41‧‧‧Eleventh NMOS Transistor

P41‧‧‧第五PMOS電晶體 P41‧‧‧Fifth PMOS Transistor

D2‧‧‧第二延遲電路 D2‧‧‧Second delay circuit

VDD‧‧‧電源供應電壓 V DD ‧‧‧Power supply voltage

VDDH1‧‧‧第一高電源供應電壓 V DDH1 ‧‧‧The highest power supply voltage

VDDH2‧‧‧第二高電源供應電壓 V DDH2 ‧‧‧The second highest power supply voltage

P51‧‧‧第六PMOS電晶體 P51‧‧‧Sixth PMOS Transistor

P52‧‧‧第七PMOS電晶體 P52‧‧‧The seventh PMOS transistor

INV4‧‧‧第四反相器 INV4‧‧‧Fourth inverter

VH‧‧‧高電壓節點 VH‧‧‧High Voltage Node

P61‧‧‧第八PMOS電晶體 P61‧‧‧Eighth PMOS Transistor

P62‧‧‧第九PMOS電晶體 P62‧‧‧Ninth PMOS Transistor

P63‧‧‧第十PMOS電晶體 P63‧‧‧Tenth PMOS Transistor

M61‧‧‧第十二NMOS電晶體 M61‧‧‧Twelfth NMOS Transistor

INV5‧‧‧第五反相器 INV5‧‧‧Fifth inverter

INV6‧‧‧第六反相器 INV6‧‧‧Sixth inverter

P71‧‧‧第十一PMOS電晶體 P71‧‧‧Eleventh PMOS Transistor

P72‧‧‧第十二PMOS電晶體 P72‧‧‧Twelfth PMOS Transistor

P73‧‧‧第十三PMOS電晶體 P73‧‧‧Thirteenth PMOS Transistor

M71‧‧‧第十三NMOS電晶體 M71‧‧‧The thirteenth NMOS transistor

INV7‧‧‧第七反相器 INV7‧‧‧Seventh inverter

INV8‧‧‧第八反相器 INV8‧‧‧Eighth inverter

P81‧‧‧第十四PMOS電晶體 P81‧‧‧14th PMOS Transistor

M81‧‧‧第十四NMOS電晶體 M81‧‧‧14th NMOS Transistor

M82‧‧‧第十五NMOS電晶體 M82‧‧‧Fifteenth NMOS Transistor

M83‧‧‧第十六NMOS電晶體 M83‧‧‧Sixteenth NMOS Transistor

INV9‧‧‧第九反相器 INV9‧‧‧Ninth inverter

INV10‧‧‧第十反相器 INV10‧‧‧Tenth inverter

D3‧‧‧第三延遲電路 D3‧‧‧The third delay circuit

D4‧‧‧第四延遲電路 D4‧‧‧Fourth delay circuit

VDDH3‧‧‧第三高電源供應電壓 V DDH3 ‧‧‧The third highest power supply voltage

Y‧‧‧行解碼器輸出信號 Y‧‧‧Line decoder output signal

Cap‧‧‧電容器 Cap‧‧‧Capacitor

Din‧‧‧輸入資料 Din‧‧‧Enter data

Claims (10)

一種雙埠靜態隨機存取記憶體，包括： A dual-port static random access memory, including: 一記憶體陣列，該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成，每一列記憶體晶胞與每一行記憶體晶胞均包含有複數個記憶體晶胞(1)； A memory array consisting of a plurality of rows of memory cell and a plurality of rows of memory cell, each row of memory cell and each row of memory cell includes a plurality of memory cell ( 1); 複數個控制電路(2)，每一列記憶體晶胞設置一個控制電路(2)； A plurality of control circuits (2), one control circuit (2) is provided for each row of memory cell; 複數個預充電電路(3)，每一行記憶體晶胞設置一個預充電電路(3)； A plurality of precharging circuits (3), one precharging circuit (3) is provided for each row of memory cell; 一待機啟動電路(4)，該待機啟動電路(4)係促使該雙埠靜態隨機存取記憶體快速進入待機模式，以有效提高該雙埠靜態隨機存取記憶體之待機效能； A standby activation circuit (4), the standby activation circuit (4) prompts the dual-port static random access memory to quickly enter the standby mode to effectively improve the standby performance of the dual-port static random access memory; 複數個寫入用字元線控制電路(6)，每一列記憶體晶胞設置一個寫入用字元線控制電路(6)，以於寫入模式有效提高由邏輯0寫入邏輯1以及由該邏輯1寫入該邏輯0之寫入速度；以及 A plurality of word line control circuits for writing (6), each column of memory cell is provided with a word line control circuit (6) for writing, in order to effectively improve the writing mode from logic 0 to logic 1 and from The writing speed of the logic 1 into the logic 0; and 複數個寫入驅動電路(8)，每一行記憶體晶胞設置一個寫入驅動電路(8)，以於該寫入模式有效提高由該邏輯0寫入該邏輯1以及由該邏輯1寫入該邏輯0之該寫入速度； A plurality of write drive circuits (8), each row of memory cell is provided with a write drive circuit (8) to effectively increase the writing of the logic 0 to the logic 1 and the logic 1 to write in the writing mode The write speed of the logic 0; 其中，每一記憶體晶胞(1)更包含： Among them, each memory cell (1) further includes: 一第一反相器，係由一第一PMOS電晶體(P11)與一第一NMOS電晶體(M11)所組成，該第一反相器係連接在一電源供應電壓(VDD)與一第一低電壓節點(VL1)之間； A first inverter is composed of a first PMOS transistor (P11) and a first NMOS transistor (M11). The first inverter is connected to a power supply voltage (V DD ) and a Between the first low voltage node (VL1); 一第二反相器，係由一第二PMOS電晶體(P12)與一第二NMOS電晶體(M12)所組成，該第二反相器係連接在一高電壓節點(VH)與一第二低電壓節點(VL2)之間； A second inverter is composed of a second PMOS transistor (P12) and a second NMOS transistor (M12). The second inverter is connected to a high voltage node (VH) and a first Between two low voltage nodes (VL2); 一儲存節點(A)，係由該第一反相器之輸出端所形成； A storage node (A) is formed by the output terminal of the first inverter; 一反相儲存節點(B)，係由該第二反相器之輸出端所形成； An inverting storage node (B) is formed by the output terminal of the second inverter; 一第三NMOS電晶體(M13)，係連接在該儲存節點(A)與一寫入用位元線(WBL)之間，且閘極連接至一寫入用字元線控制信號(WWLC)；一第一讀取用電晶體(M14)，該第一讀取用電晶體(M14)之源極、閘極與汲極係分別連接至一第二讀取用電晶體(M15)之汲極、一讀取用字元線控制信號(RWLC)與一讀取用位元線(RBL)；以及 A third NMOS transistor (M13) is connected between the storage node (A) and a writing bit line (WBL), and the gate is connected to a writing word line control signal (WWLC) ; A first reading transistor (M14), the source, gate and drain of the first reading transistor (M14) are respectively connected to the drain of a second reading transistor (M15) Pole, a word line control signal (RWLC) for reading and a bit line (RBL) for reading; and 該第二讀取用電晶體(M15)，該第二讀取用電晶體(M15)之源極、閘極與汲極係分別連接至該第二低電壓節點(VL2)、該反相儲存節點(B)與該第一讀取用電晶體(M14)之源極； The second reading transistor (M15), the source, gate and drain of the second reading transistor (M15) are respectively connected to the second low voltage node (VL2) and the inverted storage Node (B) and the source of the first read transistor (M14); 其中，該第一反相器和該第二反相器係呈交互耦合連接，亦即該第一反相器之輸出端(即該儲存節點A)係連接至該第二反相器之輸入端，而該第二反相器之輸出端(即該反相儲存節點B)則連接至該第一反相器之輸入端； Wherein, the first inverter and the second inverter are alternately coupled, that is, the output terminal of the first inverter (ie, the storage node A) is connected to the input of the second inverter Terminal, and the output terminal of the second inverter (that is, the inverting storage node B) is connected to the input terminal of the first inverter; 而每一控制電路(2)更包含：一第四NMOS電晶體(M21)、一第五NMOS電晶體(M22)、一第六NMOS電晶體(M23)、一第七NMOS電晶體(M24)、一第八NMOS電晶體(M25)、一第九NMOS電晶體(M26)、一第十NMOS電晶體(M27)、一第三PMOS電晶體(P21)、一讀取控制信號(RC)、一第三反相器(INV3)、一第一延遲電路(D1)、一加速讀取電壓(RGND)、一寫入控制信號(WC)、一待機模式控制信號(S)以及一反相待機模式控制信號(/S)； Each control circuit (2) further includes: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor (M24) , An eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), A third inverter (INV3), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), a standby mode control signal (S), and an inverted standby Mode control signal (/S); 其中，該第四NMOS電晶體(M21)之源極、閘極與汲極係分別連接至一接地電壓、該反相待機模式控制信號(/S)與該第二低電壓節點(VL2)； Wherein, the source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and the second low voltage node (VL2); 該第五NMOS電晶體(M22)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該待機模式控制信號(S)與該第二低電壓節點(VL2)； The source, gate and drain of the fifth NMOS transistor (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2) ； 該第六NMOS電晶體(M23)之源極係連接至該接地電壓，而閘極與汲極連接在一起並連接至該第一低電壓節點(VL1)； The source of the sixth NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1); 該第七NMOS電晶體(M24)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(M25)之汲極、該讀取控制信號(RC)與該第二低電壓節點(VL2)； The source, gate and drain of the seventh NMOS transistor (M24) are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); 該第八NMOS電晶體(M25)之源極、閘極與汲極係分別連接至該加速讀取電壓(RGND)、該第一延遲電路(D1)之輸出與該第七NMOS電晶體(M24)之源極； The source, gate, and drain of the eighth NMOS transistor (M25) are connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1), and the seventh NMOS transistor (M24). ) Of the source; 該第一延遲電路(D1)係連接在該第三反相器(INV3)之輸出與該第八NMOS電晶體(M25)之該閘極之間； The first delay circuit (D1) is connected between the output of the third inverter (INV3) and the gate of the eighth NMOS transistor (M25); 該第三反相器(INV3)之輸入係供接收該讀取控制信號(RC)，而輸出則連接至該第一延遲電路(D1)之輸入； The input of the third inverter (INV3) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); 該第九NMOS電晶體(M26)之源極、閘極與汲極係分別連接至該接地電壓、該第十NMOS電晶體(M27)之汲極與該第一低電壓節點(VL1)；該第十NMOS電晶體(M27)之源極、閘極與汲極係分別連接至該接地電壓、該寫入控制信號(WC)與該第九NMOS電晶體(M26)之閘極；該第三PMOS電晶體(P21)之源極、閘極與汲極係分別連接至該反相待機模式控制信號(/S)、該寫入控制信號(WC)與該第十NMOS電晶體(M27)之汲極； The source, gate and drain of the ninth NMOS transistor (M26) are connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1), respectively; The source, gate and drain of the tenth NMOS transistor (M27) are respectively connected to the ground voltage, the write control signal (WC) and the gate of the ninth NMOS transistor (M26); the third The source, gate and drain of the PMOS transistor (P21) are respectively connected to the inverted standby mode control signal (/S), the write control signal (WC) and the tenth NMOS transistor (M27). Dip pole 其中，對於非讀取模式期間之該讀取控制信號(RC)係設定為該加速讀取電壓(RGND)之位準，以防止該第七NMOS電晶體(M24)於非讀取模式期間之漏電流； Wherein, the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent the seventh NMOS transistor (M24) from malfunctioning during the non-read mode Leakage current 再者，該待機啟動電路(4)係設計成於進入待機模式之一初始期間內，對該第一低電壓節點(VL1)處之寄生電容快速充電至該第六NMOS電晶體(M23)之臨界電壓(VTM23)的電壓位準； Furthermore, the standby startup circuit (4) is designed to quickly charge the parasitic capacitance at the first low voltage node (VL1) to the sixth NMOS transistor (M23) during an initial period of entering the standby mode The voltage level of the critical voltage (V TM23 ); 其中，每一寫入用字元線控制電路(6)係由一第八PMOS電晶體(P61)、一第九PMOS電晶體(P62)、一第十PMOS電晶體(P63)、一第十二NMOS電晶體(M61)、一第五反相器(INV5)、一第六反相器(INV6)、一第二高電源供應電壓(VDDH2)、一寫入用字元線(WWL)以及該寫入用字元線控制信號(WWLC)所組成； Among them, each word line control circuit for writing (6) is composed of an eighth PMOS transistor (P61), a ninth PMOS transistor (P62), a tenth PMOS transistor (P63), and a tenth PMOS transistor (P63). Two NMOS transistors (M61), a fifth inverter (INV5), a sixth inverter (INV6), a second high power supply voltage (V DDH2 ), a word line for writing (WWL) And the word line control signal (WWLC) for writing; 其中該第八PMOS電晶體(P61)之源極、閘極與汲極係分別連接至該第二高電源供應電壓(VDDH2)、該第五反相器(INV5)之輸出與該第九PMOS電晶體(P62)之源極； The source, gate and drain of the eighth PMOS transistor (P61) are respectively connected to the second high power supply voltage (V DDH2 ), the output of the fifth inverter (INV5) and the ninth The source of PMOS transistor (P62); 該第九PMOS電晶體(P62)之源極、閘極與汲極係分別連接至該第八PMOS電晶體(P61)之汲極、該第六反相器(INV6)之輸出與該寫入用字元線控制信號(WWLC)； The source, gate, and drain of the ninth PMOS transistor (P62) are connected to the drain of the eighth PMOS transistor (P61), the output of the sixth inverter (INV6), and the write Use word line control signal (WWLC); 該第十PMOS電晶體(P63)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該第五反相器(INV5)之輸出與該寫入用字元線控制信號(WWLC)； The source, gate, and drain of the tenth PMOS transistor (P63) are respectively connected to the power supply voltage (V DD ), the output of the fifth inverter (INV5), and the word line for writing Control signal (WWLC); 該第十二NMOS電晶體(M61)之源極、閘極與汲極係分別連接至該接 地電壓、該第五反相器(INV5)之輸出與該寫入用字元線控制信號(WWLC)； The source, gate and drain of the twelfth NMOS transistor (M61) are respectively connected to the connection Ground voltage, the output of the fifth inverter (INV5) and the word line control signal (WWLC) for writing; 該第五反相器(INV5)之輸入係供接收該寫入用字元線(WWL)，而該第六反相器(INV6)之輸入則與該第五反相器(INV5)之輸出連接；最後，每一寫入驅動電路(8)更包含：一第十四PMOS電晶體(P81)、一第十五NMOS電晶體(M81)、一第十五NMOS電晶體(M82)、一第十六NMOS電晶體(M83)、一第九反相器(INV9)、一第十反相器(INV10)、一電容器(Cap)、一輸入資料(Din)、一行解碼器輸出信號(Y)、一第三延遲電路(D3)、一第四延遲電路(D4)以及一第三高電源供應電壓(VDDH3)； The input of the fifth inverter (INV5) is for receiving the word line (WWL) for writing, and the input of the sixth inverter (INV6) is the same as the output of the fifth inverter (INV5) Connection; Finally, each write drive circuit (8) further includes: a fourteenth PMOS transistor (P81), a fifteenth NMOS transistor (M81), a fifteenth NMOS transistor (M82), a Sixteenth NMOS transistor (M83), a ninth inverter (INV9), a tenth inverter (INV10), a capacitor (Cap), an input data (Din), a row of decoder output signals (Y ), a third delay circuit (D3), a fourth delay circuit (D4), and a third high power supply voltage (V DDH3 ); 其中，該第十四PMOS電晶體(P81)之源極、閘極與汲極係分別連接至該第三高電源供應電壓(VDDH3)、該第九反相器(INV9)之輸出與該第十四NMOS電晶體(M81)之汲極； Wherein, the source, gate and drain of the fourteenth PMOS transistor (P81) are respectively connected to the third high power supply voltage (V DDH3 ), the output of the ninth inverter (INV9) and the The drain of the fourteenth NMOS transistor (M81); 該第十四NMOS電晶體(M81)之源極、閘極與汲極係分別連接至該第十六NMOS電晶體(M83)之汲極、該第九反相器(INV9)之輸出與該第十四PMOS電晶體(P81)之汲極； The source, gate and drain of the fourteenth NMOS transistor (M81) are connected to the drain of the sixteenth NMOS transistor (M83), the output of the ninth inverter (INV9) and the The drain of the fourteenth PMOS transistor (P81); 該第十五NMOS電晶體(M82)之源極、閘極與汲極係分別連接至該接地電壓、該第三延遲電路(D3)之輸出與該第十四PMOS電晶體(P81)之汲極； The source, gate, and drain of the fifteenth NMOS transistor (M82) are connected to the ground voltage, the output of the third delay circuit (D3), and the drain of the fourteenth PMOS transistor (P81). pole; 該第十六NMOS電晶體(M83)之源極、閘極與汲極係分別連接至該接地電壓、該第十反相器(INV10)之輸出與該第十四NMOS電晶體(M81)之源極； The source, gate, and drain of the sixteenth NMOS transistor (M83) are connected to the ground voltage, the output of the tenth inverter (INV10), and the fourteenth NMOS transistor (M81). Source 該第九反相器(INV9)之輸入係供接收該輸入資料(Din)，而輸出則連接至該第十四PMOS電晶體(P81)之閘極、該第十四NMOS電晶體(M81)之閘極以及該第三延遲電路(D3)之輸入； The input of the ninth inverter (INV9) is for receiving the input data (Din), and the output is connected to the gate of the fourteenth PMOS transistor (P81) and the fourteenth NMOS transistor (M81) The gate and the input of the third delay circuit (D3); 該第十反相器(INV10)之輸入係供接收該行解碼器輸出信號(Y)，而輸出則連接至該第四延遲電路(D4)之輸入以及該第十六NMOS電晶體(M83)之閘極； The input of the tenth inverter (INV10) is for receiving the row decoder output signal (Y), and the output is connected to the input of the fourth delay circuit (D4) and the sixteenth NMOS transistor (M83) The gate 該電容器(Cap)之一端係連接至該第四延遲電路(D4)之輸出，而該電容器(Cap)之另一端則連接至該第十四NMOS電晶體(M81)之源極 以及該第十六NMOS電晶體(M83)之汲極； One end of the capacitor (Cap) is connected to the output of the fourth delay circuit (D4), and the other end of the capacitor (Cap) is connected to the source of the fourteenth NMOS transistor (M81) And the drain of the sixteenth NMOS transistor (M83); 其中，該第十四PMOS電晶體(P81)之汲極、該第十四NMOS電晶體(M81)之汲極與該第十五NMOS電晶體(M82)之汲極係共同連接至該寫入用位元線(WBL)，該寫入用位元線(WBL)於寫入該邏輯0之第一階段係設計成低於於該接地電壓之電壓位準，以加速寫入該邏輯0之速度，而於寫入邏輯0之第二階段，則拉回至該接地電壓，以減緩寫入該邏輯0時的干擾；而於寫入該邏輯1時，該寫入用位元線(WBL)設計成高於該電源供應電壓(VDD)之該第三高電源供應電壓(VDDH3)的位準，以加速寫入該邏輯1之速度； Wherein, the drain of the fourteenth PMOS transistor (P81), the drain of the fourteenth NMOS transistor (M81), and the drain of the fifteenth NMOS transistor (M82) are commonly connected to the write Use a bit line (WBL), the write bit line (WBL) in the first stage of writing the logic 0 is designed to be lower than the voltage level of the ground voltage to accelerate the writing of the logic 0 In the second phase of writing logic 0, it is pulled back to the ground voltage to slow down the interference when writing logic 0. When writing logic 1, the write bit line (WBL ) Is designed to be higher than the power supply voltage (V DD ) of the third highest power supply voltage (V DDH3 ) level to accelerate the writing speed of the logic 1; 其中，該每一寫入驅動電路(8)於寫入該邏輯0之該第一階段滿足下列方程式： Wherein, each write drive circuit (8) satisfies the following equation in the first stage of writing the logic 0: VWBL1=-VDD×Cap/(Cap+CWBL) V WBL1 =-V DD ×Cap/(Cap+C WBL ) 其中，VWBL1表示該寫入用位元線(WBL)於寫入該邏輯0之該第一階段的電壓位準，VWBL1的絕對值設計為小於該第三NMOS電晶體(M13)之臨界電壓，VDD為該電源供應電壓(VDD)之電壓位準，而Cap與CWBL分別表示該電容器(Cap)之電容值與該寫入用位元線(WBL)之寄生電容值。 Wherein, V WBL1 represents the voltage level of the writing bit line (WBL) in the first stage of writing the logic 0, and the absolute value of V WBL1 is designed to be smaller than the threshold of the third NMOS transistor (M13) Voltage, V DD is the voltage level of the power supply voltage (V DD ), and Cap and C WBL respectively represent the capacitance value of the capacitor (Cap) and the parasitic capacitance value of the write bit line (WBL). 如申請專利範圍第1項所述之雙埠靜態隨機存取記憶體，其中，更包括複數個高電壓位準控制電路(5)，每一列記憶體晶胞設置一個高電壓位準控制電路(5)，以在讀取邏輯0時提高讀取速度，每一高電壓位準控制電路(5)更包含：一第六PMOS電晶體(P51)、一第七PMOS電晶體(P52)以及一第四反相器(INV4)； For example, the dual-port static random access memory described in item 1 of the scope of patent application, which further includes a plurality of high-voltage level control circuits (5), and each row of memory cell is provided with a high-voltage level control circuit ( 5) To increase the reading speed when reading logic 0, each high voltage level control circuit (5) further includes: a sixth PMOS transistor (P51), a seventh PMOS transistor (P52), and a The fourth inverter (INV4); 其中，該第六PMOS電晶體(P51)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該讀取控制信號(RC)與該高電壓節點(VH)；該第七PMOS電晶體(P52)之源極、閘極與汲極係分別連接至一第一高電源供應電壓(VDDH1)、該第四反相器(INV4)之輸出與該高電壓節點(VH)； Wherein, the source, gate and drain of the sixth PMOS transistor (P51) are respectively connected to the power supply voltage (V DD ), the read control signal (RC) and the high voltage node (VH); The source, gate, and drain of the seventh PMOS transistor (P52) are respectively connected to a first high power supply voltage (V DDH1 ), the output of the fourth inverter (INV4), and the high voltage node (VH); 該第四反相器(I63)之輸入係供接收該讀取控制信號(RC)，而該輸出則連接至該第七PMOS電晶體(P52)之閘極。 The input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to the gate of the seventh PMOS transistor (P52). 如申請專利範圍第2項所述之雙埠靜態隨機存取記憶體，其中，更包括複 數個讀取用字元線控制電路(7)，每一列記憶體晶胞設置一個讀取用字元線控制電路(7)，以在讀取邏輯0時進一步減少讀取路徑之電阻，並加速該讀取用位元線(RWL)上之電荷的放電從而再進一步提高讀取速度，每一讀取用字元線控制電路(7)更包含：一第十一PMOS電晶體(P71)、一第十二PMOS電晶體(P72)、一第十三PMOS電晶體(P73)、一第十三NMOS電晶體(M71)、一第七反相器(INV7)、一第八反相器(INV8)、該第二高電源供應電壓(VDDH2)、該讀取用字元線(RWL)以及該讀取用字元線控制信號(RWLC)； The dual-port static random access memory described in item 2 of the scope of patent application further includes a plurality of read-use word line control circuits (7), and each row of memory cell is provided with a read-use character The line control circuit (7) further reduces the resistance of the read path when reading logic 0, and accelerates the discharge of the charge on the read bit line (RWL) to further increase the read speed. The word line control circuit (7) further includes: an eleventh PMOS transistor (P71), a twelfth PMOS transistor (P72), a thirteenth PMOS transistor (P73), and a thirteenth PMOS transistor (P73). NMOS transistor (M71), a seventh inverter (INV7), an eighth inverter (INV8), the second high power supply voltage (V DDH2 ), the read word line (RWL), and The read character line control signal (RWLC); 其中，該第十一PMOS電晶體(P71)之源極、閘極與汲極係分別連接至該第二高電源供應電壓(VDDH2)、該第七反相器(INV7)之輸出與該第十二PMOS電晶體(P72)之源極； Wherein, the source, gate and drain of the eleventh PMOS transistor (P71) are respectively connected to the second high power supply voltage (V DDH2 ), the output of the seventh inverter (INV7) and the The source of the twelfth PMOS transistor (P72); 該第十二PMOS電晶體(P72)之源極、閘極與汲極係分別連接至該第十一PMOS電晶體(P71)之汲極、該第八反相器(INV8)之輸出與該讀取用字元線控制信號(RWLC)； The source, gate, and drain of the twelfth PMOS transistor (P72) are connected to the drain of the eleventh PMOS transistor (P71), the output of the eighth inverter (INV8), and the Character line control signal for reading (RWLC); 第十三PMOS電晶體(P73)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該第七反相器(INV7)之輸出與該讀取用字元線控制信號(RWLC)； The source, gate and drain of the thirteenth PMOS transistor (P73) are respectively connected to the power supply voltage (V DD ), the output of the seventh inverter (INV7) and the word line for reading Control signal (RWLC); 該第十三NMOS電晶體(M71)之源極、閘極與汲極係分別連接至該接地電壓、該第七反相器(INV7)之輸出與該讀取用字元線控制信號(RWLC)； The source, gate, and drain of the thirteenth NMOS transistor (M71) are connected to the ground voltage, the output of the seventh inverter (INV7), and the read word line control signal (RWLC) ); 該第七反相器(INV7)之輸入係供接收該讀取用字元線(RWL)，而該第八反相器(INV8)之輸入則與該第七反相器(INV7)之輸出連接。 The input of the seventh inverter (INV7) is for receiving the read word line (RWL), and the input of the eighth inverter (INV8) is the same as the output of the seventh inverter (INV7) connection. 如申請專利範圍第3項所述之雙埠靜態隨機存取記憶體，其中，每一預充電電路(3)係由一第四PMOS電晶體(P31)以及一預充電信號(P)所組成； The dual-port static random access memory described in item 3 of the scope of patent application, wherein each precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P) ； 其中，該第四PMOS電晶體(P31)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該預充電信號(P)與該讀取用位元線(RBL)，以便於一預充電期間，藉由邏輯低位準之該預充電信號(P)，以將該讀取用位元線(RBL)預充電至該電源供應電壓(VDD)之位準； Wherein, the source, gate, and drain of the fourth PMOS transistor (P31) are respectively connected to the power supply voltage (V DD ), the precharge signal (P) and the read bit line (RBL ) In order to precharge the read bit line (RBL) to the level of the power supply voltage (V DD ) by the precharge signal (P) at a logic low level during a precharge period; 該待機啟動電路(4)係由一第五PMOS電晶體(P41)、一第十一NMOS 電晶體(M41)、一第二延遲電路(D2)以及該反相待機模式控制信號(/S)所組成； The standby startup circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS It is composed of transistor (M41), a second delay circuit (D2) and the inverted standby mode control signal (/S); 其中，該第五PMOS電晶體(P41)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該反相待機模式控制信號(/S)與該第十一NMOS電晶體(M41)之汲極； Wherein, the source, gate and drain of the fifth PMOS transistor (P41) are respectively connected to the power supply voltage (V DD ), the inverted standby mode control signal (/S) and the eleventh NMOS The drain of the transistor (M41); 該第十一NMOS電晶體(M41)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該第二延遲電路(D2)之輸出與該第五PMOS電晶體(P41)之該汲極； The source, gate and drain of the eleventh NMOS transistor (M41) are respectively connected to the first low voltage node (VL1), the output of the second delay circuit (D2) and the fifth PMOS transistor (P41) the drain; 該第二延遲電路(D2)之輸入連接至該反相待機模式控制信號(/S)，而該第二延遲電路(D2)之輸出則連接至該第十一NMOS電晶體(M41)之閘極。 The input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and the output of the second delay circuit (D2) is connected to the gate of the eleventh NMOS transistor (M41) pole. 如申請專利範圍第4項所述之雙埠靜態隨機存取記憶體，其中，該儲存節點(A)於原本儲存該邏輯0，而在寫入該邏輯1之寫入初始瞬間電壓(VAWI1)滿足下列方程式： For the dual-port static random access memory described in item 4 of the scope of patent application, the storage node (A) originally stores the logic 0, and the initial instant voltage (V AWI1 ) for writing the logic 1 ) Satisfies the following equation: VAWI1=VDDH3×(RM11+RM23)/(RM13+RM11+RM23)>VTM12 V AWI1 =V DDH3 ×(R M11 +R M23 )/(R M13 +R M11 +R M23 )>V TM12 其中，VAWI1表示該儲存節點(A)由儲存該邏輯0而寫入該邏輯1之該寫入初始瞬間電壓，RM11、RM13與RM23分別表示該第一NMOS電晶體(M11)、該第三NMOS電晶體(M13)與該第六NMOS電晶體(M23)之導通電阻，而VDDH3與VTM12分別表示該第三高電源供應電壓之電壓位準與該第二NMOS電晶體(M12)之臨界電壓； Wherein, V AWI1 represents the initial instant voltage at which the storage node (A) is written to the logic 1 by storing the logic 0, and R M11 , R M13 and R M23 represent the first NMOS transistor (M11), The on-resistance of the third NMOS transistor (M13) and the sixth NMOS transistor (M23), and V DDH3 and V TM12 respectively represent the voltage level of the third high power supply voltage and the second NMOS transistor ( M12) the critical voltage; 且該儲存節點(A)於原本儲存該邏輯1，而在寫入該邏輯0之寫入初始瞬間電壓(VAWI0)滿足下列方程式： And the storage node (A) originally stores the logic 1, and the initial instant voltage (V AWI0 ) for writing the logic 0 satisfies the following equation: VAWI0=VWBL1×RP11/(RM13+RP11)+VDD×RM13/(RM13+RP11) V AWI0 =V WBL1 ×R P11 /(R M13 +RP 11 )+V DD ×R M13 /(R M13 +R P11 ) 其中，VAWI0表示節點A由該邏輯1寫入該邏輯0之寫入初始瞬間電壓，RM13與RP11分別表示該第三NMOS電晶體(M13)與該第一PMOS電晶體(P11)之導通電阻，而VWBL1與VDD分別表示該寫入用位元線(WBL)於寫入該邏輯0之該第一階段的電壓位準與該電源供應電壓(VDD)之電壓位準。 Wherein, V AWI0 represents the initial instantaneous voltage at which node A is written to the logic 0 by the logic 1, R M13 and R P11 represent the difference between the third NMOS transistor (M13) and the first PMOS transistor (P11), respectively On-resistance, and V WBL1 and V DD respectively represent the voltage level of the writing bit line (WBL) in the first stage of writing the logic 0 and the voltage level of the power supply voltage (V DD ). 如申請專利範圍第5項所述之雙埠靜態隨機存取記憶體，其中，該第二高 電源供應電壓(VDDH2)係設定為滿足該電源供應電壓(VDD)與該第一讀取用電晶體(M14)之臨界電壓(VTM14)的總和(即VDD+VTM14)以及該電源供應電壓(VDD)與該第三NMOS電晶體(M13)之臨界電壓(VTM13)的總和(即VDD+VTM13)兩者中之較小者。 The dual-port static random access memory described in item 5 of the scope of patent application, wherein the second high power supply voltage (V DDH2 ) is set to satisfy the power supply voltage (V DD ) and the first read The sum of the threshold voltage (V TM14 ) of the transistor (M14) (i.e. V DD + V TM14 ) and the power supply voltage (V DD ) and the threshold voltage (V TM13 ) of the third NMOS transistor (M13) The sum (ie V DD +V TM13 ) is the smaller of the two. 如申請專利範圍第6項所述之雙埠靜態隨機存取記憶體，其中，該每一寫入用字元線控制電路(6)於致能時可再細分成二個階段，於該寫入用字元線(WWL)致能的一第一階段，將該寫入用字元線控制信號(WWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2)，以有效提高寫入速度，而於該第一階段後之一第二階段時，則將該寫入用字元線控制信號(WWLC)拉低回該電源供應電壓(VDD)，以減緩寫入干擾；其中，該每一寫入用字元線控制電路(6)之該第二階段與該第一階段相隔之時間，係等於該第五反相器(INV5)之輸出足以導通該第八PMOS電晶體(P61)之時間起算，並至該第六反相器(INV6)之輸出足以關閉該第九PMOS電晶體(P62)為止之時間，其值可藉由該第六反相器(INV6)之上升延遲時間來動態調整。 For example, the dual-port static random access memory described in item 6 of the scope of patent application, wherein the word line control circuit (6) for each writing can be subdivided into two stages when it is enabled. In a first stage of enabling the word line (WWL) for writing, the word line control signal for writing (WWLC) is set to the second high power supply voltage higher than the power supply voltage (V DD ) (V DDH2 ), in order to effectively increase the writing speed, and in the second stage after the first stage, the writing word line control signal (WWLC) is pulled down back to the power supply voltage (V DD ) To slow down write disturbance; wherein, the time between the second stage and the first stage of each word line control circuit (6) for writing is equal to the time of the fifth inverter (INV5) Calculated from the time required to turn on the eighth PMOS transistor (P61) and the time until the output of the sixth inverter (INV6) is sufficient to turn off the ninth PMOS transistor (P62), its value can be determined by the The rise delay time of the sixth inverter (INV6) is dynamically adjusted. 如申請專利範圍第7項所述之雙埠靜態隨機存取記憶體，其中，讀取操作係可再細分成二個階段，於該讀取操作之一第一階段係藉由將該第二低電壓節點(VL2)設定成較該接地電壓為低之電壓以有效提高讀取速度，而於該讀取操作之一第二階段則藉由將該第二低電壓節點(VL2)設定回該接地電壓，以便減少無謂的功率消耗；於該讀取操作之該第一階段，該第二低電壓節點(VL2)於讀取邏輯1時之讀取初始瞬間電壓(VRVL2I)必須滿足下列方程式： For the dual-port static random access memory described in item 7 of the scope of patent application, the read operation can be subdivided into two stages. In one of the read operations, the first stage is performed by the second The low voltage node (VL2) is set to a voltage lower than the ground voltage to effectively increase the reading speed. In a second stage of the reading operation, the second low voltage node (VL2) is set back to the Ground voltage to reduce unnecessary power consumption; in the first stage of the read operation, the read initial instantaneous voltage (V RVL2I ) of the second low voltage node (VL2) when reading logic 1 must satisfy the following equation : VRVL2I=RGND×RM21/(RM21+RM24+RM25)>-VTM12 V RVL2I =RGND×R M21 /(R M21 +R M24 +R M25 )>-V TM12 以有效地防止讀取時之半選定晶胞干擾，其中，VRVL2I表示該第二低電壓節點(VL2)於讀取邏輯1時之該讀取初始瞬間電壓，RGND表示該加速讀取電壓，RM21表示該第四NMOS電晶體(M21)之導通電阻，RM24表示該第七NMOS電晶體(M24)之導通電阻，RM25表示該第八NMOS電晶體(M25)之導通電阻，而VTM12表示該第二NMOS電晶體(M12) 之臨界電壓。 In order to effectively prevent the half-selected cell interference during reading, V RVL2I represents the initial instantaneous voltage of the second low voltage node (VL2) when reading logic 1, and RGND represents the accelerated reading voltage, R M21 represents the on-resistance of the fourth NMOS transistor (M21), R M24 represents the on-resistance of the seventh NMOS transistor (M24), R M25 represents the on-resistance of the eighth NMOS transistor (M25), and V TM12 represents the threshold voltage of the second NMOS transistor (M12). 如申請專利範圍第8項所述之雙埠靜態隨機存取記憶體，其中，該第一高電源供應電壓(VDDH1)係設定為高於該電源供應電壓(VDD)但低於該電源供應電壓(VDD)與該第二PMOS電晶體(P12)臨界電壓之絕對值|VTP12|的總和，亦即 The dual-port static random access memory described in item 8 of the scope of patent application, wherein the first high power supply voltage (V DDH1 ) is set higher than the power supply voltage (V DD ) but lower than the power supply The sum of the absolute value of the supply voltage (V DD ) and the threshold voltage of the second PMOS transistor (P12) |V TP12 |, that is VDD<VDDH1<VDD+|VTP12|。 V DD <V DDH1 <V DD +|V TP12 |. 如申請專利範圍第9項所述之雙埠靜態隨機存取記憶體，其中，該第一高電源供應電壓(VDDH1)、該第二高電源供應電壓(VDDH2)與該第三高電源供應電壓(VDDH3)設定成相同，其值為大於該電源供應電壓(VDD)但小於等於該電源供應電壓(VDD)與該第一讀取用電晶體(M14)臨界電壓(VTM14)的總和(VDD+VTM14)、該電源供應電壓(VDD)與該第三NMOS電晶體(M13)臨界電壓(VTM13)的總和(VDD+VTM13)以及該電源供應電壓(VDD)與該第二PMOS電晶體(P12)臨界電壓之絕對值(|VTP12|)的總和(VDD+|VTP12|)三者中之較小者。 The dual-port static random access memory described in item 9 of the scope of patent application, wherein the first high power supply voltage (V DDH1 ), the second high power supply voltage (V DDH2 ) and the third high power supply The supply voltage (V DDH3 ) is set to be the same, and its value is greater than the power supply voltage (V DD ) but less than or equal to the power supply voltage (V DD ) and the first reading transistor (M14) threshold voltage (V TM14 ) (V DD +V TM14 ), the sum of the power supply voltage (V DD ) and the third NMOS transistor (M13) threshold voltage (V TM13 ) (V DD +V TM13 ), and the power supply voltage ( V DD ) and the sum of the absolute value (|V TP12 |) of the second PMOS transistor (P12) threshold voltage (V DD +|V TP12 |), whichever is smaller.
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