TWI781667B - Method of depositing thin film and method of manufacturing semiconductor device using the same - Google Patents

Method of depositing thin film and method of manufacturing semiconductor device using the same Download PDF

Info

Publication number
TWI781667B
TWI781667B TW110123934A TW110123934A TWI781667B TW I781667 B TWI781667 B TW I781667B TW 110123934 A TW110123934 A TW 110123934A TW 110123934 A TW110123934 A TW 110123934A TW I781667 B TWI781667 B TW I781667B
Authority
TW
Taiwan
Prior art keywords
thin film
substrate
chamber
deposition method
film deposition
Prior art date
Application number
TW110123934A
Other languages
Chinese (zh)
Other versions
TW202205384A (en
Inventor
金秀仁
崔暎喆
辛昌學
朴愍隅
金智賢
金京美
Original Assignee
南韓商圓益Ｉｐｓ股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南韓商圓益Ｉｐｓ股份有限公司 filed Critical 南韓商圓益Ｉｐｓ股份有限公司
Publication of TW202205384A publication Critical patent/TW202205384A/en
Application granted granted Critical
Publication of TWI781667B publication Critical patent/TWI781667B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/01—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes on temporary substrates, e.g. substrates subsequently removed by etching
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/042—Coating on selected surface areas, e.g. using masks using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/308—Oxynitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/46—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • C23C16/509—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/52—Controlling or regulating the coating process
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32137—Radio frequency generated discharge controlling of the discharge by modulation of energy
    • H01J37/32155—Frequency modulation
    • H01J37/32165—Plural frequencies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32458—Vessel
    • H01J37/32522—Temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Mechanical Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Analytical Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

本發明為薄膜沉積方法及利用該薄膜沉積方法的半導體器件的製造方法的相關技術。本案實施例的薄膜沉積方法利用具有腔室的基板處理裝置，基板處理裝置包括：腔室，將處理空間限定於內部；基板支撐架，位於腔室的下部區域並放置基板；氣體供應部，位於腔室的上部區域，並向基板供應源氣體及反應氣體；及供電部，將高頻及低頻電源供應於腔室，該方法包括以下步驟：將包含在低溫帶的製程溫度條件下沉積之下部薄膜的基板放置在基板支撐架上；在低溫帶的製程溫度條件下在電漿環境中在下部薄膜上部沉積上部薄膜；在沉積上部薄膜的步驟之後，在低溫帶的製程溫度條件下在電漿環境中處理上部薄膜的表面，其中，該低溫帶的製程溫度為100至250℃。 The present invention relates to a thin film deposition method and a method for manufacturing a semiconductor device using the thin film deposition method. The thin film deposition method in the embodiment of the present case utilizes a substrate processing device having a chamber. The substrate processing device includes: a chamber, which limits the processing space inside; a substrate support frame, located in the lower area of the chamber and placing the substrate; a gas supply part, located the upper area of the chamber, and supply source gas and reaction gas to the substrate; and the power supply part, which supplies high-frequency and low-frequency power to the chamber, and the method includes the following steps: depositing the lower part under the process temperature condition of the low temperature zone The substrate of the thin film is placed on the substrate support frame; the upper thin film is deposited on the lower thin film in a plasma environment under the process temperature conditions of the low temperature zone; The surface of the upper film is processed in an ambient environment, wherein the process temperature in the low temperature zone is 100 to 250°C.

Description

薄膜沉積方法及利用該薄膜沉積方法的半導體器件的製造方法 Thin film deposition method and method of manufacturing semiconductor device using the thin film deposition method

本發明涉及薄膜沉積方法及利用該薄膜沉積法的半導體器件的製造方法，更詳細地說，涉及用於形成硬光罩的薄膜沉積方法及利用該薄膜沉積方法的半導體器件的製造方法。 The present invention relates to a thin film deposition method and a manufacturing method of a semiconductor device using the thin film deposition method, more specifically, to a thin film deposition method for forming a hard mask and a manufacturing method of a semiconductor device using the thin film deposition method.

在高集成化的半導體器件的製造中，圖案的細微化是必不可少的。為了在小面積集成更多的器件，有必要縮小構成器件的各個圖案及圖案之間的間距。近來，隨著半導體器件的設計規則(design rule)急劇減少，以及目前光刻製程的曝光限制，以致於在形成具有微小線寬和間距的圖形上存在侷限性。 In the manufacture of highly integrated semiconductor devices, miniaturization of patterns is essential. In order to integrate more devices in a small area, it is necessary to reduce each pattern constituting the device and the spacing between the patterns. Recently, with the drastic reduction of the design rules of semiconductor devices and the exposure limitation of the current photolithography process, there are limitations in forming patterns with small line widths and spacings.

目前，為了將精細圖案限制在曝光極限以下，提出了各種蝕刻方法，其中一種就是利用硬光罩的方法。 Currently, various etching methods have been proposed in order to limit fine patterns below the exposure limit, and one of them is a method using a hard mask.

對於所述硬光罩，要求具有針對被蝕刻層的耐蝕刻性。尤其是，在包含多個氧化矽膜和多個氮化矽膜層疊結構的3D NAND器件的情況下，為了針對層疊結構物確保高蝕刻選擇比，正利用非晶碳膜及氧氮化矽膜的層疊結構作為硬光罩。 The hard mask is required to have etching resistance to the layer to be etched. In particular, in the case of a 3D NAND device including a stacked structure of a plurality of silicon oxide films and a plurality of silicon nitride films, an amorphous carbon film and a silicon oxynitride film are being used in order to secure a high etch selectivity for the stacked structure. The stacked structure acts as a hard mask.

由所述非晶碳膜及所述氧氮化矽膜構成的硬光罩通常是在450℃至650℃的高溫下沉積。然而，在如此的高溫下製作硬光罩層時，可能劣化下部之被蝕刻層的特性，從而進一步地存在改變器件特性的問題。 The hard mask composed of the amorphous carbon film and the silicon oxynitride film is usually deposited at a high temperature of 450°C to 650°C. However, when the hard mask layer is formed at such a high temperature, the properties of the underlying etched layer may be degraded, thereby further causing the problem of changing device properties.

據此，在以往提出了在100至250℃的低溫下只沉積與被蝕刻層相對相鄰的非晶碳膜。但是，該方式仍然是在高溫下沉積構成硬光罩的 氧氮化矽膜，因此高溫可能使得在下部的非晶碳膜出現破損，從而可能引起硬光罩圖案的圖案缺陷。 Accordingly, it has been proposed in the past to deposit only the amorphous carbon film relatively adjacent to the layer to be etched at a low temperature of 100 to 250°C. However, this method is still deposited at high temperature to form the hard mask Silicon oxynitride film, so high temperature may cause damage to the lower amorphous carbon film, which may cause pattern defects in the hard mask pattern.

本發明的實施例提供一種與下部薄膜保持蝕刻選擇比的同時可降低對下部薄膜的破壞的薄膜沉積方法及利用該薄膜沉積方法的半導體器件的製造方法。 Embodiments of the present invention provide a thin film deposition method capable of reducing damage to a lower thin film while maintaining an etching selectivity ratio with the lower thin film, and a method of manufacturing a semiconductor device using the thin film deposition method.

本實施例的薄膜沉積方法為利用具有腔室的基板處理裝置的薄膜沉積方法，所述基板處理裝置包括：腔室，將處理空間限定於內部；基板支撐架，位於所述腔室的下部區域並且放置基板；氣體供應部，位於所述腔室的上部區域，並且向所述基板供應源氣體及反應氣體；以及供電部，將高頻及低頻電源供應於所述腔室。所述薄膜沉積方法包括以下步驟：將包含在低溫帶的製程溫度條件下沉積的下部薄膜的所述基板放置在所述基板支撐架上；在所述低溫帶的製程溫度條件下在電漿環境中在所述下部薄膜上部沉積上部薄膜；在沉積所述上部薄膜的步驟之後，在所述低溫帶的製程溫度條件下在電漿環境中處理所述上部薄膜的表面，其中，所述低溫帶的製程溫度為100至250℃。 The thin film deposition method of this embodiment is a thin film deposition method utilizing a substrate processing apparatus having a chamber, and the substrate processing apparatus includes: a chamber defining a processing space inside; a substrate support frame located in a lower area of the chamber And a substrate is placed; a gas supply part is located in the upper area of the chamber and supplies source gas and reaction gas to the substrate; and a power supply part supplies high frequency and low frequency power to the chamber. The film deposition method includes the following steps: placing the substrate containing the lower film deposited under the process temperature condition of the low temperature zone on the substrate supporting frame; depositing an upper thin film on top of the lower thin film; after the step of depositing the upper thin film, treating the surface of the upper thin film in a plasma environment under the process temperature conditions of the low temperature zone, wherein the low temperature zone The process temperature ranges from 100 to 250°C.

另外，本發明一實施例的半導體器件的製造方法包括以下步驟：在半導體基板上部形成基底層；在低溫帶的製程溫度下在所述基底層上部沉積與所述基底層具有蝕刻選擇比的下部薄膜；在所述低溫帶的製程溫度下在所述下部薄膜上部沉積與所述下部薄膜具有蝕刻選擇比的上部薄膜；電漿處理所述上部薄膜來形成硬光罩；以及利用所述硬光罩將所述基底層圖案化，其中，所述低溫帶的製程溫度在100至250℃的範圍；所述上部薄膜為利用反應氣體及比所述反應氣體過量的源氣體沉積，所述電漿處理是供應所述反應氣體來進行。 In addition, the manufacturing method of a semiconductor device according to an embodiment of the present invention includes the following steps: forming a base layer on the upper part of the semiconductor substrate; thin film; depositing an upper thin film having an etch selectivity to the lower thin film on top of the lower thin film at the process temperature of the low temperature zone; plasma treating the upper thin film to form a hard mask; and using the hard photo mask to pattern the base layer, wherein the process temperature of the low temperature zone is in the range of 100 to 250°C; the upper film is deposited by using a reactive gas and an excess source gas than the reactive gas, and the plasma Processing is performed by supplying the reactive gas.

根據本發明的實施例，為了代替將構成硬光罩的下部薄膜和上部薄膜全部在低溫帶的製程溫度下沉積，可改變上部薄膜的沉積方式，以 補償上部薄膜的蝕刻選擇比。據此，在充分補償蝕刻選擇比的同時可在低溫下沉積硬光罩，因此最終可防止圖案缺陷。 According to an embodiment of the present invention, instead of depositing both the lower film and the upper film constituting the hard mask at the process temperature of the low temperature zone, the deposition method of the upper film can be changed to Compensates for the etch selectivity of the upper film. According to this, a hard mask can be deposited at a low temperature while sufficiently compensating for an etching selectivity ratio, and thus pattern defects can finally be prevented.

100:基板 100: Substrate

110:基底層 110: basal layer

110a:氧化矽膜 110a: silicon oxide film

110b:氮化矽膜 110b: silicon nitride film

120:下部薄膜 120: Lower film

130:上部薄膜 130: upper film

150:基板處理裝置 150: Substrate processing device

200:腔室 200: chamber

201:控制器 201: Controller

210:主體 210: subject

212:排氣口 212: Exhaust port

213:泵 213: pump

220:頂蓋 220: top cover

230:噴灑頭 230: sprinkler head

240:基板支撐部 240: substrate support part

240a:源氣體供應部 240a: Source gas supply unit

240b:反應氣體供應部 240b: Reactive gas supply unit

242:基板放置部 242: Substrate placement department

244:支撐軸 244: Support shaft

246:加熱器 246: heater

250:驅動部 250: drive unit

260:電漿供電部 260: Plasma Power Supply Department

261:第一供電部 261: First Power Supply Department

263:第二供電部 263: The second power supply department

270:匹配網路 270: Matching network

271:第一匹配部 271: The first matching department

273:第二匹配部 273: The second matching department

290:加熱器供電部 290: heater power supply unit

HM:硬光罩層 HM: hard mask layer

r:絕緣環 r: insulation ring

W:基板 W: Substrate

G:門 G: door

L:供氣管線 L: gas supply line

V1,V2:閥門 V1, V2: Valve

S1~S3,S21~S22:步驟 S1~S3, S21~S22: steps

圖1是用於說明本發明一實施例之包含薄膜的半導體器件的製造方法的流程圖； FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor device including a thin film according to an embodiment of the present invention;

圖2至圖4是用於說明本發明一實施例之包含薄膜的半導體器件的製造方法的各個製程的剖面圖； 2 to 4 are cross-sectional views illustrating various processes of a method for manufacturing a semiconductor device including a thin film according to an embodiment of the present invention;

圖5是概略地顯示本發明一實施例之基板處理裝置的剖面圖； 5 is a cross-sectional view schematically showing a substrate processing apparatus according to an embodiment of the present invention;

圖6是用於說明本發明一實施例之上部薄膜沉積方法的流程圖；以及 FIG. 6 is a flowchart illustrating a method for depositing an upper thin film according to an embodiment of the present invention; and

圖7是用於說明本發明一實施例之上部薄膜沉積方法的時序圖。 FIG. 7 is a timing diagram illustrating a method for depositing an upper thin film according to an embodiment of the present invention.

配合附圖參照詳細後述的實施例，將明確本發明的優點及特徵、達成方法。然而，本發明不限於在以下揭露的實施例，而是可實現相互不同的各種形態，本實施例只是使本發明的揭露更加完整，且是為了將發明的範疇更加完整地告知給在本發明所屬技術領域中具有普通知識的人而提供的，本發明只由申請專利範圍定義。為了說明的明確性，在附圖中可誇張地顯示層及區域的大小及相對大小。在說明書全文中，相同的元件符號是指相同的構成元件。 The advantages, features and implementation methods of the present invention will be clarified by referring to the embodiments described later in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but various forms different from each other can be realized. This embodiment only makes the disclosure of the present invention more complete, and is to fully inform the scope of the invention to the present invention Provided by persons with ordinary knowledge in the technical field, the present invention is only defined by the claims. For clarity of illustration, the sizes and relative sizes of layers and regions may be shown exaggeratedly in the drawings. Throughout the specification, the same reference numerals refer to the same constituent elements.

圖1是用於說明本發明一實施例之包含薄膜的半導體器件的製造方法的流程圖；圖2至圖4是用於說明本發明一實施例之包含薄膜的半導體器件的製造方法的各個製程的剖面圖。 Fig. 1 is a flowchart for illustrating a method for manufacturing a semiconductor device including a thin film according to an embodiment of the present invention; Fig. 2 to Fig. 4 are various processes for illustrating a method for manufacturing a semiconductor device including a thin film according to an embodiment of the present invention sectional view.

參照圖1、圖2及圖3，本發明提供形成有下部薄膜120的基板100(S1)。在本實施例中，在基板100與下部薄膜120之間還可形成相當於被蝕刻層的基底層110。例如，基底層110可以是交替反復層疊的氧化矽膜110a及氮化矽膜110b的層疊結構體。另外，雖未在附圖詳細顯示，但是在半導體基板100與基底層110之間還可介入單獨的器件層。在本實施例中，對於基底層110顯示了交替層疊的氧化矽膜110a及氮化矽膜110b的示例，但是在此也可以是各種被蝕刻層。 Referring to FIG. 1 , FIG. 2 and FIG. 3 , the present invention provides a substrate 100 ( S1 ) on which a lower thin film 120 is formed. In this embodiment, a base layer 110 corresponding to the layer to be etched may also be formed between the substrate 100 and the lower film 120 . For example, the base layer 110 may be a stacked structure of silicon oxide films 110 a and silicon nitride films 110 b stacked alternately and repeatedly. In addition, although not shown in detail in the drawings, a separate device layer may also be interposed between the semiconductor substrate 100 and the base layer 110 . In this embodiment, an example of alternately stacking silicon oxide films 110 a and silicon nitride films 110 b is shown for the base layer 110 , but various etched layers may also be used here.

下部薄膜120為與所述被蝕刻層具有蝕刻選擇比的物質，例如可利用非晶碳膜(amorphous carbon layer)、氧化鈦膜或者旋轉塗佈二氧化矽(Spin on glass,SOG)。本實施例的下部薄膜120可在低溫帶的製程溫度，例如100至250℃下形成。據此，在沉積下部薄膜120時，可減少對所述下部的被蝕刻層的熱效應。 The lower film 120 is a material having an etching selectivity to the layer to be etched, for example, an amorphous carbon layer, a titanium oxide film, or spin-on-glass (SOG) can be used. The lower thin film 120 of this embodiment can be formed at a low-temperature process temperature, for example, 100 to 250° C. Accordingly, when the lower thin film 120 is deposited, the thermal effect on the lower etched layer can be reduced.

參照圖1和圖4，在雙頻率(例如，高頻及低頻)下在下部薄膜120上部沉積上部薄膜130作為所述硬光罩的另一部分(S2)。上部薄膜130可利用與下部薄膜120具有蝕刻選擇比的材料膜，例如，氧氮化矽膜(SiON)。本實施例的上部薄膜130可在低溫帶的製程溫度下，例如與下部薄膜120的沉積溫度實際相同的低溫帶的製程溫度(100至250℃)下沉積。據此，在沉積上部薄膜130時，不會在下部薄膜120引起熱破壞。在附圖中，「HM」可稱為硬光罩層。 Referring to FIGS. 1 and 4 , an upper film 130 is deposited on top of the lower film 120 as another part of the hard mask at dual frequencies (eg, high frequency and low frequency) ( S2 ). The upper film 130 may use a material film having an etch selectivity to the lower film 120 , for example, silicon oxynitride film (SiON). The upper film 130 of the present embodiment can be deposited at a low-temperature process temperature, for example, a low-temperature process temperature (100 to 250° C.) that is actually the same as the deposition temperature of the lower film 120 . Accordingly, when the upper thin film 130 is deposited, thermal damage is not caused in the lower thin film 120 . In the drawings, "HM" may be referred to as a hard mask layer.

例如，由所述氧氮化矽膜構成之本實施例的上部薄膜130可通過SiH4及N2O氣體(或者NO氣體)的反應形成。作為一示例，所述SiH4和N2O的比例能夠以1.2~2.5比1的比例提供。相比於所述N2O增加SiH4氣體的含量，因此可改善氧氮化矽膜的蝕刻選擇比。另外，所述氧氮化矽膜可在1.5至4.0Torr的壓力下形成。另外，在本實施例中，作為用於形成氧氮化矽膜的反應氣體，利用N2O或者NO來代替NH3可減少氧氮化矽膜內的氫(H)含量。因此，可補償低溫沉積的氧氮化矽膜的蝕刻選擇比。 For example, the upper thin film 130 of this embodiment composed of the silicon oxynitride film can be formed by the reaction of SiH 4 and N 2 O gas (or NO gas). As an example, the ratio of SiH 4 and N 2 O can be provided in a ratio of 1.2-2.5 to 1. The SiH 4 gas content is increased compared to the N 2 O, thereby improving the etch selectivity of the silicon oxynitride film. In addition, the silicon oxynitride film can be formed under a pressure of 1.5 to 4.0 Torr. In addition, in this embodiment, as the reaction gas for forming the silicon oxynitride film, using N 2 O or NO instead of NH 3 can reduce the hydrogen (H) content in the silicon oxynitride film. Therefore, the etch selectivity of the low temperature deposited silicon oxynitride film can be compensated.

例如，本實施例的上部薄膜130可在如圖5所示的基板處理裝置中沉積。 For example, the upper thin film 130 of this embodiment can be deposited in a substrate processing apparatus as shown in FIG. 5 .

圖5是概略地顯示本發明一實施例之基板處理裝置的剖面圖。 5 is a cross-sectional view schematically showing a substrate processing apparatus according to an embodiment of the present invention.

參照圖5，基板處理裝置150可包括：腔室200、控制器201、噴灑頭230、基板支撐部240、驅動部250、電漿供電部260、匹配網路270、以及加熱器供電部290。 Referring to FIG. 5 , the substrate processing apparatus 150 may include: a chamber 200 , a controller 201 , a shower head 230 , a substrate supporting part 240 , a driving part 250 , a plasma power supply part 260 , a matching network 270 , and a heater power supply part 290 .

腔室200可包括上部開放的主體210及設置在主體210上端外周的頂蓋220。頂蓋220的內部空間可被噴灑頭230封閉。在噴灑頭230與頂蓋220之間設置有絕緣環r，可電絕緣腔室200和噴灑頭230。 The chamber 200 may include a main body 210 with an open top and a top cover 220 disposed on the outer periphery of the upper end of the main body 210 . The inner space of the top cover 220 may be closed by the sprinkler head 230 . An insulating ring r is provided between the shower head 230 and the top cover 220 to electrically insulate the chamber 200 and the shower head 230 .

在腔室200內部空間中可進行上部薄膜130的沉積製程。在主體210側面的指定位置可配置有用於基板W進出的門G。 The deposition process of the upper thin film 130 can be performed in the inner space of the chamber 200 . A door G for entering and exiting the substrate W may be disposed at a designated position on the side of the main body 210 .

為了將腔室200內部真空化，在位於腔室200下部的排氣口212可連接泵213。 In order to vacuumize the inside of the chamber 200 , a pump 213 may be connected to an exhaust port 212 located at a lower portion of the chamber 200 .

噴灑頭230可與基板支撐部240相互面對地設置在頂蓋220內側。噴灑頭230通過供氣管線L接收從外部供應的各種源氣體可噴射到腔室200內部。在本實施例中，噴灑頭230可作為用於產生電漿的第一電極。 The shower head 230 may be disposed inside the top cover 220 to face each other with the substrate supporting part 240 . The shower head 230 receives various source gases supplied from the outside through the gas supply line L and may inject them into the chamber 200 . In this embodiment, the shower head 230 may serve as a first electrode for generating plasma.

在本實施例的噴灑頭230的供氣管線L可連接源氣體供應部240a及反應氣體供應部240b。在本實施例中，源氣體供應部240a可儲存例如SiH4氣體，而反應氣體供應部240b可儲存例如N2O氣體。 The gas supply line L of the shower head 230 in this embodiment can be connected to the source gas supply part 240a and the reaction gas supply part 240b. In this embodiment, the source gas supply part 240a can store, for example, SiH 4 gas, and the reaction gas supply part 240b can store, for example, N 2 O gas.

雖然在圖5中只顯示源氣體供應部240a及反應氣體供應部240b，但是在供氣管線L還可以連接吹掃(purge)氣體供應部及/或乾燥(seasoning)氣體供應部。在源氣體供應部240a與供氣管線L之間及反應氣體供應部240b和供氣管線L分別可設置閥門V1、V2。 Although only the source gas supply part 240a and the reaction gas supply part 240b are shown in FIG. 5 , a purge gas supply part and/or a drying (seasoning) gas supply part may also be connected to the gas supply line L. Valves V1 and V2 may be provided between the source gas supply part 240a and the gas supply line L and between the reaction gas supply part 240b and the gas supply line L, respectively.

基板支撐部240可包括基板放置部242(基座)及支撐軸244。基板放置部242整體可具有平板形狀，以在上面至少放置一個基板W。支撐軸244垂直結合於基板放置部242後面，並且通過腔室200底部的貫通孔與外部的驅動部250連接，可升降及/或旋轉基板放置部242。在本實施例中，基板放置部242可作為用於產生電漿的第二電極。 The substrate supporting part 240 may include a substrate placing part 242 (base) and a supporting shaft 244 . The substrate placement part 242 may have a flat plate shape as a whole to place at least one substrate W thereon. The support shaft 244 is vertically combined with the back of the substrate placing part 242 and connected with the external driving part 250 through a through hole at the bottom of the chamber 200 to lift and/or rotate the substrate placing part 242 . In this embodiment, the substrate placement part 242 may serve as a second electrode for generating plasma.

另外，在基板放置部242的內部配置有加熱器246，可調節放置在上部的基板100的溫度，更進一步地可調節腔室200內部的溫度。加熱器供電部290與所述加熱器246連接可進行供電。 In addition, a heater 246 is arranged inside the substrate placement part 242 to adjust the temperature of the substrate 100 placed on the upper part, and further, the temperature inside the chamber 200 can be adjusted. The heater power supply unit 290 is connected to the heater 246 for power supply.

控制器201構成為控制基板處理裝置150的整體動作。在一實施例中，控制器201控制基板處理裝置150的各個構成元件200~290、V1、V2的動作，並且可設定用於沉積上部薄膜130的控制參數。雖未顯示，但是控制器201可包括中央處理裝置、記憶體、輸出入介面等。 The controller 201 is configured to control the overall operation of the substrate processing apparatus 150 . In one embodiment, the controller 201 controls the actions of the components 200 - 290 , V1 , V2 of the substrate processing apparatus 150 , and can set control parameters for depositing the upper thin film 130 . Although not shown, the controller 201 may include a central processing unit, a memory, an I/O interface, and the like.

電漿供電部260可包括第一供電部261及第二供電部263。第一供電部261可提供的中心頻寬為10MHz~40MHz，例如具有13.56MHz的HF(High frequency)電源作為電漿電源。再者，第二供電部263可提供的中心頻寬為300kHz~500kHz，例如具有370KHz的LF(low frequency)電源作為電漿電源。控制器201根據控制參數可控制從第一供電部261及/或第二供電部263供應的電源。 The plasma power supply part 260 may include a first power supply part 261 and a second power supply part 263 . The central bandwidth that the first power supply unit 261 can provide is 10 MHz~40 MHz, for example, 13.56 MHz HF (High frequency) power is used as the plasma power. Furthermore, the central bandwidth that the second power supply unit 263 can provide is 300kHz˜500kHz, for example, 370KHz LF (low frequency) power is used as the plasma power. The controller 201 can control the power supplied from the first power supply part 261 and/or the second power supply part 263 according to the control parameters.

匹配網路270可包括與第一供電部261連接的第一匹配部271及與第二供電部263連接的第二匹配部273。匹配網路270的第一匹配部271及第二匹配部273將第一供電部261及第二供電部263的輸出阻抗分別與腔室200內的負載阻抗相互匹配，以清除從腔室200反射RF電源的回波損耗。 The matching network 270 may include a first matching part 271 connected to the first power supply part 261 and a second matching part 273 connected to the second power supply part 263 . The first matching part 271 and the second matching part 273 of the matching network 270 match the output impedances of the first power supply part 261 and the second power supply part 263 with the load impedance in the chamber 200 respectively, so as to eliminate reflections from the chamber 200. Return loss of the RF power supply.

圖6是用於說明本發明一實施例之上部薄膜沉積方法的流程圖；以及圖7是用於說明本發明一實施例之上部薄膜沉積方法的時序圖。 6 is a flow chart illustrating a method for depositing an upper thin film according to an embodiment of the present invention; and FIG. 7 is a timing diagram illustrating a method for depositing an upper thin film according to an embodiment of the present invention.

參照圖1、圖4至圖7，所述上部薄膜沉積步驟S2可包括將腔室200內部穩定化的步驟(S21)。所述穩定化步驟S21可以是營造可在低溫帶的製程溫度下沉積上部薄膜130的環境的步驟。為了沉積上部薄膜130，腔室200內部可營造100至250℃的溫度及1.5至4.0Torr的壓力。 1, 4 to 7, the upper thin film deposition step S2 may include a step of stabilizing the inside of the chamber 200 (S21). The stabilizing step S21 may be a step of creating an environment capable of depositing the upper thin film 130 at a process temperature in a low temperature zone. In order to deposit the upper film 130 , a temperature of 100 to 250° C. and a pressure of 1.5 to 4.0 Torr can be created inside the chamber 200 .

在將腔室200內部穩定化的狀態下在下部薄膜120上沉積上部薄膜130(S22)。上部薄膜130可以是如上所述在100至250℃的溫度及1.5至4.0Torr的壓力下以1.2~2.5比1的比例供應所述源氣體(SiH4)及反應氣體(N2O)而成。通過將所述源氣體(SiH4)的比例比反應氣體(N2O)的比例增加預定量，可改善針對下部薄膜120的上部薄膜130的蝕刻選擇比。結果，可補償上部薄膜130的低溫沉積的蝕刻選擇比。 The upper thin film 130 is deposited on the lower thin film 120 in a state where the interior of the chamber 200 is stabilized (S22). The upper thin film 130 may be formed by supplying the source gas (SiH 4 ) and the reaction gas (N 2 O) at a ratio of 1.2 to 2.5 to 1 at a temperature of 100 to 250° C. and a pressure of 1.5 to 4.0 Torr as described above. . By increasing the ratio of the source gas (SiH 4 ) to the ratio of the reaction gas (N 2 O) by a predetermined amount, the etching selectivity of the upper thin film 130 to the lower thin film 120 may be improved. As a result, the etch selectivity of the low-temperature deposition of the upper thin film 130 can be compensated.

另外，本實施例的上部薄膜130在雙頻(即高頻(HF)及低頻(LF))下沉積。通過利用所述低頻(LF)促進離子能及離子轟擊(bombardment)，補償通過低溫沉積的上部薄膜130的熱能，可防止不穩定鍵合。 In addition, the upper thin film 130 of this embodiment is deposited under dual frequency (ie high frequency (HF) and low frequency (LF)). By using the low frequency (LF) to promote ion energy and ion bombardment, compensating thermal energy of the upper thin film 130 deposited by low temperature, unstable bonding can be prevented.

然後，在所述雙頻下進行電漿處理(S3)。所述電漿處理步驟S3為停止供應所述源氣體(SiH4)，而可只供應反應氣體(N2O)來進行。利用N2O氣體的電漿處理步驟S3可在所述低溫帶的製程溫度(例如100至250℃的溫度)下可與上部薄膜130沉積步驟接連進行。為了通過所述電漿處理改善上部薄膜130表面的硬度，可改性上部薄膜130的表面。據此，可進一步改善蝕刻選擇比。雖未在附圖詳細顯示，但是通過所述電漿處理製程也可在上部薄膜130的表面生成氧化膜。 Then, plasma treatment is performed under the double frequency (S3). The plasma treatment step S3 can be performed by supplying only the reaction gas (N 2 O) without supplying the source gas (SiH 4 ). The plasma treatment step S3 using N 2 O gas may be performed successively with the deposition step of the upper thin film 130 at the process temperature of the low temperature zone (for example, a temperature of 100 to 250° C.). In order to improve the hardness of the surface of the upper thin film 130 through the plasma treatment, the surface of the upper thin film 130 may be modified. Accordingly, the etching selectivity can be further improved. Although not shown in detail in the drawings, an oxide film can also be formed on the surface of the upper film 130 through the plasma treatment process.

然後，雖未在附圖顯示，但是在吹掃製程腔室200內來清除未反應的成分及腔室200內的雜質。 Then, although not shown in the drawing, the process chamber 200 is purged to remove unreacted components and impurities in the chamber 200 .

構成硬光罩層的上部薄膜130為了確保高蝕刻選擇比，通常是高溫沉積。但是，在高溫沉積上部薄膜130的情況下，可能對下部薄膜120甚至是基底層110造成熱破壞。 The upper thin film 130 constituting the hard mask layer is usually deposited at a high temperature in order to ensure a high etch selectivity. However, in the case of depositing the upper thin film 130 at a high temperature, thermal damage may be caused to the lower thin film 120 and even the base layer 110 .

據此，在本實施例中，與下部薄膜120相同，在不影響基底層110的物理特性的低溫帶的製程溫度(例如100至250℃)下沉積上部薄膜130。 Accordingly, in this embodiment, the same as the lower film 120 , the upper film 130 is deposited at a low-temperature process temperature (for example, 100 to 250° C.) that does not affect the physical properties of the base layer 110 .

同時，為了能夠補償在低溫下沉積的上部薄膜130的蝕刻選擇比，相比於反應氣體的比例增加源氣體的比例，並可在1.5至4Torr的壓力下沉積上部薄膜130。另外，在本實施例中，為了補償在低溫下沉積的上部薄膜130的蝕刻選擇比，與上部薄膜130的沉積接連地只供應所述反應氣體在低溫帶下進行電漿處理。據此，改性所述上部薄膜的表面特性，以及補償蝕刻選擇比。 Meanwhile, in order to be able to compensate the etch selectivity of the upper thin film 130 deposited at low temperature, the ratio of the source gas is increased compared to the ratio of the reactive gas, and the upper thin film 130 may be deposited at a pressure of 1.5 to 4 Torr. In addition, in this embodiment, in order to compensate the etching selectivity of the upper thin film 130 deposited at a low temperature, plasma treatment is performed at a low temperature zone by supplying only the reactive gas successively with the deposition of the upper thin film 130 . Accordingly, the surface properties of the upper thin film are modified, and etch selectivity is compensated.

另外，利用氫含量少的N2O氣體作為用於沉積所述上部薄膜的反應氣體，進而能夠更加補償蝕刻選擇比。 In addition, by using N 2 O gas with a low hydrogen content as the reaction gas for depositing the upper thin film, the etching selectivity can be further compensated.

另外，在本實施例中，在沉積上部薄膜130時與HF電源一同利用LF電源，可以補償熱能及離子反應效率，進而可追加補償上部薄膜130的蝕刻選擇比。 In addition, in this embodiment, the LF power source is used together with the HF power source when depositing the upper film 130 to compensate thermal energy and ion reaction efficiency, and further compensate the etching selectivity of the upper film 130 .

以上，舉較佳的實施例詳細說明了本發明，但是本發明不限於上述實施例，而是在該領域具有普通知識的人可在本發明的技術思想範圍內能夠進行各種變化。 As above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above-described embodiments, and those who have ordinary knowledge in this field can make various changes within the scope of the technical idea of the present invention.

S1~S3:步驟 S1~S3: steps

Claims (11)

一種薄膜沉積方法，為利用具有腔室的基板處理裝置的薄膜沉積方法，所述基板處理裝置包括：一腔室，將處理空間限定於內部；一基板支撐架，位於所述腔室的下部區域並且放置基板；一氣體供應部，位於所述腔室的上部區域，並且向所述基板供應源氣體及反應氣體；以及一供電部，將高頻及低頻電源供應於所述腔室，所述方法包括以下步驟：將包含在低溫帶的製程溫度條件下沉積的一下部薄膜的所述基板放置在所述基板支撐架上；在所述低溫帶的製程溫度條件下在電漿環境中在所述下部薄膜上部沉積一上部薄膜；以及在沉積所述上部薄膜的步驟之後，在所述低溫帶的製程溫度條件下在電漿環境中處理所述上部薄膜的表面，其中，所述低溫帶的製程溫度為100至250℃，其中，所述處理步驟為，供應所述反應氣體並在所述製程的腔室內部施加高頻及低頻來生成電漿的狀態下進行。 A thin film deposition method, which is a thin film deposition method using a substrate processing device having a chamber, the substrate processing device comprising: a chamber, which limits the processing space inside; a substrate support frame, located in the lower area of the chamber And place the substrate; a gas supply part, located in the upper area of the chamber, and supply source gas and reaction gas to the substrate; and a power supply part, supply high-frequency and low-frequency power to the chamber, the The method includes the following steps: placing the substrate containing a lower thin film deposited under the process temperature condition of the low temperature zone on the substrate supporting frame; depositing an upper film on top of the lower film; and after the step of depositing the upper film, treating the surface of the upper film in a plasma environment under the process temperature conditions of the low temperature zone, wherein the low temperature zone The process temperature is 100 to 250° C., wherein the process step is carried out under the condition that the reaction gas is supplied and high frequency and low frequency are applied inside the process chamber to generate plasma. 根據請求項1所述的薄膜沉積方法，其中，所述上部薄膜沉積步驟為在對所述基板上供應含矽的所述源氣體及含氮和氧的所述反應氣體，並在所述製程的腔室內部施加高頻及低頻以生成電漿的狀態下進行。 The thin film deposition method according to claim 1, wherein the upper thin film deposition step is to supply the source gas containing silicon and the reaction gas containing nitrogen and oxygen on the substrate, and during the process It is carried out in the state where high frequency and low frequency are applied inside the chamber to generate plasma. 根據請求項1所述的薄膜沉積方法，其中，所述上部薄膜沉積步驟為將所述源氣體對所述反應氣體的比例以1.2~2.5比1的比例供應。 The thin film deposition method according to claim 1, wherein, in the upper thin film deposition step, the ratio of the source gas to the reaction gas is supplied at a ratio of 1.2 to 2.5 to 1. 根據請求項1所述的薄膜沉積方法，其中，所述源氣體包含SiH4氣體。 The thin film deposition method according to claim 1, wherein the source gas comprises SiH 4 gas. 根據請求項1所述的薄膜沉積方法，其中，所述反應氣體包含N2O、NO中的任意一種。 The thin film deposition method according to claim 1, wherein the reaction gas contains any one of N 2 O and NO. 根據請求項1所述的薄膜沉積方法，其中，在沉積所述上部薄膜時，所述腔室內部的壓力為1.5至4.0Torr。 The thin film deposition method according to claim 1, wherein, when depositing the upper thin film, the pressure inside the chamber is 1.5 to 4.0 Torr. 根據請求項1所述的薄膜沉積方法，其中，所述上部薄膜包含氧氮化矽膜。 The thin film deposition method according to claim 1, wherein the upper thin film comprises a silicon oxynitride film. 根據請求項1所述的薄膜沉積方法，其中，在所述供電部中，所述高頻為中心頻寬在10MHz~40MHz的範圍，而所述低頻為所述中心頻寬在300kHz~500kHz的範圍。 The thin film deposition method according to claim 1, wherein, in the power supply unit, the high frequency is in the range of 10MHz to 40MHz in the center bandwidth, and the low frequency is in the range of 300kHz to 500kHz in the center bandwidth scope. 根據請求項1所述的薄膜沉積方法，其中，所述電漿處理步驟為與所述上部薄膜沉積步驟接連，且在停止供應所述源氣體的狀態下進行。 The thin film deposition method according to claim 1, wherein the plasma treatment step is carried out in succession to the upper thin film deposition step while supplying the source gas is stopped. 根據請求項1所述的薄膜沉積方法，其中，所述下部薄膜為非晶碳膜、氧化鈦膜或者SOG。 The thin film deposition method according to claim 1, wherein the lower thin film is an amorphous carbon film, a titanium oxide film or SOG. 一種半導體器件的製造方法，利用請求項1至9中任一項所述的薄膜沉積方法，所述方法包括以下步驟：在一半導體基板上部形成一基底層；在低溫帶的製程溫度下在所述基底層上部沉積與所述基底層具有蝕刻選擇比的一下部薄膜；在所述低溫帶的製程溫度下在所述下部薄膜上部沉積與所述下部薄膜具有蝕刻選擇比的一上部薄膜；電漿處理所述上部薄膜以形成一硬光罩；以及利用所述硬光罩將所述基底層圖案化，其中，所述低溫帶的製程溫度在100至250℃的範圍，其中，所述上部薄膜利用反應氣體及比所述反應氣體過量的源氣體沉積，以及所述電漿處理是供應所述反應氣體來進行。 A method for manufacturing a semiconductor device, using the film deposition method described in any one of Claims 1 to 9, the method comprising the following steps: forming a base layer on a semiconductor substrate; Depositing a lower film having an etching selectivity ratio with the base layer on the base layer; depositing an upper film having an etching selectivity ratio with the lower film at the process temperature of the low temperature zone; slurry processing the upper film to form a hard mask; and patterning the base layer using the hard mask, wherein the process temperature of the low temperature zone is in the range of 100 to 250° C., wherein the upper A thin film is deposited using a reactive gas and a source gas in excess of the reactive gas, and the plasma treatment is performed by supplying the reactive gas.
TW110123934A 2020-07-22 2021-06-28 Method of depositing thin film and method of manufacturing semiconductor device using the same TWI781667B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020200091046A KR20220012474A (en) 2020-07-22 2020-07-22 Method of Depositing Thin Film and Method of Manufacturing Semiconductor device Using The Same
KR10-2020-0091046 2020-07-22

Publications (2)

Publication Number Publication Date
TW202205384A TW202205384A (en) 2022-02-01
TWI781667B true TWI781667B (en) 2022-10-21

Family

ID=80220770

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110123934A TWI781667B (en) 2020-07-22 2021-06-28 Method of depositing thin film and method of manufacturing semiconductor device using the same

Country Status (4)

Country Link
US (1) US11967503B2 (en)
JP (1) JP7210647B2 (en)
KR (1) KR20220012474A (en)
TW (1) TWI781667B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116804270B (en) * 2023-08-29 2023-11-10 上海陛通半导体能源科技股份有限公司 Low-temperature deposition method and device preparation method of silicon dioxide film

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201330096A (en) * 2011-09-23 2013-07-16 Novellus Systems Inc Plasma activated conformal dielectric film deposition
TW201438062A (en) * 2013-03-15 2014-10-01 Applied Materials Inc An amorphous carbon deposition process using dual RF bias frequency applications
TW201828339A (en) * 2016-09-29 2018-08-01 美商蘭姆研究公司 Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing
TW201841214A (en) * 2017-02-01 2018-11-16 美商應用材料股份有限公司 Boron doped tungsten carbide for hardmask applications
TW201925519A (en) * 2017-11-28 2019-07-01 南韓商圓益Ｉｐｓ股份有限公司 Method of forming amorphous silicon layer

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2684942B2 (en) * 1992-11-30 1997-12-03 日本電気株式会社 Chemical vapor deposition method, chemical vapor deposition apparatus, and method for manufacturing multilayer wiring
JPH0955351A (en) * 1995-08-15 1997-02-25 Sony Corp Manufacture of semiconductor device
US20060258176A1 (en) * 1998-02-05 2006-11-16 Asm Japan K.K. Method for forming insulation film
JP3328230B2 (en) 1999-06-29 2002-09-24 山形日本電気株式会社 Method of manufacturing antireflection film by plasma CVD
US6835669B2 (en) * 2000-07-21 2004-12-28 Canon Sales Co., Inc. Film forming method, semiconductor device and semiconductor device manufacturing method
JP4035298B2 (en) * 2001-07-18 2008-01-16 キヤノン株式会社 Plasma processing method, semiconductor device manufacturing method, and semiconductor device
JP5289863B2 (en) 2008-08-28 2013-09-11 東京エレクトロン株式会社 Amorphous carbon nitride film forming method, multilayer resist film, semiconductor device manufacturing method, and storage medium storing control program
US9064693B2 (en) * 2010-03-01 2015-06-23 Kirsteen Mgmt. Group Llc Deposition of thin film dielectrics and light emitting nano-layer structures
US8993435B2 (en) * 2010-03-15 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Low-k Cu barriers in damascene interconnect structures
CN103299430A (en) * 2010-12-30 2013-09-11 周星工程股份有限公司 Thin-film transistor and method for manufacturing same
KR101740616B1 (en) * 2012-11-26 2017-05-26 가부시키가이샤 히다치 고쿠사이 덴키 Method for manufacturing semiconductor device, substrate processing device, and recording medium
US10347547B2 (en) * 2016-08-09 2019-07-09 Lam Research Corporation Suppressing interfacial reactions by varying the wafer temperature throughout deposition
KR20210075266A (en) 2019-12-12 2021-06-23 주식회사 원익아이피에스 Method for Deposition of Thin Film
KR20220021863A (en) * 2020-08-14 2022-02-22 에이에스엠 아이피 홀딩 비.브이. Method for processing a substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201330096A (en) * 2011-09-23 2013-07-16 Novellus Systems Inc Plasma activated conformal dielectric film deposition
TW201438062A (en) * 2013-03-15 2014-10-01 Applied Materials Inc An amorphous carbon deposition process using dual RF bias frequency applications
TW201828339A (en) * 2016-09-29 2018-08-01 美商蘭姆研究公司 Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing
TW201841214A (en) * 2017-02-01 2018-11-16 美商應用材料股份有限公司 Boron doped tungsten carbide for hardmask applications
TW201925519A (en) * 2017-11-28 2019-07-01 南韓商圓益Ｉｐｓ股份有限公司 Method of forming amorphous silicon layer

Also Published As

Publication number Publication date
KR20220012474A (en) 2022-02-04
JP2022022111A (en) 2022-02-03
TW202205384A (en) 2022-02-01
US20220028687A1 (en) 2022-01-27
US11967503B2 (en) 2024-04-23
JP7210647B2 (en) 2023-01-23

Similar Documents

Publication Publication Date Title
US20210222296A1 (en) Film-forming device and film-forming method
KR100557666B1 (en) Susceptor for supporting substrate and apparatus for depositing film comprising the same
JP6124477B2 (en) Semiconductor device manufacturing method, substrate processing apparatus, and recording medium
TWI609986B (en) Method of depositing a film, recording medium, and film deposition apparatus
JP4426642B2 (en) Atomic layer growth apparatus and atomic layer growth method
US20220165544A1 (en) Plasma processing device, and plasma processing method
JP2021520639A (en) Carbon hardmasks and related methods for patterning applications
TWI781667B (en) Method of depositing thin film and method of manufacturing semiconductor device using the same
JP2002353214A (en) Method for manufacturing semiconductor device
US9305795B2 (en) Plasma processing method
JP2015501551A (en) Thin film manufacturing method
KR102414099B1 (en) System For Processing Semiconductor substrate and Method of Depositing Thin Film Using The Same
KR20210097045A (en) Etching method, substrate processing apparatus, and substrate processing system
KR20170129234A (en) Defect flattening
WO2016046976A1 (en) Semiconductor device manufacturing method, substrate processing apparatus, and recording medium
KR20210075266A (en) Method for Deposition of Thin Film
KR20220017055A (en) Method of Depositing Thin Film and Method of Manufacturing Semiconductor device Using The Same
JP2003086568A (en) Method for etching
KR20230087681A (en) Thin film deposition apparatus and thin film deposition method using the same
KR20200025030A (en) Method of Fabricating Amorphous Silicon film
TWI819398B (en) Tensile nitride deposition systems and methods
KR20220036390A (en) Method of Depositing Thin Film and Method of Manufacturing Semiconductor device Using The Same
KR102179281B1 (en) Apparatus For Depositing Thin Film, System Having The Same And Method of Depositing The Thin Film
WO2021070682A1 (en) Substrate processing method and substrate processing device
WO2007123211A1 (en) METHOD FOR DEPOSITING Ti FILM

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent