TWI780776B - How to write the memory multiple times - Google Patents

How to write the memory multiple times Download PDF

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TWI780776B
TWI780776B TW110121899A TW110121899A TWI780776B TW I780776 B TWI780776 B TW I780776B TW 110121899 A TW110121899 A TW 110121899A TW 110121899 A TW110121899 A TW 110121899A TW I780776 B TWI780776 B TW I780776B
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TW202301325A (en
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溫柏崴
溫文瑩
汪鈺恒
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鈺成投資股份有限公司
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一種可多次編寫記憶的操作方法，包含：依據所執行的運算，控制輸入電壓的組合及時序；其中，當所要執行的運算是在被選擇的位元寫入1時，則各輸入電壓的操作順序是：先將EL電壓提升到VEL、然後再將BL電壓也提升到VPP；最後，將WL電壓提升到VPP；當所要執行的運算是在該位元寫入0時，則各輸入電壓的操作順序是：先將EL電壓提升到VEL、然後再將BL電壓也同樣提升到VPP；最後，將WL電壓提升到Ve；當所要執行的運算是讀取在該位元的儲存值時，則各輸入電壓是：EL電壓拉低到0V、然後再將BL電壓提升到VCC；最後，將WL電壓提升到VCC；其中，VPP ＞ VCC＞=VEL＞ Ve。An operation method capable of programming memory multiple times, including: controlling the combination and timing of input voltages according to the operation to be performed; wherein, when the operation to be performed is to write 1 in the selected bit, then each input voltage The operation sequence is: first raise the EL voltage to VEL, then raise the BL voltage to VPP; finally, raise the WL voltage to VPP; when the operation to be performed is to write 0 in this bit, each input voltage The operation sequence is: first raise the EL voltage to VEL, then raise the BL voltage to VPP; finally, raise the WL voltage to Ve; when the operation to be performed is to read the stored value in this bit, The input voltages are as follows: EL voltage is pulled down to 0V, then BL voltage is raised to VCC; finally, WL voltage is raised to VCC; wherein, VPP>VCC>=VEL>Ve.

Description

可多次編寫記憶體的操作方法How to operate memory that can be written multiple times

本發明係有關一種可多次編寫記憶體的操作方法。The invention relates to an operation method for reprogramming memory.

可多次編寫記憶體(Multiple-Times Programmable，MTP)係一種非揮發性的記憶體，它不僅提供了可根據用戶的需要多次重新編程和更新的功能，而且與其他形式的記憶體相比，它的成本和功耗也相對較低。基本上，它能夠支持高達 100 萬個週期，高寫入周期耐受性使其非常適合需要經常更新的應用設備。因此，也受到業界的廣泛的應用。Multiple-Times Programmable (MTP) is a non-volatile memory that not only provides functions that can be reprogrammed and updated multiple times according to the user's needs, but also compared with other forms of memory , and its cost and power consumption are relatively low. Basically, it is capable of supporting up to 1 million cycles, and the high write cycle tolerance makes it ideal for applications that require frequent updates. Therefore, it is also widely used in the industry.

MTP的架構通常採用浮閘(floating gate)技術，例如，美國專利號US8320180B2揭露一種基於浮閘的MTP架構，包含：一浮閘PMOS電晶體、一高壓NMOS電晶體、以及一N阱(N-well)電容；該浮閘PMOS電晶體包括形成存儲單元的第一端子的源極(source)、汲極(drain)和閘極(gate)。該高壓NMOS電晶體包括接地的源極、連接到PMOS電晶體的汲極的延伸汲極、以及形成存儲單元的第二端子的閘極。該N阱電容包括連接到PMOS電晶體的閘極的第一端和形成存儲單元的第三端的第二端。該浮閘PMOS電晶體可以存儲邏輯狀態。其控制電壓的不同組合可以施加到存儲單元的第一、第二和第三端子以達到編寫、禁止編寫、讀取和消除邏輯狀態等操作。The architecture of MTP usually adopts floating gate (floating gate) technology. For example, US Pat. well) capacitance; the floating-gate PMOS transistor includes a source, a drain and a gate forming a first terminal of the memory cell. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The N-well capacitor includes a first terminal connected to the gate of the PMOS transistor and a second terminal forming a third terminal of the memory cell. The floating-gate PMOS transistor can store logic states. Different combinations of its control voltages can be applied to the first, second, and third terminals of the memory cell to achieve programming, programming inhibit, reading, and clearing logic states.

參考圖1，圖1所示為現有一種常見的MTP單元(cell)架構示意圖。如圖1所示，該MTP 單元架構包含：一第一電晶體T1、一第二電晶體T2、一耦合電容C；其中，該第一電晶體T1的汲極與第二電晶體T2的源極連接；且該第一電晶體T1的閘極與該耦合電容C的一端連接；其中該第一電晶體T1的閘極係為一浮閘。在此結構下，習知的操作方法是將該第一電晶體T1的源極連接位元線(bit line、BL)、該第二電晶體T2的汲極連接選擇線(select line、SL)、該第二電晶體T2的閘極連接致能線(enable line、EL)、以及該耦合電容C的另一端連接字元線(word line，WL)，由此構成一習知四端點元件。Referring to FIG. 1 , FIG. 1 is a schematic diagram of an existing common MTP unit (cell) architecture. As shown in Figure 1, the MTP unit structure includes: a first transistor T1, a second transistor T2, and a coupling capacitor C; wherein, the drain of the first transistor T1 and the source of the second transistor T2 and the gate of the first transistor T1 is connected to one end of the coupling capacitor C; wherein the gate of the first transistor T1 is a floating gate. Under this structure, the known operation method is to connect the source of the first transistor T1 to a bit line (BL), and the drain of the second transistor T2 to a select line (SL). , the gate of the second transistor T2 is connected to the enable line (enable line, EL), and the other end of the coupling capacitor C is connected to the word line (word line, WL), thus forming a conventional four-terminal device .

然而，由於該耦合電容C的關係，所以將該耦合電容C的另一端連接WL線會影響編寫的效率。However, due to the relationship of the coupling capacitor C, connecting the other end of the coupling capacitor C to the WL line will affect the programming efficiency.

有鑑於此，如何在上述之MTP的架構下，藉由個輸入電壓的組合，提昇MTP操作運算的效率，實為本發明之目的。In view of this, it is the purpose of the present invention how to improve the efficiency of the MTP operation by combining the input voltages under the above-mentioned MTP framework.

本發明之主要目的，在於提供一種可多次編寫記憶體(MTP)的操作方法，可在現有MTP的架構下，藉由個輸入電壓的組合，提昇MTP操作運算的效率。The main purpose of the present invention is to provide an operation method for multi-programmable memory (MTP), which can improve the efficiency of MTP operation operation under the existing MTP framework by combining the input voltages.

為達成上述目的，本發明之一實施例揭露一種可多次編寫記憶體(MTP)的操作方法，適用於一種MTP架構，該MTP架構包含：一浮閘NMOS電晶體、一控制閘(control gate)NMOS電晶體、以及一耦合電容(coupled capacitor)；其中，該浮閘NMOS電晶體的汲極連接於位元線(bit line、BL)、閘極(floating gate、FG)連接該耦合電容的一端、 源極則連接該控制閘NMOS電晶體的汲極；該控制閘NMOS電晶體的閘極連接至字元線(word line，WL)、 源極則連接選擇線(select line、SL)；該耦合電容的另一端則連接到編寫/消除致能線(program/erase enable line、EL)；該方法包含：依據所要執行的運算，控制輸入電壓的組合以及時序；其中，當所要執行的運算是在該被選擇的位元寫入1時，則各輸入電壓的操作順序是：首先將EL電壓提升到VEL、然後再將BL電壓也同樣提升到VPP；最後，將WL電壓提升到VPP；當所要執行的運算是在該被選擇的位元寫入0時，則各輸入電壓的操作順序是：首先將EL電壓提升到VEL、然後再將BL電壓也同樣提升到VPP；最後，將WL電壓提升到Ve，Ve為該WL元件的門檻電壓；當所要執行的運算是讀取在該被選擇的位元的儲存值時，則各輸入電壓是：EL電壓拉低到0V、然後再將BL電壓提升到VCC；最後，將WL電壓提升到VCC；其中，VPP>VCC>=VEL>Ve。 In order to achieve the above object, an embodiment of the present invention discloses a method for operating a memory that can be programmed many times (MTP), which is suitable for an MTP architecture, and the MTP architecture includes: a floating gate NMOS transistor, a control gate (control gate) ) NMOS transistor, and a coupling capacitor (coupled capacitor); wherein, the drain of the floating gate NMOS transistor is connected to the bit line (bit line, BL), and the gate (floating gate, FG) is connected to the coupling capacitor One end and the source are connected to the drain of the control gate NMOS transistor; the gate of the control gate NMOS transistor is connected to the word line (word line, WL), and the source is connected to the select line (select line, SL); The other end of the coupling capacitor is connected to a program/erase enable line (program/erase enable line, EL); the method includes: controlling the combination and timing of the input voltage according to the operation to be performed; wherein, when the operation to be performed When the selected bit is written into 1, the operation sequence of each input voltage is: first raise the EL voltage to VEL, then raise the BL voltage to VPP; finally, raise the WL voltage to VPP; When the operation to be performed is to write 0 in the selected bit, the operation sequence of each input voltage is: first raise the EL voltage to VEL, then raise the BL voltage to VPP; finally, raise the WL voltage The voltage is raised to Ve, and Ve is the threshold voltage of the WL element; when the operation to be performed is to read the stored value in the selected bit, each input voltage is: the EL voltage is pulled down to 0V, and then the The BL voltage is raised to VCC; finally, the WL voltage is raised to VCC; among them, VPP>VCC>=VEL>Ve.

在一較佳實施例中，在該被選擇的位元寫入1時，WL電壓被提升到高壓VPP，此時係以熱電洞注入的方式編寫；在該被選擇的位元寫入0時，WL電壓僅被提升到Ve，該WL元件的門檻電壓，此時係以熱電子注入的方式編寫。 In a preferred embodiment, when the selected bit is written into 1, the WL voltage is raised to the high voltage VPP, which is programmed by hot hole injection; when the selected bit is written into 0 , the WL voltage is only raised to Ve, the threshold voltage of the WL element, which is programmed by thermal electron injection.

在一較佳實施例中，在讀取運算中，該BL電壓維持在VCC的區間涵蓋WL電壓維持在VCC的區間。 In a preferred embodiment, in the read operation, the period in which the BL voltage is maintained at VCC covers the period in which the WL voltage is maintained at VCC.

在一較佳實施例中，在寫入運算中，該EL電壓維持在VEL的區間涵蓋BL電壓維持在VPP的區間，而且BL電壓維持在VPP的區間涵蓋WL電壓維持在VPP或Ve的區間。 In a preferred embodiment, in the writing operation, the interval in which the EL voltage is maintained at VEL covers the interval in which the BL voltage is maintained at VPP, and the interval in which the BL voltage is maintained at VPP covers the interval in which the WL voltage is maintained at VPP or Ve.

以下係藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。本發明亦可藉由其他不同的具體實例加以施行或應用，本發明說明書中的各項細節亦可基於不同觀點與應用在不悖離本發明之精神下進行各種修飾與變更。The implementation of the present invention is described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various modifications and changes can be made to the details in the description of the present invention based on different viewpoints and applications without departing from the spirit of the present invention.

須知，本說明書所附圖式繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應落在本發明所揭示之技術內容得能涵蓋之範圍內。It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification for the understanding and reading of those who are familiar with this technology, and are not used to limit the implementation of the present invention. Conditions, so there is no technical substantive meaning, any modification of structure, change of proportional relationship or adjustment of size, without affecting the effect and purpose of the present invention, should fall within the scope of the present invention. The technical content can be covered within the range.

同時參考圖2、圖3、以及圖4；圖2所示為現有的MTP單元(cell)架構示意圖、圖3所示為圖2所示結構的半導體剖面示意圖、以及圖4所示為圖2所示結構的另一軸向的半導體剖面示意圖；圖3與圖4的軸向為正交。Referring to Fig. 2, Fig. 3, and Fig. 4 simultaneously; Fig. 2 shows a schematic diagram of an existing MTP unit (cell) architecture, Fig. 3 shows a schematic cross-sectional view of a semiconductor structure shown in Fig. 2, and Fig. 4 shows a schematic diagram of a structure shown in Fig. 2 A schematic cross-sectional view of another axial direction of the semiconductor structure shown; the axial directions of FIG. 3 and FIG. 4 are orthogonal.

如圖2所示，該MTP 單元架構包含：一浮閘NMOS電晶體201、一控制閘(control gate)NMOS電晶體202、以及一耦合電容(coupled capacitor) 203；其中，該浮閘NMOS電晶體201的汲極連接於位元線(bit line、BL)、閘極(floating gate、FG)連接該耦合電容203的一端、 源極則連接該控制閘NMOS電晶體202的汲極；該控制閘NMOS電晶體202的閘極連接至字元線(word line，WL)、源極則連接選擇線(select line、SL)；該耦合電容203的另一端則連接到編寫/消除致能線(program/erase enable line、EL)；因此，本架構形成一五個端點(BL、WL、SL、EL、P well)的原件，其中P  well係指該單元架構所在的P阱。再者，圖3、及圖4中之其他符號，例如，N+、CG、FG、STI、P substrate係半導體製程領域中常見的符號，分別代表N型高摻雜濃度區域、控制閘、浮閘、淺溝槽絕緣(Shallow Trench Isolation、STI)、以及P型基板，在此不在詳述。 As shown in FIG. 2, the MTP unit structure includes: a floating gate NMOS transistor 201, a control gate (control gate) NMOS transistor 202, and a coupling capacitor (coupled capacitor) 203; wherein, the floating gate NMOS transistor The drain of 201 is connected to the bit line (bit line, BL), the gate (floating gate, FG) is connected to one end of the coupling capacitor 203, and the source is connected to the drain of the control gate NMOS transistor 202; the control gate The gate of the NMOS transistor 202 is connected to the word line (word line, WL), and the source is connected to the select line (select line, SL); the other end of the coupling capacitor 203 is connected to the programming/erasing enabling line (program /erase enable line, EL); therefore, this structure forms an original of five endpoints (BL, WL, SL, EL, P well), where P well refers to the P well where the cell structure is located. Furthermore, other symbols in Fig. 3 and Fig. 4, for example, N+, CG, FG, STI, and P substrate are common symbols in the field of semiconductor manufacturing, which respectively represent N-type high doping concentration regions, control gates, and floating gates. , shallow trench insulation (Shallow Trench Isolation, STI), and P-type substrate, which will not be described in detail here.

此五端點元件可做為電子抹除式可複寫唯讀記憶體(​Electrically-Erasable Programmable Read-Only Memory，EEPROM)的一個記憶體單元來使用，亦即一位元(bit)；另一方面，此五端點元件架構亦可當作快閃記憶體(Flash)使用，並適用於全頁抹除的功能(page erase function)。This five-terminal device can be used as a memory unit of an Electrically-Erasable Programmable Read-Only Memory (EEPROM), that is, a bit; the other On the one hand, this five-terminal device structure can also be used as a flash memory (Flash), and is suitable for a full page erase function (page erase function).

值得說明的是，由於浮閘會延伸至N阱區域，因此浮閘跟所覆蓋的N阱區域就成為一個耦合電容。當一位元被選擇時，該合電容會將電壓耦合至浮閘，使得該位元被致能(enable)，能夠寫入1(write 1)、寫入0(write 0)、或者被讀取(read)。It is worth noting that since the floating gate extends to the N-well region, the floating gate and the covered N-well region become a coupling capacitor. When a bit is selected, the capacitor will couple the voltage to the floating gate, so that the bit is enabled (enable), can write 1 (write 1), write 0 (write 0), or be read Take (read).

圖5所示為適用於本發明的可多次編寫記憶體的架構應用於記憶體陣列(array)時的配置方式示意圖。如圖5所示，其中相鄰兩行及相鄰兩列的記憶體單元，係已背對背方式對設置，以利EL、BL、SL、以及WL等控制線的配置與共用。FIG. 5 is a schematic diagram of the configuration of the architecture of the reprogrammable memory applicable to the present invention when it is applied to a memory array (array). As shown in FIG. 5 , the memory cells in two adjacent rows and two adjacent columns are arranged in a back-to-back manner to facilitate the configuration and sharing of control lines such as EL, BL, SL, and WL.

值得注意的是，本發明的一種可多次編寫記憶體的操作方法與上述習知的操作方法的主要差異在於將習知的EL線與WL線對調；其主要原因在於提高編寫的效率。再者，由於EL線的耦合電容的存在，因此需要預先將EL線致能、以縮短其升壓的時間。It is worth noting that the main difference between the operation method of the present invention and the above-mentioned conventional operation method is that the conventional EL line and WL line are swapped; the main reason is to improve the efficiency of programming. Furthermore, due to the existence of the coupling capacitance of the EL line, it is necessary to enable the EL line in advance to shorten the boosting time of the EL line.

參考表1，表1所示為本發明之可多次編寫記憶體的操作方法的輸入電壓組合。 表1:   SL WL BL EL P Well   選擇 非選擇 選擇 非選擇 選擇 非選擇 選 擇 非選擇 選擇 非選擇 寫入0 0 0 Ve 0 Vpp F VEL 0 0 0 寫入1 0 0 VPP 0 Vpp F VEL 0 0 0 讀取 0 0 VCC 0 VCC F 0 0 0 0 Referring to Table 1, Table 1 shows the combination of input voltages for the operation method of the reprogrammable memory of the present invention. Table 1: SL WL BL EL P Well choose non-choice choose non-choice choose non-choice choose non-choice choose non-choice write 0 0 0 Ve 0 Vpp f VEL 0 0 0 write 1 0 0 VPP 0 Vpp f VEL 0 0 0 read 0 0 VCC 0 VCC f 0 0 0 0

如表1所示，當所要執行的運算是在該被選擇的位元寫入1時，則各輸入電壓的操作順序是：首先將EL電壓提升到VEL、然後再將BL電壓也同樣提升到VPP；最後，將WL電壓提升到VPP。As shown in Table 1, when the operation to be performed is to write 1 in the selected bit, the operation sequence of each input voltage is: first raise the EL voltage to VEL, and then raise the BL voltage to VEL in the same way. VPP; Finally, boost the WL voltage to VPP.

當所要執行的運算是在該被選擇的位元寫入0時，則各輸入電壓的操作順序是：首先將EL電壓提升到VEL、然後再將BL電壓也同樣提升到VPP；最後，將WL電壓提升到Ve，Ve為該WL元件的門檻電壓(threshold voltage)。 When the operation to be performed is to write 0 in the selected bit, the operation sequence of each input voltage is: first raise the EL voltage to VEL, then raise the BL voltage to VPP; finally, raise the WL voltage The voltage is raised to Ve, and Ve is the threshold voltage of the WL element.

換言之，寫入1或寫入0的運算，是在最後由WL的電壓控制；寫入1時，WL電壓提升到VPP；寫入0時，WL電壓提升到Ve。 In other words, the operation of writing 1 or writing 0 is finally controlled by the voltage of WL; when writing 1, the voltage of WL is raised to VPP; when writing 0, the voltage of WL is raised to Ve.

值得說明的是，在該被選擇的位元寫入1時，WL電壓被提升到高壓VPP，此時係以熱電洞注入(hot hole injection)的方式編寫；在該被選擇的位元寫入0時，WL電壓僅被提升到Ve，該WL元件的門檻電壓(threshold voltage)，此時係以熱電子注入(hot electron injection)的方式編寫。 It is worth noting that when the selected bit is written into 1, the WL voltage is raised to the high voltage VPP. At this time, it is written in the way of hot hole injection; when the selected bit is written At 0, the WL voltage is only raised to Ve, the threshold voltage of the WL element, which is programmed by hot electron injection.

當所要執行的運算是讀取在該被選擇的位元的儲存值時，則各輸入電壓是：EL電壓拉低到0V、然後再將BL電壓也提升到VCC；最後，將WL電壓提升到VCC。 When the operation to be performed is to read the stored value in the selected bit, each input voltage is: the EL voltage is pulled down to 0V, and then the BL voltage is also raised to VCC; finally, the WL voltage is raised to VCC.

值得說明的是，VPP>VCC>=VEL>Ve。 It is worth noting that VPP>VCC>=VEL>Ve.

圖6所示為依據表1的輸入電壓組合所對應的波形時序示意圖。如圖6所示，在讀取運算中，該BL電壓維持在VCC的區間涵蓋WL電壓維持在VCC的區間。同樣地，在寫入運算中，該EL電壓維持在VEL的區間涵蓋BL電壓維持在VPP的區間，而且BL電壓維持在VPP的區間涵蓋WL電壓維持在VPP或Ve的區間。 FIG. 6 is a schematic diagram of the timing sequence of waveforms corresponding to the input voltage combinations in Table 1. As shown in FIG. 6 , in the read operation, the interval in which the BL voltage is maintained at VCC covers the interval in which the WL voltage is maintained at VCC. Likewise, in the writing operation, the interval in which the EL voltage is maintained at VEL covers the interval in which the BL voltage is maintained at VPP, and the interval in which the BL voltage is maintained at VPP covers the interval in which the WL voltage is maintained at VPP or Ve.

明確地說，如同前述，由於耦合電容的存在，所以EL線的電壓提升必須要先於WL、以及BL；藉此提升效率。 Specifically, as mentioned above, due to the existence of the coupling capacitor, the voltage of the EL line must be raised before the WL and BL; thereby improving the efficiency.

綜而言之，本發明之一種可多次編寫記憶體的操作方法，透過各輸入電壓的操作順序及時序，預先將EL的電壓提升，藉以增加可多次編寫記憶體的運算編寫效率。To sum up, an operation method of the reprogrammable memory of the present invention increases the voltage of the EL in advance through the operation sequence and timing of each input voltage, so as to increase the operation programming efficiency of the reprogrammable memory.

然而，上述實施例僅例示性說明本發明之功效，而非用於限制本發明，任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修飾與改變。此外，在上述該些實施例中之元件的數量僅為例示性說明，亦非用於限制本發明。因此本發明之權利保護範圍，應如以下之申請專利範圍所列。However, the above-mentioned embodiments are only illustrative to illustrate the effects of the present invention, and are not intended to limit the present invention. Anyone skilled in this art can modify and change the above-mentioned embodiments without departing from the spirit and scope of the present invention. . In addition, the numbers of elements in the above-mentioned embodiments are only for illustrative purposes, and are not intended to limit the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application below.

201:浮閘NMOS電晶體 202:控制閘NMOS電晶體耦合電容 203:耦合電容 BL:位元線 C:耦合電容 EL:致能線 GND:接地 P substrate:P基板 P well:P阱 N well:N阱 SL:選擇線 STI:淺溝槽絕緣 T1:第一電晶體 T2:第二電晶體 VCC、VPP、VEL、Ve:電壓值 WL:字元線 201: Floating gate NMOS transistor 202: Control gate NMOS transistor coupling capacitor 203: Coupling capacitor BL: bit line C: Coupling capacitance EL: Enabling Line GND: ground P substrate: P substrate P well: P well N well: N well SL: selection line STI: Shallow Trench Insulation T1: first transistor T2: second transistor VCC, VPP, VEL, Ve: voltage value WL: character line

圖1所示為現有一種常見的MTP單元(cell)架構示意圖； 圖2所示為適用於本發明可多次編寫記憶體的編寫方法的MTP單元(cell)架構示意圖； 圖3所示為圖2所示結構的半導體剖面示意圖； 圖4所示為圖2所示結構的另一軸向的半導體剖面示意圖； 圖5所示為適用於本發明的MTP單元的架構應用於記憶體陣列時的配置方式示意圖； 圖6所示為依據表1的輸入電壓組合所對應的波形時序示意圖。 Figure 1 shows a schematic diagram of an existing common MTP unit (cell) architecture; Fig. 2 shows the schematic diagram of the MTP unit (cell) structure applicable to the writing method of the memory that can be written multiple times in the present invention; FIG. 3 is a schematic cross-sectional view of a semiconductor with the structure shown in FIG. 2; FIG. 4 is a schematic cross-sectional view of another axial semiconductor of the structure shown in FIG. 2; FIG. 5 is a schematic diagram of a configuration method when the architecture of the MTP unit applicable to the present invention is applied to a memory array; FIG. 6 is a schematic diagram of the timing sequence of waveforms corresponding to the input voltage combinations in Table 1.

EL:致能線 EL: Enabling Line

WL:字元線 WL: character line

BL:位元線 BL: bit line

SL:選擇線 SL: selection line

VCC、VPP、VEL、Ve:電壓值 VCC, VPP, VEL, Ve: voltage value

GND:接地 GND: ground

Claims (4)

一種可多次編寫記憶體(MTP)的操作方法，適用於一種MTP架構，該MTP架構包含：一浮閘NMOS電晶體、一控制閘(control gate)NMOS電晶體、以及一耦合電容(coupled capacitor)；其中，該浮閘NMOS電晶體的汲極連接於位元線(bit line、BL)、閘極(floating gate、FG)連接該耦合電容的一端、源極則連接該控制閘NMOS電晶體的汲極；該控制閘NMOS電晶體的閘極連接至字元線(word line，WL)、源極則連接選擇線(select line、SL)；該耦合電容的另一端則連接到編寫/消除致能線(program/erase enable line、EL)；該方法包含：依據所要執行的運算，控制輸入電壓的組合以及時序；其中，當所要執行的運算是在該被選擇的位元寫入1時，則各輸入電壓的操作順序是：首先將EL電壓提升到VEL、然後再將BL電壓也同樣提升到VPP；最後，將WL電壓提升到VPP；當所要執行的運算是在該被選擇的位元寫入0時，則各輸入電壓的操作順序是：首先將EL電壓提升到VEL、然後再將BL電壓也同樣提升到VPP；最後，將WL電壓提升到Ve，Ve該WL元件的門檻電壓；當所要執行的運算是讀取在該被選擇的位元的儲存值時，則各輸入電壓是：EL電壓拉低到0V、然後再將BL電壓提升到VCC；最後，將WL電壓提升到VCC；其中，VPP>VCC>=VEL>Ve。 A method of operating a memory that can be programmed many times (MTP), applicable to an MTP architecture, the MTP architecture includes: a floating gate NMOS transistor, a control gate (control gate) NMOS transistor, and a coupled capacitor (coupled capacitor ); wherein, the drain of the floating gate NMOS transistor is connected to the bit line (bit line, BL), the gate (floating gate, FG) is connected to one end of the coupling capacitor, and the source is connected to the control gate NMOS transistor The drain of the control gate NMOS transistor is connected to the word line (word line, WL), and the source is connected to the select line (select line, SL); the other end of the coupling capacitor is connected to the programming/erasing Enable line (program/erase enable line, EL); the method includes: according to the operation to be performed, control the combination and timing of the input voltage; wherein, when the operation to be performed is to write 1 in the selected bit , the operation sequence of each input voltage is: first raise the EL voltage to VEL, then raise the BL voltage to VPP; finally, raise the WL voltage to VPP; when the operation to be performed is in the selected bit When writing 0, the operation sequence of each input voltage is: first raise the EL voltage to VEL, then raise the BL voltage to VPP as well; finally, raise the WL voltage to Ve, Ve is the threshold voltage of the WL element ; When the operation to be performed is to read the stored value in the selected bit, each input voltage is: the EL voltage is pulled down to 0V, and then the BL voltage is raised to VCC; finally, the WL voltage is raised to VCC; where, VPP>VCC>=VEL>Ve. 如請求項1述之可多次編寫記憶體的操作方法，其中在該被選擇的位元寫入1時，WL電壓被提升到高壓VPP，此時係以熱電洞注入的方 式編寫；在該被選擇的位元寫入0時，WL電壓僅被提升到Ve，此時係以熱電子注入的方式編寫。 As described in claim item 1, the operation method of the memory that can be programmed multiple times, wherein when the selected bit is written into 1, the WL voltage is raised to the high voltage VPP, and at this time, the method of hot hole injection is used When the selected bit is written into 0, the WL voltage is only raised to Ve, and at this time it is written in the way of hot electron injection. 如請求項1述之可多次編寫記憶體的操作方法，其中在讀取運算中，該BL電壓維持在VCC的區間涵蓋WL電壓維持在VCC的區間。 The operation method of the reprogrammable memory as described in Claim 1, wherein in the read operation, the interval in which the voltage of BL is maintained at VCC covers the interval in which the voltage of WL is maintained at VCC. 如請求項1述之可多次編寫記憶體的操作方法，其中在寫入運算中，該EL電壓維持在VEL的區間涵蓋BL電壓維持在VPP的區間，而且BL電壓維持在VPP的區間涵蓋WL電壓維持在VPP或Ve的區間。 As described in claim item 1, the operation method of the memory that can be programmed multiple times, wherein in the writing operation, the range where the EL voltage is maintained at VEL covers the range where the BL voltage is maintained at VPP, and the range where the BL voltage is maintained at VPP covers WL The voltage is maintained in the range of VPP or Ve.
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TW430812B (en) * 1997-06-27 2001-04-21 Aplus Integrated Circuits Inc Node-precise voltage regulation for a MOS memory system
US20080054335A1 (en) * 2006-08-31 2008-03-06 Jin Hyo Jung Embedded NV Memory and Method of Manufacturing the Same
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CN104216665A (en) * 2014-09-01 2014-12-17 上海新储集成电路有限公司 Storage management method of multi-layer unit solid state disk

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW430812B (en) * 1997-06-27 2001-04-21 Aplus Integrated Circuits Inc Node-precise voltage regulation for a MOS memory system
US20080054335A1 (en) * 2006-08-31 2008-03-06 Jin Hyo Jung Embedded NV Memory and Method of Manufacturing the Same
US20120170352A1 (en) * 2010-12-29 2012-07-05 Stmicroelectronics Pte Ltd. Thermo programmable resistor based rom
CN104216665A (en) * 2014-09-01 2014-12-17 上海新储集成电路有限公司 Storage management method of multi-layer unit solid state disk

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