TWI779990B - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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TWI779990B
TWI779990B TW111101688A TW111101688A TWI779990B TW I779990 B TWI779990 B TW I779990B TW 111101688 A TW111101688 A TW 111101688A TW 111101688 A TW111101688 A TW 111101688A TW I779990 B TWI779990 B TW I779990B
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etching
layer
region
semiconductor device
mask layer
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TW111101688A
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TW202329210A (en
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蘇品源
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南亞科技股份有限公司
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Priority to CN202210271095.5A priority patent/CN116490061A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Die Bonding (AREA)

Abstract

A method of manufacturing semiconductor device, includes: forming a mask layer on a stacked structure, in which the mask layer has a first area and a second area, the second area has a patterned structure; etching openings on the stacked structure through the patterned structure, in which an etching residue accumulates on the first area; filling a filling layer in the openings; doping the first area of the mask layer; removing the etching residue and the filling layer through an selective etching procedure; and removing the mask layer.

Description

製作半導體元件的方法Method of making semiconductor element

本揭露是有關於一種製作半導體元件的方法。The present disclosure relates to a method for manufacturing a semiconductor device.

現今半導體製程中製作電容結構時包含透過蝕刻製程製作具有高深寬比的開口。蝕刻製程實質上包含在堆疊結構上方形成一層具有圖案化的遮罩，再根據遮罩圖案蝕刻堆疊結構。然而，由於在蝕刻過程中被移除的堆疊結構的部分材料將會堆積在遮罩層上方使部分遮罩覆蓋的區域厚度增加，導致不能在後續通過一般的等向性蝕刻製程直接移除遮罩。Fabrication of capacitor structures in today's semiconductor manufacturing process involves forming openings with high aspect ratios through etching processes. The etching process essentially includes forming a patterned mask on the stack structure, and then etching the stack structure according to the mask pattern. However, since part of the material of the stack structure removed during the etching process will accumulate on the mask layer, the thickness of the area covered by the partial mask will increase, so that the mask cannot be directly removed by a general isotropic etching process. cover.

因此，如何提出一種可解決上述問題的製作半導體元件的方法，是目前業界亟欲投入研發資源解決的問題之一。Therefore, how to propose a method for manufacturing semiconductor elements that can solve the above-mentioned problems is one of the problems that the industry is eager to invest in research and development resources to solve.

有鑑於此，本揭露之一目的在於提出一種可有效解決上述問題的製作半導體元件的方法。In view of this, one purpose of the present disclosure is to provide a method for manufacturing a semiconductor device that can effectively solve the above problems.

本揭露是有關於一種製作半導體元件的方法，包含：形成遮罩層在堆疊結構上，其中遮罩層具有第一區域以及第二區域，第二區域具有圖案化結構；透過圖案化結構在堆疊結構上蝕刻出開口，其中蝕刻殘物堆積於第一區域上；填充填充層在開口中；摻雜遮罩層的第一區域；藉由選擇性蝕刻製程移除蝕刻殘物以及填充層；以及移除遮罩層。The present disclosure relates to a method of manufacturing a semiconductor device, comprising: forming a mask layer on a stacked structure, wherein the mask layer has a first region and a second region, and the second region has a patterned structure; through the patterned structure, the stacked Etching an opening on the structure, wherein the etching residue is deposited on the first region; filling the filling layer in the opening; doping the first region of the mask layer; removing the etching residue and the filling layer by a selective etching process; and Remove the mask layer.

在目前一些實施方式中，堆疊結構包含氧化層以及氮化層，並且透過圖案化結構在堆疊結構上蝕刻出開口的步驟係使得氧化層以及氮化層的每一者的至少一表面被暴露。In some current embodiments, the stack structure includes an oxide layer and a nitride layer, and the step of etching an opening on the stack structure through the patterned structure exposes at least one surface of each of the oxide layer and the nitride layer.

在目前一些實施方式中，填充填充層在開口中的步驟係使得填充層覆蓋遮罩層的第二區域。In some current embodiments, the step of filling the opening with the filling layer is such that the filling layer covers the second region of the mask layer.

在目前一些實施方式中，填充填充層在開口中的步驟係使得填充層與蝕刻殘物相對於遮罩層的高度實質上相同。In some current embodiments, the step of filling the opening with the filling layer is such that the heights of the filling layer and the etching residue relative to the mask layer are substantially the same.

在目前一些實施方式中，摻雜遮罩層的第一區域的步驟包含在第一區域形成p型摻雜物。In some current embodiments, the step of doping the first region of the mask layer includes forming a p-type dopant in the first region.

在目前一些實施方式中，藉由選擇性蝕刻製程移除蝕刻殘物以及填充層的步驟係使用第一蝕刻配方，且p型摻雜物適於抵抗第一蝕刻配方之蝕刻。In some current embodiments, the step of removing the etch residue and the filling layer by the selective etching process uses the first etching recipe, and the p-type dopant is suitable for resisting the etching of the first etching recipe.

在目前一些實施方式中，第一蝕刻配方包含HBr、He以及O 2中的至少一者。 In some current embodiments, the first etching recipe includes at least one of HBr, He and O 2 .

在目前一些實施方式中，製作半導體元件的方法進一步包含在藉由選擇性蝕刻製程移除蝕刻殘物以及填充層的步驟之前，摻雜蝕刻殘物。In some current embodiments, the method for manufacturing a semiconductor device further includes doping the etching residue before the step of removing the etching residue and the filling layer by a selective etching process.

在目前一些實施方式中，摻雜蝕刻殘物的步驟包含在蝕刻殘物形成n型摻雜物。In some current embodiments, the step of doping the etch residue includes forming an n-type dopant in the etch residue.

在目前一些實施方式中，移除遮罩層的步驟係使用第二蝕刻配方，並且第二蝕刻配方與第一蝕刻配方不同。In some present embodiments, the step of removing the mask layer uses a second etching recipe, and the second etching recipe is different from the first etching recipe.

綜上所述，於本揭露的製作半導體元件的方法中，利用選擇性蝕刻配方搭配針對適當區域進行不同種類的摻雜（例如對遮罩層的第一區域進行p型摻雜以及對蝕刻殘物進行n型摻雜），以更完整的移除蝕刻殘物並且保護遮罩層，以及被蝕刻殘物覆蓋的部分遮罩層以及堆疊材料，避免因為過度蝕刻所造成的損耗。進一步來說，第一蝕刻配方不會對p型蝕刻物蝕刻，進一步加強了摻雜後的遮罩層的保護力，並且第一蝕刻配方針對n型蝕刻物有顯著蝕刻率，也同時提升了移除蝕刻殘物的速率。此外，藉由填充填充層並覆蓋堆疊材料以在移除蝕刻殘物的同時保護其他未被蝕刻殘物覆蓋的部分堆疊材料。由於前述選擇性蝕刻移除蝕刻殘物以及填充層，使得在後續執行的移除遮罩層的非選擇性蝕刻能夠更好的被控制，以避免過度蝕刻損耗堆疊結構。To sum up, in the method for manufacturing a semiconductor device disclosed in the present disclosure, the selective etching formula is used to perform different types of doping on appropriate regions (such as p-type doping on the first region of the mask layer and etching residue n-type doping) to remove the etching residue more completely and protect the mask layer, as well as the part of the mask layer covered by the etching residue and the stacking material, to avoid loss caused by over-etching. Furthermore, the first etching formula will not etch the p-type etchant, which further strengthens the protection of the doped mask layer, and the first etching formula has a significant etch rate for the n-type etchant, which also improves the The rate at which etch residue is removed. In addition, by filling the filling layer and covering the stacking material, other parts of the stacking material not covered by the etching residue are protected while removing the etching residue. Since the aforementioned selective etching removes the etching residue and the filling layer, the subsequent non-selective etching for removing the mask layer can be better controlled to avoid excessive etching damage to the stack structure.

以下揭露內容提供用於實施所提供標的之不同特徵的許多不同實施例或實例。以下描述部件及佈置之特定實例以簡化本揭露。當然，此些僅為實例，且並不意欲為限制性的。舉例而言，在如下描述中第一特徵在第二特徵之上或在第二特徵上形成可包括其中第一特徵與第二特徵形成為直接接觸之實施例，且亦可包括其中額外特徵可在第一特徵與第二特徵之間形成而使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複係出於簡化及清楚目的，且其自身並不表示所論述之各種實施例及/或配置之間的關係。The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only, and are not intended to be limiting. For example, in the following description a first feature is formed on or on a second feature may include embodiments where the first feature is formed in direct contact with the second feature, and may also include embodiments where additional features may be An embodiment formed between a first feature and a second feature such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat element symbols and/or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

另外，為了描述簡單，可在本文中使用諸如「在……下面」、「在……下方」、「下部」、「在……上方」、「上部」及其類似術語之空間相對術語，以描述如諸圖中所示的一個元件或特徵與另一（另外）元件或特徵的關係。除了諸圖中所描繪之定向以外，此些空間相對術語意欲涵蓋元件在使用中或操作中之不同定向。裝置可以其他方式定向（旋轉90度或以其他定向），且可同樣相應地解釋本文中所使用之空間相對描述詞。Additionally, for simplicity of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and similar terms may be used herein to describe Describes the relationship of one element or feature to another (further) element or feature as shown in the figures. Such spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

本文中使用的「大約」、「約」、「近似」或者「實質上」一般表示落在給定值或範圍的百分之二十之中，或在百分之十之中，或在百分之五之中。本文中所給予的數字量值為近似值，表示使用的術語如「大約」、「約」、「近似」或者「實質上」在未明確說明時可以被推斷。As used herein, "approximately", "approximately", "approximately" or "substantially" means falling within twenty percent, or within ten percent, or within one hundred percent of a given value or range Five out of five. Numerical quantities given herein are approximations, meaning that terms such as "about," "about," "approximately," or "substantially" can be inferred when not expressly stated otherwise.

第1圖為根據本揭露之一些實施例繪示的製作半導體元件的方法M1之流程圖。請參照第1圖，一種製作半導體元件的方法M1，包含：形成遮罩層在堆疊結構上，其中遮罩層具有第一區域以及第二區域，第二區域具有圖案化結構(步驟S101)；透過圖案化結構在堆疊結構上蝕刻出開口，其中蝕刻殘物堆積於第一區域上(步驟S102)；填充填充層在開口中(步驟S103)；摻雜遮罩層的第一區域(步驟S104)；藉由選擇性蝕刻製程移除蝕刻殘物以及填充層(步驟S105)；以及移除遮罩層(步驟S106)。有關於每一個步驟的細節將會在下文中逐一被說明。FIG. 1 is a flowchart of a method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Please refer to FIG. 1, a method M1 for manufacturing a semiconductor element, comprising: forming a mask layer on the stacked structure, wherein the mask layer has a first region and a second region, and the second region has a patterned structure (step S101); Etching an opening on the stacked structure through the patterned structure, wherein the etching residue is accumulated on the first region (step S102); filling the filling layer in the opening (step S103); doping the first region of the mask layer (step S104 ); removing the etch residue and the filling layer by a selective etching process (step S105); and removing the mask layer (step S106). Details about each step will be explained one by one below.

第2A圖為根據本揭露之一些實施例繪示的半導體元件的方法M1的其中一個階段的剖面示意圖。請參照第1圖以及第2A圖，在一些實施例中，堆疊結構110包含氧化層112以及氮化層114，並且氮化層114被形成在氧化層112上方，但本揭露並不僅限於此。堆疊結構110可以根據需要由多個層或不同材料而被組成。在步驟S101中，遮罩層120被形成在堆疊結構110上，並且完全覆蓋堆疊結構110的頂表面。具體來說，在第2A圖的實施例中，遮罩層120完全覆蓋氮化層114的頂表面。然而，遮罩層120也可以根據需要僅覆蓋部分的堆疊結構110的頂表面。FIG. 2A is a schematic cross-sectional view of one stage of a method M1 of a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1 and FIG. 2A, in some embodiments, the stack structure 110 includes an oxide layer 112 and a nitride layer 114, and the nitride layer 114 is formed on the oxide layer 112, but the present disclosure is not limited thereto. The stack structure 110 may be composed of multiple layers or different materials as required. In step S101 , the mask layer 120 is formed on the stack structure 110 and completely covers the top surface of the stack structure 110 . Specifically, in the embodiment of FIG. 2A , the mask layer 120 completely covers the top surface of the nitride layer 114 . However, the mask layer 120 may also only cover part of the top surface of the stacked structure 110 as required.

第2B圖為根據本揭露之一些實施例繪示的半導體元件的方法M1的其中一個階段的剖面示意圖。在第2B圖繪示的實施例中，遮罩層120具有第一區域120a以及第二區域120b，並且第二區域120b具有圖案化結構。具體來說，當遮罩層120如第2A圖被形成於堆疊結構110上之後，可以在遮罩層120的部分區域(例如，第二區域120b)形成圖案化結構。第一區域120a以及第二區域120b在遮罩層120上的分布面積並未限制，可以依需求調整。在一些實施例中，第二區域120b的圖案化結構將會在後續步驟中成為形塑下方堆疊結構110的根據。FIG. 2B is a schematic cross-sectional view of one stage of the method M1 of the semiconductor device according to some embodiments of the present disclosure. In the embodiment shown in FIG. 2B, the mask layer 120 has a first region 120a and a second region 120b, and the second region 120b has a patterned structure. Specifically, after the mask layer 120 is formed on the stacked structure 110 as shown in FIG. 2A , a patterned structure may be formed in a partial region of the mask layer 120 (eg, the second region 120 b ). The distribution areas of the first region 120a and the second region 120b on the mask layer 120 are not limited, and can be adjusted according to requirements. In some embodiments, the patterned structure of the second region 120 b will be the basis for shaping the underlying stacked structure 110 in subsequent steps.

第2C圖為根據本揭露之一些實施例繪示的半導體元件的方法M1的其中一個階段的剖面示意圖。請參照第1圖以及第2C圖，步驟S102在堆疊結構110上蝕刻出開口140，其中蝕刻殘物130堆積於第一區域120a上。堆疊結構110在對應遮罩層120第二區域120b的圖案化結構處形成多個開口140。在一些實施例中，步驟S102係使得氧化層112以及氮化層114的每一者的至少一表面被開口140暴露，但本揭露並不以此為限。具體來說，這些開口140的內壁暴露了氧化層112以及氮化層114的一部分表面。然而，開口140也可以只暴露堆疊結構110中部分的特定層(例如，開口140可以只暴露氮化層114的部分表面)，開口140暴露的部位需取決於堆疊結構110的設計需求。在其他實施例中，組成堆疊結構110的其他多個層皆可以被開口140暴露。在第2C圖中，步驟S102的蝕刻製程被執行後，將產生蝕刻殘物130堆積於第一區域120a上。蝕刻殘物130的形成來源於堆疊結構110在蝕刻過程中被移除的部分，這些被移除的材料離開開口140之後被累積在第一區域120a上，並完全或部分地覆蓋遮罩層120的第一區域120a。FIG. 2C is a schematic cross-sectional view of one stage of the method M1 of the semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1 and FIG. 2C , step S102 etches an opening 140 on the stacked structure 110 , wherein the etching residue 130 is accumulated on the first region 120 a. The stack structure 110 forms a plurality of openings 140 at the patterned structure corresponding to the second region 120 b of the mask layer 120 . In some embodiments, step S102 is such that at least one surface of each of the oxide layer 112 and the nitride layer 114 is exposed by the opening 140 , but the present disclosure is not limited thereto. Specifically, the inner walls of the openings 140 expose part of the surfaces of the oxide layer 112 and the nitride layer 114 . However, the opening 140 may only expose part of a specific layer in the stack structure 110 (for example, the opening 140 may only expose part of the surface of the nitride layer 114 ), and the exposed portion of the opening 140 depends on the design requirements of the stack structure 110 . In other embodiments, other multiple layers constituting the stacked structure 110 may be exposed by the opening 140 . In FIG. 2C, after the etching process in step S102 is performed, etching residues 130 will be accumulated on the first region 120a. The etching residue 130 is formed from the part of the stack structure 110 that is removed during the etching process, and these removed materials are accumulated on the first region 120 a after leaving the opening 140 , and completely or partially cover the mask layer 120 The first region 120a.

第2D圖為根據本揭露之一些實施例繪示的半導體元件的方法M1的其中一個階段的剖面示意圖。請參照第1圖以及第2D圖，步驟S103中填充層150被填充在開口140中。在一些實施例中，步驟S103係使得填充層150覆蓋遮罩層120的第二區域120b。具體來說，填充層150將完全覆蓋遮罩層120的第二區域120b，但是本揭露並不以此為限。在其他一些實施例中，填充層150可以僅覆蓋部分的第二區域120b。此外，在一些實施例中，步驟S103係使得填充層150與蝕刻殘物130相對於遮罩層120的高度實質上相同。具體來說，填充層150的目的在於使遮罩層120被蝕刻殘物130所覆蓋的第一區域120a與第二區域120b齊平，其原因在於，填充層150可以在後續步驟中保護其所覆蓋的堆疊結構110。在後續移除蝕刻殘物130的步驟時，填充層150可以最小化地減少遮罩層120未被蝕刻殘物130被覆蓋的部分(例如，第二區域120b)在移除的步驟中被耗損。FIG. 2D is a schematic cross-sectional view of one stage of the method M1 of the semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1 and FIG. 2D , the filling layer 150 is filled in the opening 140 in step S103 . In some embodiments, step S103 is to make the filling layer 150 cover the second region 120 b of the mask layer 120 . Specifically, the filling layer 150 will completely cover the second region 120b of the mask layer 120, but the present disclosure is not limited thereto. In some other embodiments, the filling layer 150 may only cover part of the second region 120b. In addition, in some embodiments, step S103 is to make the heights of the filling layer 150 and the etching residue 130 relative to the mask layer 120 substantially the same. Specifically, the purpose of the filling layer 150 is to make the first region 120a of the mask layer 120 covered by the etching residue 130 flush with the second region 120b. Covered stack structure 110 . During the subsequent step of removing the etching residue 130, the filling layer 150 can minimize the loss of the portion of the mask layer 120 not covered by the etching residue 130 (for example, the second region 120b) during the removal step. .

第2E圖為根據本揭露之一些實施例繪示的半導體元件的方法M1的其中一個階段的剖面示意圖。請參照第1圖以及第2E圖，步驟S104摻雜了遮罩層120的第一區域120a，形成了摻雜區域122。在一些實施例中，步驟S104包含在第一區域120a形成p型摻雜物。具體來說，步驟S104可以藉由離子佈植製程被執行，但其他合適的方式皆可以被利用對第一區域120a進行摻雜。藉由離子佈植將摻雜物打入材料中特定深度的位置(例如，被蝕刻殘物130所覆蓋的遮罩層120的第一區域120a中)，以此摻雜材料特定深度中的區域。於離子佈植中可以使用任意的第三族材料（例如，硼、鋁、鎵、銦等）以形成p型摻雜物。FIG. 2E is a schematic cross-sectional view of one stage of the method M1 of the semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1 and FIG. 2E , in step S104 , the first region 120 a of the mask layer 120 is doped to form a doped region 122 . In some embodiments, step S104 includes forming p-type dopants in the first region 120a. Specifically, step S104 can be performed by an ion implantation process, but other suitable methods can be used to dope the first region 120a. Implanting dopants into the material at a specific depth (for example, in the first region 120a of the mask layer 120 covered by the etch residue 130 ) by ion implantation, thereby doping the material at a specific depth . Any Group III material (eg, boron, aluminum, gallium, indium, etc.) can be used in ion implantation to form p-type dopants.

第2F圖為根據本揭露之一些實施例繪示的半導體元件的方法M1的其中一個階段的剖面示意圖。請參照第1圖以及第2F圖，步驟S105中選擇性蝕刻製程被執行以移除蝕刻殘物130以及填充層150。在一些實施例中，步驟S105係使用第一蝕刻配方，且p型摻雜物適於抵抗第一蝕刻配方之蝕刻。進一步來說，第一蝕刻配方包含HBr、He以及O 2中的至少一者。具體來說，第一蝕刻配方針對蝕刻材料具有選擇性，並且第一蝕刻配方不會針對p型摻雜物進行蝕刻，因此被摻雜區域122覆蓋的堆疊結構110將不會因為步驟S105的蝕刻製程而受到損耗。藉由步驟S105可以移除蝕刻殘物130以及填充層150，並暴露出開口140以及遮罩層120的第一區域120a以及第二區域120b。 FIG. 2F is a schematic cross-sectional view of one stage of the method M1 of the semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1 and FIG. 2F , a selective etching process is performed in step S105 to remove the etching residue 130 and the filling layer 150 . In some embodiments, step S105 uses the first etching recipe, and the p-type dopant is suitable for resisting the etching of the first etching recipe. Further, the first etching recipe includes at least one of HBr, He and O 2 . Specifically, the first etching formula is selective for the etching material, and the first etching formula will not etch the p-type dopant, so the stacked structure 110 covered by the doped region 122 will not be affected by the etching in step S105. Lost due to process. The etching residue 130 and the filling layer 150 can be removed by step S105 , and the opening 140 and the first region 120 a and the second region 120 b of the mask layer 120 are exposed.

在另外一些實施例中，方法M1進一步包含在步驟S105之前摻雜蝕刻殘物130。進一步來說，摻雜蝕刻殘物130的步驟包含在蝕刻殘物130形成n型摻雜物。承前一個段落中說明的包含HBr、He以及O 2中的至少一者的第一蝕刻配方，其特別適用於蝕刻n型摻雜物。一般來說，可以藉由離子佈植製程以摻雜蝕刻殘物130，然而其他合適的方法也可以被使用。在執行步驟S105前先摻雜蝕刻殘物130可以進一步提升移除蝕刻殘物130的效率，其原因在於，藉由針對n型摻雜物具有高選擇性的第一蝕刻配方移除摻雜後的蝕刻殘物130，將可以提升對蝕刻殘物130的蝕刻速度。 In some other embodiments, the method M1 further includes doping the etching residue 130 before step S105 . Further, the step of doping the etching residue 130 includes forming n-type dopant in the etching residue 130 . The first etch recipe described in the previous paragraph comprising at least one of HBr, He, and O2 is particularly suitable for etching n-type dopants. Generally, the etch residue 130 can be doped by an ion implantation process, but other suitable methods can also be used. Doping the etch residue 130 before performing step S105 can further improve the efficiency of removing the etch residue 130 because, after removing the dopant by the first etching recipe with high selectivity for the n-type dopant The etching residue 130 can increase the etching rate of the etching residue 130 .

第2G圖為根據本揭露之一些實施例繪示的半導體元件的方法M1的其中一個階段的剖面示意圖。請參照第1圖以及第2G圖，在移除蝕刻殘物130以及填充層150之後，遮罩層120以及開口140內壁所暴露的氧化層112以及氮化層114皆再次被暴露。在步驟S106中，遮罩層120被移除。在一些實施例中，步驟S106係使用第二蝕刻配方，並且第二蝕刻配方與第一蝕刻配方不同。具體來說，步驟S106以非選擇性蝕刻製程被執行。第二蝕刻配方針對蝕刻材料並不具有選擇性，因此將會均一的移除遮罩層120的各個部位（例如，第一區域120a以及第二區域120b）。由於蝕刻殘物130於前述步驟中被移除，因此步驟S106可以更好地控制蝕刻過程，以避免在執行蝕刻移除或損耗堆疊結構110。FIG. 2G is a schematic cross-sectional view of one stage of the method M1 of the semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1 and FIG. 2G , after removing the etching residue 130 and the filling layer 150 , the oxide layer 112 and the nitride layer 114 exposed on the inner wall of the mask layer 120 and the opening 140 are exposed again. In step S106, the mask layer 120 is removed. In some embodiments, step S106 uses a second etching recipe, and the second etching recipe is different from the first etching recipe. Specifically, step S106 is performed by a non-selective etching process. The second etching recipe is not selective to the etching material, and thus will uniformly remove various parts of the mask layer 120 (eg, the first region 120 a and the second region 120 b ). Since the etching residue 130 is removed in the previous steps, the etching process can be better controlled in step S106 to avoid removal or loss of the stacked structure 110 during etching.

第2H圖為根據本揭露之一些實施例繪示的半導體元件的方法M1的其中一個階段的剖面示意圖。第2H圖繪示具有開口140的堆疊結構110，透過前述步驟S101至步驟S106可以進一步降低因移除遮罩層120(請參照第2A圖至第2G圖)致使對堆疊結構110的損耗，以更完整的保留堆疊結構110，不影響堆疊結構110預期的效能。FIG. 2H is a schematic cross-sectional view of one stage of the method M1 of the semiconductor device according to some embodiments of the present disclosure. FIG. 2H shows a stacked structure 110 with an opening 140. Through the aforementioned steps S101 to S106, the loss to the stacked structure 110 caused by removing the mask layer 120 (please refer to FIG. 2A to FIG. 2G ) can be further reduced, so that The stack structure 110 is preserved more completely without affecting the expected performance of the stack structure 110 .

以上對於本揭露之具體實施方式之詳述，可以明顯地看出，於本揭露的製作半導體元件的方法中，利用選擇性蝕刻配方搭配針對適當區域進行不同種類的摻雜（例如對遮罩層的第一區域進行p型摻雜以及對蝕刻殘物進行n型摻雜），以更完整的移除蝕刻殘物並且保護遮罩層，以及被蝕刻殘物覆蓋的部分遮罩層以及堆疊材料，避免因為過度蝕刻所造成的損耗。進一步來說，第一蝕刻配方不會對p型蝕刻物蝕刻，進一步加強了摻雜後的遮罩層的保護力，並且第一蝕刻配方針對n型蝕刻物有顯著蝕刻率，也同時提升了移除蝕刻殘物的速率。此外，藉由填充填充層並覆蓋堆疊材料以在移除蝕刻殘物的同時保護其他未被蝕刻殘物覆蓋的部分堆疊材料。由於前述選擇性蝕刻移除蝕刻殘物以及填充層，使得在後續執行的移除遮罩層的非選擇性蝕刻能夠更好的被控制，以避免過度蝕刻損耗堆疊結構。From the above detailed description of the specific implementation of the present disclosure, it can be clearly seen that in the method of manufacturing a semiconductor device disclosed in the present disclosure, the selective etching formula is used to carry out different types of doping for appropriate regions (for example, for the mask layer P-type doping of the first region and n-type doping of the etch residue) to remove the etch residue more completely and protect the mask layer, as well as the part of the mask layer covered by the etch residue and the stacking material , to avoid loss caused by over-etching. Furthermore, the first etching formula will not etch the p-type etchant, which further strengthens the protection of the doped mask layer, and the first etching formula has a significant etch rate for the n-type etchant, which also improves the The rate at which etch residue is removed. In addition, by filling the filling layer and covering the stacking material, other parts of the stacking material not covered by the etching residue are protected while removing the etching residue. Since the aforementioned selective etching removes the etching residue and the filling layer, the subsequent non-selective etching for removing the mask layer can be better controlled to avoid excessive etching damage to the stack structure.

前文概述了若干實施例之特徵，使得熟習此項技術者可較佳地理解本揭露之態樣。熟習此項技術者應瞭解，他們可容易地使用本揭露作為設計或修改用於實現相同目的及/或達成本文中所介紹之實施例之相同優勢的其他製程及結構的基礎。熟習此項技術者亦應認識到，此些等效構造不脫離本揭露之精神及範疇，且他們可在不脫離本揭露之精神及範疇的情況下於本文作出各種改變、代替及替換。The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and substitutions herein without departing from the spirit and scope of the present disclosure.

110:堆疊結構 112:氧化層 114:氮化層 120:遮罩層 120a:第一區域 120b:第二區域 122:摻雜區域 130:蝕刻殘物 140:開口 150:填充層 M1:方法 S101,S102,S103,S104,S105,S106:步驟110:Stack structure 112: oxide layer 114: Nitriding layer 120: mask layer 120a: first area 120b: Second area 122: Doped area 130: etch residue 140: opening 150: filling layer M1: method S101, S102, S103, S104, S105, S106: steps

當結合隨附諸圖閱讀時，得以自以下詳細描述最佳地理解本揭露之態樣。應注意，根據行業上之標準實務，各種特徵未按比例繪製。事實上，為了論述清楚，可任意地增大或減小各種特徵之尺寸。 第1圖為根據本揭露之一些實施例繪示的製作半導體元件的方法之流程圖。 第2A圖為根據本揭露之一些實施例繪示的半導體元件的方法的其中一個階段的剖面示意圖。 第2B圖為根據本揭露之一些實施例繪示的半導體元件的方法的其中一個階段的剖面示意圖。 第2C圖為根據本揭露之一些實施例繪示的半導體元件的方法的其中一個階段的剖面示意圖。 第2D圖為根據本揭露之一些實施例繪示的半導體元件的方法的其中一個階段的剖面示意圖。 第2E圖為根據本揭露之一些實施例繪示的半導體元件的方法的其中一個階段的剖面示意圖。 第2F圖為根據本揭露之一些實施例繪示的半導體元件的方法的其中一個階段的剖面示意圖。 第2G圖為根據本揭露之一些實施例繪示的半導體元件的方法的其中一個階段的剖面示意圖。 第2H圖為根據本揭露之一些實施例繪示的半導體元件的方法的其中一個階段的剖面示意圖。 Aspects of the present disclosure are best understood from the following Detailed Description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 2A is a schematic cross-sectional view of one stage of a method for a semiconductor device according to some embodiments of the present disclosure. FIG. 2B is a schematic cross-sectional view of one stage of a method for a semiconductor device according to some embodiments of the present disclosure. FIG. 2C is a schematic cross-sectional view of one stage of a method for a semiconductor device according to some embodiments of the present disclosure. FIG. 2D is a schematic cross-sectional view of one stage of a method for a semiconductor device according to some embodiments of the present disclosure. FIG. 2E is a schematic cross-sectional view of one stage of a method for a semiconductor device according to some embodiments of the present disclosure. FIG. 2F is a schematic cross-sectional view of one stage of a method for a semiconductor device according to some embodiments of the present disclosure. FIG. 2G is a schematic cross-sectional view of one stage of a method for a semiconductor device according to some embodiments of the present disclosure. FIG. 2H is a schematic cross-sectional view of one stage of a method for a semiconductor device according to some embodiments of the present disclosure.

國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

M1:方法 M1: method

S101,S102.S103,S104,S105,S106:步驟 S101, S102.S103, S104, S105, S106: steps

Claims (10)

一種製作半導體元件的方法，該方法包含： 形成一遮罩層在一堆疊結構上，其中該遮罩層具有一第一區域以及一第二區域，該第二區域具有一圖案化結構； 透過該圖案化結構在該堆疊結構上蝕刻出複數個開口，其中一蝕刻殘物堆積於該第一區域上； 填充一填充層在該些開口中； 摻雜該遮罩層的該第一區域； 藉由一選擇性蝕刻製程移除該蝕刻殘物以及該填充層；以及 移除該遮罩層。 A method of making a semiconductor device, the method comprising: forming a mask layer on a stacked structure, wherein the mask layer has a first region and a second region, and the second region has a patterned structure; Etching a plurality of openings on the stacked structure through the patterned structure, wherein an etching residue is deposited on the first region; filling a filling layer in the openings; doping the first region of the mask layer; removing the etch residue and the filling layer by a selective etching process; and Remove this mask layer. 如請求項1所述之製造半導體元件的方法，其中該堆疊結構包含一氧化層以及一氮化層，並且該透過該圖案化結構在該堆疊結構上蝕刻出該些開口的步驟係使得該氧化層以及該氮化層的每一者的至少一表面被暴露。The method for manufacturing a semiconductor device as claimed in claim 1, wherein the stack structure includes an oxide layer and a nitride layer, and the step of etching the openings on the stack structure through the patterned structure is to make the oxide layer layer and at least one surface of each of the nitride layer is exposed. 如請求項1所述之製造半導體元件的方法，其中該填充該填充層在該些開口中的步驟係使得該填充層覆蓋該遮罩層的該第二區域。The method of manufacturing a semiconductor device as claimed in claim 1, wherein the step of filling the filling layer in the openings is such that the filling layer covers the second region of the mask layer. 如請求項1所述之製作半導體元件的方法，其中該填充該填充層在該些開口中的步驟係使得該填充層與該蝕刻殘物相對於該遮罩層的高度實質上相同。The method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of filling the filling layer in the openings is such that the heights of the filling layer and the etching residue relative to the mask layer are substantially the same. 如請求項1所述之製作半導體元件的方法，其中該摻雜該遮罩層的該第一區域的步驟包含在該第一區域形成一p型摻雜物。The method of manufacturing a semiconductor device as claimed in claim 1, wherein the step of doping the first region of the mask layer includes forming a p-type dopant in the first region. 如請求項5所述之製作半導體元件的方法，其中該藉由該選擇性蝕刻製程移除該蝕刻殘物以及該填充層的步驟係使用一第一蝕刻配方，且該p型摻雜物適於抵抗該第一蝕刻配方之蝕刻。The method for manufacturing a semiconductor device as described in claim 5, wherein the step of removing the etching residue and the filling layer by the selective etching process uses a first etching recipe, and the p-type dopant is suitable for In resisting the etching of the first etching formula. 如請求項6所述之製作半導體元件的方法，其中該第一蝕刻配方包含HBr、He以及O 2中的至少一者。 The method for manufacturing a semiconductor device as claimed in claim 6, wherein the first etching recipe includes at least one of HBr, He and O 2 . 如請求項1所述之製作半導體元件的方法，進一步包含在該藉由該選擇性蝕刻製程移除該蝕刻殘物以及該填充層的步驟之前，摻雜該蝕刻殘物。The method for manufacturing a semiconductor device as claimed in claim 1, further comprising doping the etching residue before the step of removing the etching residue and the filling layer by the selective etching process. 如請求項8所述之製作半導體元件的方法，其中該摻雜該蝕刻殘物的步驟包含在該蝕刻殘物形成一n型摻雜物。The method of manufacturing a semiconductor device as claimed in claim 8, wherein the step of doping the etch residue includes forming an n-type dopant in the etch residue. 如請求項1所述之製作半導體元件的方法，其中該移除該遮罩層的步驟係使用一第二蝕刻配方，並且該第二蝕刻配方與該第一蝕刻配方不同。The method of manufacturing a semiconductor device as claimed in claim 1, wherein the step of removing the mask layer uses a second etching recipe, and the second etching recipe is different from the first etching recipe.
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TW201533547A (en) * 2014-02-27 2015-09-01 Macronix Int Co Ltd Etching method and etching composition
TW202141573A (en) * 2020-04-22 2021-11-01 南亞科技股份有限公司 Method of forming a pattern

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201533547A (en) * 2014-02-27 2015-09-01 Macronix Int Co Ltd Etching method and etching composition
TW202141573A (en) * 2020-04-22 2021-11-01 南亞科技股份有限公司 Method of forming a pattern

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