TWI776142B - Chip on film package structure - Google Patents
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- TWI776142B TWI776142B TW109112757A TW109112757A TWI776142B TW I776142 B TWI776142 B TW I776142B TW 109112757 A TW109112757 A TW 109112757A TW 109112757 A TW109112757 A TW 109112757A TW I776142 B TWI776142 B TW I776142B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
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Abstract
Description
本發明是有關於一種封裝結構,且特別是有關於一種薄膜覆晶封裝結構。The present invention relates to a package structure, and more particularly, to a chip on film package structure.
在薄膜覆晶封裝結構中,內引腳接合(ILB)通常是利用熱壓合技術使可撓性薄膜上的引腳與晶片上的凸塊在高溫下產生共晶接合。進一步而言,由於可撓性薄膜與晶片的熱膨脹係數不同,可撓性薄膜遇熱收縮程度較大,而收縮會導致引腳由原設計位置往中央引腳偏移,且越往晶片的兩側(即晶片長度方向的兩端)引腳偏移程度越大,因此引腳的設計會自中央引腳向兩側分別對引腳的設置位置加上補償值,且補償值自中央向兩側逐步加大,以使所有引腳在可撓性薄膜收縮的情況下仍能與凸塊順利對位接合。In the chip-on-film structure, the inner lead bonding (ILB) usually utilizes thermocompression bonding technology to produce eutectic bonding between the leads on the flexible film and the bumps on the wafer at high temperature. Further, due to the different thermal expansion coefficients of the flexible film and the chip, the flexible film shrinks to a greater extent when exposed to heat, and the shrinkage will cause the pins to shift from the original design position to the central pin, and the further to the two sides of the chip. The greater the deviation of the pins on the side (ie both ends of the chip length), the design of the pins will add compensation values to the setting positions of the pins from the center pin to the two sides, and the compensation values will be from the center to the two sides. The sides are gradually enlarged so that all pins can still be smoothly aligned with the bumps when the flexible film shrinks.
然而,在晶片尺寸加長的情況下,可撓性薄膜收縮的影響加劇,即便加上補償值,靠近晶片兩側的引腳仍可能隨引腳寬度不同而產生對位上的誤差,進而導致引腳與凸塊之間接合不良的問題。因此,如何有效地抑制可撓性薄膜的脹縮幅度,降低引腳與凸塊之間對位上的誤差,進而改善引腳與凸塊之間接合不良的問題實已成目前亟欲解決的課題。However, as the chip size increases, the effect of the shrinkage of the flexible film is intensified. Even with the compensation value, the pins close to the two sides of the chip may still have misalignment due to the difference in the width of the pins, resulting in lead Problems with poor engagement between feet and bumps. Therefore, how to effectively suppress the expansion and contraction of the flexible film, reduce the alignment error between the pins and the bumps, and further improve the problem of poor bonding between the pins and the bumps has become an urgent problem to be solved at present. subject.
本發明提供一種薄膜覆晶封裝結構,其可以有效地抑制可撓性薄膜的脹縮幅度,降低引腳與凸塊之間對位上的誤差,進而改善引腳與凸塊之間接合不良的問題。The invention provides a film-on-chip package structure, which can effectively restrain the expansion and contraction of the flexible film, reduce the alignment error between the pins and the bumps, and further improve the poor bonding between the pins and the bumps. question.
本發明的一種薄膜覆晶封裝結構,包括可撓性薄膜、線路結構以及晶片。可撓性薄膜具有晶片接合區。線路結構設置於可撓性薄膜上,且包括多個第一引腳、多個第二引腳與多個第三引腳。各第一引腳具有第一內引腳部與第一延伸部,各第二引腳具有第二內引腳部與第二延伸部。晶片設置於晶片接合區內。晶片包括第一區、第二區與位於第一區與第二區之間的第三區,且具有位於第一區內的多個第一凸塊、位於第二區內的多個第二凸塊與位於第三區內的多個第三凸塊。第一凸塊、第二凸塊與第三凸塊沿著晶片的邊緣相鄰排列,且分別對應連接第一內引腳部、第二內引腳部與第三引腳。第一內引腳部自第一區內斜向延伸經過晶片的邊緣並與第一延伸部連接於第一彎折點,第二內引腳部自第二區內斜向延伸經過邊緣並與第二延伸部連接於第二彎折點,多個第三引腳自第三區內延伸正交邊緣而向外延伸。A film-on-chip packaging structure of the present invention includes a flexible film, a circuit structure and a chip. The flexible film has a die bond area. The circuit structure is arranged on the flexible film and includes a plurality of first pins, a plurality of second pins and a plurality of third pins. Each of the first pins has a first inner pin part and a first extension part, and each of the second pins has a second inner pin part and a second extension part. The wafer is disposed in the wafer bonding area. The wafer includes a first area, a second area, and a third area located between the first area and the second area, and has a plurality of first bumps located in the first area and a plurality of second bumps located in the second area The bump and a plurality of third bumps located in the third area. The first bump, the second bump and the third bump are adjacently arranged along the edge of the wafer, and are respectively connected to the first inner pin part, the second inner pin part and the third pin. The first inner lead portion extends obliquely through the edge of the chip from the first area and is connected to the first bending point with the first extension portion, and the second inner lead portion extends obliquely from the second area through the edge and is connected with the first bending point. The second extension portion is connected to the second bending point, and the plurality of third pins extend from orthogonal edges in the third area and extend outward.
在本發明的一實施例中,上述的第一凸塊與第二凸塊分別順應第一內引腳部與第二內引腳部的延伸方向斜向延伸。In an embodiment of the present invention, the first bump and the second bump extend obliquely along the extending directions of the first inner lead portion and the second inner lead portion, respectively.
在本發明的一實施例中,上述的第一彎折點與第二彎折點位於晶片的覆蓋範圍之外,且與晶片的邊緣之間具有間隙。In an embodiment of the present invention, the first bending point and the second bending point are located outside the coverage of the wafer and have a gap with the edge of the wafer.
在本發明的一實施例中,上述的間隙不小於30微米。In an embodiment of the present invention, the above-mentioned gap is not less than 30 microns.
在本發明的一實施例中,上述的第一內引腳部自第一區內往遠離第三引腳的方向斜向延伸,第二內引腳部自第二區內往遠離第三引腳的方向斜向延伸。In an embodiment of the present invention, the above-mentioned first inner lead portion extends obliquely from the first area to a direction away from the third lead, and the second inner lead portion extends away from the third lead from the second area. The direction of the feet extends diagonally.
在本發明的一實施例中,上述的第一內引腳部與邊緣形成第一夾角,第二內引腳部與邊緣形成第二夾角,第一夾角與第二夾角大於零度且小於九十度。In an embodiment of the present invention, the first inner pin portion and the edge form a first included angle, the second inner pin portion and the edge form a second included angle, and the first included angle and the second included angle are greater than zero degrees and less than ninety degrees Spend.
在本發明的一實施例中,上述的薄膜覆晶封裝結構更包括防銲層。防銲層設置於可撓性薄膜上,局部覆蓋線路結構,且暴露出晶片接合區。In an embodiment of the present invention, the above-mentioned chip on film package structure further includes a solder mask layer. The solder resist layer is arranged on the flexible film, partially covers the circuit structure, and exposes the chip bonding area.
在本發明的一實施例中,上述的防銲層暴露出第一彎折點與第二彎折點。In an embodiment of the present invention, the above-mentioned solder mask exposes a first bending point and a second bending point.
在本發明的一實施例中,上述的薄膜覆晶封裝結構更包括封裝膠體。封裝膠體填充於晶片與可撓性薄膜之間,且覆蓋晶片接合區。In an embodiment of the present invention, the above-mentioned chip on film packaging structure further includes an encapsulant. The encapsulant is filled between the chip and the flexible film and covers the chip bonding area.
在本發明的一實施例中,上述的封裝膠體覆蓋第一彎折點與第二彎折點。In an embodiment of the present invention, the above-mentioned encapsulant covers the first bending point and the second bending point.
基於上述,本發明的引腳(第一引腳與第二引腳)藉由內引腳部(第一內引腳部與第二內引腳部)的斜向設計可以擴大抑制可撓性薄膜脹縮的影響範圍,進而可以有效地抑制可撓性薄膜的脹縮幅度,降低引腳與凸塊之間對位上的誤差,進而改善引腳與凸塊之間接合不良的問題。Based on the above, the lead (the first lead and the second lead) of the present invention can expand and suppress the flexibility by the oblique design of the inner lead part (the first inner lead part and the second inner lead part) The influence range of film expansion and contraction can effectively suppress the expansion and contraction range of the flexible film, reduce the error in the alignment between the pins and the bumps, and further improve the problem of poor bonding between the pins and the bumps.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.
圖1是本發明一實施例的薄膜覆晶封裝結構的俯視示意圖。圖2是圖1的區域A的放大示意圖。圖3是斜向引腳與直向引腳的比較示意圖。圖4是斜向凸塊與直向凸塊與引腳接合的比較示意圖。為求清楚表示,圖1與圖2中的晶片130、第一凸塊131、第二凸塊132、第三凸塊133及封裝膠體150採用透視繪法呈現。FIG. 1 is a schematic top view of a chip on film packaging structure according to an embodiment of the present invention. FIG. 2 is an enlarged schematic view of area A of FIG. 1 . Figure 3 is a schematic diagram of a comparison between oblique pins and straight pins. FIG. 4 is a schematic diagram showing a comparison between the oblique bump and the straight bump and pin bonding. For the sake of clarity, the
請同時參考圖1與圖2,在本實施例中,薄膜覆晶封裝結構100包括可撓性薄膜110、線路結構120以及晶片130。進一步來說,可撓性薄膜110具有晶片接合區112,晶片130設置於晶片接合區112內,而線路結構120設置於可撓性薄膜110上。Please refer to FIG. 1 and FIG. 2 at the same time. In this embodiment, the chip on
可撓性薄膜110的材質例如是聚醯亞胺(Polyimide, PI)、聚乙烯對苯二甲酸酯(polyethylene terephthalate, PET)、聚醚(polyethersulfone, PES)、碳酸脂(polycarbonate, PC)或其他適合的可撓性材料,因此使用可撓性薄膜110的薄膜覆晶封裝結構100具有可撓曲性。The material of the
線路結構120包括多個第一引腳121、多個第二引腳122與多個第三引腳123,其中各第一引腳121具有第一內引腳部1211與第一延伸部1212,各第二引腳122具有第二內引腳部1221與第二延伸部1222。線路結構120的材質例如是銅或其他適合的金屬。The circuit structure 120 includes a plurality of
晶片130包括第一區A1、第二區A2與位於第一區A1與第二區A2之間的第三區A3,其中晶片130具有位於第一區A1內的多個第一凸塊131、位於第二區A2內的多個第二凸塊132與位於第三區A3內的多個第三凸塊133。此外,第一凸塊131、第三凸塊133與第二凸塊132沿著晶片130的一邊緣E相鄰排列,且分別對應連接第一內引腳部1211、第三引腳123與第二內引腳部1221。換言之,第一內引腳部1211、第三引腳123與第二內引腳部1221也是沿著晶片130的邊緣E相鄰排列。舉例而言,晶片130具有相對的兩個短邊側與相對的兩個長邊側,而第一凸塊131、第三凸塊133與第二凸塊132可以是分別沿著晶片130的相對的兩個長邊側的邊緣E相鄰排列。The
在本實施例中,第一內引腳部1211自第一區A1內斜向延伸經過晶片130的邊緣E並與第一延伸部1212連接於第一彎折點B1,第二內引腳部1221自第二區A2內斜向延伸經過邊緣E並與第二延伸部1222連接於第二彎折點B2,多個第三引腳123自第三區A3內延伸正交邊緣E而向外延伸。本發明藉由第一內引腳部1211與第二內引腳部1221的斜向設計可有效抑制可撓性薄膜110的脹縮幅度。詳細而言,如圖3所示,圖3中係以第一引腳121與第一凸塊131為例,本實施例的第一引腳121將第一內引腳部1211作斜向設計,使得第一內引腳部1211抑制可撓性薄膜110脹縮的影響範圍AR2相較於直向引腳10所形成的影響範圍AR1來得大,因此可達到較佳的脹縮抑制效果,有效地抑制可撓性薄膜110的脹縮幅度,降低第一內引腳部1211偏移的程度,進而避免第一引腳121與第一凸塊131之間對位上的誤差,改善第一引腳121與第一凸塊131之間接合不良的問題。In this embodiment, the first
在一實施例中,第一彎折點B1與第二彎折點B2位於晶片130的覆蓋範圍C之外,且與晶片130的邊緣E之間可以具有間隙。舉例而言,第一彎折點B1與晶片130的邊緣E之間具有間隙G1,第二彎折點B2與晶片130的邊緣E之間具有間隙G2。進一步而言,當間隙(間隙G1與間隙G2)較小時,彎折點(第一彎折點B1與第二彎折點B2)較靠近晶片接合區112,易導致引腳(第一引腳121與第二引腳122)在接合時因受力而在彎折點(第一彎折點B1與第二彎折點B2)處斷裂,因此,間隙(間隙G1與間隙G2)例如是不小於30微米,以降低引腳(第一引腳部121與第二引腳122)在接合時易因受力而斷裂的機率,進而可以提升薄膜覆晶封裝結構100的可靠度,但本發明不限於此。此外,間隙G1與間隙G2可以是相同,因此,第一彎折點B1與第二彎折點B2於晶片130的兩側可以是對位配置,但本發明不限於此。間隙G1與間隙G2可以視實際設計上的需求而定。In one embodiment, the first bending point B1 and the second bending point B2 are located outside the coverage C of the
在一實施例中,第一內引腳部1211可以自第一區A1內往遠離第三引腳123的方向斜向延伸,而第二內引腳部1221可以自第二區A2內往遠離第三引腳123的方向斜向延伸。換句話說,第一內引腳部1211位於第一區A1內的一端部可以較第一內引腳部1211位於第一區A1外的另一端部靠近第三引腳123,而第二內引腳部1221位於第二區A2內的一端部可以較第二內引腳部1221位於第二區A2外的另一端部靠近第三引腳123。In one embodiment, the first
此外,第一凸塊131與第二凸塊132可以分別順應第一內引腳部1211與第二內引腳部1221的延伸方向斜向延伸。換句話說,第一凸塊131的延伸方向可以平行於第一內引腳部1211的延伸方向,而第二凸塊132的延伸方向可以平行於第二內引腳部1221的延伸方向。因此,如圖4所示,圖4中係以第一引腳121與第一凸塊131為例,當第一引腳121於接合時發生偏移時,例如朝方向D偏移,本實施例的斜向延伸的第一凸塊131與偏移的第一引腳121的接合面積AR4相較於直向凸塊20與偏移的第一引腳121的接合面積AR3來得大,也就是說,本實施例的第一凸塊131與第二凸塊132分別順應第一內引腳部1211與第二內引腳部1221的延伸方向斜向配置,即便第一引腳121與第二引腳122於接合時發生偏移,第一凸塊131與第一引腳121之間以及第二凸塊132與第二引腳122之間仍能維持足夠的接合面積,以確保內引腳接合的品質。In addition, the
在一實施例中,第一內引腳部1211與邊緣E形成第一夾角θ1,第二內引腳部1221與邊緣E形成第二夾角θ2,第一夾角θ1與第二夾角θ2大於零度且小於九十度。換句話說,第一內引腳部1211與第二內引腳部1221不會正交或平行邊緣E。舉例來說,第一夾角θ1與第二夾角θ2較佳的例如是45°,但本發明不限制第一夾角θ1與第二夾角θ2的角度,可以視實際設計上的需求而定。In one embodiment, the first
在一實施例中,由於引腳的偏移程度越往晶片130的兩側越趨嚴重,為了抑制可撓性薄膜110在這些區域的脹縮幅度,第一引腳121與第二引腳122的分布範圍可以是分別占晶片130的長度的三分之一,也就是說,第一區A1與第二區A2分別占晶片130的長度的三分之一,但本發明不限於此。第一引腳121與第二引腳122的分布範圍可以依實際設計上的需求進行調整。In one embodiment, since the deviation of the pins is more serious toward the two sides of the
在一實施例中,為使線路結構120維持良好的電性,薄膜覆晶封裝結構100還可以包括防銲層140。防銲層140可以設置於可撓性薄膜110上,局部覆蓋線路結構120,且暴露出晶片接合區112。進一步來說,防銲層140具有開口142,且晶片接合區112實質上是由防銲層140的開口142所界定。在一實施例中,防銲層140可以暴露出第一彎折點B1與第二彎折點B2。In one embodiment, in order to maintain good electrical properties of the circuit structure 120 , the chip on
在一實施例中,為避免濕氣及汙染侵入,薄膜覆晶封裝結構100還可以包括封裝膠體150。特別說明,圖1與圖2中封裝膠體150係採用透視繪法呈現,因此僅框示出封裝膠體150的概略分佈範圍。封裝膠體150可以填充於晶片130與可撓性薄膜110之間,且覆蓋晶片接合區112。在一實施例中,封裝膠體150可以覆蓋第一彎折點B1與第二彎折點B2。換句話說,第一彎折點B1與第二彎折點B2不會超出封裝膠體150的邊緣。In one embodiment, in order to avoid the intrusion of moisture and contamination, the chip on
綜上所述,本發明的的引腳(第一引腳與第二引腳)藉由內引腳部(第一內引腳部與第二內引腳部)的斜向設計可以擴大抑制可撓性薄膜脹縮的影響範圍,進而可以有效地抑制可撓性薄膜的脹縮幅度,降低引腳與凸塊之間對位上的誤差,進而改善引腳與凸塊之間接合不良的問題。此外,本發明藉由凸塊(第一凸塊與第二凸塊)的斜向設計可以使內引腳部(第一內引腳部與第二內引腳部)與凸塊(第一凸塊與第二凸塊)之間維持足夠的接合面積,確保當引腳(第一引腳與第二引腳)發生偏移時仍能與凸塊(第一凸塊與第二凸塊)順利對位接合,以確保內引腳接合的品質。To sum up, the pins (the first pin and the second pin) of the present invention can be enlarged and suppressed by the oblique design of the inner pin parts (the first inner pin part and the second inner pin part) The influence range of the expansion and contraction of the flexible film can effectively suppress the expansion and contraction of the flexible film, reduce the error in the alignment between the pins and the bumps, and improve the poor bonding between the pins and the bumps. question. In addition, the present invention can make the inner lead part (the first inner lead part and the second inner lead part) and the bump (the first inner lead part) and the bump (the first inner lead part) and the bump (the first Maintain sufficient bonding area between the bump and the second bump) to ensure that when the pins (the first pin and the second pin) are offset, they can still contact the bumps (the first bump and the second bump) ) Smoothly aligned joints to ensure the quality of the inner pin joints.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.
10:直向引腳 20:直向凸塊 100:薄膜覆晶封裝結構 110:可撓性薄膜 112:晶片接合區 120:線路結構 121:第一引腳 1211:第一內引腳部 1212:第一延伸部 122:第二引腳 1221:第二內引腳部 1222:第二延伸部 123:第三引腳 130:晶片 131:第一凸塊 132:第二凸塊 133:第三凸塊 140:防銲層 142:開口 150:封裝膠體 A:區域 A1:第一區 A2:第二區 A3:第三區 AR1、AR2:影響範圍 AR3、AR4:面積 B1:第一彎折點 B2:第二彎折點 C:覆蓋範圍 D:方向 E:邊緣 G1、G2:間隙 θ1:第一夾角 θ2:第二夾角10: Straight pins 20: Straight bump 100: Thin film flip chip package structure 110: Flexible film 112: Wafer bonding area 120: Line Structure 121: the first pin 1211: The first inner pin part 1212: First extension 122: the second pin 1221: Second inner pin part 1222: Second extension 123: The third pin 130: Wafer 131: First bump 132: Second bump 133: Third bump 140: Solder mask 142: Opening 150: encapsulating colloid A: area A1: District 1 A2: The second area A3: The third district AR1, AR2: sphere of influence AR3, AR4: Area B1: The first bending point B2: The second bending point C: Coverage D: direction E: edge G1, G2: Gap θ1: the first angle θ2: Second included angle
圖1是本發明一實施例的薄膜覆晶封裝結構的俯視示意圖。 圖2是圖1的區域A的放大示意圖。 圖3是斜向引腳與直向引腳的比較示意圖。 圖4是斜向凸塊與直向凸塊與引腳接合的比較示意圖。FIG. 1 is a schematic top view of a chip on film packaging structure according to an embodiment of the present invention. FIG. 2 is an enlarged schematic view of area A of FIG. 1 . Figure 3 is a schematic diagram of a comparison between oblique pins and straight pins. FIG. 4 is a schematic diagram showing a comparison between the oblique bump and the straight bump and pin bonding.
100:薄膜覆晶封裝結構100: Thin film flip chip package structure
110:可撓性薄膜110: Flexible film
112:晶片接合區112: Wafer bonding area
120:線路結構120: Line Structure
121:第一引腳121: the first pin
1211:第一內引腳部1211: The first inner pin part
1212:第一延伸部1212: First extension
122:第二引腳122: the second pin
1221:第二內引腳部1221: Second inner pin part
1222:第二延伸部1222: Second extension
123:第三引腳123: The third pin
130:晶片130: Wafer
131:第一凸塊131: First bump
132:第二凸塊132: Second bump
133:第三凸塊133: Third bump
140:防銲層140: Solder mask
142:開口142: Opening
150:封裝膠體150: encapsulating colloid
A:區域A: area
A1:第一區A1: District 1
A2:第二區A2: The second area
A3:第三區A3: The third district
B1:第一彎折點B1: The first bending point
B2:第二彎折點B2: The second bending point
C:覆蓋範圍C: Coverage
E:邊緣E: edge
Claims (10)
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TW109112757A TWI776142B (en) | 2020-04-16 | 2020-04-16 | Chip on film package structure |
CN202010563872.4A CN113540011B (en) | 2020-04-16 | 2020-06-19 | Thin film flip chip package structure |
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TW109112757A TWI776142B (en) | 2020-04-16 | 2020-04-16 | Chip on film package structure |
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Citations (4)
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TW200807668A (en) * | 2006-07-26 | 2008-02-01 | Chipmos Technologies Inc | Pluggable tape type IC package |
TW200847372A (en) * | 2007-05-30 | 2008-12-01 | Chipmos Technologies Inc | Tape type semiconductor package and its substrate |
TW201025532A (en) * | 2008-12-16 | 2010-07-01 | Powertech Technology Inc | Chip stacked package having single-sided pads on chips |
TWI653717B (en) * | 2017-09-11 | 2019-03-11 | 南茂科技股份有限公司 | Film flip chip package structure |
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JP2005005306A (en) * | 2003-06-09 | 2005-01-06 | Seiko Epson Corp | Semiconductor device, semiconductor module, electronic device, electronic apparatus, and process for fabricating semiconductor module |
JP3807502B2 (en) * | 2003-11-28 | 2006-08-09 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
JP2010199191A (en) * | 2009-02-24 | 2010-09-09 | Oki Semiconductor Co Ltd | Semiconductor package and method of manufacturing semiconductor package |
TWI455273B (en) * | 2011-08-04 | 2014-10-01 | Chipmos Technologies Inc | Chip package structure |
TWI673845B (en) * | 2018-04-19 | 2019-10-01 | 南茂科技股份有限公司 | Chip-on-film package structure |
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TW200807668A (en) * | 2006-07-26 | 2008-02-01 | Chipmos Technologies Inc | Pluggable tape type IC package |
TW200847372A (en) * | 2007-05-30 | 2008-12-01 | Chipmos Technologies Inc | Tape type semiconductor package and its substrate |
TW201025532A (en) * | 2008-12-16 | 2010-07-01 | Powertech Technology Inc | Chip stacked package having single-sided pads on chips |
TWI653717B (en) * | 2017-09-11 | 2019-03-11 | 南茂科技股份有限公司 | Film flip chip package structure |
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