TWI776142B - Chip on film package structure - Google Patents

Chip on film package structure Download PDF

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Publication number
TWI776142B
TWI776142B TW109112757A TW109112757A TWI776142B TW I776142 B TWI776142 B TW I776142B TW 109112757 A TW109112757 A TW 109112757A TW 109112757 A TW109112757 A TW 109112757A TW I776142 B TWI776142 B TW I776142B
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chip
area
bumps
edge
bending point
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TW109112757A
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Chinese (zh)
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TW202141724A (en
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陳崇龍
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南茂科技股份有限公司
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Priority to CN202010563872.4A priority patent/CN113540011B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

A chip on film package structure includes a flexible film, circuit structure and a chip. The flexible film has a chip bonding area. The circuit structure is disposed on the flexible film and includes a plurality of first leads, a plurality of second leads, and a plurality of third leads. Each of the first leads has a first inner lead portion and a first extension portion, and each of the second leads has a second inner lead portion and a second extension portion. The chip is disposed in a chip bonding area. The chip includes a first region, a second region, and a third region located between the first region and the second region. The chip has a plurality of first bumps located in the first region, a plurality of second bumps located in the second region and a plurality of third bumps located in the third region. The first bumps, the second bumps, and the third bumps are arranged along an edge of the chip, and respectively connect the first inner lead portions, the second inner lead portions, and the third leads. The first inner lead portions extend obliquely from the first region through the edge of the chip and connect the first extension portions at first bending points, the second inner lead portions extend obliquely from the second region through the edge and connect the second extension portions at second extension points, and the third leads extend outward from the third region passing orthogonal to the edge.

Description

薄膜覆晶封裝結構Chip-on-Film Package Structure

本發明是有關於一種封裝結構，且特別是有關於一種薄膜覆晶封裝結構。The present invention relates to a package structure, and more particularly, to a chip on film package structure.

在薄膜覆晶封裝結構中，內引腳接合(ILB)通常是利用熱壓合技術使可撓性薄膜上的引腳與晶片上的凸塊在高溫下產生共晶接合。進一步而言，由於可撓性薄膜與晶片的熱膨脹係數不同，可撓性薄膜遇熱收縮程度較大，而收縮會導致引腳由原設計位置往中央引腳偏移，且越往晶片的兩側(即晶片長度方向的兩端)引腳偏移程度越大，因此引腳的設計會自中央引腳向兩側分別對引腳的設置位置加上補償值，且補償值自中央向兩側逐步加大，以使所有引腳在可撓性薄膜收縮的情況下仍能與凸塊順利對位接合。In the chip-on-film structure, the inner lead bonding (ILB) usually utilizes thermocompression bonding technology to produce eutectic bonding between the leads on the flexible film and the bumps on the wafer at high temperature. Further, due to the different thermal expansion coefficients of the flexible film and the chip, the flexible film shrinks to a greater extent when exposed to heat, and the shrinkage will cause the pins to shift from the original design position to the central pin, and the further to the two sides of the chip. The greater the deviation of the pins on the side (ie both ends of the chip length), the design of the pins will add compensation values to the setting positions of the pins from the center pin to the two sides, and the compensation values will be from the center to the two sides. The sides are gradually enlarged so that all pins can still be smoothly aligned with the bumps when the flexible film shrinks.

然而，在晶片尺寸加長的情況下，可撓性薄膜收縮的影響加劇，即便加上補償值，靠近晶片兩側的引腳仍可能隨引腳寬度不同而產生對位上的誤差，進而導致引腳與凸塊之間接合不良的問題。因此，如何有效地抑制可撓性薄膜的脹縮幅度，降低引腳與凸塊之間對位上的誤差，進而改善引腳與凸塊之間接合不良的問題實已成目前亟欲解決的課題。However, as the chip size increases, the effect of the shrinkage of the flexible film is intensified. Even with the compensation value, the pins close to the two sides of the chip may still have misalignment due to the difference in the width of the pins, resulting in lead Problems with poor engagement between feet and bumps. Therefore, how to effectively suppress the expansion and contraction of the flexible film, reduce the alignment error between the pins and the bumps, and further improve the problem of poor bonding between the pins and the bumps has become an urgent problem to be solved at present. subject.

本發明提供一種薄膜覆晶封裝結構，其可以有效地抑制可撓性薄膜的脹縮幅度，降低引腳與凸塊之間對位上的誤差，進而改善引腳與凸塊之間接合不良的問題。The invention provides a film-on-chip package structure, which can effectively restrain the expansion and contraction of the flexible film, reduce the alignment error between the pins and the bumps, and further improve the poor bonding between the pins and the bumps. question.

本發明的一種薄膜覆晶封裝結構，包括可撓性薄膜、線路結構以及晶片。可撓性薄膜具有晶片接合區。線路結構設置於可撓性薄膜上，且包括多個第一引腳、多個第二引腳與多個第三引腳。各第一引腳具有第一內引腳部與第一延伸部，各第二引腳具有第二內引腳部與第二延伸部。晶片設置於晶片接合區內。晶片包括第一區、第二區與位於第一區與第二區之間的第三區，且具有位於第一區內的多個第一凸塊、位於第二區內的多個第二凸塊與位於第三區內的多個第三凸塊。第一凸塊、第二凸塊與第三凸塊沿著晶片的邊緣相鄰排列，且分別對應連接第一內引腳部、第二內引腳部與第三引腳。第一內引腳部自第一區內斜向延伸經過晶片的邊緣並與第一延伸部連接於第一彎折點，第二內引腳部自第二區內斜向延伸經過邊緣並與第二延伸部連接於第二彎折點，多個第三引腳自第三區內延伸正交邊緣而向外延伸。A film-on-chip packaging structure of the present invention includes a flexible film, a circuit structure and a chip. The flexible film has a die bond area. The circuit structure is arranged on the flexible film and includes a plurality of first pins, a plurality of second pins and a plurality of third pins. Each of the first pins has a first inner pin part and a first extension part, and each of the second pins has a second inner pin part and a second extension part. The wafer is disposed in the wafer bonding area. The wafer includes a first area, a second area, and a third area located between the first area and the second area, and has a plurality of first bumps located in the first area and a plurality of second bumps located in the second area The bump and a plurality of third bumps located in the third area. The first bump, the second bump and the third bump are adjacently arranged along the edge of the wafer, and are respectively connected to the first inner pin part, the second inner pin part and the third pin. The first inner lead portion extends obliquely through the edge of the chip from the first area and is connected to the first bending point with the first extension portion, and the second inner lead portion extends obliquely from the second area through the edge and is connected with the first bending point. The second extension portion is connected to the second bending point, and the plurality of third pins extend from orthogonal edges in the third area and extend outward.

在本發明的一實施例中，上述的第一凸塊與第二凸塊分別順應第一內引腳部與第二內引腳部的延伸方向斜向延伸。In an embodiment of the present invention, the first bump and the second bump extend obliquely along the extending directions of the first inner lead portion and the second inner lead portion, respectively.

在本發明的一實施例中，上述的第一彎折點與第二彎折點位於晶片的覆蓋範圍之外，且與晶片的邊緣之間具有間隙。In an embodiment of the present invention, the first bending point and the second bending point are located outside the coverage of the wafer and have a gap with the edge of the wafer.

在本發明的一實施例中，上述的間隙不小於30微米。In an embodiment of the present invention, the above-mentioned gap is not less than 30 microns.

在本發明的一實施例中，上述的第一內引腳部自第一區內往遠離第三引腳的方向斜向延伸，第二內引腳部自第二區內往遠離第三引腳的方向斜向延伸。In an embodiment of the present invention, the above-mentioned first inner lead portion extends obliquely from the first area to a direction away from the third lead, and the second inner lead portion extends away from the third lead from the second area. The direction of the feet extends diagonally.

在本發明的一實施例中，上述的第一內引腳部與邊緣形成第一夾角，第二內引腳部與邊緣形成第二夾角，第一夾角與第二夾角大於零度且小於九十度。In an embodiment of the present invention, the first inner pin portion and the edge form a first included angle, the second inner pin portion and the edge form a second included angle, and the first included angle and the second included angle are greater than zero degrees and less than ninety degrees Spend.

在本發明的一實施例中，上述的薄膜覆晶封裝結構更包括防銲層。防銲層設置於可撓性薄膜上，局部覆蓋線路結構，且暴露出晶片接合區。In an embodiment of the present invention, the above-mentioned chip on film package structure further includes a solder mask layer. The solder resist layer is arranged on the flexible film, partially covers the circuit structure, and exposes the chip bonding area.

在本發明的一實施例中，上述的防銲層暴露出第一彎折點與第二彎折點。In an embodiment of the present invention, the above-mentioned solder mask exposes a first bending point and a second bending point.

在本發明的一實施例中，上述的薄膜覆晶封裝結構更包括封裝膠體。封裝膠體填充於晶片與可撓性薄膜之間，且覆蓋晶片接合區。In an embodiment of the present invention, the above-mentioned chip on film packaging structure further includes an encapsulant. The encapsulant is filled between the chip and the flexible film and covers the chip bonding area.

在本發明的一實施例中，上述的封裝膠體覆蓋第一彎折點與第二彎折點。In an embodiment of the present invention, the above-mentioned encapsulant covers the first bending point and the second bending point.

基於上述，本發明的引腳(第一引腳與第二引腳)藉由內引腳部(第一內引腳部與第二內引腳部)的斜向設計可以擴大抑制可撓性薄膜脹縮的影響範圍，進而可以有效地抑制可撓性薄膜的脹縮幅度，降低引腳與凸塊之間對位上的誤差，進而改善引腳與凸塊之間接合不良的問題。Based on the above, the lead (the first lead and the second lead) of the present invention can expand and suppress the flexibility by the oblique design of the inner lead part (the first inner lead part and the second inner lead part) The influence range of film expansion and contraction can effectively suppress the expansion and contraction range of the flexible film, reduce the error in the alignment between the pins and the bumps, and further improve the problem of poor bonding between the pins and the bumps.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

圖1是本發明一實施例的薄膜覆晶封裝結構的俯視示意圖。圖2是圖1的區域A的放大示意圖。圖3是斜向引腳與直向引腳的比較示意圖。圖4是斜向凸塊與直向凸塊與引腳接合的比較示意圖。為求清楚表示，圖1與圖2中的晶片130、第一凸塊131、第二凸塊132、第三凸塊133及封裝膠體150採用透視繪法呈現。FIG. 1 is a schematic top view of a chip on film packaging structure according to an embodiment of the present invention. FIG. 2 is an enlarged schematic view of area A of FIG. 1 . Figure 3 is a schematic diagram of a comparison between oblique pins and straight pins. FIG. 4 is a schematic diagram showing a comparison between the oblique bump and the straight bump and pin bonding. For the sake of clarity, the chip 130 , the first bump 131 , the second bump 132 , the third bump 133 and the encapsulant 150 in FIGS. 1 and 2 are represented by perspective drawing.

請同時參考圖1與圖2，在本實施例中，薄膜覆晶封裝結構100包括可撓性薄膜110、線路結構120以及晶片130。進一步來說，可撓性薄膜110具有晶片接合區112，晶片130設置於晶片接合區112內，而線路結構120設置於可撓性薄膜110上。Please refer to FIG. 1 and FIG. 2 at the same time. In this embodiment, the chip on film package structure 100 includes a flexible film 110 , a circuit structure 120 and a chip 130 . Further, the flexible film 110 has a die bonding area 112 , the chip 130 is disposed in the die bonding area 112 , and the circuit structure 120 is disposed on the flexible film 110 .

可撓性薄膜110的材質例如是聚醯亞胺(Polyimide, PI)、聚乙烯對苯二甲酸酯(polyethylene terephthalate, PET)、聚醚(polyethersulfone, PES)、碳酸脂(polycarbonate, PC)或其他適合的可撓性材料，因此使用可撓性薄膜110的薄膜覆晶封裝結構100具有可撓曲性。The material of the flexible film 110 is, for example, polyimide (PI), polyethylene terephthalate (PET), polyethersulfone (PES), carbonate (polycarbonate, PC) or Other suitable flexible materials, so the chip on film package structure 100 using the flexible film 110 has flexibility.

線路結構120包括多個第一引腳121、多個第二引腳122與多個第三引腳123，其中各第一引腳121具有第一內引腳部1211與第一延伸部1212，各第二引腳122具有第二內引腳部1221與第二延伸部1222。線路結構120的材質例如是銅或其他適合的金屬。The circuit structure 120 includes a plurality of first pins 121 , a plurality of second pins 122 and a plurality of third pins 123 , wherein each of the first pins 121 has a first inner pin part 1211 and a first extension part 1212 , Each of the second pins 122 has a second inner pin portion 1221 and a second extension portion 1222 . The material of the circuit structure 120 is, for example, copper or other suitable metals.

晶片130包括第一區A1、第二區A2與位於第一區A1與第二區A2之間的第三區A3，其中晶片130具有位於第一區A1內的多個第一凸塊131、位於第二區A2內的多個第二凸塊132與位於第三區A3內的多個第三凸塊133。此外，第一凸塊131、第三凸塊133與第二凸塊132沿著晶片130的一邊緣E相鄰排列，且分別對應連接第一內引腳部1211、第三引腳123與第二內引腳部1221。換言之，第一內引腳部1211、第三引腳123與第二內引腳部1221也是沿著晶片130的邊緣E相鄰排列。舉例而言，晶片130具有相對的兩個短邊側與相對的兩個長邊側，而第一凸塊131、第三凸塊133與第二凸塊132可以是分別沿著晶片130的相對的兩個長邊側的邊緣E相鄰排列。The wafer 130 includes a first area A1, a second area A2 and a third area A3 located between the first area A1 and the second area A2, wherein the wafer 130 has a plurality of first bumps 131, The plurality of second bumps 132 in the second area A2 and the plurality of third bumps 133 in the third area A3. In addition, the first bumps 131 , the third bumps 133 and the second bumps 132 are adjacently arranged along an edge E of the wafer 130 and are respectively connected to the first inner lead portion 1211 , the third lead 123 and the Two inner pin parts 1221 . In other words, the first inner lead portion 1211 , the third lead portion 123 and the second inner lead portion 1221 are also arranged adjacent to each other along the edge E of the wafer 130 . For example, the wafer 130 has two opposite short sides and two opposite long sides, and the first bump 131 , the third bump 133 and the second bump 132 may be opposite along the wafer 130 , respectively. The edges E of the two long side sides are arranged adjacently.

在本實施例中，第一內引腳部1211自第一區A1內斜向延伸經過晶片130的邊緣E並與第一延伸部1212連接於第一彎折點B1，第二內引腳部1221自第二區A2內斜向延伸經過邊緣E並與第二延伸部1222連接於第二彎折點B2，多個第三引腳123自第三區A3內延伸正交邊緣E而向外延伸。本發明藉由第一內引腳部1211與第二內引腳部1221的斜向設計可有效抑制可撓性薄膜110的脹縮幅度。詳細而言，如圖3所示，圖3中係以第一引腳121與第一凸塊131為例，本實施例的第一引腳121將第一內引腳部1211作斜向設計，使得第一內引腳部1211抑制可撓性薄膜110脹縮的影響範圍AR2相較於直向引腳10所形成的影響範圍AR1來得大，因此可達到較佳的脹縮抑制效果，有效地抑制可撓性薄膜110的脹縮幅度，降低第一內引腳部1211偏移的程度，進而避免第一引腳121與第一凸塊131之間對位上的誤差，改善第一引腳121與第一凸塊131之間接合不良的問題。In this embodiment, the first inner lead portion 1211 extends obliquely from the first area A1 through the edge E of the wafer 130 and is connected with the first extension portion 1212 at the first bending point B1, and the second inner lead portion 1221 extends obliquely through the edge E from the second area A2 and is connected to the second bending point B2 with the second extension 1222 , and a plurality of third pins 123 extend from the third area A3 to the orthogonal edge E and outwards extend. The present invention can effectively restrain the expansion and contraction of the flexible film 110 by the oblique design of the first inner pin portion 1211 and the second inner pin portion 1221 . In detail, as shown in FIG. 3 , the first pin 121 and the first bump 131 are taken as an example in FIG. 3 . The first pin 121 in this embodiment is designed with the first inner pin portion 1211 obliquely designed. , so that the influence range AR2 of the first inner pin portion 1211 to suppress the expansion and contraction of the flexible film 110 is larger than the influence range AR1 formed by the straight pins 10 , so that a better expansion and contraction suppression effect can be achieved, effectively Therefore, the expansion and contraction of the flexible film 110 is effectively restrained, and the degree of deflection of the first inner pin portion 1211 is reduced, thereby avoiding the alignment error between the first pin 121 and the first bump 131, and improving the first pin portion 1211. The problem of poor bonding between the feet 121 and the first bumps 131 .

在一實施例中，第一彎折點B1與第二彎折點B2位於晶片130的覆蓋範圍C之外，且與晶片130的邊緣E之間可以具有間隙。舉例而言，第一彎折點B1與晶片130的邊緣E之間具有間隙G1，第二彎折點B2與晶片130的邊緣E之間具有間隙G2。進一步而言，當間隙(間隙G1與間隙G2)較小時，彎折點(第一彎折點B1與第二彎折點B2)較靠近晶片接合區112，易導致引腳(第一引腳121與第二引腳122)在接合時因受力而在彎折點(第一彎折點B1與第二彎折點B2)處斷裂，因此，間隙(間隙G1與間隙G2)例如是不小於30微米，以降低引腳(第一引腳部121與第二引腳122)在接合時易因受力而斷裂的機率，進而可以提升薄膜覆晶封裝結構100的可靠度，但本發明不限於此。此外，間隙G1與間隙G2可以是相同，因此，第一彎折點B1與第二彎折點B2於晶片130的兩側可以是對位配置，但本發明不限於此。間隙G1與間隙G2可以視實際設計上的需求而定。In one embodiment, the first bending point B1 and the second bending point B2 are located outside the coverage C of the wafer 130 and may have a gap with the edge E of the wafer 130 . For example, there is a gap G1 between the first bending point B1 and the edge E of the wafer 130 , and there is a gap G2 between the second bending point B2 and the edge E of the wafer 130 . Further, when the gaps (the gap G1 and the gap G2) are small, the bending points (the first bending point B1 and the second bending point B2) are closer to the die bonding area 112, which is easy to cause the pins (the first bending point B1 and the second bending point B2) to be close to the die bonding area 112. The leg 121 and the second lead 122) are broken at the bending point (the first bending point B1 and the second bending point B2) due to the force when they are joined, so the gap (the gap G1 and the gap G2) is, for example, Not less than 30 microns, in order to reduce the probability of the lead (the first lead portion 121 and the second lead 122 ) being easily broken due to force during bonding, thereby improving the reliability of the film-on-chip package structure 100, but this The invention is not limited to this. In addition, the gap G1 and the gap G2 may be the same. Therefore, the first bending point B1 and the second bending point B2 may be aligned on both sides of the wafer 130 , but the invention is not limited thereto. The gap G1 and the gap G2 can be determined according to actual design requirements.

在一實施例中，第一內引腳部1211可以自第一區A1內往遠離第三引腳123的方向斜向延伸，而第二內引腳部1221可以自第二區A2內往遠離第三引腳123的方向斜向延伸。換句話說，第一內引腳部1211位於第一區A1內的一端部可以較第一內引腳部1211位於第一區A1外的另一端部靠近第三引腳123，而第二內引腳部1221位於第二區A2內的一端部可以較第二內引腳部1221位於第二區A2外的另一端部靠近第三引腳123。In one embodiment, the first inner pin portion 1211 may extend obliquely from the first area A1 in a direction away from the third pin 123 , and the second inner pin portion 1221 may extend away from the second area A2 The direction of the third pin 123 extends obliquely. In other words, one end of the first inner lead portion 1211 inside the first area A1 may be closer to the third lead 123 than the other end of the first inner lead portion 1211 outside the first area A1, while the second inner lead portion 1211 may be closer to the third lead 123 than the other end of the first inner lead portion 1211 outside the first area A1. One end of the lead portion 1221 located in the second area A2 may be closer to the third lead 123 than the other end of the second inner lead portion 1221 located outside the second area A2.

此外，第一凸塊131與第二凸塊132可以分別順應第一內引腳部1211與第二內引腳部1221的延伸方向斜向延伸。換句話說，第一凸塊131的延伸方向可以平行於第一內引腳部1211的延伸方向，而第二凸塊132的延伸方向可以平行於第二內引腳部1221的延伸方向。因此，如圖4所示，圖4中係以第一引腳121與第一凸塊131為例，當第一引腳121於接合時發生偏移時，例如朝方向D偏移，本實施例的斜向延伸的第一凸塊131與偏移的第一引腳121的接合面積AR4相較於直向凸塊20與偏移的第一引腳121的接合面積AR3來得大，也就是說，本實施例的第一凸塊131與第二凸塊132分別順應第一內引腳部1211與第二內引腳部1221的延伸方向斜向配置，即便第一引腳121與第二引腳122於接合時發生偏移，第一凸塊131與第一引腳121之間以及第二凸塊132與第二引腳122之間仍能維持足夠的接合面積，以確保內引腳接合的品質。In addition, the first bumps 131 and the second bumps 132 may extend obliquely in accordance with the extending directions of the first inner pin portion 1211 and the second inner pin portion 1221 , respectively. In other words, the extending direction of the first bump 131 may be parallel to the extending direction of the first inner pin portion 1211 , and the extending direction of the second bump 132 may be parallel to the extending direction of the second inner pin portion 1221 . Therefore, as shown in FIG. 4 , the first pin 121 and the first bump 131 are used as an example in FIG. 4 . The bonding area AR4 between the obliquely extending first bump 131 and the offset first pin 121 is larger than the bonding area AR3 between the straight bump 20 and the offset first pin 121, that is, That is to say, the first bump 131 and the second bump 132 of the present embodiment are arranged obliquely in accordance with the extending directions of the first inner pin portion 1211 and the second inner pin portion 1221 respectively, even if the first pin 121 and the second inner pin portion 1221 are obliquely arranged When the pins 122 are offset during bonding, a sufficient bonding area can still be maintained between the first bump 131 and the first pin 121 and between the second bump 132 and the second pin 122 to ensure the inner pin Bonding quality.

在一實施例中，第一內引腳部1211與邊緣E形成第一夾角θ1，第二內引腳部1221與邊緣E形成第二夾角θ2，第一夾角θ1與第二夾角θ2大於零度且小於九十度。換句話說，第一內引腳部1211與第二內引腳部1221不會正交或平行邊緣E。舉例來說，第一夾角θ1與第二夾角θ2較佳的例如是45°，但本發明不限制第一夾角θ1與第二夾角θ2的角度，可以視實際設計上的需求而定。In one embodiment, the first inner pin portion 1211 and the edge E form a first included angle θ1, the second inner pin portion 1221 and the edge E form a second included angle θ2, and the first included angle θ1 and the second included angle θ2 are greater than zero degrees and less than ninety degrees. In other words, the edges E of the first inner pin portion 1211 and the second inner pin portion 1221 are not orthogonal or parallel. For example, the first included angle θ1 and the second included angle θ2 are preferably 45°, but the present invention does not limit the angle between the first included angle θ1 and the second included angle θ2, which may be determined according to actual design requirements.

在一實施例中，由於引腳的偏移程度越往晶片130的兩側越趨嚴重，為了抑制可撓性薄膜110在這些區域的脹縮幅度，第一引腳121與第二引腳122的分布範圍可以是分別占晶片130的長度的三分之一，也就是說，第一區A1與第二區A2分別占晶片130的長度的三分之一，但本發明不限於此。第一引腳121與第二引腳122的分布範圍可以依實際設計上的需求進行調整。In one embodiment, since the deviation of the pins is more serious toward the two sides of the wafer 130 , in order to suppress the expansion and contraction of the flexible film 110 in these areas, the first pins 121 and the second pins 122 The distribution range of A1 and A2 may respectively occupy one third of the length of the wafer 130 , that is, the first area A1 and the second area A2 respectively occupy one third of the length of the wafer 130 , but the invention is not limited thereto. The distribution range of the first pins 121 and the second pins 122 can be adjusted according to actual design requirements.

在一實施例中，為使線路結構120維持良好的電性，薄膜覆晶封裝結構100還可以包括防銲層140。防銲層140可以設置於可撓性薄膜110上，局部覆蓋線路結構120，且暴露出晶片接合區112。進一步來說，防銲層140具有開口142，且晶片接合區112實質上是由防銲層140的開口142所界定。在一實施例中，防銲層140可以暴露出第一彎折點B1與第二彎折點B2。In one embodiment, in order to maintain good electrical properties of the circuit structure 120 , the chip on film package structure 100 may further include a solder resist layer 140 . The solder mask layer 140 may be disposed on the flexible film 110 to partially cover the circuit structure 120 and expose the die bonding area 112 . Further, the solder mask 140 has an opening 142 , and the die bonding area 112 is substantially defined by the opening 142 of the solder mask 140 . In one embodiment, the solder mask layer 140 may expose the first bending point B1 and the second bending point B2.

在一實施例中，為避免濕氣及汙染侵入，薄膜覆晶封裝結構100還可以包括封裝膠體150。特別說明，圖1與圖2中封裝膠體150係採用透視繪法呈現，因此僅框示出封裝膠體150的概略分佈範圍。封裝膠體150可以填充於晶片130與可撓性薄膜110之間，且覆蓋晶片接合區112。在一實施例中，封裝膠體150可以覆蓋第一彎折點B1與第二彎折點B2。換句話說，第一彎折點B1與第二彎折點B2不會超出封裝膠體150的邊緣。In one embodiment, in order to avoid the intrusion of moisture and contamination, the chip on film package structure 100 may further include an encapsulant 150 . In particular, the encapsulant 150 in FIG. 1 and FIG. 2 is presented by a perspective drawing method, so only a general distribution range of the encapsulant 150 is shown in a frame. The encapsulant 150 can be filled between the chip 130 and the flexible film 110 and cover the die bonding area 112 . In one embodiment, the encapsulant 150 can cover the first bending point B1 and the second bending point B2. In other words, the first inflection point B1 and the second inflection point B2 do not exceed the edge of the encapsulant 150 .

綜上所述，本發明的的引腳(第一引腳與第二引腳)藉由內引腳部(第一內引腳部與第二內引腳部)的斜向設計可以擴大抑制可撓性薄膜脹縮的影響範圍，進而可以有效地抑制可撓性薄膜的脹縮幅度，降低引腳與凸塊之間對位上的誤差，進而改善引腳與凸塊之間接合不良的問題。此外，本發明藉由凸塊(第一凸塊與第二凸塊)的斜向設計可以使內引腳部(第一內引腳部與第二內引腳部)與凸塊(第一凸塊與第二凸塊)之間維持足夠的接合面積，確保當引腳(第一引腳與第二引腳)發生偏移時仍能與凸塊(第一凸塊與第二凸塊)順利對位接合，以確保內引腳接合的品質。To sum up, the pins (the first pin and the second pin) of the present invention can be enlarged and suppressed by the oblique design of the inner pin parts (the first inner pin part and the second inner pin part) The influence range of the expansion and contraction of the flexible film can effectively suppress the expansion and contraction of the flexible film, reduce the error in the alignment between the pins and the bumps, and improve the poor bonding between the pins and the bumps. question. In addition, the present invention can make the inner lead part (the first inner lead part and the second inner lead part) and the bump (the first inner lead part) and the bump (the first inner lead part) and the bump (the first Maintain sufficient bonding area between the bump and the second bump) to ensure that when the pins (the first pin and the second pin) are offset, they can still contact the bumps (the first bump and the second bump) ) Smoothly aligned joints to ensure the quality of the inner pin joints.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10:直向引腳 20:直向凸塊 100:薄膜覆晶封裝結構 110:可撓性薄膜 112:晶片接合區 120:線路結構 121:第一引腳 1211:第一內引腳部 1212:第一延伸部 122:第二引腳 1221:第二內引腳部 1222:第二延伸部 123:第三引腳 130:晶片 131:第一凸塊 132:第二凸塊 133:第三凸塊 140:防銲層 142:開口 150:封裝膠體 A:區域 A1:第一區 A2:第二區 A3:第三區 AR1、AR2:影響範圍 AR3、AR4:面積 B1:第一彎折點 B2:第二彎折點 C:覆蓋範圍 D:方向 E:邊緣 G1、G2:間隙 θ1:第一夾角 θ2:第二夾角10: Straight pins 20: Straight bump 100: Thin film flip chip package structure 110: Flexible film 112: Wafer bonding area 120: Line Structure 121: the first pin 1211: The first inner pin part 1212: First extension 122: the second pin 1221: Second inner pin part 1222: Second extension 123: The third pin 130: Wafer 131: First bump 132: Second bump 133: Third bump 140: Solder mask 142: Opening 150: encapsulating colloid A: area A1: District 1 A2: The second area A3: The third district AR1, AR2: sphere of influence AR3, AR4: Area B1: The first bending point B2: The second bending point C: Coverage D: direction E: edge G1, G2: Gap θ1: the first angle θ2: Second included angle

圖1是本發明一實施例的薄膜覆晶封裝結構的俯視示意圖。 圖2是圖1的區域A的放大示意圖。 圖3是斜向引腳與直向引腳的比較示意圖。 圖4是斜向凸塊與直向凸塊與引腳接合的比較示意圖。FIG. 1 is a schematic top view of a chip on film packaging structure according to an embodiment of the present invention. FIG. 2 is an enlarged schematic view of area A of FIG. 1 . Figure 3 is a schematic diagram of a comparison between oblique pins and straight pins. FIG. 4 is a schematic diagram showing a comparison between the oblique bump and the straight bump and pin bonding.

100:薄膜覆晶封裝結構100: Thin film flip chip package structure

110:可撓性薄膜110: Flexible film

112:晶片接合區112: Wafer bonding area

120:線路結構120: Line Structure

121:第一引腳121: the first pin

1211:第一內引腳部1211: The first inner pin part

1212:第一延伸部1212: First extension

122:第二引腳122: the second pin

1221:第二內引腳部1221: Second inner pin part

1222:第二延伸部1222: Second extension

123:第三引腳123: The third pin

130:晶片130: Wafer

131:第一凸塊131: First bump

132:第二凸塊132: Second bump

133:第三凸塊133: Third bump

140:防銲層140: Solder mask

142:開口142: Opening

150:封裝膠體150: encapsulating colloid

A:區域A: area

A1:第一區A1: District 1

A2:第二區A2: The second area

A3:第三區A3: The third district

B1:第一彎折點B1: The first bending point

B2:第二彎折點B2: The second bending point

C:覆蓋範圍C: Coverage

E:邊緣E: edge

Claims (10)

一種薄膜覆晶封裝結構，包括：可撓性薄膜，具有晶片接合區；線路結構，設置於所述可撓性薄膜上，且包括多個第一引腳、多個第二引腳與多個第三引腳，其中各所述第一引腳具有第一內引腳部與第一延伸部，各所述第二引腳具有第二內引腳部與第二延伸部；以及晶片，設置於所述晶片接合區內，所述晶片包括第一區、第二區與位於所述第一區與所述第二區之間的第三區，且具有位於所述第一區內的多個第一凸塊、位於所述第二區內的多個第二凸塊與位於所述第三區內的多個第三凸塊，所述多個第一凸塊、所述多個第二凸塊與所述多個第三凸塊沿著所述晶片的一邊緣相鄰排列，且分別對應連接所述多個第一內引腳部、所述多個第二內引腳部與所述多個第三引腳；其中所述第一內引腳部自所述第一區內斜向延伸經過所述晶片的所述邊緣並與所述第一延伸部連接於第一彎折點，所述第一延伸部局部自所述第一彎折點沿正交所述邊緣且朝遠離所述晶片接合區的方向延伸，所述第二內引腳部自所述第二區內斜向延伸經過所述邊緣並與所述第二延伸部連接於第二彎折點，所述第二延伸部局部自所述第二彎折點沿正交所述邊緣且朝遠離所述晶片接合區的方向延伸，所述多個第三引腳自所述第三區內延伸正交所述邊緣而向外延伸。 A film-on-chip packaging structure, comprising: a flexible film having a chip bonding area; a circuit structure disposed on the flexible film and comprising a plurality of first pins, a plurality of second pins and a plurality of a third pin, wherein each of the first pins has a first inner pin part and a first extension part, and each of the second pins has a second inner pin part and a second extension part; and a chip, provided In the wafer bonding area, the wafer includes a first area, a second area, and a third area located between the first area and the second area, and has a plurality of areas located in the first area. a plurality of first bumps, a plurality of second bumps in the second area, and a plurality of third bumps in the third area, the plurality of first bumps, the plurality of first bumps Two bumps and the plurality of third bumps are adjacently arranged along an edge of the wafer, and are respectively connected to the plurality of first inner lead portions, the plurality of second inner lead portions and the the plurality of third pins; wherein the first inner pin portion extends obliquely through the edge of the wafer from the first area and is connected to the first bending portion with the first extension portion point, the first extension portion partially extends from the first bending point along the direction orthogonal to the edge and away from the die bonding area, and the second inner lead portion extends from the second area extending obliquely across the edge and connecting with the second extension at a second bending point, the second extension partially extending from the second bending point along the edge perpendicular to the edge and facing away from the wafer The direction of the bonding area extends, and the plurality of third pins extend from the third area perpendicular to the edge and extend outward. 如請求項1所述的薄膜覆晶封裝結構，其中所述多個第一凸塊與所述多個第二凸塊分別順應所述多個第一內引腳部與所述多個第二內引腳部的延伸方向斜向延伸。 The thin film flip chip package structure of claim 1, wherein the plurality of first bumps and the plurality of second bumps conform to the plurality of first inner lead portions and the plurality of second bumps, respectively The extending direction of the inner pin portion extends obliquely. 如請求項1所述的薄膜覆晶封裝結構，其中所述第一彎折點與所述第二彎折點位於所述晶片的覆蓋範圍之外，且與所述晶片的所述邊緣之間具有間隙。 The chip on film package structure of claim 1, wherein the first bending point and the second bending point are located outside the coverage of the wafer and between the edge of the wafer with gaps. 如請求項3所述的薄膜覆晶封裝結構，其中所述間隙不小於30微米。 The chip on film package structure of claim 3, wherein the gap is not less than 30 microns. 如請求項1所述的薄膜覆晶封裝結構，其中所述第一內引腳部自所述第一區內往遠離所述多個第三引腳的方向斜向延伸，所述第二內引腳部自所述第二區內往遠離所述多個第三引腳的方向斜向延伸。 The chip on film package structure of claim 1, wherein the first inner lead portion extends obliquely from the first area in a direction away from the plurality of third leads, and the second inner lead portion extends obliquely in a direction away from the plurality of third leads. The lead portion extends obliquely from the second area in a direction away from the plurality of third leads. 如請求項1所述的薄膜覆晶封裝結構，其中所述第一內引腳部與所述邊緣形成第一夾角，所述第二內引腳部與所述邊緣形成第二夾角，所述第一夾角與所述第二夾角大於零度且小於九十度。 The chip on film package structure according to claim 1, wherein the first inner lead portion forms a first included angle with the edge, the second inner lead portion forms a second included angle with the edge, and the The first included angle and the second included angle are greater than zero degrees and less than ninety degrees. 如請求項1所述的薄膜覆晶封裝結構，更包括防銲層，設置於所述可撓性薄膜上，所述防銲層局部覆蓋所述線路結構，且暴露出所述晶片接合區。 The chip-on-film package structure according to claim 1, further comprising a solder resist layer disposed on the flexible film, the solder resist layer partially covering the circuit structure and exposing the die bonding area. 如請求項7所述的薄膜覆晶封裝結構，其中所述防銲層暴露出所述第一彎折點與所述第二彎折點。 The chip on film package structure of claim 7, wherein the solder mask layer exposes the first bending point and the second bending point. 如請求項1所述的薄膜覆晶封裝結構，更包括封裝膠體，填充於所述晶片與所述可撓性薄膜之間，且覆蓋所述晶片接合區。 The chip-on-film packaging structure of claim 1, further comprising an encapsulant, which is filled between the chip and the flexible film and covers the chip bonding area. 如請求項9所述的薄膜覆晶封裝結構，其中所述封裝膠體覆蓋所述第一彎折點與所述第二彎折點。The chip-on-film packaging structure of claim 9, wherein the encapsulant covers the first bending point and the second bending point.
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