TWI775167B - Operating system and control method - Google Patents

Operating system and control method Download PDF

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TWI775167B
TWI775167B TW109134073A TW109134073A TWI775167B TW I775167 B TWI775167 B TW I775167B TW 109134073 A TW109134073 A TW 109134073A TW 109134073 A TW109134073 A TW 109134073A TW I775167 B TWI775167 B TW I775167B
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circuit
trigger
control parameter
core circuit
parameter
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TW109134073A
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TW202215201A (en
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王政治
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新唐科技股份有限公司
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Abstract

An operating system including a first storage circuit, a second storage circuit, a selection circuit, a core circuit, and a trigger-source management circuit is provided. The first storage circuit stores a first control parameter. The second storage circuit stores a second control parameter. When a first trigger source enables a first trigger signal, the trigger-source management circuit directs the selection circuit to serve the first control parameter as an output parameter such that the core circuit enters a first mode to perform a first operation. When a second trigger source enables a second trigger signal, the trigger-source management circuit directs the selection circuit to serve the second control parameter the output parameter such that the core circuit enters a second mode to perform a second operation.

Description

操作系統及控制方法Operating system and control method

本發明係有關於一種操作系統，特別是有關於一種具有複數操作模式的操作系統。The present invention relates to an operating system, and more particularly, to an operating system having a plurality of operating modes.

隨著科技的進步，電子裝置的種類及功能愈來愈多。大部分的電子裝置的內部具有一中央處理器以及許多處理電路。中央處理器用以控制所有處理電路的操作。然而，中央處理器在同一時間只能與單一處理電路溝通。因此，造成許多處理電路的閒置。With the advancement of technology, there are more and more types and functions of electronic devices. Most electronic devices have a central processing unit and many processing circuits inside. The central processing unit is used to control the operation of all processing circuits. However, the central processing unit can only communicate with a single processing circuit at a time. Therefore, many processing circuits are idle.

本發明之一實施例提供一種操作系統，包括一第一儲存電路、一第二儲存電路、一選擇電路、一核心電路以及一觸發源管理電路。第一儲存電路儲存一第一控制參數。第二儲存電路儲存一第二控制參數。選擇電路用以提供一輸出參數。核心電路接收輸出參數。觸發源管理電路用以控制選擇電路。當一第一觸發源致能一第一觸發信號時，觸發源管理電路命令選擇電路將第一控制參數作為輸出參數，使得核心電路進入第一模式，用以執行一第一操作。當一第二觸發源致能一第二觸發信號時，觸發源管理電路命令選擇電路將第二控制參數作為輸出參數，使得核心電路進入第二模式，用以執行一第二操作。An embodiment of the present invention provides an operating system including a first storage circuit, a second storage circuit, a selection circuit, a core circuit, and a trigger source management circuit. The first storage circuit stores a first control parameter. The second storage circuit stores a second control parameter. The selection circuit is used to provide an output parameter. The core circuit receives output parameters. The trigger source management circuit is used to control the selection circuit. When a first trigger source enables a first trigger signal, the trigger source management circuit instructs the selection circuit to use the first control parameter as an output parameter, so that the core circuit enters the first mode for executing a first operation. When a second trigger source enables a second trigger signal, the trigger source management circuit instructs the selection circuit to use the second control parameter as an output parameter, so that the core circuit enters the second mode for executing a second operation.

本發明另提供一種控制方法，用以控制一核心電路的操作模式。本發明的控制方法包括，儲存一第一控制參數於一第一儲存電路中；儲存一第二控制參數於一第二儲存電路中；判斷一第一觸發源是否致能一第一觸發信號；當第一觸發信號被致能時，提供第一控制參數予核心電路，使得核心電路進入一第一模式，用以進行一第一操作；判斷一第二觸發源是否發出致能一第二觸發信號；以及當第二觸發信號被致能時，提供第二控制參數予核心電路，使得核心電路進入一第二模式，用以進行一第二操作。The present invention further provides a control method for controlling the operation mode of a core circuit. The control method of the present invention includes: storing a first control parameter in a first storage circuit; storing a second control parameter in a second storage circuit; determining whether a first trigger source enables a first trigger signal; When the first trigger signal is enabled, a first control parameter is provided to the core circuit, so that the core circuit enters a first mode for performing a first operation; it is judged whether a second trigger source has issued a second trigger to enable a second trigger signal; and when the second trigger signal is enabled, the second control parameter is provided to the core circuit, so that the core circuit enters a second mode for performing a second operation.

本發明之控制方法可經由本發明之操作系統來實作，其為可執行特定功能之硬體或韌體，亦可以透過程式碼方式收錄於一紀錄媒體中，並結合特定硬體來實作。當程式碼被電子裝置、處理器、電腦或機器載入且執行時，電子裝置、處理器、電腦或機器變成用以實行本發明之操作系統。The control method of the present invention can be implemented through the operating system of the present invention, which is hardware or firmware that can perform specific functions, and can also be recorded in a recording medium by means of code, and implemented in combination with specific hardware. . When the code is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes an operating system for implementing the present invention.

為讓本發明之目的、特徵和優點能更明顯易懂，下文特舉出實施例，並配合所附圖式，做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中，實施例中的各元件之配置係為說明之用，並非用以限制本發明。另外，實施例中圖式標號之部分重覆，係為了簡化說明，並非意指不同實施例之間的關聯性。In order to make the objects, features and advantages of the present invention more obvious and easy to understand, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings. The present specification provides different embodiments to illustrate the technical features of different embodiments of the present invention. Wherein, the configuration of each element in the embodiment is for illustration, and not for limiting the present invention. In addition, parts of the reference numerals in the drawings in the embodiments are repeated for the purpose of simplifying the description, and do not mean the correlation between different embodiments.

第1圖為本發明之操作系統的示意圖。如圖所示，操作系統100包括一中央處理器(CPU)102、一匯流排104、一處理電路106以及觸發源108、110及112。中央處理器102透過匯流排104與處理電路106溝通。在一可能實施例中，中央處理器102寫入資料至處理電路106的儲存電路(未顯示)中。本發明並不限定匯流排104的種類。在一可能實施例中，匯流排104係以一並列方式或是一串列方式，在中央處理器102與處理電路106之間傳送資料、信號及電源之至少一者。FIG. 1 is a schematic diagram of the operating system of the present invention. As shown, the operating system 100 includes a central processing unit (CPU) 102 , a bus 104 , a processing circuit 106 , and trigger sources 108 , 110 and 112 . The central processing unit 102 communicates with the processing circuit 106 through the bus bar 104 . In one possible embodiment, the central processing unit 102 writes data to a storage circuit (not shown) of the processing circuit 106 . The present invention does not limit the type of the bus bar 104 . In a possible embodiment, the bus bar 104 transmits at least one of data, signals, and power between the central processing unit 102 and the processing circuit 106 in a parallel manner or a serial manner.

處理電路106耦接匯流排104，用以接收來自中央處理器102的訊息(資料、信號及電源之至少一者)。處理電路106更耦接觸發源108、110及112，用以接收觸發信號STA 1~STA N、STB 1~STB M及STC 1~STC Q。在本實施例中，當觸發信號STA 1~STA N、STB 1~STB M及STC 1~STC Q之一者被致能時，處理電路106根據被致能的觸發信號的來源，進入相對應的的操作模式，用以進行相對應的操作。 The processing circuit 106 is coupled to the bus bar 104 for receiving information (at least one of data, signal and power) from the central processing unit 102 . The processing circuit 106 is further coupled to the contact generators 108 , 110 and 112 for receiving the trigger signals STA 1 ˜STA N , STB 1 ˜STB M and STC 1 ˜STC Q . In this embodiment, when one of the trigger signals STA 1 ˜STA N , STB 1 ˜STB M and STC 1 ˜STC Q is enabled, the processing circuit 106 enters the corresponding trigger signal according to the source of the enabled trigger signal. The operation mode is used to perform the corresponding operation.

舉例而言，當觸發源108致能觸發信號STA 1~STA N之一者時，處理電路106進入一第一模式。在第一模式下，處理電路106進行一第一操作。當觸發源110致能觸發信號STB 1~STB M之一者時，處理電路106進入一第二模式。在第二模式下，處理電路106進行一第二操作。當觸發源112致能觸發信號STC 1~STC Q之一者時，處理電路106可能進入第一或第二模式。在其它實施例中，當觸發信號STC 1~STC Q之一者被致能時，處理電路106可能進入一第三模式，用以進行一第三操作。 For example, when the trigger source 108 enables one of the trigger signals STA 1 ˜STA N , the processing circuit 106 enters a first mode. In the first mode, the processing circuit 106 performs a first operation. When the trigger source 110 enables one of the trigger signals STB 1 to STB M , the processing circuit 106 enters a second mode. In the second mode, the processing circuit 106 performs a second operation. When the trigger source 112 enables one of the trigger signals STC 1 ˜STC Q , the processing circuit 106 may enter the first or second mode. In other embodiments, when one of the trigger signals STC 1 ˜STC Q is enabled, the processing circuit 106 may enter a third mode for performing a third operation.

在一些實施例中，當處理電路106進入第一模式並執行第一操作時，處理電路106忽略來自觸發源110及112的觸發信號。因此，在第一模式下，即使觸發源110致能觸發信號STB 1~STB M之一者時，處理電路106持續進行第一操作，直到處理電路106完成第一操作。同樣地，當處理電路106進入第二模式並進行第二操作時，即使觸發源108致能觸發信號STA 1~STA N之一者時，處理電路106持續進行第二操作，直到處理電路106完成第二操作。 In some embodiments, the processing circuit 106 ignores trigger signals from the trigger sources 110 and 112 when the processing circuit 106 enters the first mode and performs the first operation. Therefore, in the first mode, even when the trigger source 110 enables one of the trigger signals STB 1 to STB M , the processing circuit 106 continues to perform the first operation until the processing circuit 106 completes the first operation. Likewise, when the processing circuit 106 enters the second mode and performs the second operation, even if the trigger source 108 enables one of the trigger signals STA 1 -STA N , the processing circuit 106 continues to perform the second operation until the processing circuit 106 completes Second operation.

在一可能實施例中，處理電路106根據觸發信號STA 1~STA N、STB 1~STB M及STC 1~STC Q的位準，得知觸發信號STA 1~STA N、STB 1~STB M及STC 1~STC Q是否被致能。以觸發信號STA 1為例，當觸發信號STA 1為一第一特定位準時，表示觸發源108致能觸發信號STA 1。因此，處理電路106進入第一模式。當觸發信號STA 1不為特定位準時，表示觸發源108未致能觸發信號STA 1。因此，處理電路106繼續偵測其它觸發信號的位準。第一特定位準可能是一高位準或是一低位準。 In a possible embodiment, the processing circuit 106 obtains the trigger signals STA 1 ˜STA N , STB 1 ˜STB M and the trigger signals STA 1 ˜STA N , STB 1 ˜STB M and Whether STC 1 ~STC Q are enabled. Taking the trigger signal STA 1 as an example, when the trigger signal STA 1 is at a first specific level, it means that the trigger source 108 enables the trigger signal STA 1 . Therefore, the processing circuit 106 enters the first mode. When the trigger signal STA 1 is not at a specific level, it means that the trigger source 108 does not enable the trigger signal STA 1 . Therefore, the processing circuit 106 continues to detect the levels of other trigger signals. The first specific level may be a high level or a low level.

本發明並不限定處理電路106的架構。在一可能實施例中，處理電路106係為一計時器/計數器(timer/counter)。在此例中，當處理電路106進入第一模式時，處理電路106進行一計時操作。此時，處理電路106作為一計時器。當處理電路106進入第二模式，處理電路106進行一計數操作。此時，處理電路106作為一計數器。在另一可能實施例中，處理電路106係為一串列/並列電路(series and parallel circuit)。在此例中，處理電路106可能具有一第一介面以及一第二介面。第一介面係為一串列介面，如一通用非同步接收器傳輸 (UART)介面、一同步週邊設備介面(SPI)或是一內部積體電路(I2C)介面。第二介面係為一並列介面，如一通用介面匯流排(General-Purpose Interface Bus；GPIB)。當處理電路106進入第一模式時，處理電路106利用第一介面與一外部裝置(如中央處理器102、觸發源108及110之至少一者)溝通。當處理電路106進入第二模式時，處理電路106利用第二介面與外部裝置溝通。在其它實施例中，處理電路106具有更多的操作模式，用以進行更多的操作。The present invention does not limit the structure of the processing circuit 106 . In one possible embodiment, the processing circuit 106 is a timer/counter. In this example, when the processing circuit 106 enters the first mode, the processing circuit 106 performs a timing operation. At this time, the processing circuit 106 acts as a timer. When the processing circuit 106 enters the second mode, the processing circuit 106 performs a counting operation. At this time, the processing circuit 106 acts as a counter. In another possible embodiment, the processing circuit 106 is a series and parallel circuit. In this example, the processing circuit 106 may have a first interface and a second interface. The first interface is a serial interface, such as a Universal Asynchronous Receiver Transmission (UART) interface, a Synchronous Peripheral Device Interface (SPI) or an Inter-Integrated Circuit (I2C) interface. The second interface is a parallel interface, such as a General-Purpose Interface Bus (GPIB). When the processing circuit 106 enters the first mode, the processing circuit 106 communicates with an external device (eg, the central processing unit 102 , at least one of the trigger sources 108 and 110 ) using the first interface. When the processing circuit 106 enters the second mode, the processing circuit 106 communicates with the external device through the second interface. In other embodiments, the processing circuit 106 has more operating modes to perform more operations.

在一些實施例中，在處理電路160完成相對應的操作時，處理電路106可能致能一輸出信號SOUT。在一可能實施例中，中央處理器102透過匯流排104，接收輸出信號SOUT。在另一實施例中，中央處理器102可能透過其它匯流排接收輸出信號SOUT。在其它實施例中，中央處理器102可能直接耦接處理電路106，用以接收輸出信號SOUT。在一些實施例中，處理電路106可能透過匯流排104提供輸出信號SOUT予其它外部元件(如觸發源108、110及112之至少一者)，或是直接提供輸出信號SOUT予其它外部元件。In some embodiments, when the processing circuit 160 completes the corresponding operation, the processing circuit 106 may enable an output signal SOUT. In a possible embodiment, the central processing unit 102 receives the output signal SOUT through the bus bar 104 . In another embodiment, the CPU 102 may receive the output signal SOUT through other bus bars. In other embodiments, the central processing unit 102 may be directly coupled to the processing circuit 106 for receiving the output signal SOUT. In some embodiments, the processing circuit 106 may provide the output signal SOUT to other external components (eg, at least one of the trigger sources 108 , 110 and 112 ) through the bus bar 104 , or directly provide the output signal SOUT to other external components.

在一可能實施例中，中央處理器102根據輸出信號SOUT，判斷處理電路106是否完成相對應的操作。舉例而言，當處理電路106完成第一操作或是第二操作時，處理電路106可能設定輸出信號SOUT為一第二特定位準。因此，中央處理器102根據具有特定位準的輸出信號SOUT，得知處理電路106已完成第一操作或是第二操作。第二特定位準可能為一高位準或是一低位準。在本實施例中，由於處理電路106根據被致能的觸發信號的來源，主動地執行相對應的操作，而不需中央處理器102時時監控觸發源108、110及112是否致能觸發信號，故可節省中央處理器102的功耗。In a possible embodiment, the central processing unit 102 determines whether the processing circuit 106 completes the corresponding operation according to the output signal SOUT. For example, when the processing circuit 106 completes the first operation or the second operation, the processing circuit 106 may set the output signal SOUT to a second specific level. Therefore, the central processing unit 102 knows that the processing circuit 106 has completed the first operation or the second operation according to the output signal SOUT having a specific level. The second specific level may be a high level or a low level. In this embodiment, since the processing circuit 106 actively performs the corresponding operation according to the source of the enabled trigger signal, it is not necessary for the central processing unit 102 to constantly monitor whether the trigger sources 108, 110 and 112 enable the trigger signal , so the power consumption of the central processing unit 102 can be saved.

在其它實施例中，處理電路106更接收時脈信號CLK 1及CLK 2。在此例中，當處理電路106進入第一模式時，處理電路106可能根據時脈信號CLK 1或CLK 2，進行第一操作。同樣地，當處理電路106進入第二模式時，處理電路106可能根據時脈信號CLK 1或CLK 2，進行第二操作。在其它實施例中，處理電路106可能接收更多或更少的時脈信號。 In other embodiments, the processing circuit 106 further receives the clock signals CLK 1 and CLK 2 . In this example, when the processing circuit 106 enters the first mode, the processing circuit 106 may perform the first operation according to the clock signal CLK 1 or CLK 2 . Likewise, when the processing circuit 106 enters the second mode, the processing circuit 106 may perform a second operation according to the clock signal CLK 1 or CLK 2 . In other embodiments, the processing circuit 106 may receive more or fewer clock signals.

觸發源108包括週邊電路PA 1~PA N，用以提供觸發信號STA 1~STA N。觸發源110包括週邊電路PB 1~PB M，用以提供觸發信號STB 1~STB M。觸發源112包括週邊電路PC 1~PC Q，用以提供觸發信號STC 1~STC Q。在本實施例中，週邊電路PA 1~PA N位於同一觸發源中，故週邊電路PA 1~PA N可稱為第一週邊電路。在此例中，週邊電路PB 1~PB M稱為第二週邊電路，週邊電路PC 1~PC Q稱為第三週邊電路。 The trigger source 108 includes peripheral circuits PA 1 ˜PA N for providing trigger signals STA 1 ˜STA N . The trigger source 110 includes peripheral circuits PB 1 ˜PB M for providing trigger signals STB 1 ˜STB M . The trigger source 112 includes peripheral circuits PC 1 ˜PC Q for providing trigger signals STC 1 ˜STC Q . In this embodiment, the peripheral circuits PA 1 ˜PAN are located in the same trigger source, so the peripheral circuits PA 1 ˜PAN can be referred to as first peripheral circuits. In this example, the peripheral circuits PB 1 to PB M are referred to as second peripheral circuits, and the peripheral circuits PC 1 to PC Q are referred to as third peripheral circuits.

本發明並不限定週邊電路PA 1~PA N、PB 1~PB M及PC 1~PC Q的種類。任何電路均可作為週邊電路PA 1~PA N、PB 1~PB M及PC 1~PC Q之一者。由於週邊電路PA 1~PA N、PB 1~PB M及PC 1~PC Q的特性相似，故以週邊電路PA 1為例。在此例中，當週邊電路PA 1完成本身的操作時，週邊電路PA 1致能觸發信號STA 1。此時，觸發信號STA 1可能為一特定位準。然而，如果週邊電路PA 1尚未完成本身的操作時，週邊電路PA 1不致能觸發信號STA 1。此時，觸發信號STA 1可能不為特定位準。 The present invention does not limit the types of the peripheral circuits PA 1 ˜PAN , PB 1 ˜PB M , and PC 1 ˜PC Q. Any circuit can be used as one of the peripheral circuits PA 1 ˜PAN , PB 1 ˜PB M and PC 1 ˜PC Q . Since the characteristics of the peripheral circuits PA 1 ˜PAN , PB 1 ˜PB M and PC 1 ˜PC Q are similar, the peripheral circuit PA 1 is taken as an example. In this example, when the peripheral circuit PA 1 completes its own operation, the peripheral circuit PA 1 enables the trigger signal STA 1 . At this time, the trigger signal STA1 may be at a specific level. However, if the peripheral circuit PA 1 has not completed its own operation, the peripheral circuit PA 1 cannot trigger the signal STA 1 . At this time, the trigger signal STA1 may not be at a specific level.

觸發源108、110及112各自獨立。換句話說，觸發源108、110及112不共用任何週邊電路。另外，本發明不限定觸發源108、110及112的週邊電路的數量。在一可能實施例中，觸發源108、110及112之一者的週邊電路的數量可能相同於觸發源108、110及112之另一者的週邊電路的數量。在另一可能實施例中，觸發源108、110及112之一者的週邊電路的數量可能不同於觸發源108、110及112之另一者的週邊電路的數量。Trigger sources 108, 110 and 112 are each independent. In other words, trigger sources 108, 110 and 112 do not share any peripheral circuits. In addition, the present invention does not limit the number of peripheral circuits of the trigger sources 108 , 110 and 112 . In a possible embodiment, the number of peripheral circuits of one of the trigger sources 108 , 110 and 112 may be the same as the number of peripheral circuits of the other of the trigger sources 108 , 110 and 112 . In another possible embodiment, the number of peripheral circuits of one of the trigger sources 108 , 110 and 112 may be different from the number of peripheral circuits of the other of the trigger sources 108 , 110 and 112 .

第2圖為本發明之處理電路的示意圖。如圖所示，處理電路200包括儲存電路RT 1~RT 3、一選擇電路202、一核心電路204以及一觸發源管理電路206。儲存電路RT 1~RT 3各自獨立。在一可能實施例中，儲存電路RT 1~RT 3係為暫存器。儲存電路RT 1~RT 3分別儲存控制參數P 1~P 3。控制參數P 1~P 3用以控制核心電路204的操作模式。在一可能實施例中，控制參數P 1~P 3由處理電路200以外的一外部裝置(如第1圖的中央處理器102)所提供。在此例中，第1圖的中央處理器102可能透過匯流排104，將控制參數P 1~P 3分別寫入儲存電路RT 1~RT 3。本發明並不限定儲存電路的數量。在其它實施例中，處理電路200可能具有更多或更少的儲存電路。 FIG. 2 is a schematic diagram of the processing circuit of the present invention. As shown in the figure, the processing circuit 200 includes storage circuits RT 1 -RT 3 , a selection circuit 202 , a core circuit 204 and a trigger source management circuit 206 . The storage circuits RT 1 to RT 3 are independent of each other. In a possible embodiment, the storage circuits RT 1 -RT 3 are registers. The storage circuits RT 1 ˜RT 3 store the control parameters P 1 ˜P 3 respectively. The control parameters P 1 -P 3 are used to control the operation mode of the core circuit 204 . In a possible embodiment, the control parameters P 1 -P 3 are provided by an external device other than the processing circuit 200 (eg, the central processing unit 102 in FIG. 1 ). In this example, the central processing unit 102 of FIG. 1 may write the control parameters P 1 ˜P 3 into the storage circuits RT 1 ˜RT 3 respectively through the bus bar 104 . The present invention does not limit the number of storage circuits. In other embodiments, the processing circuit 200 may have more or less storage circuits.

選擇電路202耦接儲存電路RT 1~RT 3。在一可能實施例中，選擇電路202根據一選擇信號SEL，將控制參數P 1~P 3之一者作為一輸出參數PO。舉例而言，當選擇信號SEL具有一第一狀態(如第一電壓)時，選擇電路202將控制參數P 1作為輸出參數PO。當選擇信號SEL具有一第二狀態(如第二電壓)時，選擇電路202將控制參數P 2作為輸出參數PO。當選擇信號SEL具有一第三狀態(如第三電壓)時，選擇電路202將控制參數P 3作為輸出參數PO。在其它實施例中，選擇電路202係根據選擇信號SEL的頻率，將控制參數P 1~P 3之一者作為一輸出參數PO。在一些實施例中，選擇電路202根據多個選擇信號，將控制參數P 1~P 3之一者作為輸出參數PO。本發明並不限定選擇電路202的架構。在一可能實施例中，選擇電路202係為一多工器。 The selection circuit 202 is coupled to the storage circuits RT 1 -RT 3 . In a possible embodiment, the selection circuit 202 uses one of the control parameters P 1 to P 3 as an output parameter PO according to a selection signal SEL. For example, when the selection signal SEL has a first state (eg, a first voltage), the selection circuit 202 uses the control parameter P 1 as the output parameter PO. When the selection signal SEL has a second state (eg, the second voltage), the selection circuit 202 uses the control parameter P 2 as the output parameter PO. When the selection signal SEL has a third state (eg, a third voltage), the selection circuit 202 uses the control parameter P3 as the output parameter PO. In other embodiments, the selection circuit 202 uses one of the control parameters P 1 to P 3 as an output parameter PO according to the frequency of the selection signal SEL. In some embodiments, the selection circuit 202 uses one of the control parameters P 1 to P 3 as the output parameter PO according to a plurality of selection signals. The present invention does not limit the structure of the selection circuit 202 . In one possible embodiment, the selection circuit 202 is a multiplexer.

核心電路204耦接選擇電路202，用以接收輸出參數PO，並根據輸出參數PO進入相對應的模式。舉例而言，當選擇電路202將控制參數P 1作為輸出參數PO時，核心電路204進入一第一模式，用以執行一第一操作。當選擇電路202將控制參數P 2作為輸出參數PO時，核心電路204進入一第二模式，用以執行一第二操作。當選擇電路202將控制參數P 3作為輸出參數PO時，核心電路204進入一第三模式，用以執行一第三操作。在其它實施例中，當選擇電路202將控制參數P 3作為輸出參數PO時，核心電路204進入第一模式或第二模式。 The core circuit 204 is coupled to the selection circuit 202 for receiving the output parameter PO and entering a corresponding mode according to the output parameter PO. For example, when the selection circuit 202 uses the control parameter P1 as the output parameter PO, the core circuit 204 enters a first mode for performing a first operation. When the selection circuit 202 uses the control parameter P 2 as the output parameter PO, the core circuit 204 enters a second mode for performing a second operation. When the selection circuit 202 uses the control parameter P3 as the output parameter PO, the core circuit 204 enters a third mode for performing a third operation. In other embodiments, when the selection circuit 202 uses the control parameter P3 as the output parameter PO, the core circuit 204 enters the first mode or the second mode.

本發明並不限定核心電路204的架構。在一可能實施例中，核心電路204係為一計時器/計數器的核心電路。在此例中，核心電路204具有雙操作模式。當選擇電路202將控制參數P 1作為輸出參數PO時，核心電路204進入第一模式，用以執行一計時操作。當選擇電路202將控制參數P 2作為輸出參數PO時，核心電路204進入第二模式，用以執行一計數操作。 The present invention does not limit the architecture of the core circuit 204 . In a possible embodiment, the core circuit 204 is the core circuit of a timer/counter. In this example, the core circuit 204 has a dual mode of operation. When the selection circuit 202 uses the control parameter P1 as the output parameter PO, the core circuit 204 enters the first mode for performing a timing operation. When the selection circuit 202 uses the control parameter P 2 as the output parameter PO, the core circuit 204 enters the second mode for performing a counting operation.

在一可能實施例中，當選擇電路202將控制參數P 3作為輸出參數PO時，核心電路204可能進入第一模式，用以執行計時操作。在此例中，當選擇電路202將控制參數P 1作為輸出參數PO時，核心電路204執行計時操作的總執行時間為一第一時間(如10秒)。當選擇電路202將控制參數P 3作為輸出參數PO時，核心電路204執行計時操作的總執行時間為一第二時間(如5秒)。第一時間不同於第二時間。 In a possible embodiment, when the selection circuit 202 uses the control parameter P3 as the output parameter PO, the core circuit 204 may enter the first mode for performing the timing operation. In this example, when the selection circuit 202 uses the control parameter P 1 as the output parameter PO, the total execution time for the core circuit 204 to perform the timing operation is a first time (eg, 10 seconds). When the selection circuit 202 uses the control parameter P 3 as the output parameter PO, the total execution time of the core circuit 204 for performing the timing operation is a second time (eg, 5 seconds). The first time is different from the second time.

在另一可能實施例中，當選擇電路202將控制參數P 3作為輸出參數PO時，核心電路204進入第二模式，用以執行計數操作。在此例中，當選擇電路202將控制參數P 2作為輸出參數PO時，核心電路204可能先設定一第一目標值，並重置一計數值。核心電路204可能根據時脈信號CLK 1的脈衝數量，調整計數值。當計數值達第一目標值時，核心電路204停止執行計數操作。當選擇電路202將控制參數P 3作為輸出參數PO時，核心電路204設定一第二目標值，並再次重置計數值。核心電路204可能根據時脈信號CLK 1的脈衝數量，調整計數值。當計數值達第二目標值時，核心電路204停止執行計數操作。在此例中，第一目標值不同於第二目標值。本發明並不限定核心電路204如何調整計數值。核心電路204可能逐漸減少或逐漸增加計數值。 In another possible embodiment, when the selection circuit 202 uses the control parameter P3 as the output parameter PO, the core circuit 204 enters the second mode for performing the counting operation. In this example, when the selection circuit 202 uses the control parameter P 2 as the output parameter PO, the core circuit 204 may first set a first target value and reset a count value. The core circuit 204 may adjust the count value according to the number of pulses of the clock signal CLK1. When the count value reaches the first target value, the core circuit 204 stops performing the count operation. When the selection circuit 202 uses the control parameter P3 as the output parameter PO, the core circuit 204 sets a second target value and resets the count value again. The core circuit 204 may adjust the count value according to the number of pulses of the clock signal CLK1. When the count value reaches the second target value, the core circuit 204 stops performing the count operation. In this example, the first target value is different from the second target value. The present invention does not limit how the core circuit 204 adjusts the count value. The core circuit 204 may gradually decrease or gradually increase the count value.

在本實施例中，核心電路204根據輸出參數PO，決定計時操作的總執行時間、計時操作的時脈來源、計數操作的目標值、計數操作的時脈來源、計數操作的種類(一向上計數或是一向下計數)。在其它實施例中，核心電路204根據輸出參數PO，計數一外部時脈(如CLK 1或CLK 2)的上升邊緣或是下降邊緣的數量。 In this embodiment, the core circuit 204 determines the total execution time of the timing operation, the clock source of the timing operation, the target value of the counting operation, the clock source of the counting operation, and the type of the counting operation according to the output parameter PO (one up counting or counting down). In other embodiments, the core circuit 204 counts the number of rising edges or falling edges of an external clock (eg, CLK 1 or CLK 2 ) according to the output parameter PO.

觸發源管理電路206耦接觸發源108、110及112。觸發源管理電路206用以判斷觸發源108、110及112是否發出致能的觸發信號。當觸發源108、110或112發出致能的觸發信號時，觸發源管理電路206透過選擇信號SEL，命令選擇電路202將相對應的控制參數作為輸出參數PO，用以控制核心電路204的操作模式。 Trigger source management circuit 206 is coupled to trigger sources 108 , 110 and 112 . The trigger source management circuit 206 is used for judging whether the trigger sources 108 , 110 and 112 send enabled trigger signals. When the trigger source 108 , 110 or 112 sends an enabled trigger signal, the trigger source management circuit 206 instructs the selection circuit 202 to use the corresponding control parameter as the output parameter PO through the selection signal SEL to control the operation mode of the core circuit 204 .

舉例而言，當觸發源108致能一觸發信號(如第1圖的觸發信號STA1~STAN之一者)時，觸發源管理電路208產生選擇信號SEL，用以命令選擇電路202將控制參數P1作為輸出參數PO。因此，核心電路204進入第一模式，用以進行第一操作。在一可能實施例中，核心電路204根據輸出參數PO(即控制參數P1)，選擇時脈信號CLK1或CLK2，並根據選擇的時脈信號進行第一操作。在完成第一操作後，核心電路204致能輸出信號SOUT。 For example, when the trigger source 108 enables a trigger signal (such as one of the trigger signals STA 1 ˜STA N in FIG. 1 ), the trigger source management circuit 208 generates the selection signal SEL for instructing the selection circuit 202 to control the Parameter P 1 as output parameter PO. Therefore, the core circuit 204 enters the first mode for performing the first operation. In a possible embodiment, the core circuit 204 selects the clock signal CLK 1 or CLK 2 according to the output parameter PO (ie, the control parameter P 1 ), and performs the first operation according to the selected clock signal. After completing the first operation, the core circuit 204 enables the output signal SOUT.

當觸發源110致能一觸發信號(如第1圖的觸發信號STB1~STBM之一者)時，觸發源管理電路206透過選擇信號SEL，命令選擇電路202將控制參數P2作為輸出參數PO。因此，核心電路204進入第二模式，用以執行第二操作。在第二模式下，核心電路204可能根據輸出參數PO(即控制參數P2)，選擇時脈信號CLK1或CLK2，並根據選擇的時脈信號進行第二操作。在完成第二操作後，核心電路204致能輸出信號SOUT。 When the trigger source 110 enables a trigger signal (such as one of the trigger signals STB 1 to STB M in FIG. 1 ), the trigger source management circuit 206 instructs the selection circuit 202 to use the control parameter P 2 as an output parameter through the selection signal SEL po. Therefore, the core circuit 204 enters the second mode for performing the second operation. In the second mode, the core circuit 204 may select the clock signal CLK 1 or CLK 2 according to the output parameter PO (ie, the control parameter P 2 ), and perform the second operation according to the selected clock signal. After completing the second operation, the core circuit 204 enables the output signal SOUT.

當觸發源112致能一觸發信號(如第1圖的觸發信號STC1~STCQ之一者)時，觸發源管理電路208可能命令選擇電路202將控制參數P3作為輸出參數PO。此時，核心電路204可能進入第一、第二模式或是第三模式。在此例中，核心電路204可能根據輸出參數PO(即控制參數P3)，選擇時脈信號CLK1或CLK2。 When the trigger source 112 enables a trigger signal (eg, one of the trigger signals STC 1 to STC Q in FIG. 1 ), the trigger source management circuit 208 may instruct the selection circuit 202 to use the control parameter P 3 as the output parameter PO. At this time, the core circuit 204 may enter the first mode, the second mode or the third mode. In this example, the core circuit 204 may select the clock signal CLK 1 or CLK 2 according to the output parameter PO (ie, the control parameter P 3 ).

在一些實施例中，當核心電路204進入一特定模式時，即使觸發源管理電路206發現其它的觸發源致能觸發信號時，觸發源管理電路206忽略來自其它觸發源的觸發信號。舉例而言，在核心電路204進入第一模式後，即使觸發源110致能觸發信號STB1~STBM之一者時，核心電路204維持執行第一操作。 In some embodiments, when the core circuit 204 enters a specific mode, even if the trigger source management circuit 206 finds that other trigger sources enable trigger signals, the trigger source management circuit 206 ignores trigger signals from other trigger sources. For example, after the core circuit 204 enters the first mode, even when the trigger source 110 enables one of the trigger signals STB 1 to STB M , the core circuit 204 keeps executing the first operation.

由於處理電路200具有多個獨立的儲存電路，每一儲存電路儲存一控制參數，故觸發源管理電路206只要根據被致能的觸發信號的來源，提供相對應的控制參數予核心電路204，便可調整核心電路204的操作模式。因此，核心電路204的模式切換不需中央處理器的介入，故可節省中央處理器的功耗。再者，在核心電路204切換模式時，中央處理器可執行其它的操作，故可提高中央處理器的效能。Since the processing circuit 200 has a plurality of independent storage circuits, and each storage circuit stores a control parameter, the trigger source management circuit 206 only needs to provide the corresponding control parameter to the core circuit 204 according to the source of the enabled trigger signal, so as to The mode of operation of the core circuit 204 can be adjusted. Therefore, the mode switching of the core circuit 204 does not require the intervention of the central processing unit, so the power consumption of the central processing unit can be saved. Furthermore, when the core circuit 204 switches modes, the central processing unit can perform other operations, so that the performance of the central processing unit can be improved.

在一些實施例中，觸發源管理電路206更提供一觸發信號ST予核心電路204。觸發信號ST係為觸發源108、110及112所致能的觸發信號。舉例而言，當選擇電路202將控制參數P 1作為輸出參數PO時，觸發源管理電路206將觸發源108所致能的觸發信號作為觸發信號ST。當選擇電路202將控制參數P 2作為輸出參數PO時，觸發源管理電路206將觸發源110所致能的觸發信號作為觸發信號ST。當選擇電路202將控制參數P 3作為輸出參數PO時，觸發源管理電路206將觸發源112所致能的觸發信號作為觸發信號ST。 In some embodiments, the trigger source management circuit 206 further provides a trigger signal ST to the core circuit 204 . The trigger signal ST is a trigger signal enabled by the trigger sources 108 , 110 and 112 . For example, when the selection circuit 202 uses the control parameter P 1 as the output parameter PO, the trigger source management circuit 206 uses the trigger signal enabled by the trigger source 108 as the trigger signal ST. When the selection circuit 202 takes the control parameter P 2 as the output parameter PO, the trigger source management circuit 206 takes the trigger signal enabled by the trigger source 110 as the trigger signal ST. When the selection circuit 202 takes the control parameter P3 as the output parameter PO, the trigger source management circuit 206 takes the trigger signal enabled by the trigger source 112 as the trigger signal ST.

第3圖為本發明之處理電路的動作示意圖。為方便說明，假設處理電路係為一計時器/計數器。在此例中，當觸發源108致能觸發信號STA 1~STA N之一者時，觸發源管理電路206命令選擇電路202將控制參數P 1作為輸出參數PO。因此，核心電路204進入第一模式，準備進行一計時操作。此時，核心電路204可能根據輸出參數PO，選擇時脈信號CLK 1，並根據時脈信號CLK 1的脈衝，準備進行一計時操作。 FIG. 3 is a schematic diagram of the operation of the processing circuit of the present invention. For convenience of description, it is assumed that the processing circuit is a timer/counter. In this example, when the trigger source 108 enables one of the trigger signals STA 1 ˜STA N , the trigger source management circuit 206 instructs the selection circuit 202 to use the control parameter P 1 as the output parameter PO. Therefore, the core circuit 204 enters the first mode, ready to perform a timing operation. At this time, the core circuit 204 may select the clock signal CLK 1 according to the output parameter PO, and prepare to perform a timing operation according to the pulse of the clock signal CLK 1 .

然後，觸發源管理電路206將被致能的觸發信號(如STA 1)作為觸發信號ST提供予核心電路204。核心電路204根據觸發信號ST(STA 1)開始執行計時操作。在核心電路204執行計時操作的同時，如果觸發源108致能另一觸發信號(如STA N)時，觸發源管理電路206將被致能的觸發信號(STA N)作為觸發信號ST提供予核心電路204。此時，核心電路204可能根據觸發信號ST(STA N)暫停執行計時操作。當觸發源108致能另一觸發信號(如STA 2)時，觸發源管理電路206將被致能的觸發信號(STA 2)作為觸發信號ST提供予核心電路204。此時，核心電路204可能根據觸發信號ST(STA 2)繼續執行計時操作。當核心電路204完成計時操作時，核心電路204致能一完成信號Timeout。在此例中，完成信號Timeout作為輸出信號SOUT。 Then, the trigger source management circuit 206 provides the enabled trigger signal (eg, STA 1 ) to the core circuit 204 as the trigger signal ST. The core circuit 204 starts to perform the timing operation according to the trigger signal ST(STA 1 ). While the core circuit 204 performs the timing operation, if the trigger source 108 enables another trigger signal (eg, STA N ), the trigger source management circuit 206 provides the enabled trigger signal (STA N ) to the core as the trigger signal ST circuit 204 . At this time, the core circuit 204 may suspend the timing operation according to the trigger signal ST(STA N ). When the trigger source 108 enables another trigger signal (eg STA 2 ), the trigger source management circuit 206 provides the enabled trigger signal (STA 2 ) to the core circuit 204 as the trigger signal ST. At this time, the core circuit 204 may continue to perform the timing operation according to the trigger signal ST (STA 2 ). When the core circuit 204 completes the timing operation, the core circuit 204 enables a completion signal Timeout. In this example, the completion signal Timeout is used as the output signal SOUT.

在另一可能實施例中，當觸發源110致能觸發信號STB 1~STB M之一者時，觸發源管理電路206命令選擇電路202將控制參數P 2作為輸出參數PO。因此，核心電路204進入第二模式，用以進行一計數操作。核心電路204可能根據輸出參數PO，選擇時脈信號CLK 1，並根據時脈信號CLK 1的脈衝，進行一計數操作。在另一可能實施例中，核心電路204可能根據輸出參數PO，選擇時脈信號CLK 2。 In another possible embodiment, when the trigger source 110 enables one of the trigger signals STB 1 to STB M , the trigger source management circuit 206 instructs the selection circuit 202 to use the control parameter P 2 as the output parameter PO. Therefore, the core circuit 204 enters the second mode for performing a counting operation. The core circuit 204 may select the clock signal CLK 1 according to the output parameter PO, and perform a counting operation according to the pulse of the clock signal CLK 1 . In another possible embodiment, the core circuit 204 may select the clock signal CLK 2 according to the output parameter PO.

接著，觸發源管理電路206將被致能的觸發信號(如STB M)作為觸發信號ST提供予核心電路204。因此，核心電路204開始執行一計數操作。在一可能實施例中，核心電路204根據輸出參數PO(即控制參數P 2)進行一向上計數操作或是一向下計數操作。當觸發源110致能另一觸發信號時，觸發源管理電路206將被致能的觸發信號(如STB 2)作為觸發信號ST。此時，核心電路204可能根據觸發信號ST暫停執行計數操作。當觸發源110致能另一觸發信號(如STB 1)時，觸發源管理電路206將被致能的觸發信號(STB 1)作為觸發信號ST。此時，核心電路204可能根據觸發信號ST(STB 1)繼續執行計數操作。當核心電路204完成計數操作時，核心電路204致能完成信號Overflow或Underflow。在一可能實施例中，當核心電路204完成向上計數操作時，核心電路204致能完成信號Overflow。在此例中，完成信號Overflow作為輸出信號SOUT。在另一可能實施例中，當核心電路204完成向下計數操作時，核心電路204致能完成信號Underflow。在此例中，完成信號Underflow作為輸出信號SOUT。 Next, the trigger source management circuit 206 provides the enabled trigger signal (eg, STB M ) to the core circuit 204 as the trigger signal ST. Therefore, the core circuit 204 starts to perform a counting operation. In a possible embodiment, the core circuit 204 performs an up-counting operation or a down-counting operation according to the output parameter PO (ie, the control parameter P 2 ). When the trigger source 110 enables another trigger signal, the trigger source management circuit 206 uses the enabled trigger signal (eg STB 2 ) as the trigger signal ST. At this time, the core circuit 204 may suspend the counting operation according to the trigger signal ST. When the trigger source 110 enables another trigger signal (eg STB 1 ), the trigger source management circuit 206 uses the enabled trigger signal ( STB 1 ) as the trigger signal ST. At this time, the core circuit 204 may continue to perform the counting operation according to the trigger signal ST (STB 1 ). When the core circuit 204 completes the counting operation, the core circuit 204 enables the completion signal Overflow or Underflow. In a possible embodiment, when the core circuit 204 completes the count-up operation, the core circuit 204 enables the completion signal Overflow. In this example, the completion signal Overflow is used as the output signal SOUT. In another possible embodiment, when the core circuit 204 completes the down-counting operation, the core circuit 204 enables the completion signal Underflow. In this example, the completion signal Underflow is used as the output signal SOUT.

在其它實施例中，當觸發源112致能觸發信號STC 1~STC Q之一者(如STC 1)時，觸發源管理電路206命令選擇電路202將控制參數P 3作為輸出參數PO。因此，核心電路204可能再次進入第一模式，用以進行一計時操作。在此例中，核心電路204根據控制參數P 3，選擇時脈信號CLK 1及CLK 2之一者(如CLK 2)。核心電路204根據時脈信號CLK 2的脈衝，再次進行一計時操作。 In other embodiments, when the trigger source 112 enables one of the trigger signals STC 1 ˜STC Q (eg, STC 1 ), the trigger source management circuit 206 instructs the selection circuit 202 to use the control parameter P 3 as the output parameter PO. Therefore, the core circuit 204 may enter the first mode again to perform a timing operation. In this example, the core circuit 204 selects one of the clock signals CLK 1 and CLK 2 (eg, CLK 2 ) according to the control parameter P 3 . The core circuit 204 performs a timing operation again according to the pulse of the clock signal CLK2.

接著，觸發源管理電路206將被致能的信號(如STC 1)作為觸發信號ST提供予核心電路204。因此，核心電路204開始執行計時操作。當核心電路204完成計時操作時，核心電路204致能完成信號Timeout。在一可能實施例中，當選擇電路202將控制參數P 1作為輸出參數PO時，核心電路204執行計時操作的總執行時間為一時間302。當選擇電路202將控制參數P 3作為輸出參數PO時，核心電路204執行計時操作的總執行時間為一時間304。在此例中，時間302不同於時間304。在本實施例中，時間302的長短與控制參數P 1有關。同樣地，時間304的長短與控制參數P 3有關。 Next, the trigger source management circuit 206 provides the enabled signal (eg, STC 1 ) to the core circuit 204 as the trigger signal ST. Therefore, the core circuit 204 starts to perform the timing operation. When the core circuit 204 completes the timing operation, the core circuit 204 enables the completion signal Timeout. In a possible embodiment, when the selection circuit 202 uses the control parameter P 1 as the output parameter PO, the total execution time for the core circuit 204 to perform the timing operation is a time 302 . When the selection circuit 202 takes the control parameter P 3 as the output parameter PO, the total execution time for the core circuit 204 to perform the timing operation is a time 304 . In this example, time 302 is different from time 304. In this embodiment, the length of the time 302 is related to the control parameter P1. Likewise, the length of time 304 is related to control parameter P3 .

第4A圖為本發明之控制方法的一可能流程示意圖。本發明的控制方法用以控制一核心電路的操作模式。首先，儲存複數控制參數於複數儲存電路中(步驟S401)。在一可能實施例中，該等控制參數係由一中央處理器寫入該等儲存電路中。在此例中，每一儲存電路儲存一控制參數。FIG. 4A is a schematic flow chart of a possible control method of the present invention. The control method of the present invention is used to control the operation mode of a core circuit. First, the complex control parameters are stored in the complex storage circuit (step S401 ). In a possible embodiment, the control parameters are written into the storage circuits by a central processing unit. In this example, each storage circuit stores a control parameter.

判斷一第一觸發源是否致能一第一觸發信號(步驟S402)。當第一觸發源致能第一觸發信號時，提供該等儲存電路中的一第一儲存電路的控制參數予核心電路，用以命令核心電路進入一第一模式(步驟S403)。在第一模式下，核心電路根據第一觸發信號執行一第一操作，如一計時操作。在第一模式下，如果第一觸發源致能另一觸發信號(或稱第四觸發信號)時，核心電路可能暫停進行計時操作。當第一觸發源致能另一觸發信號(或稱第五觸發信號)時，核心電路繼續進行計時操作。在其它實施例中，在完成計時操作後，回到步驟S402，繼續判斷第一觸發源是否致能第一觸發信號。It is determined whether a first trigger source enables a first trigger signal (step S402). When the first trigger source enables the first trigger signal, a control parameter of a first storage circuit among the storage circuits is provided to the core circuit for instructing the core circuit to enter a first mode (step S403 ). In the first mode, the core circuit performs a first operation, such as a timing operation, according to the first trigger signal. In the first mode, if the first trigger source enables another trigger signal (or the fourth trigger signal), the core circuit may suspend the timing operation. When the first trigger source enables another trigger signal (or the fifth trigger signal), the core circuit continues to perform the timing operation. In other embodiments, after the timing operation is completed, go back to step S402 to continue to determine whether the first trigger source enables the first trigger signal.

當第一觸發源未致能第一觸發信號時，判斷一第二觸發源是否致能一第二觸發信號(步驟S404)。當第二觸發源致能第二觸發信號時，將該等儲存電路中的一第二儲存電路的控制參數提供予核心電路，用以命令核心電路進入一第二模式(步驟S405)。在第二模式下，核心電路根據第二觸發信號執行一第二操作，如一計數操作。在此例中如果第二觸發源致能另一觸發信號(或稱第六觸發信號)時，核心電路可能暫停進行計數操作。當第二觸發源致能另一觸發信號(或稱第七觸發信號)時，核心電路繼續進行計數操作。當第二觸發源未致能第二觸發信號時，回到步驟S402。在一些實施例中，在核心電路在完成計數操作後，可能回到步驟S402。When the first trigger source does not enable the first trigger signal, it is determined whether a second trigger source enables a second trigger signal (step S404 ). When the second trigger source enables the second trigger signal, the control parameters of a second storage circuit in the storage circuits are provided to the core circuit to instruct the core circuit to enter a second mode (step S405 ). In the second mode, the core circuit performs a second operation, such as a counting operation, according to the second trigger signal. In this example, if the second trigger source enables another trigger signal (or the sixth trigger signal), the core circuit may suspend the counting operation. When the second trigger source enables another trigger signal (or the seventh trigger signal), the core circuit continues the counting operation. When the second trigger source does not enable the second trigger signal, go back to step S402. In some embodiments, after the core circuit completes the counting operation, it may return to step S402.

第4B圖為本發明之控制方法的另一可能流程示意圖。第4B圖相似第4A圖，不同之處在於第4B圖多了步驟S406及S407。在步驟S406中，判斷一第三觸發源是否致能一第三觸發信號。當第三觸發源致能第三觸發信號時，將該等儲存電路中的一第三儲存電路的控制參數提供予核心電路，用以命令核心電路進入第一或第二模式(步驟S407)。在一可能實施例中，當核心電路接收到第三儲存電路的控制參數時，核心電路進入第一模式。在此例中，核心電路根據不同的控制參數，決定計時操作的總執行時間。舉例而言，當核心電路接收第一控制參數時，核心電路執行計時操作的總執行時間為一第一時間。當核心電路接收第三控制參數時，核心電路執行計時操作的總執行時間為一第二時間。在此例中，第一時間不同於第二時間。FIG. 4B is a schematic diagram of another possible flow of the control method of the present invention. Fig. 4B is similar to Fig. 4A, except that Fig. 4B has more steps S406 and S407. In step S406, it is determined whether a third trigger source enables a third trigger signal. When the third trigger source enables the third trigger signal, the control parameter of a third storage circuit in the storage circuits is provided to the core circuit to instruct the core circuit to enter the first or second mode (step S407 ). In a possible embodiment, when the core circuit receives the control parameter of the third storage circuit, the core circuit enters the first mode. In this example, the core circuit determines the total execution time of the timing operation according to different control parameters. For example, when the core circuit receives the first control parameter, the total execution time for the core circuit to perform the timing operation is a first time. When the core circuit receives the third control parameter, the total execution time for the core circuit to perform the timing operation is a second time. In this example, the first time is different from the second time.

在另一可能實施例中，當核心電路接收到第三儲存電路的控制參數時，核心電路進入第二模式。在此例中，核心電路根據不同的控制參數，決定計數操作的目標值。舉例而言，核心電路根據第二控制參數，決定一第一目標值。核心電路可能根據一第一時脈信號的脈衝數量，調整一計數值。當計數值達第一目標值時，核心電路停止執行計數操作。在此例中，核心電路根據第三控制參數，決定一第二目標值。核心電路可能根據一第二時脈信號(或第一時脈)的脈衝數量，調整計數值。當計數值達第二目標值時，核心電路停止執行計數操作。第一目標值不同於第二目標值。In another possible embodiment, when the core circuit receives the control parameter of the third storage circuit, the core circuit enters the second mode. In this example, the core circuit determines the target value of the counting operation according to different control parameters. For example, the core circuit determines a first target value according to the second control parameter. The core circuit may adjust a count value according to the number of pulses of a first clock signal. When the count value reaches the first target value, the core circuit stops performing the count operation. In this example, the core circuit determines a second target value according to the third control parameter. The core circuit may adjust the count value according to the number of pulses of a second clock signal (or the first clock). When the count value reaches the second target value, the core circuit stops performing the count operation. The first target value is different from the second target value.

由於核心電路在不同觸發源致能觸發信號時，接收到不同的控制參數，並根據不同的控制參數執行不同的操作，而不需中央處理器持續偵測觸發源是否發出致能的觸發信號，故中央處理器可進行其它的操作，因而提高中央處理器的效能。Since the core circuit receives different control parameters when different trigger sources enable the trigger signal, and performs different operations according to the different control parameters, it is not necessary for the central processor to continuously detect whether the trigger source sends the enabled trigger signal. Therefore, the central processing unit can perform other operations, thereby improving the performance of the central processing unit.

本發明之控制方法，或特定型態或其部份，可以以程式碼的型態存在。程式碼可儲存於實體媒體，如軟碟、光碟片、硬碟、或是任何其他機器可讀取(如電腦可讀取)儲存媒體，亦或不限於外在形式之電腦程式產品，其中，當程式碼被機器，如電腦載入且執行時，此機器變成用以參與本發明之操作系統。程式碼也可透過一些傳送媒體，如電線或電纜、光纖、或是任何傳輸型態進行傳送，其中，當程式碼被機器，如電腦接收、載入且執行時，此機器變成用以參與本發明之操作系統。當在一般用途處理單元實作時，程式碼結合處理單元提供一操作類似於應用特定邏輯電路之獨特裝置。The control method of the present invention, or a specific form or part thereof, may exist in the form of code. The code can be stored on physical media, such as floppy disks, optical discs, hard disks, or any other machine-readable (such as computer-readable) storage media, or not limited to external forms of computer program products, where, When the code is loaded and executed by a machine, such as a computer, the machine becomes an operating system for participating in the present invention. The code may also be transmitted through some transmission medium, such as wire or cable, optical fiber, or any type of transmission, wherein when the code is received, loaded, and executed by a machine, such as a computer, the machine becomes used to participate in this document. Invented operating system. When implemented on a general-purpose processing unit, the code combines with the processing unit to provide a unique device that operates similarly to application-specific logic circuits.

除非另作定義，在此所有詞彙(包含技術與科學詞彙)均屬本發明所屬技術領域中具有通常知識者之一般理解。此外，除非明白表示，詞彙於一般字典中之定義應解釋為與其相關技術領域之文章中意義一致，而不應解釋為理想狀態或過分正式之語態。雖然“第一”、“第二”等術語可用於描述各種信號，但這些信號不應受這些術語的限制。這些術語只是用以區分一個信號和另一個信號。Unless otherwise defined, all terms (including technical and scientific terms) herein are commonly understood by those of ordinary skill in the art to which this invention belongs. Furthermore, unless expressly stated otherwise, the definitions of words in general dictionaries should be construed as consistent with their meanings in articles in the related technical field, and should not be construed as ideal states or overly formal voices. Although terms such as "first," "second," etc. may be used to describe various signals, these signals should not be limited by these terms. These terms are only used to distinguish one signal from another.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾。舉例來說，本發明實施例所述之系統、裝置或是方法可以硬體、軟體或硬體以及軟體的組合的實體實施例加以實現。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, apparatus, or method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention should be determined by the scope of the appended patent application.

100:操作系統 102:中央處理器 104:匯流排 106、200:處理電路 108、110、112:觸發源 STA 1~STA N、STB 1~STB M、STC 1~STC Q:觸發信號 SOUT:輸出信號 CLK 1、CLK 2:時脈信號 PA 1~PA N、PB 1~PB M、PC 1~PC Q:週邊電路 RT 1~RT 3:儲存電路 202:選擇電路 204:核心電路 206:觸發源管理電路 P 1~P 3:控制參數 SEL:選擇信號 PO:輸出參數 ST:觸發信號 Timeout、Overflow、Underflow:完成信號 302、304:時間 S401~S407:步驟 100: operating system 102: central processing unit 104: bus bar 106, 200: processing circuit 108, 110, 112: trigger source STA 1 ~STA N , STB 1 ~STB M , STC 1 ~STC Q : trigger signal SOUT: output Signals CLK 1 , CLK 2 : clock signals PA 1 ˜PAN , PB 1 ˜PB M , PC 1 ˜PC Q : peripheral circuits RT 1 ˜RT 3 : storage circuit 202 : selection circuit 204 : core circuit 206 : trigger source Management circuit P 1 ~P 3 : Control parameter SEL: Selection signal PO: Output parameter ST: Trigger signal Timeout, Overflow, Underflow: Completion signal 302, 304: Time S401~S407: Step

第1圖為本發明之操作系統的示意圖。 第2圖為本發明之處理電路的示意圖。 第3圖為本發明之處理電路的動作示意圖。 第4A圖為本發明之控制方法的一可能流程示意圖。 第4B圖為本發明之控制方法的另一可能流程示意圖。 FIG. 1 is a schematic diagram of the operating system of the present invention. FIG. 2 is a schematic diagram of the processing circuit of the present invention. FIG. 3 is a schematic diagram of the operation of the processing circuit of the present invention. FIG. 4A is a schematic flow chart of a possible control method of the present invention. FIG. 4B is a schematic diagram of another possible flow of the control method of the present invention.

108、110、112:觸發源 108, 110, 112: Trigger source

200:處理電路 200: Processing Circuits

RT1~RT3:儲存電路 RT 1 ~RT 3 : Storage circuit

202:選擇電路 202: Selection circuit

204:核心電路 204: Core Circuit

206:觸發源管理電路 206: Trigger source management circuit

P1~P3:控制參數 P 1 ~P 3 : Control parameters

SEL:選擇信號 SEL: select signal

PO:輸出參數 PO: output parameter

ST:觸發信號 ST: trigger signal

SOUT:輸出信號 SOUT: output signal

CLK1、CLK2:時脈信號 CLK 1 , CLK 2 : clock signal

Claims (10)

一種操作系統，包括： 一第一儲存電路，儲存一第一控制參數； 一第二儲存電路，儲存一第二控制參數； 一選擇電路，用以提供一輸出參數； 一核心電路，接收該輸出參數；以及 一觸發源管理電路，用以控制該選擇電路； 其中： 當一第一觸發源致能一第一觸發信號時，該觸發源管理電路命令該選擇電路將該第一控制參數作為該輸出參數，使得該核心電路進入一第一模式，用以執行一第一操作； 當一第二觸發源致能一第二觸發信號時，該觸發源管理電路命令該選擇電路將該第二控制參數作為該輸出參數，使得該核心電路進入一第二模式，用以執行一第二操作。 An operating system that includes: a first storage circuit, storing a first control parameter; a second storage circuit, storing a second control parameter; a selection circuit for providing an output parameter; a core circuit that receives the output parameter; and a trigger source management circuit for controlling the selection circuit; in: When a first trigger source enables a first trigger signal, the trigger source management circuit instructs the selection circuit to use the first control parameter as the output parameter, so that the core circuit enters a first mode for executing a first an operation; When a second trigger source enables a second trigger signal, the trigger source management circuit instructs the selection circuit to use the second control parameter as the output parameter, so that the core circuit enters a second mode for executing a first Second operation. 如請求項1之操作系統，其中該第一操作係為一計時操作，該第二操作係為一計數操作。The operating system of claim 1, wherein the first operation is a timing operation, and the second operation is a counting operation. 如請求項2之操作系統，其中當該選擇電路將該第一控制參數作為該輸出參數時，該觸發源管理電路提供該第一觸發信號予該核心電路，當該選擇電路將該第二控制參數作為該輸出參數，該觸發源管理電路提供該第二觸發信號予該核心電路。The operating system of claim 2, wherein when the selection circuit takes the first control parameter as the output parameter, the trigger source management circuit provides the first trigger signal to the core circuit, and when the selection circuit takes the second control parameter The parameter is used as the output parameter, and the trigger source management circuit provides the second trigger signal to the core circuit. 如請求項3之操作系統，更包括： 一第三儲存電路，儲存一第三控制參數； 其中當一第三觸發源致能一第三觸發信號時，該觸發源管理電路命令該選擇電路將該第三控制參數作為該輸出參數，並提供該第三觸發信號予該核心電路。 For the operating system of claim 3, it also includes: a third storage circuit, storing a third control parameter; When a third trigger source enables a third trigger signal, the trigger source management circuit instructs the selection circuit to use the third control parameter as the output parameter, and provides the third trigger signal to the core circuit. 如請求項4之操作系統，其中： 當該選擇電路將該第三控制參數作為該輸出參數時，該核心電路進入該第一模式； 當該選擇電路將該第一控制參數作為該輸出參數時，該核心電路執行該第一操作的總執行時間為一第一時間，當該選擇電路將該第三控制參數作為該輸出參數時，該核心電路執行該計時操作的總執行時間為一第二時間，該第一時間不同於該第二時間。 The operating system of claim 4, wherein: When the selection circuit uses the third control parameter as the output parameter, the core circuit enters the first mode; When the selection circuit uses the first control parameter as the output parameter, the total execution time for the core circuit to perform the first operation is a first time, and when the selection circuit uses the third control parameter as the output parameter, The total execution time for the core circuit to perform the timing operation is a second time, and the first time is different from the second time. 如請求項4之操作系統，其中： 當該選擇電路將該第三控制參數作為該輸出參數時，該核心電路進入該第二模式； 當該選擇電路將該第二控制參數作為該輸出參數時，該核心電路執行該計數操作，用以調整一計數值，當該計數值達一第一目標值時，該核心電路停止執行該計數操作； 當該選擇電路將該第三控制參數作為該輸出參數時，該核心電路執行該計數操作，用以調整該計數值，當該計數值達一第二目標值時，該核心電路停止執行該計數操作； 該第一目標值不同於該第二目標值。 The operating system of claim 4, wherein: When the selection circuit uses the third control parameter as the output parameter, the core circuit enters the second mode; When the selection circuit takes the second control parameter as the output parameter, the core circuit executes the counting operation to adjust a count value, and when the count value reaches a first target value, the core circuit stops executing the count operate; When the selection circuit takes the third control parameter as the output parameter, the core circuit executes the counting operation to adjust the count value, and when the count value reaches a second target value, the core circuit stops executing the count operate; The first target value is different from the second target value. 如請求項1之操作系統，其中該核心電路根據該輸出參數，從複數時脈信號中選擇一者。The operating system of claim 1, wherein the core circuit selects one of a plurality of clock signals according to the output parameter. 如請求項1之操作系統，更包括： 一中央處理器，用以提供該第一控制參數及該第二控制參數；以及 一匯流排，用以傳送該第一控制參數至該第一儲存電路，並傳送該第二控制參數至該第二儲存電路。 For the operating system of claim 1, it also includes: a central processing unit for providing the first control parameter and the second control parameter; and a bus bar for transmitting the first control parameter to the first storage circuit and transmitting the second control parameter to the second storage circuit. 一種控制方法，用以控制一核心電路的操作模式，該控制方法包括： 儲存一第一控制參數於一第一儲存電路中； 儲存一第二控制參數於一第二儲存電路中； 判斷一第一觸發源是否致能一第一觸發信號； 當該第一觸發信號被致能時，提供該第一控制參數予該核心電路，使得該核心電路進入一第一模式，用以進行一第一操作； 判斷一第二觸發源是否發出致能一第二觸發信號；以及 當該第二觸發信號被致能時，提供該第二控制參數予該核心電路，使得該核心電路進入一第二模式，用以進行一第二操作。 A control method for controlling an operation mode of a core circuit, the control method comprising: storing a first control parameter in a first storage circuit; storing a second control parameter in a second storage circuit; determining whether a first trigger source enables a first trigger signal; When the first trigger signal is enabled, the first control parameter is provided to the core circuit, so that the core circuit enters a first mode for performing a first operation; determining whether a second trigger source sends out a second trigger signal enabling a second trigger; and When the second trigger signal is enabled, the second control parameter is provided to the core circuit, so that the core circuit enters a second mode for performing a second operation. 如請求項9之控制方法，其中該第一操作係為一計時操作，該第二操作係為一計數操作。The control method of claim 9, wherein the first operation is a timing operation, and the second operation is a counting operation.
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JPH04124735A (en) * 1990-09-17 1992-04-24 Fujitsu Ltd System starting system
TWM381828U (en) * 2010-01-27 2010-06-01 Biostar Microtech Int L Corp Outside reset circuit of system-setting storage
CN104268019A (en) * 2014-09-23 2015-01-07 广州金山网络科技有限公司 Software operating method and device and terminal
TWI697841B (en) * 2018-12-18 2020-07-01 新唐科技股份有限公司 Control circuit and method for fast setting power mode

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04124735A (en) * 1990-09-17 1992-04-24 Fujitsu Ltd System starting system
TWM381828U (en) * 2010-01-27 2010-06-01 Biostar Microtech Int L Corp Outside reset circuit of system-setting storage
CN104268019A (en) * 2014-09-23 2015-01-07 广州金山网络科技有限公司 Software operating method and device and terminal
TWI697841B (en) * 2018-12-18 2020-07-01 新唐科技股份有限公司 Control circuit and method for fast setting power mode

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