TWI772702B - 製造半導體裝置的方法及半導體裝置 - Google Patents
製造半導體裝置的方法及半導體裝置 Download PDFInfo
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- TWI772702B TWI772702B TW108139138A TW108139138A TWI772702B TW I772702 B TWI772702 B TW I772702B TW 108139138 A TW108139138 A TW 108139138A TW 108139138 A TW108139138 A TW 108139138A TW I772702 B TWI772702 B TW I772702B
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- dielectric layer
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- nitride
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- semiconductor device
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
在一種製造半導體裝置之方法中,在基板之上形成第一介電層,在第一介電層之表面上形成黏附增強層,且在黏附增強層上形成第二介電層。
Description
本揭露是關於一種製造半導體裝置的方法及半導體裝置。
剝離是存在氮化鋁層與氮化矽接觸蝕刻終止層之間的問題。解決剝離問題的一種方式為增大氮化鋁層之厚度;然而,這種方式增加了總裝置的厚度並減小了裝置密度。因此,需要一種針對氮化鋁剝離問題的解決方案。
根據本揭示之一實施方式,提供一種一種製造半導體裝置之方法,包括在基板之上形成第一介電層;在第一介電層之表面上形成黏附增強層;以及在黏附增強層上形成第二介電層,其中第二介電層包括氮化鋁基材料。
根據本揭示之一實施方式,提供一種製造半導體裝置之方法,包括在基板上之半導體裝置結構之上形成第一氮化物基介電層;在第一氮化物基介電層之上形成黏附增強層;在黏附增強層之上形
成第二氮化物基介電層;以及至少部分地氧化第二氮化物基介電層,其中第一氮化物基介電層由與第二氮化物基介電層不同的材料製成。
根據本揭示之一實施方式,提供一種半導體裝置,包括第一介電層,設置在半導體裝置結構之上;黏附增強層,設置在第一介電層之上;以及第二介電層,設置在黏附增強層之上,其中第一介電層包括第一金屬氮化物,且第二介電層包括與第一金屬氮化物不同的第二金屬氮化物,以及第二介電層之氮濃度沿垂直方向不均勻。
1:基板
5:通道層(鰭片結構)
10:金屬閘極結構
12:閘極介電層
14:功函數調整層
16:金屬材料
20:覆蓋絕緣層
30:側壁間隔物
40:層間介電(ILD)層
45:第一層間介電層
50:源極/汲極區域
60:第一蝕刻終止層
65:第二層間介電層
67:接觸孔(開口)
68:第一接觸內襯層
70:第一(源極/汲極)接觸件
71:閘極接觸件
75:第二蝕刻終止層
80:第三層間介電層
82:接觸孔(開口)
90:第二接觸內襯層
100:第二(源極/汲極)接觸件
102:第一閘極接觸件
110:黏附增強層
120:第三蝕刻終止層
125:經氧化的蝕刻終止層
130:第四層間介電層
135:接觸孔(開口)
140:第三(源極/汲極)接觸件
142:第二閘極接觸件
200:第一介電層
200A:底層
200B:中間層
200C:上層
201:開口
205:下層
210:黏附增強層
215:電子結構
220:第二介電層
225:導電圖案
230:經氧化之第二介電層
300:基板
310:鰭片結構
315:通道區域
320:隔離絕緣層
330:金屬閘極結構
340:覆蓋絕緣層
350:側壁間隔物
360:源極/汲極區域
370:層間介電層(ILD)
X1-X1:線段
當結合隨附圖式閱讀時,自以下詳細描述將很好地理解本揭示之實施方式。應注意,根據工業中的標準實務,各個特徵並非按比例繪製,並且僅出於說明目的而使用。事實上,出於論述清晰之目的,可任意增加或減小各個特徵之尺寸。
第1A圖、第1B圖、第1C圖及第1D圖圖示根據本揭示之一實施方式的半導體裝置之依序製造操作的各種階段。
第2A圖、第2B圖、第2C圖及第2D圖圖示根據本揭示之一實施方式的半導體裝置之依序製造操作的各種階段。
第3A圖、第3B圖、第3C圖及第3D圖圖示根據本揭示之一實施方式的半導體裝置之依序製造操作的各種階段。
第3E圖、第3F圖、第3G圖及第3H圖圖示根據本揭示之一實施方式的半導體裝置之依序製造操作的各種階段。
第4A圖圖示根據本揭示之一實施方式的半導體裝置之依序製造製程之各種階段中之一者的平面圖(自上方觀察)。
第4B圖圖示沿第4A圖之線段X1-X1的橫截面圖。
第4C圖及第4D圖為閘極結構之放大圖。
第4E圖圖示根據本揭示之一實施方式的半導體裝置之依序製造製程之各種階段中之一者的透視圖。
第5A圖、第5B圖、第5C圖、第5D圖及第5E圖示出根據本揭示之一實施方式的半導體裝置之依序製造製程之各種階段的橫截面圖。
第6A圖、第6B圖、第6C圖及第6D圖示出根據本揭示之一實施方式的半導體裝置之依序製造製程之各種階段的橫截面圖。
第7A圖、第7B圖、第7C圖及第7D圖示出根據本揭示之一實施方式的半導體裝置之依序製造製程之各種階段的橫截面圖。
第8A圖、第8B圖及第8C圖示出根據本揭示之一實施方式的半導體裝置之依序製造製程之各種階段的橫截面圖。
第9A圖、第9B圖、第9C圖及第9D圖示出根據本揭示之一實施方式的半導體裝置的各種視圖。
以下揭示內容提供許多不同實施例或實例,以便實施本揭示之一實施方式的不同特徵。下文描述部件及佈置的具體實例以簡化本揭示之一實施方式。當然,此等僅為實例且並不意欲為限制性。例如,以下描述中在第二特徵上方或第二特徵上形成第一特徵可包括以直接接觸形成第一特徵及第二特徵的實施例,且亦可包括在第
一特徵與第二特徵之間形成額外特徵以使得第一特徵及第二特徵可不處於直接接觸的實施例。另外,本揭示之一實施方式可在各種實例中重複元件符號及/或字母。此重複是出於簡化及清楚之目的,且其自身並不表示所論述之各種實施例及/或配置之間的關係。
另外,為了描述簡單,可在本文中使用諸如「在......下面」、「在......下方」、「下部」、「在......上方」、「上部」及其類似術語之空間相對術語,以描述如諸圖中所圖示之一個元件或特徵與另一(其他)元件或特徵的關係。除了諸圖中所描繪之定向以外,此些空間相對術語意欲涵蓋設備在使用或操作中之不同定向。裝置可以其他方式定向(旋轉90度或以其他定向),且可同樣相應地解釋本文中所使用之空間相對描述詞。另外,術語「由......製成」可意謂「包括」抑或「由......組成」。在本揭示之一實施方式中,短語「A、B及C中之一者」意謂「A、B及/或C」(A、B、C、A與B、A與C、B與C,或A、B及C),且並不意謂來自A之一個元件、來自B之一個元件以及來自C之一個元件,除非另有描述。
在半導體裝置中,在半導體裝置結構之上形成金屬化層。在一些實施例中,半導體裝置結構包括電晶體。在一些實施例中,電晶體包括鰭式場效應電晶體(FinFET)或環繞式閘極場效應電晶體(GAAFET)。金屬化層包括嵌入介電層中之導電層。形成於半導體裝置結構之上的金屬化層包括嵌入絕緣層(諸如,氮化矽、氮氧化矽或氧化矽)中之導電層(諸如,鎢層)。在金屬化層之上形成蝕刻終止層,例如,鋁基絕緣層(例如,氮化鋁(AlN)層)。在一些實施例中,導電層為與下面的半導體裝置結構接觸之接觸件。在一些實施例中,在將氮化鋁層暴露於環境空氣中之氧氣之後,氮化
鋁層經氧化以形成氮氧化鋁(AlxOyNz)。由於氧化而使氧原子***氮化鋁晶格中導致氮化鋁層與氮化矽層的黏附性喪失,並導致氮化鋁層自氮化矽的表面剝離。剝離可導致形成氧化鋁小凸起的形成。這些小凸起為缺陷,且其造成半導體裝置之不均勻表面,因此降低半導體裝置良率。晶格中***的氧原子會破壞晶格並產生應變。
在本揭示之一實施例中,在形成蝕刻終止層(例如,氮化鋁層)之前,在下層(例如,氮化矽層)上形成黏附增強層(黏附層),以吸收或減少在氮化鋁層的氧化所引起的應變,並抑制蝕刻終止層之剝離。
第1A圖、第1B圖、第1C圖及第1D圖圖示根據本揭示之一實施方式的半導體裝置之依序製造操作的各種階段。應理解,對於方法的額外實施例,可在第1A圖至第1D圖之操作之前、期間以及之後提供額外操作,且可替代或消除以下所述的一些操作。操作/製程之次序可互換。
如第1A圖所示,在半導體基板(未示出)上之下層結構(未示出)之上形成第一介電層200。在一些實施例中,第一介電層200包括氮化物基(nitride-based)絕緣材料的一層或多層。在一些實施例中,氮化物基絕緣層為矽的氮化物或氮氧化物、鍺、或矽鍺(SiGe)。在一些實施例中,氮化物基絕緣材料包括氮化矽或氮氧化矽。在為氮氧化矽之情形下,在一些實施例中氮的量大於氧的量(SixOyNz,其中y<z)。在某些實施例中,使用氮化矽作為第一介電層200。藉由包括低壓化學氣相沉積(LPCVD)及電漿增強化學氣相沉積(PECVD)之化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適當製程形成第一介電層200。
接著,如第1B圖中所示,在第一介電層200之表面上形成黏附增強層210。在一些實施例中,黏附增強層210為富氧層,其具有比第一介電層200更高的氧量。在一些實施例中,黏附增強層210包括氧化矽。在某些實施例中,此氧化矽為缺氧氧化矽(SiOx,其中0<x<2)。在其他實施例中,此氧化矽為二氧化矽(SiO2)。在其他實施例中,黏附增強層210包括富氧氮氧化矽SixOyNz,其中y>z。
在一些實施例中,藉由將第一介電層200暴露於受熱之含氧氣體(熱氧化)而形成黏附增強層210。在一些實施例中,含氧氣體為選自氧氣(O2)、臭氧(O3)、氧化氮(N2O,NO2)及氧化碳(CO,CO2)中的至少一者。在一些實施例中,氧化氮為一氧化二氮,且氧化碳為二氧化碳。在一些實施例中,不包括含矽(Si)氣體。在一些實施例中,在約0.5托至約20托之壓力下施加含氧氣體。在其他實施例中,在約1.5托至約8托之壓力下施加含氧氣體。在一些實施例中,在約150℃至約500℃之範圍中的基板溫度下執行氧處理。在其他實施例中,基板溫度在約250℃至約400℃之範圍中。
在一些實施例中,使用含氧電漿處理(氧化)第一介電層200之表面。在其他實施例中,黏附增強層210為藉由CVD、PVD、ALD或其他適當製程形成之沉積膜。
在一些實施例中,黏附增強層210具有在約0.5nm至約10nm之範圍中的厚度。在其他實施例中,黏附增強層210具有在約1nm至約5nm之範圍中的厚度。當黏附增強層210之厚度小於上述範圍之最小值時,黏附增強層210及/或隨後形成於黏附增強層210上之上層的剝離可能發生。當黏附增強層210之厚度大於上
述範圍之最大值時,其可導致後的續蝕刻操作。
另外,如第1C圖所示,在黏附增強層210之上形成第二介電層220。在一些實施例中,第二介電層220作為蝕刻終止層。在一些實施例中,第二介電層220包括氮化物基之絕緣材料。在一些實施例中,第二介電層220包括鋁基(aluminum based)絕緣材料。在某些實施例中,第二介電層220包括氮化鋁及/或氮氧化鋁(AlxOyNz)。在為氮氧化鋁之情形下,在一些實施例中氮的量大於氧的量(AlxOyNz,其中y<z)。
在一些實施例中,第二介電層220的厚度大於黏附增強層210的厚度。在一些實施例中,第二介電層220具有在約1nm至約20nm之範圍中的厚度。在其他實施例中,第二介電層220具有在約2nm至約10nm之範圍中的厚度。在其他實施例中,藉由CVD、PVD、ALD或其他適當製程形成第二介電層220。鋁基絕緣層藉由例如使用三甲基鋁(TMA)之金屬有機化學氣相沉積(MOCVD)或ALD來形成。在一些實施例中,氮化鋁層為結晶的,例如,纖鋅礦(wurtzite)(2H)AlN。
隨後,在一些實施例中,第二介電層220經進一步氧化,以形成經氧化之第二介電層230,如第1D圖所示。在一些實施例中,當第二介電層220由氮化鋁製成時,經氧化之第二介電層230為氧化鋁或氮氧化鋁。在一些實施例中,在氮化鋁層上執行使用O2、CO2及/或CO氣體(含氧氣體)之電漿處理,以至少部分地將氮化鋁層轉換為氧化鋁。在一些實施例中,在經電漿處理之氮化鋁層中的Al、O及/或N之濃度是不均勻的,尤其是沿垂直方向。在一些實施例中,經氧化之第二介電層230包括氧化鋁層(頂部)及氮氧
化鋁層(底部)。在其他實施例中,經氧化之第二介電層230包括氧化鋁層(頂部)、氮氧化鋁層(中部)及氮化鋁層(底部)。在一些實施例中,經氧化之第二介電層230為氧化鋁層。在一些實施例中,氧化鋁層為結晶的,諸如γ-Al2O3或α-Al2O3。在一些實施例中,經氧化之第二介電層230為富氧的氮氧化鋁AlxOyNz,其中y>z。在一些實施例中,在氮氧化鋁層中的氧及/或氮的濃度不均勻,且在某些實施例中,氧濃度從上部表面朝著經氧化之第二介電層230之底部表面減小,而氮濃度自上部表面朝著經氧化之第二介電層230之底部表面增大。
在一些實施例中,當電漿含有碳時,經氧化之第二介電層230包括具有不均勻碳濃度之AlOC。在一些實施例中,執行熱氧化製程以形成經氧化之第二介電層230。
在一些實施例中,經氧化之第二介電層220具有在約1nm至約20nm之範圍中的厚度。在其他實施例中,經氧化之第二介電層220具有在約2nm至約10nm之範圍中的厚度。
第2A圖、第2B圖、第2C圖及第2D圖圖示根據本揭示之一實施方式的半導體裝置之依序製造操作的各種階段。應理解,可在第2A圖至第2D圖之操作之前、期間以及之後提供額外操作,且可替代或消除以下所述操作中之一些而獲得方法的額外實施例。操作/製程之次序可互換。可在以下實施例中採用關於前述實施例所述之材料、配置、尺寸、製程及/或操作,且可省略其詳細說明。
在一些實施例中,在下層205之上形成第一介電層200,在下層205上或在下層205中形成電子結構215,如第2A圖所示。在一些實施例中,電子結構215包括電晶體、佈線、接觸件、互連
件、通孔及/或擴散區域。在一些實施例中,下層205包括半導體基板及/或絕緣層。
另外,如第2A圖所示,在一些實施例中,導電圖案225形成於第一介電層200中並與電子結構215接觸。在一些實施例中,第一介電層200由氮化矽製成。在一些實施例中,導電圖案225包括接觸件、通孔、導線、互連件及/或條。在一些實施例中,藉由使用一或多個微影及蝕刻操作在第一介電層200中形成開口,且藉由使用一或多個膜形成操作及一或多個平坦化操作(諸如,化學機械研磨(CMP)操作)用一或多種導電材料填充開口。在一些實施例中,導電圖案225包括多晶矽、鋁、鋁矽、鈦、矽化鈦、氮化鈦、鎢、矽化鎢、鉬、矽化鉬、銅、鉑、鈷、矽化鈷、鉭、氮化鉭、銦、金及銀,或其合金。在某些實施例中,導電圖案225包括鎢。當使用鎢時,在形成鎢層之前形成一或多個膠層及/或阻障層(未示出)。在一些實施例中,膠層及/或阻障層包括鈦、氮化鈦、鉭及/或氮化鉭。
類似於第1B圖,在第一介電層200之表面處形成黏附增強層210,如第2B圖所示。在一些實施例中,使用如上所述之熱或電漿氧化操作以形成黏附增強層210。在一些實施例中,未在導電圖案225之表面上形成黏附增強層210。在一些實施例中,在導電圖案225之表面處形成構成導電圖案225之元素的氧化物。
接著,類似於第1C圖,在黏附增強層210及導電圖案225上形成第二介電層220,如第2C圖所示。在一些實施例中,第二介電層220由氮化鋁製成。
隨後,類似於第1D圖,第二介電層220部分地或完全地
氧化以形成經氧化之第二介電層230,如第2D圖所示。
第3A圖、第3B圖、第3C圖及第3D圖圖示根據本揭示之一實施方式的半導體裝置之依序製造操作的各種階段。應理解,可在第3A圖至第3D圖之操作之前、期間以及之後提供額外操作,且可替代或消除以下所述操作中之一些而獲得方法的額外實施例。操作/製程之次序可互換。可在以下實施例中採用關於前述實施例所述之材料、配置、尺寸、製程及/或操作,且可省略其詳細說明。
在形成第2A圖所示之結構之後,類似於第1B圖,在第一介電層200之表面及導電圖案225之表面上形成黏附增強層210,如第3A圖所示。在一些實施例中,使用如上所述之沉積製程(諸如,CVD、PVD或ALD)以形成黏附增強層210。
接著,類似於第1C圖,在黏附增強層210上形成第二介電層220,如第3B圖所示。在一些實施例中,第二介電層220由氮化鋁製成。
隨後,類似於第1D圖,第二介電層220部分地或完全地氧化以形成經氧化之第二介電層230,如第3C圖所示。如第3C圖所示,經氧化之第二介電層230不直接接觸導電圖案225。在一些實施例中,如第2B圖所示形成第一黏附增強層210,且另外在第一黏附增強層210及導電圖案225之上形成第二黏附增強層210,如第3D圖所示。
在一些實施例中,第一介電層200包括多個介電層。如第3E圖所示,依序地在下層205及電子結構215之上形成底層200A、中間層200B及上層200C。在一些實施例中,底層200A及上層200C由氮化矽製成,且中間層200B由氧化矽製成。接著,藉由使
用一或多個微影及蝕刻操作在電子結構215之上形成開口201,如第3F圖所示。另外,在開口中且在上層200C上形成用於導電圖案225之導電材料,如第3G圖所示。接著,執行諸如化學機械研磨(CMP)及/或回蝕製程之平坦化操作以獲得導電圖案225,如第3H圖所示。隨後,執行參照第2B圖至第2D圖或第3A圖至第3D圖所述之操作。
第4A圖至第8C圖圖示根據本揭示之一實施方式的半導體裝置之依序製造操作的各種階段。應理解,可在第4A圖至第8C圖之操作之前、期間以及之後提供額外操作,且可替代或消除以下所述操作中之一些而獲得方法的額外實施例。操作/製程之次序可互換。可在以下實施例中採用關於前述實施例所述之材料、配置、尺寸、製程及/或操作,且可省略其詳細說明。
第4A圖及第4B圖示出根據本揭示之一實施方式的半導體裝置之依序製造製程的階段中之一者。第4A圖示出平面(俯視)圖,且第4B圖示出沿第4A圖之線段X1-X1的橫截面圖。
第4A圖及第4B圖示出在形成金屬閘極結構10之後的半導體裝置的結構。在第4A圖及第4B圖中,在通道層5(例如,鰭片結構的一部分)之上形成金屬閘極結構10,並在金屬閘極結構10之上沉積覆蓋絕緣層20。在一些實施例中,金屬閘極結構10之厚度在15nm至50nm之範圍中。覆蓋絕緣層20之厚度在一些實施例中在約10nm至約30nm之範圍中,且在其他實施例中在約15nm至約20nm之範圍中。將側壁間隔物30設置在金屬閘極結構10及覆蓋絕緣層20之側壁上。在側壁間隔物30之底部處的側壁間隔物30之膜厚度在一些實施例中在約3nm至約15nm之範圍中,
且在其他實施例中在約4nm至約8nm之範圍中。金屬閘極結構10、覆蓋絕緣層20及側壁間隔物30之組合可統稱作閘極結構。另外,使源極/汲極區域50形成為與閘極結構相鄰,且以層間介電(interlayer dielectric,ILD)層40填充閘極結構之間的空間。
第4C圖為閘極結構的放大圖。金屬閘極結構10包括一或多層金屬材料16,諸如,Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlC、TiAlN、TaN、NiSi、CoSi、其他導電材料。設置於通道層5與金屬材料16之間的閘極介電層12包括一或多個層金屬氧化物,諸如,高k金屬氧化物。用於高k介電質之金屬氧化物的實例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu之氧化物,及/或其混合物。
在一些實施例中,一或多個功函數調整層14(MG)***閘極介電層12與金屬材料16之間。功函數調整層14由導電材料製成,諸如,TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的單層,或此些材料中之兩者或更多者的多層。對於n通道場效應電晶體(n-channel FET)而言,將TaN、TaAIC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi中之一或多者用作功函數調整層14,且對於p通道場效應電晶體(p-channel FET)而言,將TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co中之一或多者用作功函數調整層14。
覆蓋絕緣層20包括一或多層絕緣材料,諸如,氮化矽基材料,包括SiN、SiCN及SiOCN。側壁間隔物30由與覆蓋絕緣層20不同的材料製成,且包括一或多層絕緣材料,諸如,氮化矽基材料,包括SiN、SiON、SiCN及SiOCN。層間介電層40包括一
或多層絕緣材料,諸如,氧化矽基材料,諸如,二氧化矽(SiO2)及SiON。
在一些實施例中,不形成閘極覆蓋絕緣層20,如第4D圖所示。
側壁間隔物30之材料、覆蓋絕緣層20之材料及層間介電層40之材料彼此不同,使得可選擇性地蝕刻這些層中之每一者。在一個實施例中,側壁間隔物30由SiOCN、SiCN或SiON製成,覆蓋絕緣層20由SiN製成,且層間介電層40由SiO2製成。
在此實施例中,採用藉由閘極替代製程製造之鰭式場效應電晶體(Fin FET)。
第4E圖示出鰭式場效應電晶體結構之示意性透視圖。
首先,在基板300之上製造鰭片結構310。鰭片結構包括底部區域及上部區域作為通道區域315。舉例而言,基板300為具有在約1×1015cm-3至約1×1018cm-3之範圍中之雜質濃度的p型矽基板。在其他實施例中,基板300為具有在約1×1015cm-3至約1×1018cm-3之範圍中之雜質濃度的n型矽基板。或者,基板300可包括另一元素半導體,諸如,鍺;化合物半導體,包括諸如SiC及SiGe之IV-IV族化合物半導體,諸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP之III-V族化合物半導體;或其組合。在一個實施例中,基板300為SOI(絕緣體上矽)基板之矽層。
在形成鰭片結構310之後,在鰭片結構310之上形成隔離絕緣層320。隔離絕緣層320包括藉由低壓化學氣相沉積(LPCVD)、電漿化學氣相沉積(plasma-CVD)或可流動化學氣相沉
積(flowable CVD)形成的一或多層絕緣材料(諸如,氧化矽、氮氧化矽或氮化矽)。隔離絕緣層320可由一或多層旋塗玻璃(spin-on-glass,SOG)、SiO、SiON、SiOCN及/或氟摻雜矽酸鹽玻璃(fluorine-doped silicate glass,FSG)形成。
在鰭片結構310之上形成隔離絕緣層320之後,執行平坦化操作以便移除隔離絕緣層320之一部分。平坦化操作可包括化學機械研磨(CMP)及/或回蝕製程。接著,進一步移除(凹陷)隔離絕緣層320,以使得鰭片結構310之上部區域被暴露。
在暴露的鰭片結構310之上形成虛設閘極結構。虛設閘極結構包括由多晶矽製成之虛設閘電極層以及虛設閘極介電層。亦在虛設閘電極層之側壁上形成包括一或多層絕緣材料的側壁間隔物350。在形成虛設閘極結構之後,未被虛設閘極結構覆蓋之鰭片結構310凹陷成低於隔離絕緣層320之上部表面。接著,藉由使用磊晶生長方法在凹陷的鰭片結構之上形成源極/汲極區域360。源極/汲極區域360可包括應變材料以向通道區域315施加應力。
接著,在虛設閘極結構及源極/汲極區域之上形成層間介電層(ILD)370。在平坦化操作之後,移除虛設閘極結構以便形成閘極空間。接著,在閘極空間中,形成金屬閘極結構330,其包括金屬閘電極及閘極介電層,諸如,高k介電層。另外,在金屬閘極結構330之上形成覆蓋絕緣層340,以便獲得第4E圖所示之鰭式場效應電晶體結構。在第4E圖中,切割金屬閘極結構330、覆蓋隔離層340、側壁330及層間介電層370之部分以露出下層結構。
第4E圖之金屬閘極結構330、覆蓋隔離層340、側壁間隔物350、源極/汲極360及層間介電層370大體上分別對應於第
4A圖至第4D圖之金屬閘極結構10、覆蓋絕緣層20、側壁間隔物30、源極/汲極區域50及層間介電層(ILD)40。在一些實施例中,另外在層間介電層40之上形成一或多個層間介電層,藉此形成第5A圖至第8C圖所示之第一層間介電層45。
在以下說明中,如第5A圖至第8C圖所示,在基板1之上形成四個鰭片結構5,但鰭片結構5之數目並不限於四個,且可為一個、二個、三個或五個或多個。
在形成金屬閘極結構之後,在第一層間介電層45(或40)之上形成第一蝕刻終止層60,且在第一蝕刻終止層60之上形成第二層間介電層65,如第5A圖所示。藉由適當的膜形成方法來形成蝕刻終止層60及層間介電層65,該等方法諸如,CVD、PVD或ALD。
藉由使用一或多個微影及蝕刻操作,在第一層間介電層45及第二層間介電層65中形成用於第一接觸件70之接觸孔(開口)67,如第5B圖所示。
接著,在接觸孔67中及在第二層間介電層65之上部表面上保形地形成第一接觸內襯層68,並在第一接觸內襯層68之上形成導電材料。藉由適當的膜形成方法來形成接觸內襯層68及導電材料層,該等方法諸如,CVD、PVD、ALD或電鍍。隨後,執行平坦化操作(諸如,回蝕操作或化學機械研磨(CMP)操作),以形成源極/汲極接觸件70,如第5C圖所示。
隨後,形成第二蝕刻終止層75及第三層間介電層80,如第5D圖所示。在一些實施例中,類似於第一介電層200,第三層間介電層80包括一或多層氮化物基絕緣材料。在一些實施例中,氮
化物基絕緣層為矽的氮化物或氮氧化物、鍺,或矽鍺(SiGe)。在一些實施例中,氮化物基絕緣材料包括氮化矽或氮氧化矽。在為氮氧化矽之情形下,在一些實施例中氮的量大於氧的量(SixOyNz,其中y<z)。在某些實施例中,使用氮化矽作為第三層間介電層80。
如第5E圖所示,藉由使用一或多個微影及蝕刻操作,在第三層間介電層80及第二蝕刻終止層75中形成用於第二接觸件之接觸孔(開口)82。
接著,如第6A圖所示,在接觸孔82中保形地形成第二接觸內襯層90。藉由適當的膜形成方法來形成第二接觸內襯層90,該等方法諸如,CVD、PVD、ALD或電鍍。
接著,如第6B圖所示,在接觸孔82及第三層間介電層80中形成一或多個導電材料層。藉由適當的膜形成方法來形成導電層,該等方法諸如,CVD、PVD、ALD或電鍍。在一些實施例中,在約200℃至約400℃之範圍中的溫度下形成導電材料。在一些實施例中,類似於導電圖案225,導電材料包括多晶矽、鋁、鋁矽、鈦、矽化鈦、氮化鈦、鎢、矽化鎢、鉬、矽化鉬、銅、鉑、鈷、矽化鈷、鉭、氮化鉭、銦、金及銀,或其合金。在某些實施例中,導電材料包括鎢。接著,執行平坦化操作(諸如,回蝕操作或CMP操作),以形成第二接觸件100,如第6C圖所示。
隨後,類似於第1B圖、第2B圖及第3B圖,藉由含氧氣體及/或含氧電漿來處理第三層間介電層80之表面,以形成黏附增強層110,如第6D圖所示。在一些實施例中,使用沉積製程來形成黏附增強層110。
另外,如第7A圖所示,類似於第1C圖、第2C圖及第3C
圖,在黏附增強層110上形成第三蝕刻終止層120。在一些實施例中,類似於第二介電層220,第三蝕刻終止層120在一些實施例中包括氮化物基絕緣材料。在一些實施例中,第三蝕刻終止層120包括鋁基絕緣材料。在某些實施例中,第三蝕刻終止層120包括氮化鋁及/或氮氧化鋁(AlxOyNz)。在為氮氧化鋁之情形下,在一些實施例中氮的量大於氧的量(AlxOyNz,其中y<z)。
接著,如第7B圖所示,類似於第1D圖、第2D圖及第3D圖,第三蝕刻終止層120氧化為經氧化的蝕刻終止層125。經氧化的蝕刻終止層125之結構及/或配置與如以上所述經氧化的第二介電層230之彼些結構及/或配置相同或類似。
隨後,如第7C圖所示,在經氧化的蝕刻終止層125之上形成第四層間介電層130。用於第四層間介電層130之材料包括氧化矽、氮化矽、SiOC、SiOCN、SiCN、SiON、低k材料或多孔材料或任何其他適當介電材料中的一或多者。低k材料通常具有比二氧化矽(3.9)小的介電常數。在一些實施例中,低k材料具有小於2.0的介電常數。
接著,如第7D圖所示,藉由使用一或多個微影及蝕刻操作,在第四層間介電層130中形成用於第三接觸件之接觸孔(開口)135。在一些實施例中,蝕刻操作在經氧化的蝕刻終止層125處終止,如第7D圖所示。接著,執行額外蝕刻操作以移除在開口135之底部處之經氧化的蝕刻終止層125,如第8A圖所示。
接著,在接觸孔135中及在第四層間介電層130上形成一或多個導電材料層,且執行平坦化操作(諸如,回蝕操作或CMP操作)以形成第三接觸件140,如第8B圖所示。在一些實施例中,
在接觸孔135中保形地形成第三接觸內襯層(未示出)。藉由適當的膜形成方法來形成導電層,該等方法諸如,CVD、PVD、ALD或電鍍。在一些實施例中,用於第三接觸件140及/或第三內襯層之導電材料包括多晶矽、鋁、鋁矽、鈦、矽化鈦、氮化鈦、鎢、矽化鎢、鉬、矽化鉬、銅、鉑、鈷、矽化鈷、鉭、氮化鉭、銦、金及銀,或其合金。當第三接觸件140之底部面積小於第二接觸件100之頂部面積時,經氧化的蝕刻終止層125之一部分保留在第二接觸件100之上部表面上。
在一些實施例中,當藉由沉積方法形成黏附增強層110時,在第二接觸件100之上部表面上形成黏附增強層110。當第三接觸件140之底部面積小於第二接觸件100之頂部面積時,黏附增強層110之一部分保留在第二接觸件100之上部表面上,如第8C圖所示。
在形成閘電極之後,執行另外的CMOS製程,以形成各種特徵,諸如,額外的層間介電層、接觸件/通孔、互連金屬層及鈍化層等。
第9A圖、第9B圖、第9C圖及第9D圖示出根據本揭之一實施方式的半導體裝置的各種視圖。第9A圖為平面圖,第9B圖為橫截面圖(Y剖面),第9C圖為橫截面圖(X剖面1),且第9D圖為橫截面圖(X剖面2)。可在以下實施例中採用關於前述實施例所述之材料、配置、尺寸、製程及/或操作,且可省略其詳細說明。
在9A圖中,在沿X方向延伸之一個鰭片結構5之上設置沿Y方向延伸的三個閘極結構10。在閘極結構10之間的部分為源極/汲極區域50,且在源極/汲極區域50之上設置源極/汲極接觸件
70。在一些實施例中,源極/汲極區域50包括一或多個磊晶形成的半導體層(磊晶層)。在一些實施例中,源極/汲極接觸件70為在Y方向上延伸超過源極/汲極區域50之接觸條。因此,在Y方向上,源極/汲極磊晶層(源極/汲極區域)50之寬度小於源極/汲極接觸件70之寬度。如第9A圖及第9B圖所示,在一些實施例中,在Y方向上源極/汲極接觸件70之寬度大於上部接觸件100之寬度。在一些實施例中,在閘極結構10之一或多個閘電極之上設置一或多個閘極接觸件71。另外,在一些實施例中,分別在源極/汲極接觸件70及閘極接觸件71之上設置第二源極/汲極接觸件100及第一閘極接觸件102。
如第9B圖至第9D圖所示,源極/汲極區域50形成在凹槽中,上述凹槽形成在鰭片結構5中。閘極結構10包括形成於鰭片結構5、閘電極及側壁間隔物30之上的閘極介電層。閘極結構10嵌入第一層間介電(ILD)層45中。第一層間介電層45包括一或多個介電層。在一些實施例中,第一蝕刻終止層60設置在第一層間介電層45之上,且第二層間介電層65形成在第一蝕刻終止層60之上。另外,第二蝕刻終止層75設置在第二層間介電層65之上,且第三層間介電層80形成在第二蝕刻終止層75之上。
第一層間介電層45及第二層間介電層65包括一或多層絕緣材料,例如,氧化矽基材料,諸如,二氧化矽(SiO2)、SiOC及SiOCN。在一些實施例中,將低k材料或有機材料用於層間介電層。第三層間介電層80包括氮化矽或富氮的氮氧化矽。第一蝕刻終止層60及第二蝕刻終止層75由與層間介電層不同之材料製成,且包括一或多層絕緣材料,例如,氮化矽基材料,諸如,氮化矽及SiON。
第一源極/汲極接觸件70形成在穿過第一層間介電層45及第二層間介電層65以及第一蝕刻終止層60及第二蝕刻終止層75之接觸孔中。在一些實施例中,第一接觸內襯層68形成在接觸孔之內表面上。在一些實施例中,第一接觸內襯層68包括一或多種導電材料層,諸如,Ti、TiN、Ta及TaN。在某些實施例中,將TiN層用作第一接觸內襯層68。
第一源極/汲極接觸件70及閘極接觸件71包括一或多種導電材料層,諸如,W、Co、Ni、Mo及其合金。在某些實施例中,第一源極/汲極接觸件70及閘極接觸件71由Co製成。
在一些實施例中,第二源極/汲極接觸件100形成在第一源極/汲極接觸件70之上。第一閘極接觸件102形成在穿過第二層間介電層65及第三層間介電層80以及第一蝕刻終止層60及第二蝕刻終止層75之接觸孔中。第二源極/汲極接觸件100及第一閘極接觸件102包括一或多種導電材料層,諸如,W、Co、Ni、Mo、Cu、Al及其合金。在某些實施例中,第二源極/汲極接觸件100及第一閘極接觸件102由W製成。
另外,黏附增強層110及經氧化的蝕刻終止層125設置在第三層間介電層80之表面上,如第9B圖至第9D圖所示。如第9C圖所示,第三源極/汲極接觸件140設置在第二源極/汲極接觸件100上,且如第9D圖所示,第二閘極接觸件142設置在第一閘極接觸件102上,如第9D圖所示。
在本揭示之一實施方式中,在氮化矽基介電層與氮化鋁基介電層之間形成黏附增強層,因此可以抑制在氮化鋁基介電材料層的氧化期間以及在其之後的氮化鋁基介電層的剝離。
應理解,未必已在本揭示之實施方式中論述了所有優勢,對於所有實施例或實例而言,無特定優勢為必需,且其他實施例或實例可提供不同優勢。
根據本揭示之實施方式之一個態樣,在一種製造半導體裝置之方法中,在基板之上形成第一介電層,在第一介電層之表面上形成黏附增強層,且在黏附增強層上形成第二介電層,其中第二介電層包括一氮化鋁基材料。在前述及以下實施例中之一或多者中,第一介電層由氮化矽製成,且第二介電層由氮化鋁製成。在前述及以下實施例中之一或多者中,黏附增強層由氧化矽製成。在前述及以下實施例中之一或多者中,氧化第二介電層。在前述及以下實施例中之一或多者中,藉由以含氧氣體處理第一介電層之表面來形成黏附增強層。在前述及以下實施例中之一或多者中,含氧氣體包括選自由N2O、O2、臭氧及CO2所組成之群組的至少一者。在前述及以下實施例中之一或多者中,其中在以含氧氣體處理第一介電層之表面期間,在250℃至400℃之範圍中的溫度下加熱基板,且在0.5托至20托之範圍中壓力下施加此含氧氣體。在前述及以下實施例中之一或多者中,黏附增強層之厚度在1nm至5nm之範圍中。在前述及以下實施例中之一或多者中,藉由以含氧電漿處理第一介電層之表面來形成黏附增強層。在前述及以下實施例中之一或多者中,藉由沉積方法形成黏附增強層。
根據本揭示之實施方式之另一態樣,在一種製造半導體裝置之方法中,在基板上之半導體裝置結構之上形成第一氮化物基介電層,在第一氮化物基介電層之上形成黏附增強層,在黏附增強層之上形成第二氮化物基介電層,且至少部分地氧化第二氮化物基介
電層。第一氮化物基介電層由與第二氮化物基介電層不同的材料製成。在前述及以下實施例中之一或多者中,在第一氮化物基介電層中形成導電圖案,且導電圖案之上部表面自第一氮化物基介電層暴露。在前述及以下實施例中之一或多者中,導電圖案包括鎢。在前述及以下實施例中之一或多者中,黏附增強層形成在導電圖案之上部表面上。在前述及以下實施例中之一或多者中,黏附增強層形成在第一氮化物基介電層上,而不在導電圖案之上部表面上。在前述及以下實施例中之一或多者中,第一氮化物基介電層由氮化矽製成,且第二氮化物基介電層由氮化鋁製成。
根據本揭示之實施方式之另一態樣,在一種製造半導體裝置之方法中,形成嵌入第一絕緣層中之第一導電接觸件,在第一導電接觸件之上形成第二絕緣層,在第二絕緣層中形成第一開口以至少部分地暴露第一導電接觸件,藉由第一導電材料填充第一開口以形成與第一導電接觸件接觸之第二導電接觸件,在第二絕緣層上形成黏附增強層,在黏附增強層上形成氮化物基絕緣層,氧化氮化物基絕緣層,在經氧化的氮化物基絕緣層上形成第三絕緣層,藉由蝕刻第三絕緣層形成第二開口,移除經氧化的氮化物基絕緣層,且藉由第二導電材料填充第二開口。在前述及以下實施例中之一或多者中,第二絕緣層由氮化矽製成,且氮化物基絕緣層由氮化鋁製成。在前述及以下實施例中之一或多者中,第一導電接觸件形成在源極/汲極磊晶層上。在前述及以下實施例中之一或多者中,第一導電接觸件形成在閘電極上。
根據本揭示之實施方式之一個態樣,一種半導體裝置包括設置在半導體裝置結構之上的第一介電層、設置在第一介電層之上
的黏附增強層,以及設置在黏附增強層之上的第二介電層。第一金屬氮化物層及第二金屬氮化物層包括不同金屬。第二介電層之氮濃度沿垂直方向不均勻。在前述及以下實施例中之一或多者中,第一介電層由氮化矽製成。在前述及以下實施例中之一或多者中,第二介電層由氮氧化鋁製成,且第二介電層之氮濃度沿垂直方向朝著第一介電層增加,且第二介電層之氧濃度沿垂直方向朝著第一介電層減小。在前述及以下實施例中之一或多者中,第二介電層包括在氮化鋁層上之氮氧化鋁層。在前述及以下實施例中之一或多者中,黏附增強層由SiOx製成,其中0<x<2。在前述及以下實施例中之一或多者中,黏附增強層具有0.5nm至10nm之厚度。
根據本揭示之實施方式之另一態樣,一種半導體裝置包括設置在半導體裝置結構之上的第一氮化物基介電層;形成在第一氮化物基介電層中的第一導電圖案;設置在第一氮化物基介電層之上的黏附增強層;設置在黏附增強層之上的第二氮化物基介電層;設置在第二氮化物基介電層之上的第三介電層;以及形成在第三介電層中與第一導體圖案接觸之第二導電圖案。在前述及以下實施例中之一或多者中,第一氮化物基介電層由氮化矽製成,且第二氮化物基介電層包括氮化鋁層及氮氧化鋁層中之至少一者。在前述及以下實施例中之一或多者中,第一導電圖案包括鎢。在前述及以下實施例中之一或多者中,第一導電圖案形成在與源極/汲極磊晶層接觸的接觸件上。在前述及以下實施例中之一或多者中,第一導電圖案形成在與閘電極接觸的接觸件上。在前述及以下實施例中之一或多者中,第三介電質包括低k介電材料。在前述及以下實施例中之一或多者中,第二氮化物基介電層部分地覆蓋第一導電圖案之上部表面。
在前述及以下實施例中之一或多者中,黏附增強層部分地覆蓋第一導電圖案之上部表面,且第二氮化物基介電層不與第一導電圖案之上部表面接觸。
根據本揭示之實施方式之另一態樣,一種半導體裝置包括閘電極;源極/汲極結構;設置在第一層間介電層(ILD)中並接觸源極/汲極結構之第一導電接觸件;接觸第一導電接觸件並設置在形成於第二層間介電層中之開口中的第二導電接觸件,此第二層間介電層設置在第一層間介電層之上;接觸閘電極並設置在第一及第二層間介電層中之閘極接觸件;設置在第二層間介電層之上的黏附絕緣層;設置在黏附絕緣層上之蝕刻終止層;設置在蝕刻終止層之上的第三層間介電層;以及接觸第二導電接觸件或閘極接觸件並設置在第三層間介電層中之第三導電接觸件。在前述及以下實施例中之一或多者中,黏附絕緣層具有比第二層間介電層高的氧濃度。在前述及以下實施例中之一或多者中,蝕刻終止層含有鋁。在前述及以下實施例中之一或多者中,半導體裝置進一步包括設置在第三層間介電層中的第四導電接觸件。第三導電接觸件接觸第二導電接觸件,且第四導電接觸件接觸閘極接觸件。在前述及以下實施例中之一或多者中,第二導電接觸件及閘極接觸件包括鎢。在前述及以下實施例中之一或多者中,黏附絕緣層之厚度在1nm至5nm之範圍中,且蝕刻終止層之厚度大於黏附絕緣層之厚度。
前文概述了若干實施例或實例之特徵,使得熟習此項技藝者可較佳理解本揭示之實施方式之態樣。熟習此項技藝者應瞭解,他們可容易地使用本揭示之實施方式作為設計或修改用於實現相同目的及/或達成本文中所介紹之實施例或實例之相同優勢的其他製
程及結構之基礎。熟習此項技藝者亦應認識到,此些等效構造不脫離本揭示之實施方式之精神及範疇,且他們可在不脫離本揭示之實施方式之精神及範疇的情況下在本文進行各種改變、代替及替換。
1:基板
5:鰭片結構
45:第一層間介電層
50:源極/汲極區域
60:第一蝕刻終止層
65:第二層間介電層
68:第一接觸內襯層
70:第一源極/汲極接觸件
75:第二蝕刻終止層
80:第三層間介電層
90:第二接觸內襯層
100:第二源極/汲極接觸件
110:黏附增強層
125:經氧化的蝕刻終止層
130:第四層間介電層
140:第三源極/汲極接觸件
Claims (10)
- 一種製造半導體裝置之方法,包括:在設置於一基板之上的一底部電子結構上形成一第一介電層;形成一導電接觸件在該第一介電層中使得該導電接觸件穿過該第一介電層而接觸該底部電子結構,以及該導電接觸件的一上表面自該第一介電層暴露;在該第一介電層之一表面上藉由一熱氧化製程以一含氧氣體處理該第一介電層之該表面來形成一黏附增強層而不形成在該導電接觸件的該上表面,其中該黏附增強層物理接觸該導電接觸件的一側面的一部分並且由氧化矽或氮氧化矽製成;以及在該黏附增強層上和該導電接觸件的該上表面上形成一第二介電層,其中該第二介電層包括一氮化鋁基材料,並且該第一介電層由氮化矽製成。
- 如請求項1所述之方法,其中:該第二介電層由氮化鋁製成。
- 如請求項1所述之方法,其中該黏附增強層之一厚度在1nm至5nm的範圍中。
- 如請求項1所述之方法,進一步包括氧化該 第二介電層。
- 如請求項1所述之方法,其中在以該含氧氣體處理該第一介電層之該表面期間,在250℃至400℃之範圍中的一溫度下加熱該基板,且在0.5托至20托之範圍中的一壓力下施加該含氧氣體。
- 一種製造半導體裝置之方法,包括:在一基板上之一半導體裝置結構之上形成一第一氮化物基介電層;形成一導電圖案在該第一氮化物基介電層中使得該導電圖案的一上表面自該第一氮化物基介電層暴露;在該第一氮化物基介電層之上藉由一熱氧化製程以一含氧氣體處理該第一氮化物基介電層來形成一黏附增強層而不形成在該導電圖案的該上表面,其中該黏附增強層物理接觸該導電圖案的一側面的一部分;在該黏附增強層之上和該導電圖案的該上表面之上形成一第二氮化物基介電層;以及至少部分地氧化該第二氮化物基介電層,其中該第一氮化物基介電層由與該第二氮化物基介電層不同的材料製成。
- 如請求項6所述之方法,其中該第一氮化物基介電層包括SixOyNz,其中y<z。
- 如請求項6所述之方法,其中:該第一氮化物基介電層由氮化矽製成,以及該第二氮化物基介電層由氮化鋁製成。
- 一種半導體裝置,包括:一第一介電層,設置在一半導體裝置結構之上;一黏附增強層,設置在該第一介電層之上;以及一第二介電層,設置在該黏附增強層之上,其中該第一介電層包括第一金屬氮化物,且該第二介電層包括與該第一金屬氮化物不同的第二金屬氮化物,以及該第二介電層之一氮濃度沿一垂直方向不均勻。
- 如請求項9所述之半導體裝置,其中:該第二介電層包括氮氧化鋁,以及該第二介電層之該氮濃度沿該垂直方向朝著該第一介電層增加,且該第二介電層之一氧濃度沿該垂直方向朝著該第一介電層減小。
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