TWI762346B - A kind of ohmic contact manufacturing method of group III nitride semiconductor element - Google Patents

A kind of ohmic contact manufacturing method of group III nitride semiconductor element Download PDF

Info

Publication number
TWI762346B
TWI762346B TW110120474A TW110120474A TWI762346B TW I762346 B TWI762346 B TW I762346B TW 110120474 A TW110120474 A TW 110120474A TW 110120474 A TW110120474 A TW 110120474A TW I762346 B TWI762346 B TW I762346B
Authority
TW
Taiwan
Prior art keywords
nitride semiconductor
group iii
layer
iii nitride
barrier layer
Prior art date
Application number
TW110120474A
Other languages
Chinese (zh)
Other versions
TW202249092A (en
Inventor
何焱騰
陳乃榕
Original Assignee
瑞礱科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 瑞礱科技股份有限公司 filed Critical 瑞礱科技股份有限公司
Priority to TW110120474A priority Critical patent/TWI762346B/en
Priority to CN202210049485.8A priority patent/CN115440591A/en
Application granted granted Critical
Publication of TWI762346B publication Critical patent/TWI762346B/en
Publication of TW202249092A publication Critical patent/TW202249092A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本發明提供一種降低III族氮化物半導體元件之接觸電阻的歐姆接觸製作方法。主要是使用氟化物氣體電漿進行蝕刻與表面處理，並進行退火處理以實現超低接觸電阻之歐姆接觸。此製造方法不會造成半導體通道表面損傷，整體製程相對簡單，且製造出的III族氮化物半導體元件的可靠度佳，可應用於三族氮化物電晶體與二極體。The present invention provides a method for fabricating an ohmic contact for reducing the contact resistance of a group III nitride semiconductor element. It mainly uses fluoride gas plasma for etching and surface treatment, and annealing treatment to achieve ohmic contact with ultra-low contact resistance. The manufacturing method does not cause damage to the surface of the semiconductor channel, the overall process is relatively simple, and the manufactured group III nitride semiconductor device has good reliability, which can be applied to group III nitride transistors and diodes.

Description

一種III族氮化物半導體元件之歐姆接觸製造方法A kind of ohmic contact manufacturing method of group III nitride semiconductor element

本發明是有關於一種III族氮化物半導體元件，且特別是有關於一種III族氮化物半導體元件之歐姆接觸的製造方法。The present invention relates to a group III nitride semiconductor device, and in particular, to a method for manufacturing an ohmic contact of a group III nitride semiconductor device.

現今在電力電子領域中，導入寬帶隙半導體元件以提升設備和模組能效並降低能耗，已是未來趨勢。特別是氮化鎵高頻功率元件，由於其優異的性能而成為下一代高功率和高頻器件中，最有希望超越矽材料極限的半導體元件。III族氮化物半導體元件，例如，氮化鎵(GaN)半導體高電子遷移率電晶體(HEMTs)，通常會形成二維電子氣(2DEG，two-dimensional electron gas)，以藉此達到高頻操作與高功率輸出。In the field of power electronics, it is a future trend to introduce wide-bandgap semiconductor components to improve the energy efficiency of equipment and modules and reduce energy consumption. In particular, gallium nitride high-frequency power components have become the most promising semiconductor components in the next-generation high-power and high-frequency devices due to their excellent performance beyond the limits of silicon materials. Group III nitride semiconductor devices, such as gallium nitride (GaN) semiconductor high electron mobility transistors (HEMTs), typically form a two-dimensional electron gas (2DEG) to achieve high frequency operation with high power output.

以金屬-絕緣-半導體(MIS)結構的高電子遷移(HEMT)的III族氮化物半導體元件為例，其開啟電阻大致上會相關於接觸電阻、二維電子氣的源極與閘極間電阻、二維電子氣的閘極與汲極間電阻以及通道電阻，其中接觸電阻佔開啟電阻的最大部分，故在設計上需要降低其電阻值成為歐姆接觸，以藉此達到高開啟狀態電流、低功率損耗、低熱量產生與長生命週期。Taking metal-insulator-semiconductor (MIS) high electron mobility (HEMT) III-nitride semiconductor devices as an example, the turn-on resistance is roughly related to the contact resistance and the resistance between the source and gate of the two-dimensional electron gas , The resistance between the gate and the drain of the two-dimensional electron gas and the channel resistance, of which the contact resistance accounts for the largest part of the on-resistance, so it is necessary to reduce its resistance value to become an ohmic contact in design, so as to achieve high on-state current, low Power loss, low heat generation and long life cycle.

已知在形成歐姆接觸的降低接觸電阻的作法有兩種，並說明如下。其中一種是蝕刻阻障層的接觸電極區域後重新長出重摻雜N型通道層(例如，N+ GaN層)於阻障層的兩側以及於通道層之上，並接著形成Ti/Au金屬的源極與汲極，以在N型通道層上形成歐姆接觸。然而，此種作法可能有下面的缺點：良率不高；製造成本高；蝕刻後造成阻障層內側損傷導致缺陷並容易引發漏電；以及需要複雜且昂貴的分子束磊晶(MBE)來重新長出重摻雜N型通道層。Two methods of reducing contact resistance in forming ohmic contacts are known, and are described below. One is to re-grow a heavily doped N-type channel layer (eg, N+ GaN layer) on both sides of the barrier layer and on the channel layer after etching the contact electrode region of the barrier layer, and then form Ti/Au metal source and drain to form ohmic contacts on the N-type channel layer. However, this approach may have the following disadvantages: low yield; high manufacturing cost; damage to the inner side of the barrier layer after etching, leading to defects and easy leakage; and requiring complex and expensive molecular beam epitaxy (MBE) to recreate A heavily doped N-type channel layer is grown.

其中另一種降低接觸電阻的作法是選擇讓Ti/Au金屬的源極與閘極部分埋入阻障層中。然而，此種作法可能有下面的缺點：難以控制蝕刻深度與側牆斜率精度；在晶圓等級(wafer-scale)的晶片製程可能有不均勻問題；可能有殘留物與蝕刻損害；以及非常難以實現具有超薄的AlN或Al(Ga)N的阻障層的HEMT III族氮化物半導體元件(註：因為不易控制蝕刻深度)。據此，對於低複雜度、低成本與高良率的低接觸電阻的歐姆接觸的製造方法，業界仍有迫切需求。Another way to reduce the contact resistance is to choose to bury the source and gate parts of the Ti/Au metal in the barrier layer. However, this approach may have the following disadvantages: difficulty in controlling etch depth and sidewall slope accuracy; possible non-uniformity issues in wafer-scale wafer processing; possible residue and etch damage; and very difficult Realize HEMT III-nitride semiconductor devices with ultra-thin AlN or Al(Ga)N barrier layers (note: it is difficult to control the etching depth). Accordingly, there is still an urgent need in the industry for a low-complexity, low-cost, and high-yield low-contact-resistance ohmic contact manufacturing method.

根據本發明之目的，提供一種III族氮化物半導體元件之歐姆接觸的製造方法，且此III族氮化物半導體元件包括電晶體以及二極體。此III族氮化物半導體元件之歐姆接觸的製造方法包括：提供未形成源極及汲極的III族氮化物半導體結構；於III族氮化物半導體結構的阻障層上形成保護層；在保護層形成具有圖案的遮罩層(例如，光阻層或其他可以抵抗氟化物氣體電漿腐蝕的材料層)，以定義出源極及汲極的位置；使用氟化物氣體電漿對III族氮化物半導體結構的保護層進行蝕刻處理，其中保護層對應於源極與汲極的位置處的部分至少被蝕刻至阻障層的表面；使用氟化物氣體電漿對III族氮化物半導體結構裸露的阻障層進行表面處理；移除遮罩層，並進行退火處理；在退火處理後，於源極與汲極的位置處植入金屬，以形成源極與汲極；以及對形成有源極與汲極的III族氮化物半導體結構進行快速退火處理。According to the purpose of the present invention, a method for manufacturing an ohmic contact of a group III nitride semiconductor device is provided, and the group III nitride semiconductor device includes a transistor and a diode. The manufacturing method of the ohmic contact of the group III nitride semiconductor device includes: providing a group III nitride semiconductor structure without forming a source electrode and a drain electrode; forming a protective layer on the barrier layer of the group III nitride semiconductor structure; on the protective layer Form a patterned mask layer (eg, photoresist layer or other layer of material resistant to fluoride gas plasma etching) to define the location of source and drain electrodes; use fluoride gas plasma to The protective layer of the semiconductor structure is etched, wherein the part of the protective layer at the positions corresponding to the source electrode and the drain electrode is etched at least to the surface of the barrier layer; using fluoride gas plasma to expose the barrier layer of the III-nitride semiconductor structure. The barrier layer is subjected to surface treatment; the mask layer is removed and annealed; after the annealing treatment, metal is implanted at the position of the source electrode and the drain electrode to form the source electrode and the drain electrode; The Ill-nitride semiconductor structure of the drain is subjected to a rapid annealing process.

根據本發明之目的，提供一種III族氮化物半導體元件半成品，係使用前述III族氮化物半導體元件之歐姆接觸的製造方法所製造，包括：III族氮化物半導體結構；以及保護層、源極與汲極，形成於III族氮化物半導體結構的阻障層之上。According to the purpose of the present invention, a semi-finished product of a group III nitride semiconductor device is provided, which is manufactured by using the above-mentioned method for manufacturing an ohmic contact of a group III nitride semiconductor device, comprising: a group III nitride semiconductor structure; and a protective layer, a source electrode and a The drain electrode is formed on the barrier layer of the III-nitride semiconductor structure.

根據本發明之目的，提供一種III族氮化物半導體元件，系包括將上述之III族氮化物半導體元件半成品的部分該保護層去除後所形成的另一III族氮化物半導體元件半成以及閘極，其中閘極形成在阻障層之上，且於水平方向上，係位於源極與汲極之間。According to the purpose of the present invention, a group III nitride semiconductor device is provided, which comprises another group III nitride semiconductor device semi-finished and a gate electrode formed by removing part of the protective layer of the above-mentioned semi-finished product of the group III nitride semiconductor device. , wherein the gate electrode is formed on the barrier layer, and is located between the source electrode and the drain electrode in the horizontal direction.

總而言之，相對於先前技術，本發明實施例提供的III族氮化物半導體元件之歐姆接觸製造方法具有低製造成本、高生產良率與製程簡單等技術效果。All in all, compared with the prior art, the method for manufacturing the ohmic contact of the III-nitride semiconductor device provided by the embodiment of the present invention has the technical effects of low manufacturing cost, high production yield, and simple manufacturing process.

為利 貴審查員瞭解本發明之技術特徵、內容與優點及其所能達成之功效，茲將本發明配合附圖，並以實施例之表達形式詳細說明如下，而其中所使用之圖式，其主旨僅為示意及輔助說明書之用，未必為本發明實施後之真實比例與精準配置，故不應就所附之圖式的比例與配置關係解讀、侷限本發明於實際實施上的權利範圍，合先敘明。In order to facilitate the examiners to understand the technical features, content and advantages of the present invention and the effects that can be achieved, the present invention is hereby described in detail with the accompanying drawings and in the form of embodiments as follows. The subject matter is only for illustration and auxiliary description, and is not necessarily the real scale and precise configuration after the implementation of the present invention. Therefore, the ratio and configuration relationship of the attached drawings should not be interpreted or limited to the scope of rights of the present invention in actual implementation. Together first to describe.

為了解決先前技術之III族氮化物半導體元件之歐姆接觸其製造良率低與製造成本高的技術問題，本發明提出一種新穎可行的降低III族氮化物半導體元件之歐姆接觸製造方法，其不會造成半導體通道表面損傷，整體製程相對簡單，且製造出的III族氮化物半導體元件的可靠度佳，甚至，接觸電阻的電阻率最低可達0.1歐姆·公釐。進一步地說，本發明的降低III族氮化物半導體元件之接觸電阻的歐姆接觸製造方法主要是在未形成源極及汲極的III族氮化物半導體結構形成保護層於阻障層上，接著，透過遮罩材料(例如，光阻)定義出圖案後，使用氟化物氣體電漿進行對未被遮罩材料遮蔽的保護層進行蝕刻與表面處理， 然後移除光阻，並進行退火處理後，才植入金屬以形成源極與閘極，最後再進行快速退火處理，以達到超低接觸電阻之歐姆接觸。In order to solve the technical problems of low manufacturing yield and high manufacturing cost of the ohmic contact of the group III nitride semiconductor device in the prior art, the present invention proposes a novel and feasible method for reducing the ohmic contact of the group III nitride semiconductor device, which does not The surface of the semiconductor channel is damaged, the overall process is relatively simple, and the reliability of the manufactured III-nitride semiconductor element is good, and even the resistivity of the contact resistance can be as low as 0.1 ohm·mm. Further, the ohmic contact manufacturing method for reducing the contact resistance of the III-nitride semiconductor element of the present invention is mainly to form a protective layer on the barrier layer on the III-nitride semiconductor structure without the source and drain electrodes, and then, After the pattern is defined through the mask material (eg, photoresist), the protective layer that is not masked by the mask material is etched and surface treated using fluoride gas plasma, and then the photoresist is removed and annealed. Metal is implanted to form the source and gate, and finally, rapid annealing is performed to achieve ohmic contact with ultra-low contact resistance.

於本發明的III族氮化物半導體元件之歐姆接觸的製作方法中，由於存在著保護層，因此氟化物氣體電漿處理不會傷害到通道層表面，且透過控制功率與處理時間，氟離子不會穿透到通道層。另外，退火處理更可將殘留的氟離子移除。據此，本發明實施例的降低III族氮化物半導體元件之接觸電阻的歐姆接觸製造方法具有低製造成本、高生產良率與製程簡單等技術效果。另外，本發明實施例還提供了一種使用上述III族氮化物半導體元件之歐姆接觸的製造方法所製造出來的III族氮化物半導體元件與其半成品。In the method for fabricating the ohmic contact of the III-nitride semiconductor element of the present invention, due to the existence of the protective layer, the fluoride gas plasma treatment will not damage the surface of the channel layer, and by controlling the power and treatment time, the fluoride ions will not be damaged. penetrates into the channel layer. In addition, the annealing treatment can further remove the residual fluoride ions. Accordingly, the ohmic contact manufacturing method for reducing the contact resistance of the III-nitride semiconductor device according to the embodiment of the present invention has the technical effects of low manufacturing cost, high production yield, and simple manufacturing process. In addition, an embodiment of the present invention also provides a group III nitride semiconductor element and a semi-finished product thereof manufactured by using the above-mentioned method for manufacturing an ohmic contact of a group III nitride semiconductor element.

請參照圖2H，本發明實施例III族氮化物半導體元件半成品的剖面示意圖如圖2H。III族氮化物半導體結構11包括未形成源極12及汲極13的III族氮化物半導體結構11、源極12、汲極13與保護層14，其中源極12、汲極13與保護層14位於III族氮化物半導體結構11的阻障層115的表面上，且於水平方上，部分保護層14位於源極12的側牆與汲極13的側牆之間。由於經過氟化物氣體電漿進行蝕刻與表面處理，並經過真空退火處理與快速退火處理，源極12與汲極13相對於阻障層115的接觸電阻的電阻率可達到0.1至0.2歐姆·公釐(包括0.1與0.2歐姆·公釐)。Referring to FIG. 2H , a schematic cross-sectional view of a semi-finished product of a Group III nitride semiconductor device according to an embodiment of the present invention is shown in FIG. 2H . The group III nitride semiconductor structure 11 includes the group III nitride semiconductor structure 11 without the source electrode 12 and the drain electrode 13 , the source electrode 12 , the drain electrode 13 and the protective layer 14 , wherein the source electrode 12 , the drain electrode 13 and the protective layer 14 On the surface of the barrier layer 115 of the III-nitride semiconductor structure 11 , and in the horizontal direction, part of the protective layer 14 is located between the sidewall of the source electrode 12 and the sidewall of the drain electrode 13 . Due to etching and surface treatment by fluoride gas plasma, vacuum annealing and rapid annealing, the resistivity of the contact resistance of the source electrode 12 and the drain electrode 13 with respect to the barrier layer 115 can reach 0.1 to 0.2 ohm·kg centimeters (including 0.1 and 0.2 ohm·mm).

於本發明實施例中，保護層14為介電材質，且可以是SiN x層、SiO 2層或Si層，其中x表示大於0的任意數。保護層14的厚度原則可以選自5至100奈米之間(包括5奈米與100奈米)，較佳地，選自5至40奈米之間 (包括5奈米與40奈米)。另外，保護層14的厚度選擇與材料與氟化物氣體電漿功率與處理時間相關，其主要目的是為了保護二維電子氣(2DEG)層1141在氟化物氣體電漿處理時不會損傷。源極12與汲極13的每一者可以是金屬堆疊結構，其包括由下往上排序的第一結構層與第二結構層，第一結構層可以是Ti/Al雙層結構，而第二結構層可以是Ni/Au雙層結構、Ti/Ta雙層結構、Ti層、TiN層、Cu層或W層，且本發明不以此為限制。 In the embodiment of the present invention, the protective layer 14 is made of a dielectric material, and may be a SiN x layer, a SiO 2 layer or a Si layer, wherein x represents any number greater than 0. The thickness of the protective layer 14 can be selected from 5 to 100 nm (including 5 nm and 100 nm), preferably, from 5 to 40 nm (including 5 nm and 40 nm) . In addition, the thickness selection of the protective layer 14 is related to the material, fluoride gas plasma power and processing time, and its main purpose is to protect the two-dimensional electron gas (2DEG) layer 1141 from damage during fluoride gas plasma processing. Each of the source electrode 12 and the drain electrode 13 may be a metal stack structure including a first structure layer and a second structure layer ordered from bottom to top, the first structure layer may be a Ti/Al double-layer structure, and the first structure layer may be a Ti/Al double layer structure. The two-structure layer may be a Ni/Au double-layer structure, a Ti/Ta double-layer structure, a Ti layer, a TiN layer, a Cu layer or a W layer, and the present invention is not limited thereto.

於圖1與圖2A至圖2H的實施例中， III族氮化物半導體結構11為HEMT半導體結構，且最後的III族氮化物半導體元件半成品1不具有閘極，故可以作為HEMT二極體使用，但本發明不以此為限制，且在其他實施例中，III族氮化物半導體元件半成品1可以形成有閘極，且於水平方向上，閘極位於源極12的側牆與汲極13的側牆之間。III族氮化物半導體結構11包括基板111、成核層(nucleation layer)112、緩衝層113、通道層114與阻障層115，其中成核層112形成於基板111的表面上，緩衝層113形成於成核層112的表面上，通道層114形成於緩衝層113的表面上，以及阻障層115形成於通道層114的表面上。於III族氮化物半導體結構11，二維電子氣層1141形成通道層114與阻障層115之間的界面中。In the embodiments of FIGS. 1 and 2A to 2H , the III-nitride semiconductor structure 11 is a HEMT semiconductor structure, and the final semi-finished III-nitride semiconductor device 1 does not have a gate, so it can be used as a HEMT diode. , but the present invention is not limited to this, and in other embodiments, the semi-finished product 1 of the III-nitride semiconductor device may be formed with a gate electrode, and in the horizontal direction, the gate electrode is located on the sidewall of the source electrode 12 and the drain electrode 13 between the side walls. The group III nitride semiconductor structure 11 includes a substrate 111 , a nucleation layer 112 , a buffer layer 113 , a channel layer 114 and a barrier layer 115 , wherein the nucleation layer 112 is formed on the surface of the substrate 111 , and the buffer layer 113 is formed On the surface of the nucleation layer 112 , the channel layer 114 is formed on the surface of the buffer layer 113 , and the barrier layer 115 is formed on the surface of the channel layer 114 . In the III-nitride semiconductor structure 11 , the two-dimensional electron gas layer 1141 is formed in the interface between the channel layer 114 and the barrier layer 115 .

基板111例如為矽、絕緣層上覆矽(SOI)、碳化矽(SiC)、藍寶石基板或其他能夠讓III族氮化物半導體磊晶的基板，且本發明不以此為限制。成核層112例如為低溫的GaN層、低溫的AlN層、高溫的GaN層或高溫的AlN層，且本發明不以此為限制。緩衝層113可以例如為AlN層、AlGaN層、InGaN層、超晶體(super lattice) AlN/GaN層、超晶體AlGaN/GaN層、超晶體AlN/AlGaN、碳摻雜GaN層、鐵摻雜GaN層或無摻雜GaN層，且本發明不以此為限制。在緩衝層113選用AlGaN層時，AlGaN的化學組成式為的化學組成式為Al yGa 1-yN，5%＜=y。通道層114可以例如為GaN層、AlGaN層、InN層或InGaN層，且本發明不以此為限制。阻障層115可以例如為AlGaN層、InAlN層、InAlGaN層、InGaN層或AlN層，且本發明不以此為限制。在阻障層115選用AlGaN層時，AlGaN的化學組成式為Al xGa 1-xN，0＜=x ＜=40%，例如，x可以是20%，阻障層115的厚度為20奈米，且此時二維電子氣層1141的片電阻值為＜450歐姆/□。 The substrate 111 is, for example, silicon, silicon-on-insulator (SOI), silicon carbide (SiC), sapphire substrate, or other substrates capable of epitaxy of group III nitride semiconductors, and the invention is not limited thereto. The nucleation layer 112 is, for example, a low-temperature GaN layer, a low-temperature AlN layer, a high-temperature GaN layer or a high-temperature AlN layer, and the present invention is not limited thereto. The buffer layer 113 may be, for example, an AlN layer, an AlGaN layer, an InGaN layer, a super lattice AlN/GaN layer, a supercrystalline AlGaN/GaN layer, a supercrystalline AlN/AlGaN, a carbon-doped GaN layer, an iron-doped GaN layer or an undoped GaN layer, and the present invention is not limited thereto. When the buffer layer 113 is an AlGaN layer, the chemical composition formula of AlGaN is AlyGa1 -yN , 5%<=y. The channel layer 114 may be, for example, a GaN layer, an AlGaN layer, an InN layer or an InGaN layer, and the present invention is not limited thereto. The barrier layer 115 may be, for example, an AlGaN layer, an InAlN layer, an InAlGaN layer, an InGaN layer or an AlN layer, and the present invention is not limited thereto. When the barrier layer 115 is an AlGaN layer, the chemical composition formula of AlGaN is AlxGa1 - xN , 0<=x<=40%, for example, x can be 20%, and the thickness of the barrier layer 115 is 20 nanometers m, and the sheet resistance value of the two-dimensional electron gas layer 1141 is <450 ohms/□.

請接著參照圖1，圖2A至圖2H，圖1是本發明實施例的降低III族氮化物半導體元件之歐姆接觸的製造方法的流程圖，以及圖2A至圖2H是本發明實施例的III族氮化物半導體元件之歐姆接觸製造方法之各步驟成品的剖面示意圖。1, FIG. 2A to FIG. 2H, FIG. 1 is a flow chart of a method for reducing the ohmic contact of a group III nitride semiconductor device according to an embodiment of the present invention, and FIG. 2A to FIG. 2H are an embodiment of the present invention. The cross-sectional schematic diagram of the finished product of each step of the ohmic contact manufacturing method of the group nitride semiconductor device.

首先，在步驟S31中，提供一個如圖2A之未形成源極12及汲極13且具有二維電子氣的III族氮化物半導體結構11，其結構上類似於圖1的III族氮化物半導體結構11。接著，於步驟S32中，在III族氮化物半導體結構11的阻障層115上形成保護層14'，如圖2B所示，其中形成保護層14'的方式例如透過電漿增強化學氣相沉積 (PECVD)的方式來沉積形成，保護層14'的材質如前面所述，且厚度選擇自40奈米以下，例如，10、20或40奈米。另外，沉積保護層14'的方式更可以是原位金屬有機氣相外延(in-situ MOCVD)、任一種化學氣相沉積(CVD)、任一種物理氣相沉積(PVD)或任一種原子層沉積(ALD)。之後，在步驟S33，在保護層14'形成具有圖案的遮罩層17，以定義出源極12與汲極13的位置，如圖2C。First, in step S31, a group III nitride semiconductor structure 11 having a two-dimensional electron gas without forming the source electrode 12 and the drain electrode 13 as shown in FIG. 2A is provided, which is similar in structure to the group III nitride semiconductor structure in FIG. 1 . Structure 11. Next, in step S32 , a protective layer 14 ′ is formed on the barrier layer 115 of the III-nitride semiconductor structure 11 , as shown in FIG. 2B , wherein the protective layer 14 ′ is formed by, for example, plasma enhanced chemical vapor deposition (PECVD) method, the material of the protective layer 14' is as described above, and the thickness is selected from 40 nm or less, for example, 10, 20 or 40 nm. In addition, the method of depositing the protective layer 14 ′ may be in-situ metal organic vapor phase epitaxy (in-situ MOCVD), any chemical vapor deposition (CVD), any physical vapor deposition (PVD), or any atomic layer deposition (ALD). After that, in step S33 , a mask layer 17 with a pattern is formed on the protective layer 14 ′ to define the positions of the source electrode 12 and the drain electrode 13 , as shown in FIG. 2C .

接著，在步驟S34中，以乾蝕刻方式使用氟化物氣體電漿對III族氮化物半導體結構11的保護層14'進行蝕刻處理，如圖2D所示；在步驟S35中，使用氟化物氣體電漿進行表面處理，如圖2E所示。蝕刻與表面處理例如可以透過感應耦合電漿(ICP)系統產生CF 4電漿，其中保護層14對應於源極12與汲極13的位置處的部分會被蝕刻至阻障層115的表面而形成保護層14與實現歐姆區的處理。氟化物氣體電漿的功率選自50至300瓦特之間(包括50與300瓦特)，以及處理時間選自5至300秒之間(包括5與300秒)，較佳地是選自5至50秒之間(包括5與50秒)。當保護層14’的厚度為10至40奈米間，處理時間可以是50秒，且保護層14'的最佳厚度為30奈米。另外，除了CF 4電漿之外，也可以選用SF 6、CHF 3或C 4F 8電漿，且更能選擇性地混入Ar電漿。再者，除了選用感應耦合電漿系統外，也可以選用反應離子刻蝕(RIE)或電感耦合等離子體-反應離子刻蝕(ICP-RIE)系統。在保護層14'大概是20奈米時，使用氟化物氣體電漿的處理大概30與50秒，能夠將原來接觸電阻的電阻率從0.8分別降低至0.44與0.2歐姆·公釐。附帶一提的是，蝕刻與表面處理的氟化物氣體電漿之種類、功率與處理時間等可以彼此相同或不同。 Next, in step S34 , the protective layer 14 ′ of the III-nitride semiconductor structure 11 is etched by dry etching using fluoride gas plasma, as shown in FIG. 2D ; in step S35 , using fluoride gas plasma The slurry was surface treated as shown in Figure 2E. Etching and surface treatment can, for example, generate CF 4 plasma through an Inductively Coupled Plasma (ICP) system, wherein the portion of the protective layer 14 corresponding to the positions of the source electrode 12 and the drain electrode 13 is etched to the surface of the barrier layer 115 . The process of forming the protective layer 14 and realizing the ohmic region. The power of the fluoride gas plasma is selected from between 50 and 300 watts (including 50 and 300 watts), and the treatment time is selected from between 5 and 300 seconds (including 5 and 300 seconds), preferably from 5 to 300 seconds. Between 50 seconds (including 5 and 50 seconds). When the thickness of the protective layer 14' is between 10 and 40 nm, the processing time may be 50 seconds, and the optimum thickness of the protective layer 14' is 30 nm. In addition, in addition to CF 4 plasma, SF 6 , CHF 3 or C 4 F 8 plasma can also be selected, and Ar plasma can be selectively mixed. Furthermore, in addition to the inductively coupled plasma system, a reactive ion etching (RIE) or an inductively coupled plasma-reactive ion etching (ICP-RIE) system can also be selected. When the protective layer 14' is about 20 nm, the fluoride gas plasma treatment for about 30 and 50 seconds can reduce the resistivity of the original contact resistance from 0.8 to 0.44 and 0.2 ohm·mm, respectively. Incidentally, the kind, power, processing time, etc. of the fluoride gas plasma for etching and surface treatment may be the same or different from each other.

接著，在步驟S36中，移除遮罩層17，並以真空退火處理進行表面熱處理去除氟離子鍵結，如圖2F所示。此處的退火處理可以是多步階退火處理或單步階退火處理，例如，退火處理的步階數較佳地是1至4(包括1與4)。然後，在進行退火處理後，於步驟S37中，才將金屬植入，如圖2G。金屬植入方式可以例如是透過電子束槍沉積，以形成源極12與汲極13。退火處理可以是真空腔室內進行或在Ar環境下進行，且在Ar環境下更可以導入其他氣體。退火處理可以是快速退火處理或其他類型的退火處理，退火處理的溫度大致在攝氏450度到650度之間(包括450與650度)，退火處理的總時間大概在30至240秒之間(包括30與240秒)，若是進行多步階退火處理，則每個步階的時間在15至60秒之間(包括15與60秒)。Next, in step S36, the mask layer 17 is removed, and a surface heat treatment is performed by vacuum annealing to remove fluoride ion bonds, as shown in FIG. 2F . The annealing treatment here may be a multi-step annealing treatment or a single-step annealing treatment, for example, the number of steps of the annealing treatment is preferably 1 to 4 (including 1 and 4). Then, after the annealing treatment, in step S37, the metal is implanted, as shown in FIG. 2G. The metal implantation method may be, for example, deposition through an electron beam gun to form the source electrode 12 and the drain electrode 13 . The annealing treatment can be performed in a vacuum chamber or in an Ar environment, and other gases can be introduced in an Ar environment. The annealing treatment can be rapid annealing treatment or other types of annealing treatment. The temperature of the annealing treatment is approximately between 450 and 650 degrees Celsius (including 450 and 650 degrees), and the total annealing time is approximately between 30 and 240 seconds ( Including 30 and 240 seconds), if the multi-step annealing process is performed, the time of each step is between 15 and 60 seconds (15 and 60 seconds inclusive).

然後，在步驟S38中，進行快速退火處理以達到超低接觸電阻，如圖2H，其中快速退火處理的溫度是攝氏750至850度(包括750與850度)，快速退火處理的總時間大概在10至60秒之間(包括10與60秒，較佳地是30秒)，而且接觸電阻的電阻率更可以降低至0.1至0.15歐姆·公釐。Then, in step S38, a rapid annealing treatment is performed to achieve ultra-low contact resistance, as shown in Figure 2H, wherein the temperature of the rapid annealing treatment is 750 to 850 degrees Celsius (including 750 and 850 degrees Celsius), and the total time of the rapid annealing treatment is about Between 10 and 60 seconds (including 10 and 60 seconds, preferably 30 seconds), and the resistivity of the contact resistance can be reduced to 0.1 to 0.15 ohm·mm.

請參照圖3A，圖3A是本發明實施例之III族氮化物半導體元件的剖面示意圖。於圖3A中，III族氮化物半導體元件3為HEMT的III族氮化物半導體元件。III族氮化物半導體元件3的實現方式如下。首先，將圖2H的III族氮化物半導體元件半成品1進行檯面蝕刻，定義出隔離區域RI後。接著，去除水平方向中介於源極12與汲極13之間的部分保護層14，以定義出閘極區域。接著，在閘極區域處形成位於阻障層115之上的閘極15。Please refer to FIG. 3A . FIG. 3A is a schematic cross-sectional view of a group III nitride semiconductor device according to an embodiment of the present invention. In FIG. 3A , the group III nitride semiconductor element 3 is a group III nitride semiconductor element of HEMT. The implementation of the group III nitride semiconductor element 3 is as follows. First, the semi-finished product 1 of the group III nitride semiconductor element shown in FIG. 2H is mesa-etched to define the isolation region RI. Next, a portion of the protective layer 14 between the source electrode 12 and the drain electrode 13 in the horizontal direction is removed to define a gate region. Next, the gate electrode 15 over the barrier layer 115 is formed at the gate electrode region.

請參照圖3B，圖3B是本發明另一實施例之III族氮化物半導體元件的剖面示意圖。不同於圖3A的實施例，III族氮化物半導體元件4去除部分保護層14之後，還沉積了厚度大概是1至10奈米(包括1與10奈米的兩個端點值)的介電層88於保護層14與閘極區域處的阻障層115之上，然後，閘極15形成於閘極區域處的介電層88之上。Please refer to FIG. 3B . FIG. 3B is a schematic cross-sectional view of a group III nitride semiconductor device according to another embodiment of the present invention. Different from the embodiment of FIG. 3A , after removing part of the protective layer 14 in the III-nitride semiconductor device 4 , a dielectric with a thickness of about 1 to 10 nanometers (including the two end values of 1 and 10 nanometers) is also deposited Layer 88 is over protective layer 14 and barrier layer 115 at the gate region, and gate 15 is then formed over dielectric layer 88 at the gate region.

請參照圖3C，圖3C是本發明再一實施例之III族氮化物半導體元件的剖面示意圖。不同於圖3B的實施例，III族氮化物半導體元件5去除部分保護層14時，更將部分阻障層115去除， 因此閘極 15 位於阻障層115的凹槽(recess)之上。 Please refer to FIG. 3C , which is a schematic cross-sectional view of a group III nitride semiconductor device according to still another embodiment of the present invention. Different from the embodiment of FIG. 3B , when part of the protective layer 14 is removed from the III-nitride semiconductor device 5 , part of the barrier layer 115 is also removed, so that the gate electrode 15 is located on the recess of the barrier layer 115 .

具體而言，本發明實施例的降低III族氮化物半導體元件之接觸電阻的歐姆接觸製造方法要使用搭配保護層的氟化物氣體電漿處理以及退火處理共兩次地降低接觸電阻，故接觸電阻的電阻率可以有效降低。再者，相對於先前技術，本發明實施例的III族氮化物半導體元件之歐姆接觸製造方法具有低製造成本、高生產良率與製程簡單等技術效果。Specifically, the ohmic contact manufacturing method for reducing the contact resistance of the III-nitride semiconductor device according to the embodiment of the present invention uses a fluoride gas plasma treatment with a protective layer and an annealing treatment to reduce the contact resistance twice, so the contact resistance The resistivity can be effectively reduced. Furthermore, compared with the prior art, the method for manufacturing the ohmic contact of the III-nitride semiconductor device according to the embodiment of the present invention has the technical effects of low manufacturing cost, high production yield, and simple manufacturing process.

綜觀上述，可見本發明在突破先前之技術下，確實已達到所欲增進之功效，且也非熟悉該項技藝者所易於思及，再者，本發明申請前未曾公開，且其所具之進步性、實用性，顯已符合專利之申請要件，爰依法提出專利申請，懇請  貴局核准本件發明專利申請案，以勵發明，至感德便。Looking at the above, it can be seen that the present invention has indeed achieved the desired enhancement effect under the breakthrough of the previous technology, and it is not easy for those who are familiar with the art to think about it. Furthermore, the present invention has not been disclosed before the application, and it has It is progressive and practical, and obviously meets the requirements for patent application. It is recommended to file a patent application in accordance with the law. I urge your bureau to approve this patent application for invention, in order to encourage invention, and it is extremely convenient.

以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍內。The above-mentioned embodiments are only to illustrate the technical ideas and characteristics of the present invention, and the purpose is to enable those who are familiar with the art to understand the content of the present invention and implement it accordingly. It should not be used to limit the patent scope of the present invention. That is, all equivalent changes or modifications made according to the spirit disclosed in the present invention should still be covered within the patent scope of the present invention.

1:III族氮化物族半導體元件半成品 3～5:III族氮化物族半導體元件 11:III族氮化物半導體結構 111:基板 112:成核層 113:緩衝層 114:通道層 115:阻障層 12:源極 13:汲極 14、14':保護層 15:閘極 88:介電層 17:遮罩層 S31～S38:步驟 RI:隔離區域 1141:二維電子氣層 1: Semi-finished products of III-nitride semiconductor devices 3 to 5: Group III nitride semiconductor devices 11: Group III nitride semiconductor structure 111: Substrate 112: Nucleation layer 113: Buffer layer 114: channel layer 115: Barrier layer 12: Source 13: Drain 14, 14': protective layer 15: Gate 88: Dielectric layer 17: Mask layer S31～S38: Steps RI: Isolated area 1141: Two-dimensional electron gas layer

本發明之多個附圖僅是用於使本發明所屬技術領域的通常知識者易於了解本發明，其尺寸與配置關係僅為示意，且非用於限制本發明，其中各附圖簡要說明如下： 圖1是本發明實施例的III族氮化物半導體元件之歐姆接觸電阻的製造方法的流程圖； 圖2A至圖2H是本發明實施例的III族氮化物半導體元件之歐姆接觸電阻的製造方法其各步驟成品的剖面示意圖； 圖3A是本發明實施例之III族氮化物半導體元件的剖面示意圖； 圖3B是本發明另一實施例之III族氮化物半導體元件的剖面示意圖； 圖3C是本發明再一實施例之III族氮化物半導體元件的剖面示意圖。 The drawings of the present invention are only used to facilitate the understanding of the present invention by those skilled in the art to which the present invention pertains, and the dimensions and dispositions thereof are merely schematic representations, and are not intended to limit the present invention, wherein the drawings are briefly described as follows : 1 is a flowchart of a method for manufacturing an ohmic contact resistance of a group III nitride semiconductor device according to an embodiment of the present invention; 2A to 2H are schematic cross-sectional views of a finished product of each step of a method for manufacturing an ohmic contact resistance of a group III nitride semiconductor device according to an embodiment of the present invention; 3A is a schematic cross-sectional view of a group III nitride semiconductor device according to an embodiment of the present invention; 3B is a schematic cross-sectional view of a group III nitride semiconductor device according to another embodiment of the present invention; 3C is a schematic cross-sectional view of a group III nitride semiconductor device according to still another embodiment of the present invention.

1:III族氮化物半導體元件半成品 1: Semi-finished products of group III nitride semiconductor devices

11:III族氮化物半導體結構 11: Group III nitride semiconductor structure

111:基板 111: Substrate

112:成核層 112: Nucleation layer

113:緩衝層 113: Buffer layer

114:通道層 114: channel layer

115:阻障層 115: Barrier layer

12:源極 12: Source

13:汲極 13: Drain

14:保護層 14: Protective layer

1141:二維電子氣層 1141: Two-dimensional electron gas layer

Claims (9)

一種III族氮化物半導體元件之歐姆接觸的製造方法，包括：提供未形成一源極(12)及一汲極(13)的一III族氮化物半導體結構(11')；於該III族氮化物半導體結構(11)的一阻障層(115)上形成一保護層(14')；在該保護層(14')形成具有圖案的一遮罩層(17)，以定義出該源極(12)及該汲極(13)的位置；使用氟化物氣體電漿對該III族氮化物半導體結構(11')的該保護層(14')進行蝕刻處理，其中該保護層(14')對應於該源極(12)與該汲極(13)的位置處的部分至少被蝕刻至該阻障層(115)的表面；使用該氟化物氣體電漿對該III族氮化物半導體結構(11)裸露的該阻障層(115)進行表面處理；以及移除該遮罩層(17)，並進行一退火處理；在該退火處理後，於該源極(12)與該汲極(13)的位置處植入金屬，以形成該源極(12)與該汲極(13)；以及對形成有該源極(12)與該汲極(13)的III族氮化物半導體結構(11)進行一快速退火處理；其中該保護層(14')為SiNx層或SiO2層，該保護層(14')的厚度為5至100奈米之間，該氟化物氣體電漿為CF4、SF6或C4F8電漿，該氟化物氣體電漿的功率為50至300瓦特之間，以及該氟化物氣體電漿的處理時間為5至300秒之間。 A method for manufacturing an ohmic contact of a group III nitride semiconductor device, comprising: providing a group III nitride semiconductor structure (11') without forming a source electrode (12) and a drain electrode (13); A protective layer (14') is formed on a barrier layer (115) of the compound semiconductor structure (11); a mask layer (17) with a pattern is formed on the protective layer (14') to define the source electrode (12) and the position of the drain electrode (13); use fluoride gas plasma to perform etching treatment on the protective layer (14') of the III-nitride semiconductor structure (11'), wherein the protective layer (14') ) corresponding to the position of the source (12) and the drain (13) is etched at least to the surface of the barrier layer (115); using the fluoride gas plasma for the III-nitride semiconductor structure (11) The exposed barrier layer (115) is subjected to surface treatment; and the mask layer (17) is removed, and an annealing treatment is performed; after the annealing treatment, the source electrode (12) and the drain electrode are Metal is implanted at the position of (13) to form the source (12) and the drain (13); and for the group III nitride semiconductor structure formed with the source (12) and the drain (13) (11) performing a rapid annealing treatment; wherein the protective layer (14') is a SiNx layer or a SiO2 layer, the thickness of the protective layer (14') is between 5 and 100 nm, the fluoride gas plasma For a CF4 , SF6 or C4F8 plasma, the power of the fluoride gas plasma is between 50 and 300 watts, and the treatment time of the fluoride gas plasma is between 5 and 300 seconds. 如請求項1所述之III族氮化物半導體元件之歐姆接觸的製造方法，其中該退火處理的溫度為攝氏450度至650度之間。 The method for manufacturing an ohmic contact of a group III nitride semiconductor device according to claim 1, wherein the temperature of the annealing treatment is between 450 degrees Celsius and 650 degrees Celsius. 如請求項1所述之III族氮化物半導體元件之歐姆接觸的製造方法，其中該快速退火處理的溫度為攝氏750度至850度之間。 The method for manufacturing an ohmic contact of a group III nitride semiconductor device according to claim 1, wherein the temperature of the rapid annealing treatment is between 750 degrees Celsius and 850 degrees Celsius. 如請求項1所述之III族氮化物半導體元件之歐姆接觸的製造方法，其中該阻障層(115)是AlGaN層，其化學組成式為AlxGa1-xN,0<=x<=40%，或者，該阻障層(115)是AlN層。 The method for manufacturing an ohmic contact of a group III nitride semiconductor device according to claim 1, wherein the barrier layer (115) is an AlGaN layer, and its chemical composition formula is Al x Ga 1-x N, 0<=x< =40%, or the barrier layer (115) is an AlN layer. 一種III族氮化物半導體元件半成品，係使用一如請求項1至4其中一項所述的III族氮化物半導體元件之歐姆接觸的製造方法所製造，包括：該III族氮化物半導體結構(11)；以及該保護層(14)、該源極(12)與該汲極(13)，形成於該III族氮化物半導體結構(11)的該阻障層(115)之上。 A semi-finished product of a group III nitride semiconductor element, which is manufactured by using the method for manufacturing an ohmic contact of a group III nitride semiconductor element according to one of claims 1 to 4, comprising: the group III nitride semiconductor structure (11 ); and the protective layer (14), the source electrode (12) and the drain electrode (13) are formed on the barrier layer (115) of the III-nitride semiconductor structure (11). 如請求項5所述之III族氮化物半導體元件半成品，其中該III族氮化物半導體元件的接觸電阻的電阻率為0.1至0.2歐姆．公釐之間。 The group III nitride semiconductor element semi-finished product as claimed in claim 5, wherein the resistivity of the contact resistance of the group III nitride semiconductor element is 0.1 to 0.2 ohms. between millimeters. 一種III族氮化物半導體元件，包括：一另一III族氮化物半導體元件半成品(1)，係將一如請求項5所述之III族氮化物半導體元件半成品(1)的部分該保護層(14)去除後所形成；以及一閘極(15)，該閘極(15)形成在該阻障層(115)之上，且於水平方向上，係位於該源極(12)與該汲極(13)之間。 A group III nitride semiconductor element, comprising: another semi-finished product (1) of a group III nitride semiconductor element, wherein a part of the protective layer ( 14) formed after removal; and a gate electrode (15), the gate electrode (15) is formed on the barrier layer (115), and in the horizontal direction, is located between the source electrode (12) and the drain electrode between poles (13). 如請求項7所述之III族氮化物半導體元件，更包括： 一介電層(88)，位於該閘極(15)之下與該阻障層(115)之上，以及位於該保護層(14)之上。 The group III nitride semiconductor device according to claim 7, further comprising: A dielectric layer (88) under the gate (15) and over the barrier layer (115) and over the protective layer (14). 如請求項7所述之III族氮化物半導體元件，其中所述之III族氮化物半導體元件半成品(1)的部分該阻障層(115)更被去除，以形成該阻障層(115)具有一凹槽的該另一III族氮化物半導體元件半成品(1)，且該閘極(15)位於該凹槽之上。 The group III nitride semiconductor device according to claim 7, wherein part of the barrier layer (115) of the semi-finished product (1) of the group III nitride semiconductor device is further removed to form the barrier layer (115) The other group III nitride semiconductor element semi-finished product (1) has a groove, and the gate electrode (15) is located on the groove.
TW110120474A 2021-06-04 2021-06-04 A kind of ohmic contact manufacturing method of group III nitride semiconductor element TWI762346B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW110120474A TWI762346B (en) 2021-06-04 2021-06-04 A kind of ohmic contact manufacturing method of group III nitride semiconductor element
CN202210049485.8A CN115440591A (en) 2021-06-04 2022-01-17 Method for manufacturing ohmic contact of group III nitride semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW110120474A TWI762346B (en) 2021-06-04 2021-06-04 A kind of ohmic contact manufacturing method of group III nitride semiconductor element

Publications (2)

Publication Number Publication Date
TWI762346B true TWI762346B (en) 2022-04-21
TW202249092A TW202249092A (en) 2022-12-16

Family

ID=82199068

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110120474A TWI762346B (en) 2021-06-04 2021-06-04 A kind of ohmic contact manufacturing method of group III nitride semiconductor element

Country Status (2)

Country Link
CN (1) CN115440591A (en)
TW (1) TWI762346B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200525760A (en) * 2004-01-16 2005-08-01 Cree Inc Nitride-based transistors with a protective layer and a low-damage recess and methods of fabrication thereof
TW201036156A (en) * 2009-03-31 2010-10-01 Sanken Electric Co Ltd Semiconductor device and method for manufacturing the same
TW201442230A (en) * 2013-02-28 2014-11-01 Power Integrations Inc Heterostructure power transistor and method of fabricating a heterostructure semiconductor device
CN105074876A (en) * 2013-03-19 2015-11-18 夏普株式会社 Nitride semiconductor device and method for manufacturing nitride semiconductor device
CN107230617A (en) * 2016-03-25 2017-10-03 北京大学 The preparation method of gallium nitride semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200525760A (en) * 2004-01-16 2005-08-01 Cree Inc Nitride-based transistors with a protective layer and a low-damage recess and methods of fabrication thereof
TW201036156A (en) * 2009-03-31 2010-10-01 Sanken Electric Co Ltd Semiconductor device and method for manufacturing the same
TW201442230A (en) * 2013-02-28 2014-11-01 Power Integrations Inc Heterostructure power transistor and method of fabricating a heterostructure semiconductor device
CN105074876A (en) * 2013-03-19 2015-11-18 夏普株式会社 Nitride semiconductor device and method for manufacturing nitride semiconductor device
CN107230617A (en) * 2016-03-25 2017-10-03 北京大学 The preparation method of gallium nitride semiconductor device

Also Published As

Publication number Publication date
TW202249092A (en) 2022-12-16
CN115440591A (en) 2022-12-06

Similar Documents

Publication Publication Date Title
CN110190116B (en) High-threshold-voltage normally-off high-electron-mobility transistor and preparation method thereof
Lee et al. 245-GHz InAlN/GaN HEMTs with oxygen plasma treatment
CN103681835B (en) Heterostructure transistors with multiple gate dielectric layers
CN101794815B (en) Compound semiconductor device and manufacturing method thereof
TWI594431B (en) Compound semiconductor device and method of manufacturing the same
US10770556B2 (en) Fluorinated graphene passivated AlGaN/GaN-based HEMT device and manufacturing method
JP2016139781A (en) Enhancement high electron mobility transistor and method of manufacturing the same
TW201417280A (en) Compound semiconductor device and method of manufacturing the same
CN104201104A (en) Manufacturing method for gallium nitride-based enhanced device
CN102651385A (en) Method of producing semiconductor device and semiconductor device
CN114899227A (en) Enhanced gallium nitride-based transistor and preparation method thereof
CN110429127B (en) Gallium nitride transistor structure and preparation method thereof
CN111584628B (en) Enhanced GaN HEMT device and preparation method thereof
JP5379391B2 (en) Semiconductor device comprising gallium nitride compound semiconductor and method for manufacturing the same
CN102646705A (en) Metal insulated semi-conductor (MIS) grid GaN base enhancing high electro mobility transistor (HEMT) device and manufacture method
CN109742144B (en) Groove gate enhanced MISHEMT device and manufacturing method thereof
CN116092935A (en) Manufacturing method of AlGaN/GaN HEMT device
TWI762346B (en) A kind of ohmic contact manufacturing method of group III nitride semiconductor element
TWI779612B (en) Enhancement-mode III-V semiconductor device with good lattice matching and method of making the same
KR101291148B1 (en) N-polar Nitride semiconductor device and method for manufacturing thereof
KR101985897B1 (en) Method of manufacturing high-electron-mobility transistor with high linearlity and high power
KR101952176B1 (en) Enhancement nitride semiconductor device and method for manufacturing the same
CN108695156B (en) Method for improving III-nitride MIS-HEMT ohmic contact and MIS-HEMT device
JP5648307B2 (en) Vertical AlGaN / GaN-HEMT and manufacturing method thereof
CN108695383B (en) Method for realizing high-frequency MIS-HEMT and MIS-HEMT device