TWI759817B

TWI759817B - Simulation system for soc-level power integrity and method thereof

Info

Publication number: TWI759817B
Application number: TW109127148A
Authority: TW
Inventors: 高小芳
Original assignee: 大陸商昆山吉崴微電子科技有限公司
Priority date: 2020-08-11
Filing date: 2020-08-11
Publication date: 2022-04-01
Also published as: TW202207071A

Abstract

A simulation system for SoC-level power integrity is provided. A nodal current profile of each standard cell is computed based on a gate-level netlist and a workload of each core block and time delay and a current profile of each standard cell with a load capacitor. A current profile of each core power bump is generated based on the correspondence between the standard cells and the core power bumps. A current profile of each I/O power bump is computed based on data activity and current step response of each I/O buffer and electrical connection relationship between the I/O power bumps and the I/O buffers. A power delivery network is obtained based on the current profiles of each core power bump and each I/O power bump. Therefore, the technical effects of an accurate simulation result and a fast simulation speed can be achieved.

Description

系統單晶片級電源完整性模擬系統及其方法System-on-wafer-level power integrity simulation system and method

本發明涉及一種電源完整性模擬系統及其方法，特別是系統單晶片級電源完整性模擬系統及其方法。The invention relates to a power integrity simulation system and a method thereof, in particular to a system single wafer level power integrity simulation system and a method thereof.

電源完整性模擬是當前與未來系統單晶片設計的瓶頸，它直接影響系統單晶片（System on a Chip，SoC）的性能。由於以下兩個當前的因素，使得電源完整性模擬仍然是一個挑戰。Power integrity simulation is the bottleneck of current and future system-on-a-chip designs, and it directly affects System on a Chip (SoC) performance. Power integrity simulation remains a challenge due to two current factors.

第一個因素為與電源完整性相關的所有模擬都需要在完整的系統單晶片環境中進行。商業使用的著重於積體電路之模擬程式（SPICE）因受限於其模擬能力而無法處理系統單晶片級電源完整性模擬，而當前一般的系統單晶片中標準單元（standard cell）的數量超過一千萬個，使得其他現有模擬工具（例如：Redhawk）進行系統單晶片級電源完整性模擬時模擬時間非常長，通常需要一週的時間。因此，傳統的電源完整性模擬方法是將系統單晶片中核心區域的電源完整性模擬由Redhawk工具進行，系統單晶片中輸入輸出區域的電源完整性模擬由SPICE進行，而核心區域與輸入輸出區域之間的交互作用因模擬器容量問題被忽略，然而，Redhawk工具或SPICE沒有足夠的能力來處理完整的系統單晶片環境中的電源完整性模擬。此外，使用SPICE進行輸入輸出區域的電源完整性模擬時，由於SPICE係對電流曲線進行短時間的模擬，然後以重複進行的方式滿足長時間的模擬，但此種模擬方式是不精確的。The first factor is that all simulations related to power integrity need to be performed in a full system-on-chip environment. Commercially used simulation programs focused on integrated circuits (SPICE) cannot handle SoC-level power integrity simulation due to their limited simulation capabilities, and the number of standard cells in a typical SoC is more than Ten million makes other existing simulation tools (eg, Redhawk) very long simulation times for SoC-level power integrity simulations, typically a week. Therefore, the traditional power integrity simulation method is that the power integrity simulation of the core area in the SoC is performed by the Redhawk tool, the power integrity simulation of the input and output areas in the SoC is performed by SPICE, and the core area and the input and output areas are simulated by SPICE. The interaction between them is ignored due to simulator capacity issues, however, Redhawk tools or SPICE are not powerful enough to handle power integrity simulation in a full SoC environment. In addition, when using SPICE to simulate the power integrity of the input and output areas, because SPICE simulates the current curve for a short time, and then repeats it to meet the long-term simulation, but this simulation method is inaccurate.

第二個因素為電源完整性與電源傳輸噪聲（Power Delivery Noise）很大程度上取決於系統單晶片的工作負載（workload）（即系統單晶片的應用環境）。因此，進行電源完整性模擬時應考慮數千種應用情境，以了解電源傳輸噪聲的限制及其對工作負載的統計信息，從而使設計人員能夠專注對於特定的工作負載進行優化設計。然而，不同的工作負載將導致系統單晶片中的閘極具有不同的活動（activity），且對應連接該些標準單元的每一核心電源凸塊具有不同的電流曲線，使得在傳統系統單晶片級電源完整性模擬方法存在為了評估不同工作負載的電源完整性所造成電流曲線的產生非常耗時的問題。The second factor is that power integrity and power delivery noise (Power Delivery Noise) largely depend on the workload of the SoC (ie, the application environment of the SoC). Therefore, thousands of application scenarios should be considered when conducting power integrity simulations to understand the limits of power delivery noise and its statistics on the workload, allowing the designer to focus on optimizing the design for a specific workload. However, different workloads will result in different activities of the gates in the SoC, and different current curves corresponding to each core power bump connected to the standard cells, so that in conventional SoCs the gates have different activities. The power integrity simulation method suffers from the problem of time-consuming generation of current curves in order to evaluate the power integrity of different workloads.

綜上所述，可知先前技術中存在使用著重於積體電路之模擬程式進行電源完整性模擬所存在不精確的問題以及為了評估不同工作負載的電源完整性所造成電流曲線的產生非常耗時的問題，因此，實有必要提出改進的技術手段，來解決此一問題。To sum up, it can be seen that in the prior art, there are inaccurate problems in power integrity simulation using simulation programs focusing on integrated circuits, and the generation of current curves for evaluating the power integrity of different workloads is very time-consuming. Therefore, it is necessary to propose improved technical means to solve this problem.

為解決上述先前技術所存在的問題，本發明揭露一種系統單晶片級電源完整性模擬系統及其方法。In order to solve the above-mentioned problems of the prior art, the present invention discloses a system-on-chip level power integrity simulation system and a method thereof.

首先，本發明揭露一種系統單晶片級電源完整性模擬系統，其包括：記憶體模組與處理器，記憶體模組用以儲存多個指令，處理器用以執行記憶體模組所儲存的該些指令，以對系統單晶片進行電源完整性模擬程序，其中，系統單晶片包括多個輸入輸出區域與多個核心區域。電源完整性模擬程序包括：獲取模組用以基於每一核心區域的閘級網表（gate level netlist）與工作負載取得每一核心區域中每一標準單元在二進制模式下的節點活動；分類模組用以基於每一核心區域的閘級網表與每一核心區域中定義的多個核心電源凸塊（core power bumps），對每一核心區域中的該些標準單元進行分類，以使每一核心區域中的該些標準單元對應到同一核心區域中不同的核心電源凸塊；單元電流模組用以基於每一標準單元的負載電容與標準單元庫（standard cell library），取得每一標準單元在其負載電容下的時間延遲（cell delay）與電流曲線；節點電流模組，連接獲取模組與單元電流模組，用以依據每一標準單元在二進制模式下的節點活動以及每一標準單元在其負載電容下的時間延遲與電流曲線計算出每一標準單元的節點電流曲線；核心電流模組，連接節點電流模組與分類模組，用以基於該些標準單元與該些核心電源凸塊的對應關係疊加每一標準單元的節點電流曲線，以產生每一核心電源凸塊的電流曲線；模擬模組，用以藉由著重於積體電路之模擬程式模擬出每一輸入輸出區域中每一輸入輸出緩衝器（I/O buffer）的電流步階響應；輸入輸出電流模組，連接模擬模組，用以基於每一輸入輸出緩衝器的資料活動與電流步階響應以及每一輸入輸出電源凸塊（I/O power bump）與該些輸入輸出緩衝器的電性連接關係計算出每一輸入輸出電源凸塊的電流曲線；以及電源模組，連接輸入輸出電流模組與核心電流模組，用以基於核心電流模組所產生的每一核心電源凸塊的電流曲線與輸入輸出電流模組所計算取得的每一輸入輸出電源凸塊的電流曲線取得電源傳輸網路（Power Delivery Network，PDN）。First, the present invention discloses a system-on-chip power integrity simulation system, which includes: a memory module and a processor, the memory module is used for storing a plurality of instructions, and the processor is used for executing the stored in the memory module. These instructions are used to perform a power integrity simulation program on a system-on-chip, wherein the system-on-chip includes a plurality of input and output regions and a plurality of core regions. The power integrity simulation program includes: the acquisition module is used to obtain the node activity of each standard cell in each core area in binary mode based on the gate level netlist and workload of each core area; the classification model The group is used to classify the standard cells in each core region based on the gate netlist of each core region and a plurality of core power bumps defined in each core region so that each The standard cells in a core area correspond to different core power bumps in the same core area; the cell current module is used to obtain each standard based on the load capacitance of each standard cell and the standard cell library (standard cell library) Cell delay and current curve of a cell under its load capacitance; node current module, connecting acquisition module and cell current module, for node activity in binary mode for each standard cell and for each standard The node current curve of each standard unit is calculated from the time delay and current curve of the unit under its load capacitance; the core current module, which connects the node current module and the classification module, is based on the standard units and the core power supplies The corresponding relationship of the bumps superimposes the node current curve of each standard cell to generate the current curve of each core power supply bump; the simulation module is used to simulate each input and output area by a simulation program focusing on integrated circuits The current step response of each input and output buffer (I/O buffer) in The electrical connection relationship between the input and output power bumps (I/O power bumps) and the input and output buffers calculates the current curve of each input and output power bumps; and the power module, which connects the input and output current modules and the core The current module is used to obtain the power transmission network (Power Transmission Network) based on the current curve of each core power bump generated by the core current module and the current curve of each input and output power bump calculated by the input and output current module. Delivery Network, PDN).

此外，本發明揭露一種系統單晶片級電源完整性模擬方法，用以對系統單晶片進行電源完整性模擬，系統單晶片包括多個輸入輸出區域與多個核心區域，系統單晶片級電源完整性模擬方法包括以下步驟：（a）基於每一核心區域的閘級網表與工作負載取得每一核心區域中每一標準單元在二進制模式下的節點活動；（b）基於每一核心區域的閘級網表與每一核心區域中定義的多個核心電源凸塊，對每一核心區域中的該些標準單元進行分類，以使每一核心區域中的該些標準單元對應到同一核心區域中不同的核心電源凸塊；（c）基於每一標準單元的負載電容與標準單元庫，取得每一標準單元在其負載電容下的時間延遲與電流曲線；（d）依據每一標準單元在二進制模式下的節點活動以及每一標準單元在其負載電容下的時間延遲與電流曲線計算出每一標準單元的節點電流曲線；（e）基於該些標準單元與該些核心電源凸塊的對應關係疊加每一標準單元的節點電流曲線，以產生每一核心電源凸塊的電流曲線；（f）藉由著重於積體電路之模擬程式模擬每一輸入輸出區域中每一輸入輸出緩衝器的電流步階響應；（g）基於每一輸入輸出緩衝器的資料活動與電流步階響應以及每一輸入輸出電源凸塊與該些輸入輸出緩衝器的電性連接關係計算出每一輸入輸出電源凸塊的電流曲線；以及（h）基於步驟（e）所產生的每一核心電源凸塊的電流曲線以及步驟（g）所計算取得的每一輸入輸出電源凸塊的電流曲線取得電源傳輸網路。In addition, the present invention discloses a SoC-level power integrity simulation method for performing power integrity simulation on a SoC, where the SoC includes a plurality of input and output areas and a plurality of core areas, and the SoC-level power integrity The simulation method includes the following steps: (a) based on the gate level netlist and workload of each core region to obtain the node activity of each standard cell in each core region in binary mode; (b) based on the gate level of each core region Level netlist and a plurality of core power bumps defined in each core area, classify the standard cells in each core area, so that the standard cells in each core area correspond to the same core area Different core power bumps; (c) based on the load capacitance of each standard cell and the standard cell library, obtain the time delay and current curve of each standard cell under its load capacitance; (d) according to each standard cell in binary node activity in the mode and the time delay and current curve of each standard cell under its load capacitance to calculate the node current curve of each standard cell; (e) based on the correspondence between the standard cells and the core power bumps Superimpose the node current curve of each standard cell to generate the current curve of each core power bump; (f) simulate the current of each I/O buffer in each I/O area by a simulation program focusing on integrated circuits Step response; (g) calculating each input and output power bump based on the data activity and current step response of each input and output buffer and the electrical connection relationship between each input and output power bump and the input and output buffers and (h) obtaining the power delivery network based on the current curve of each core power bump generated in step (e) and the current curve of each input and output power bump calculated in step (g) .

本發明所揭露之系統與方法如上，與先前技術的差異在於本發明是透過基於每一核心區域的閘級網表與工作負載以及每一標準單元在其負載電容下的時間延遲與電流曲線計算出每一標準單元的節點電流曲線；基於該些標準單元與該些核心電源凸塊的對應關係產生每一核心電源凸塊的電流曲線；基於每一輸入輸出緩衝器的資料活動與電流步階響應以及每一輸入輸出電源凸塊與該些輸入輸出緩衝器的電性連接關係計算出每一輸入輸出電源凸塊的電流曲線；以及基於每一核心電源凸塊與每一輸入輸出電源凸塊的電流曲線取得電源傳輸網路。The system and method disclosed in the present invention are as above, and the difference from the prior art is that the present invention calculates the time delay and current curve based on the gate level netlist and workload of each core region and the load capacitance of each standard cell. Generate the node current curve of each standard cell; generate the current curve of each core power bump based on the corresponding relationship between the standard cells and the core power bumps; based on the data activity and current step of each input and output buffer Calculating a current curve of each I/O power bump in response to the electrical connection relationship between each I/O power bump and the I/O buffers; and based on each core power bump and each I/O power bump The current curve of the power delivery network is obtained.

透過上述的技術手段，本發明可達到模擬結果精確且模擬速度快之技術功效。Through the above technical means, the present invention can achieve the technical effects of accurate simulation results and fast simulation speed.

以下將配合圖式及實施例來詳細說明本發明之實施方式，藉此對本發明如何應用技術手段來解決技術問題並達成技術功效的實現過程能充分理解並據以實施。The embodiments of the present invention will be described in detail below in conjunction with the drawings and examples, so as to fully understand and implement the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects.

請先參閱「第1A圖」與「第1B圖」，「第1A圖」為本發明系統單晶片級電源完整性模擬系統之一實施例元件示意圖，「第1B圖」為本發明系統單晶片級電源完整性模擬系統之一實施例系統架構圖。在本實施例中，系統單晶片級電源完整性模擬系統100可包括但不限於一個或多個處理器101、一個或多個記憶體模組102、匯流排103等硬體元件，其中，匯流排103可以連接不同的硬體元件。透過所包括之多個硬體元件，系統單晶片級電源完整性模擬系統100可應用於計算裝置，以執行對應的軟體或應用程式。Please refer to "Fig. 1A" and "Fig. 1B" first, "Fig. 1A" is a schematic diagram of the components of an embodiment of the system-on-chip power integrity simulation system of the present invention, and "Fig. 1B" is the system-on-chip of the present invention A system architecture diagram of an embodiment of a high-level power integrity simulation system. In this embodiment, the SoC level power integrity simulation system 100 may include, but is not limited to, one or more processors 101 , one or more memory modules 102 , bus bars 103 and other hardware components, wherein the bus Row 103 may connect different hardware components. Through the included hardware components, the system-on-chip power integrity simulation system 100 can be applied to a computing device to execute corresponding software or applications.

其中，匯流排103可包括一種或多個類型，例如包括資料匯流排（data bus）、位址匯流排（address bus）、控制匯流排（control bus）、擴充功能匯流排（expansion bus）與/或局域匯流排（local bus）等類型的匯流排。計算設備的匯流排包括但不限於並列的工業標準架構（ISA）匯流排、周邊元件互連（PCI）匯流排、視頻電子標準協會（VESA）局域匯流排、串列的通用序列匯流排（USB）、快速周邊元件互連（PCI-E）匯流排等。The bus 103 may include one or more types, such as data bus, address bus, control bus, expansion bus and/or Or a type of bus such as a local bus. Busbars for computing devices include, but are not limited to, Side-by-Side Industry Standard Architecture (ISA) busbars, Peripheral Component Interconnect (PCI) busbars, Video Electronics Standards Association (VESA) Local Busbars, Serial Generic Serial Busbars ( USB), Peripheral Component Interconnect Express (PCI-E) bus, etc.

在本實施例中，處理器101可與匯流排103耦接。處理器101可包括暫存器（Register）組或暫存器空間，暫存器組或暫存器空間可以完全的被設置在處理晶片上，或全部或部分被設置在處理晶片外並經由專用電氣連接與/或經由匯流排103耦接至處理器101。其中，處理器101可為處理單元、微處理器或任何合適的處理元件。當系統單晶片級電源完整性模擬系統100包括多個處理器時，該些處理器可為相同或類似的處理器，且透過匯流排103耦接與通訊。處理器101可以解釋一連串的多個指令以進行特定的運算或操作，例如：數學運算、邏輯運算、資料比對、複製/移動資料等，藉以執行各種應用程式、模組與/或元件。In this embodiment, the processor 101 may be coupled to the bus bar 103 . The processor 101 may include a register bank or register space, and the register bank or register space may be provided entirely on the processing wafer, or wholly or partially provided outside the processing wafer and via dedicated Electrically connected and/or coupled to processor 101 via bus bar 103 . Here, the processor 101 may be a processing unit, a microprocessor or any suitable processing element. When the SoC level power integrity simulation system 100 includes multiple processors, the processors may be the same or similar processors and are coupled and communicated through the bus bar 103 . The processor 101 can interpret a series of multiple instructions to perform specific operations or operations, such as mathematical operations, logical operations, data comparison, copy/move data, etc., to execute various applications, modules and/or components.

此外，處理器101可與晶片組耦接或透過匯流排103與晶片組電性連接。其中，晶片組是由一個或多個積體電路（IC）組成，包括記憶體控制器以及周邊輸出入（I/O）控制器，也就是說，記憶體控制器以及周邊輸出入控制器可以包括在一個積體電路內，也可以使用兩個或更多的積體電路實現。晶片組通常提供了輸出入和記憶體管理功能、以及提供多個通用及/或專用暫存器、計時器等，其中，上述之通用及/或專用暫存器與計時器可以讓耦接或電性連接至晶片組的一個或多個處理器101存取或使用。In addition, the processor 101 can be coupled to the chip set or electrically connected to the chip set through the bus bar 103 . Among them, the chipset is composed of one or more integrated circuits (ICs), including a memory controller and a peripheral input/output (I/O) controller, that is to say, the memory controller and the peripheral I/O controller can be Included in one integrated circuit, it can also be implemented using two or more integrated circuits. Chip sets usually provide I/O and memory management functions, and provide a plurality of general-purpose and/or special-purpose registers, timers, etc., wherein the above-mentioned general-purpose and/or special-purpose registers and timers can be coupled or One or more processors 101 electrically connected to the chipset are accessed or used.

另外，處理器101也可透過記憶體控制器存取安裝於系統單晶片級電源完整性模擬系統100上的記憶體模組102與大容量儲存區中的資料。上述之記憶體模組102包括任何類型的揮發性記憶體（volatile memory）與/或非揮發性（non-volatile memory, NVRAM）記憶體，例如：靜態隨機存取記憶體（SRAM）、動態隨機存取記憶體（DRAM）、快閃記憶體（Flash）、唯讀記憶體（ROM）等。上述之大容量儲存區可以包括任何類型的儲存裝置或儲存媒體，例如：硬碟機、光碟片、隨身碟（快閃記憶體）、記憶卡（memory card）、固態硬碟（Solid State Disk, SSD）或任何其他儲存裝置等。也就是說，記憶體控制器可以存取靜態隨機存取記憶體、動態隨機存取記憶體、快閃記憶體、硬碟機、固態硬碟中的資料。In addition, the processor 101 can also access the data in the memory module 102 and the mass storage area installed on the SoC level power integrity simulation system 100 through the memory controller. The above-mentioned memory module 102 includes any type of volatile memory (volatile memory) and/or non-volatile memory (NVRAM), such as static random access memory (SRAM), dynamic random access memory Access memory (DRAM), flash memory (Flash), read-only memory (ROM), etc. The above-mentioned large-capacity storage area can include any type of storage device or storage medium, such as: hard disk drive, optical disc, pen drive (flash memory), memory card (memory card), solid state hard disk (Solid State Disk, SSD) or any other storage device, etc. That is, the memory controller can access data in static random access memory, dynamic random access memory, flash memory, hard disk drive, and solid state hard disk.

再者，處理器101也可透過周邊輸出入控制器經由匯流排103與周邊輸出裝置、周邊輸入裝置、通訊介面與GPS接收器等周邊裝置或介面連接並通訊。周邊輸入裝置可以是任何類型的輸入裝置，例如：鍵盤、滑鼠、軌跡球、觸控板、搖桿等，周邊輸出裝置可以是任何類型的輸出裝置，例如：顯示器、印表機等，周邊輸入裝置與周邊輸出裝置也可以是同一裝置，例如觸控螢幕等。通訊介面可以包括無線通訊介面及/或有線通訊介面，無線通訊介面可以包括支援Wi-Fi、Zigbee等無線區域網路、藍牙、紅外線、近場通訊（NFC）、3G/4G/5G等行動通訊網路或其他無線資料傳輸協定的介面，有線通訊介面可為乙太網路裝置、非同步傳輸模式（ATM）裝置、DSL數據機、纜線（Cable）數據機等。處理器101可週期性地輪詢（polling）各種周邊裝置與介面，使得系統單晶片級電源完整性模擬系統100能夠透過各種周邊裝置與介面進行資料的輸入與輸出。Furthermore, the processor 101 can also connect and communicate with peripheral devices or interfaces such as peripheral output devices, peripheral input devices, communication interfaces, and GPS receivers through the peripheral I/O controller via the bus bar 103 . The peripheral input device can be any type of input device, such as: keyboard, mouse, trackball, touchpad, joystick, etc. The peripheral output device can be any type of output device, such as: monitor, printer, etc. The input device and the peripheral output device can also be the same device, such as a touch screen. The communication interface may include a wireless communication interface and/or a wired communication interface, and the wireless communication interface may include a wireless local area network such as Wi-Fi, Zigbee, Bluetooth, infrared, near field communication (NFC), 3G/4G/5G and other mobile communication networks The interface of the wireless data transmission protocol or other wireless data transmission protocol, the wired communication interface can be an Ethernet network device, an asynchronous transfer mode (ATM) device, a DSL modem, a cable modem, etc. The processor 101 can periodically poll various peripheral devices and interfaces, so that the SoC level power integrity simulation system 100 can input and output data through various peripheral devices and interfaces.

如「第1B圖」所示，系統單晶片級電源完整性模擬系統100含有獲取模組110、分類模組120、單元電流模組130、節點電流模組140、核心電流模組150、模擬模組160、輸入輸出電流模組170與電源模組180，節點電流模組140可連接獲取模組110與單元電流模組130，核心電流模組150可連接節點電流模組140與分類模組120，輸入輸出電流模組170可連接模擬模組160，電源模組180可連接輸入輸出電流模組170與核心電流模組150。其中，獲取模組110、分類模組120、單元電流模組130、節點電流模組140、核心電流模組150、模擬模組160、輸入輸出電流模組170與電源模組180通常是在處理器101執行被載入記憶體模組102之特定程式後產生，或是包括在處理器101中。在實際實施中，系統單晶片級電源完整性模擬系統100可應用但不限於平板電腦、桌上型電腦或筆記型電腦。As shown in "FIG. 1B", the SoC-level power integrity simulation system 100 includes an acquisition module 110, a classification module 120, a unit current module 130, a node current module 140, a core current module 150, and a simulation module The group 160 , the input and output current module 170 and the power module 180 , the node current module 140 can be connected to the acquisition module 110 and the unit current module 130 , and the core current module 150 can be connected to the node current module 140 and the classification module 120 , the input and output current module 170 can be connected to the analog module 160 , and the power module 180 can be connected to the input and output current module 170 and the core current module 150 . Among them, the acquisition module 110 , the classification module 120 , the unit current module 130 , the node current module 140 , the core current module 150 , the simulation module 160 , the input and output current module 170 and the power module 180 are usually processed The processor 101 is generated after executing a specific program loaded into the memory module 102 , or is included in the processor 101 . In practical implementation, the SoC level power integrity simulation system 100 can be applied to but not limited to tablet computers, desktop computers or notebook computers.

接著，請參閱「第2圖」，「第2圖」為「第1B圖」的系統單晶片級電源完整性模擬系統執行電源完整性模擬程序之一實施例方法流程圖。在本實施例中，電源完整性模擬程序可用以對系統單晶片300進行電源完整性模擬，其中，系統單晶片300可包括多個輸入輸出區域310與多個核心區域320（如「第3圖」所示，「第3圖」為系統單晶片的一實施例示意圖），每一輸入輸出區域310可包括至少一輸入輸出電源凸塊10與多個輸入輸出緩衝器（未繪製），每一輸入輸出電源凸塊10供電予與其對應電性連接的輸入輸出緩衝器；每一核心區域320可包括至少一核心電源凸塊20與多個標準單元（未繪製），每一核心電源凸塊20供電予與其對應電性連接的標準單元，與同一核心電源凸塊20電性連接的該些標準單元以串聯或陣列方式連接；其中，與同一核心電源凸塊20電性連接的該些標準單元分成若干級，第B級標準單元的輸出端與第（B +1）級標準單元的輸入端連接，B為正整數，大於或等於1且小於或等於與同一核心電源凸塊20電性連接的標準單元的數量；當與同一核心電源凸塊20電性連接的該些標準單元以陣列方式連接時，第X行第Y列的標準單元為第

級標準單元，X與Y皆為正整數且大於或等於1，（X×Y）小於或等於與同一核心電源凸塊20電性連接的標準單元的數量。 Next, please refer to "FIG. 2", "FIG. 2" is a flowchart of an embodiment of a method for executing a power integrity simulation program by the system-on-chip level power integrity simulation system of "FIG. 1B". In this embodiment, the power integrity simulation program can be used to perform power integrity simulation on the SoC 300, wherein the SoC 300 can include a plurality of input and output areas 310 and a plurality of core areas 320 (as shown in FIG. 3 ). ”, “FIG. 3” is a schematic diagram of an embodiment of a system-on-chip), each I/O area 310 may include at least one I/O power bump 10 and a plurality of I/O buffers (not shown), each The input and output power bumps 10 supply power to the input and output buffers electrically connected to them; each core area 320 may include at least one core power bump 20 and a plurality of standard cells (not shown), each core power bump 20 Power is supplied to the standard cells that are electrically connected to them, and the standard cells that are electrically connected to the same core power bump 20 are connected in series or in an array; wherein, the standard cells that are electrically connected to the same core power bump 20 Divided into several stages, the output end of the B-th standard unit is connected to the input end of the (B+1)-th standard unit, B is a positive integer, greater than or equal to 1 and less than or equal to the same core power supply bump 20 Electrically connected The number of standard cells; when the standard cells electrically connected to the same core power bump 20 are connected in an array, the standard cells in the Xth row and the Yth column are the

Level standard cells, X and Y are both positive integers and greater than or equal to 1, and (X×Y) is less than or equal to the number of standard cells electrically connected to the same core power bump 20 .

其中，每一標準單元可包括輸入針腳及輸出針腳且可對經由輸入針腳接收的信號進行處理以經由輸出針腳輸出信號；舉例而言，標準單元可為基本單元（諸如：與（AND）邏輯閘、或（OR）邏輯閘、或非（NOR）邏輯閘或反相器）、複雜單元（諸如：由或邏輯閘/與邏輯閘/反相器（OR/AND/INVERTER，OAI）所組成的複雜單元，或者由與邏輯閘/或邏輯閘/反相器（AND/OR/INVERTER，AOI）所組成的複雜單元）或者記憶元件（諸如：主-從雙穩態正反器或鎖存器）。Wherein, each standard cell may include input pins and output pins and may process signals received via the input pins to output signals via the output pins; for example, the standard cells may be basic cells such as AND (AND) logic gates , or (OR) logic gate, or not (NOR) logic gate or inverter), complex units (such as: composed of OR logic gate/AND logic gate/inverter (OR/AND/INVERTER, OAI) Complex cells, or complex cells consisting of AND/OR/INVERTER (AOI) or memory elements (such as master-slave flip-flops or latches) ).

請參閱「第1B圖」與「第2圖」，電源完整性模擬程序包括以下步驟：基於每一核心區域的閘級網表與工作負載取得每一核心區域中每一標準單元在二進制模式下的節點活動（步驟210）；基於每一核心區域的閘級網表與每一核心區域中定義的多個核心電源凸塊，對每一核心區域中的該些標準單元進行分類，以使每一核心區域中的該些標準單元對應到同一核心區域中不同的核心電源凸塊（步驟220）；基於每一標準單元的負載電容與標準單元庫，取得每一標準單元在其負載電容下的時間延遲與電流曲線（步驟230）；依據每一標準單元在二進制模式下的節點活動以及每一標準單元在其負載電容下的時間延遲與電流曲線計算出每一標準單元的節點電流曲線（步驟240）；基於該些標準單元與該些核心電源凸塊的對應關係疊加每一標準單元的節點電流曲線，以產生每一核心電源凸塊的電流曲線（步驟250）；藉由著重於積體電路之模擬程式模擬每一輸入輸出區域中每一輸入輸出緩衝器的電流步階響應（步驟260）；基於每一輸入輸出緩衝器的資料活動與電流步階響應以及每一輸入輸出電源凸塊與該些輸入輸出緩衝器的電性連接關係計算出每一輸入輸出電源凸塊的電流曲線（步驟270）；基於每一核心電源凸塊的電流曲線以及每一輸入輸出電源凸塊的電流曲線取得電源傳輸網路（步驟280）。Please refer to "Figure 1B" and "Figure 2", the power integrity simulation program includes the following steps: Based on the gate netlist and workload of each core region, each standard cell in each core region is obtained in binary mode. (step 210); based on the gate-level netlist of each core region and the plurality of core power bumps defined in each core region, the standard cells in each core region are classified so that each The standard cells in a core area correspond to different core power bumps in the same core area (step 220 ); based on the load capacitance of each standard cell and the standard cell library, obtain the load capacitance of each standard cell under its load capacitance time delay and current curve (step 230 ); calculating the node current curve of each standard cell according to the node activity of each standard cell in binary mode and the time delay and current curve of each standard cell under its load capacitance (step 230 ) 240); superimpose the node current curve of each standard cell based on the corresponding relationship between the standard cells and the core power bumps to generate the current curve of each core power bump (step 250); by focusing on the integrated The circuit simulator simulates the current step response of each I/O buffer in each I/O region (step 260); based on the data activity and current step response of each I/O buffer and each I/O power bump Calculate the current curve of each I/O power bump based on the electrical connection relationship with the I/O buffers (step 270 ); based on the current curve of each core power bump and the current curve of each I/O power bump Obtain the power delivery network (step 280).

在步驟210中，獲取模組110可基於每一核心區域320的閘級網表與工作負載取得每一核心區域320中每一標準單元在二進制模式下的節點活動。更詳細地說，獲取模組110可根據每一核心區域320的閘級網表與工作負載利用Verilog硬體描述語言（例如：ModelSim模擬工具、VCS模擬工具或NC-Sim模擬工具）進行暫存器傳輸級（register transfer level，RTL）設計，進而取得每一核心區域320中每一標準單元在二進制模式下的節點活動。舉例而言，請參閱「第4圖」，「第4圖」為某一核心區域的閘級網表的一實施例示意圖，在本實施例中，該核心區域320的閘級網表可包括標準單元50A、標準單元50B與標準單元50C，標準單元50A包括節點X，標準單元50B包括節點Y，標準單元50C包括節點Z，獲取模組110可基於該核心區域320的閘級網表與工作負載取得節點X的節點活動為“0110100…”，節點Y的節點活動為“0010110…”，節點Z的節點活動為“0010100…”。In step 210 , the obtaining module 110 may obtain the node activity of each standard cell in each core region 320 in binary mode based on the gate-level netlist and workload of each core region 320 . To be more specific, the acquisition module 110 may use the Verilog hardware description language (eg, ModelSim simulation tool, VCS simulation tool or NC-Sim simulation tool) to temporarily store the gate-level netlist and workload of each core region 320 A register transfer level (RTL) design is used to obtain the node activity of each standard cell in each core area 320 in binary mode. For example, please refer to "Fig. 4", "Fig. 4" is a schematic diagram of an embodiment of the gate-level netlist of a certain core region. In this embodiment, the gate-level netlist of the core region 320 may include Standard cell 50A, standard cell 50B and standard cell 50C, standard cell 50A includes node X, standard cell 50B includes node Y, standard cell 50C includes node Z, the acquisition module 110 can be based on the gate level netlist and work of the core area 320 The node activity of the load acquisition node X is "0110100...", the node activity of the node Y is "0010110...", and the node activity of the node Z is "0010100...".

在步驟220中，分類模組120可基於每一核心區域320的閘級網表與每一核心區域320中定義的多個核心電源凸塊20，對每一核心區域320中的該些標準單元進行分類，以使每一核心區域320中的該些標準單元對應到同一核心區域320中不同的核心電源凸塊20。更詳細地說，分類模組120可先基於每一核心區域320的閘級網表進行自動佈局與佈線（automatic placement and routing，APR），以取得每一核心區域320的平面佈置圖；接著，基於每一核心區域320的平面佈置圖利用專業軟體生成對應的網表文件，每一網表文件包括多個寄生電容；最後，基於每一網表文件取得每一核心電源凸塊20對應供電的標準單元，再對每一核心區域320中的該些標準單元進行分類，以使每一核心區域320中的該些標準單元對應到同一核心區域320中不同的核心電源凸塊20。舉例而言，分類模組120可基於每一核心區域320的平面佈置圖利用專業軟體STAR-RC進行帶寄生電容的網表文件的生成（即生成每一核心區域對應的網表文件），其中，每一網表文件的格式可為標準寄生交換格式（standard parasitic exchange format，SPEF），由於從每一網表文件可知每一核心區域320中該些標準單元的供電分屬於不同的核心電源凸塊20，因此，可對每一核心區域320中該些標準單元進行分類，以使每一核心區域320中的該些標準單元對應到同一核心區域320中不同的核心電源凸塊20。In step 220 , the classification module 120 may classify the standard cells in each core region 320 based on the gate-level netlist of each core region 320 and the plurality of core power bumps 20 defined in each core region 320 . Sorting is performed so that the standard cells in each core area 320 correspond to different core power bumps 20 in the same core area 320 . More specifically, the classification module 120 may first perform automatic placement and routing (APR) based on the gate-level netlist of each core area 320 to obtain a floor plan of each core area 320 ; then, Based on the floor plan of each core area 320, a corresponding netlist file is generated by professional software, and each netlist file includes a plurality of parasitic capacitances; finally, based on each netlist file, the corresponding power supply of each core power bump 20 is obtained. standard cells, and then classify the standard cells in each core area 320 so that the standard cells in each core area 320 correspond to different core power bumps 20 in the same core area 320 . For example, the classification module 120 can use the professional software STAR-RC to generate a netlist file with parasitic capacitance based on the floor plan of each core region 320 (ie, generate a netlist file corresponding to each core region), wherein , the format of each netlist file may be a standard parasitic exchange format (SPEF), since it can be known from each netlist file that the power supplies of the standard cells in each core area 320 belong to different core power sources Block 20, therefore, the standard cells in each core region 320 may be sorted such that the standard cells in each core region 320 correspond to different core power bumps 20 in the same core region 320.

在步驟230中，單元電流模組130可基於每一標準單元的負載電容與標準單元庫，取得每一標準單元在其負載電容下的時間延遲與電流曲線。其中，標準單元庫儲存有多個標準單元的資訊，例如：標準單元的名稱及功能、時序資訊（含時間延遲、電流曲線與轉換時間（transition time））、功率資訊與佈局資訊，轉換時間係為定義信號波形從其最終值的10%行走到90%所需的時間。In step 230, the cell current module 130 can obtain the time delay and current curve of each standard cell under its load capacitance based on the load capacitance of each standard cell and the standard cell library. Among them, the standard cell library stores the information of a plurality of standard cells, such as: the name and function of the standard cell, timing information (including time delay, current curve and transition time), power information and layout information. The transition time is Defines the time it takes for a signal waveform to travel from 10% to 90% of its final value.

更詳細地說，單元電流模組130可先基於標準單元庫取得每一標準單元的負載電容。對應到同一核心電源凸塊的該些標準單元中，當標準單元為第一級標準單元時，該標準單元的負載電容包括自身具有的金屬寄生電容；當某一標準單元為第N級標準單元（N為正整數，大於或等於2，且小於或等於對應到同一核心電源凸塊的該些標準單元的數量）時，該標準單元的負載電容包括自身具有的金屬寄生電容與下一級標準單元的閘極的電容。對應到同一核心電源凸塊的該些標準單元中，當標準單元為第一級標準單元時，單元電流模組130可根據標準單元庫與該標準單元的負載電容取得該標準單元的時間延遲、電流曲線與轉換時間；以及當某一標準單元為第N級標準單元時，單元電流模組130可將第（N-1）級標準單元的轉換時間作為該標準單元的輸入特性，並根據標準單元庫、第N級標準單元的負載電容與輸入特性取得第N級標準單元的時間延遲、電流曲線與轉換時間。In more detail, the cell current module 130 may first obtain the load capacitance of each standard cell based on the standard cell library. Among the standard cells corresponding to the same core power bump, when the standard cell is the first-level standard cell, the load capacitance of the standard cell includes its own metal parasitic capacitance; when a standard cell is the Nth-level standard cell (N is a positive integer, greater than or equal to 2, and less than or equal to the number of standard cells corresponding to the same core power bump), the load capacitance of the standard cell includes its own metal parasitic capacitance and the next-level standard cell. the gate capacitance. Among the standard cells corresponding to the same core power bump, when the standard cell is a first-level standard cell, the cell current module 130 can obtain the time delay of the standard cell according to the standard cell library and the load capacitance of the standard cell, current curve and conversion time; and when a certain standard cell is an Nth-level standard cell, the cell current module 130 can use the conversion time of the (N-1)th-level standard cell as the input characteristic of the standard cell, and according to the standard cell The cell library, load capacitance and input characteristics of the N-th standard cell obtain the time delay, current curve and switching time of the N-th standard cell.

在步驟240中，節點電流模組140可依據每一標準單元在二進制模式下的節點活動以及每一標準單元在其負載電容下的時間延遲與電流曲線計算出每一標準單元的節點電流曲線。舉例而言，請參閱「第4圖」，由於每一節點需在其節點活動自0到1的變化過程中才能自對應的核心電源凸塊取得電力，因此，節點X可依據其節點活動自0到1的變化過程、前一階段的時間延遲與在該轉換時間的電流曲線進行計算而取得對應的節點電流曲線（即節點X的節點電流曲線），而由於標準單元50A僅包括節點X，故標準單元50A的節點電流曲線等於節點X的節點電流曲線；節點Y可依據其節點活動自0到1的變化過程、前一階段的時間延遲與在該轉換時間的電流曲線進行計算而取得對應的節點電流曲線（即節點Y的節點電流曲線），而由於標準單元50B僅包括節點Y，故標準單元50B的節點電流曲線等於節點Y的節點電流曲線；節點Z可依據其節點活動自0到1的變化過程、其輸入驅動器（即X’與Y’）的時間延遲中最大的時間延遲以及在節點X與節點Y的轉換時間之最大的轉換時間中的電流曲線進行計算而取得對應的節點電流曲線（即節點Z的節點電流曲線），而由於標準單元50C僅包括節點Z，故標準單元50C的節點電流曲線等於節點Z的節點電流曲線。In step 240, the node current module 140 can calculate the node current curve of each standard cell according to the node activity of each standard cell in binary mode and the time delay and current curve of each standard cell under its load capacitance. For example, please refer to "Figure 4", since each node needs to obtain power from the corresponding core power bump when its node activity changes from 0 to 1, node X can automatically The change process from 0 to 1, the time delay of the previous stage and the current curve at this transition time are calculated to obtain the corresponding node current curve (that is, the node current curve of node X), and since the standard cell 50A only includes node X, Therefore, the node current curve of the standard cell 50A is equal to the node current curve of node X; the node Y can be calculated according to the change process of its node activity from 0 to 1, the time delay of the previous stage and the current curve at the transition time. The node current curve of node Y (that is, the node current curve of node Y), and since the standard cell 50B only includes node Y, the node current curve of the standard cell 50B is equal to the node current curve of node Y; node Z can be based on its node activity from 0 to The change process of 1, the maximum time delay among the time delays of its input drivers (ie X' and Y'), and the current curve in the maximum switching time between the switching times of node X and node Y are calculated to obtain the corresponding node. current curve (ie, node current curve of node Z), and since standard cell 50C includes only node Z, the node current curve of standard cell 50C is equal to the node current curve of node Z.

在步驟250中，核心電流模組150可基於該些標準單元與該些核心電源凸塊20的對應關係疊加每一標準單元的節點電流曲線，以產生每一核心電源凸塊20的電流曲線。換句話說，核心電流模組150可將對應連接到同一核心電源凸塊20的該些標準單元的節點電流曲線相加，以取得該核心電源凸塊20的電流曲線。In step 250 , the core current module 150 may superimpose the node current curve of each standard cell based on the corresponding relationship between the standard cells and the core power bumps 20 to generate the current curve of each core power bump 20 . In other words, the core current module 150 can add the node current curves corresponding to the standard cells connected to the same core power bump 20 to obtain the current curve of the core power bump 20 .

在步驟260中，模擬模組160可藉由SPICE模擬每一輸入輸出區域310中每一輸入輸出緩衝器的電流步階響應。更詳細地說，模擬模組160可藉由SPICE模擬出當每一輸入輸出緩衝器的資料輸入端所接收的資料由0改變為1（即資料上升邊緣）時其電流量測點的電流變化；以及當每一輸入輸出緩衝器的資料輸入端所接收的資料由1改變為0（即資料下降邊緣）時其電流量測點的電流變化；因此，模擬模組160可模擬出每一輸入輸出緩衝器的電流步階響應。換句話說，模擬模組160係可用以模擬出每一輸入輸出緩衝器在不同資料模型（pattern）條件下快速生成對應的電流曲線。In step 260 , the simulation module 160 can simulate the current step response of each I/O buffer in each I/O region 310 by using SPICE. More specifically, the simulation module 160 can use SPICE to simulate the current change of the current measurement point when the data received by the data input terminal of each input and output buffer changes from 0 to 1 (ie, the rising edge of the data). ; and when the data received by the data input terminal of each input and output buffer changes from 1 to 0 (ie, the data falling edge), the current change of its current measurement point; therefore, the simulation module 160 can simulate each input The current step response of the output buffer. In other words, the simulation module 160 can be used to simulate each input and output buffer to quickly generate corresponding current curves under different data patterns.

在步驟270中，輸入輸出電流模組170可基於每一輸入輸出緩衝器的資料活動與電流步階響應以及每一輸入輸出電源凸塊10與該些輸入輸出緩衝器的電性連接關係計算出每一輸入輸出電源凸塊10的電流曲線。更詳細地說，輸入輸出電流模組170可先基於每一輸入輸出緩衝器的資料活動與電流步階響應取得每一輸入輸出緩衝器的電流曲線；接著，基於與同一輸入輸出電源凸塊10電性連接的該/該些輸入輸出緩衝器的該/該些電流曲線計算出每一輸入輸出電源凸塊10的電流曲線。In step 270 , the I/O current module 170 may calculate a value based on the data activity and current step response of each I/O buffer and the electrical connection relationship between each I/O power bump 10 and the I/O buffers. The current curve of each input and output power bump 10 . More specifically, the I/O current module 170 can first obtain the current curve of each I/O buffer based on the data activity and current step response of each I/O buffer; then, based on the same I/O power bump 10 The current curve of each I/O power supply bump 10 is calculated from the current curve(s) of the electrically connected I/O buffers.

舉例而言，請參閱「第5圖」，「第5圖」為某一輸入輸出電源凸塊及其電性連接多個輸入輸出緩衝器的一實施例示意圖，在本實施例中，輸入輸出電源凸塊10與三個輸入輸出緩衝器（即輸入輸出緩衝器60A、輸入輸出緩衝器60B與輸入輸出緩衝器60C）電性連接（輸入輸出電源凸塊10供電予該些輸入輸出緩衝器）。每一輸入輸出緩衝器的資料輸入端可接收輸入資料串（例如：“10100101101”或“1100110001”）（即每一輸入輸出緩衝器具有其資料活動），對於每一輸入輸出緩衝器的輸入資料串（例如：“10100101101”或“1100110001”）中，若當前輸入資料與前一輸入資料比較為由0變化成1時，該輸入輸出緩衝器的電流量測點的電流變化為步階上升；若當前輸入資料與前一輸入資料比較為由1變化成0時，該輸入輸出緩衝器的電流量測點的電流變化為步階下降；若當前輸入資料與前一輸入資料比較為沒有變化（即當前輸入資料與前一輸入資料皆為0或1）時，該輸入輸出緩衝器的電流量測點沒有電流變化。因此，根據上述方法，可以快速生成每一輸入輸出緩衝器在其特定資料活動（即其接收特定輸入資料串）下的電流曲線。在本實施例中，輸入輸出電流模組170可將輸入輸出緩衝器60A、輸入輸出緩衝器60B與輸入輸出緩衝器60C分別在其特定資料活動下的電流曲線相加，以取得該輸入輸出電源凸塊10的電流曲線。For example, please refer to “FIG. 5”. “FIG. 5” is a schematic diagram of an input/output power bump and its electrical connection with a plurality of input/output buffers. In this embodiment, the input/output The power bump 10 is electrically connected to three input and output buffers (ie, the input and output buffer 60A, the input and output buffer 60B, and the input and output buffer 60C) (the input and output power bump 10 supplies power to these input and output buffers) . The data input terminal of each I/O buffer can receive an input data string (eg "10100101101" or "1100110001") (ie each I/O buffer has its data activity), for the input data of each I/O buffer In the string (for example: "10100101101" or "1100110001"), if the current input data compared with the previous input data changes from 0 to 1, the current change of the current measurement point of the input and output buffers is a step increase; If the current input data compared with the previous input data is changed from 1 to 0, the current change of the current measurement point of the input and output buffers is a step down; if the current input data is compared with the previous input data, there is no change ( That is, when the current input data and the previous input data are both 0 or 1), the current measurement point of the input and output buffers has no current change. Therefore, according to the above method, the current curve of each I/O buffer at its specific data activity (ie, it receives a specific input data string) can be quickly generated. In this embodiment, the I/O current module 170 can add the current curves of the I/O buffer 60A, I/O buffer 60B, and I/O buffer 60C respectively under their specific data activities to obtain the I/O power supply Current curve of bump 10.

在步驟280中，電源模組180可基於每一核心電源凸塊20的電流曲線以及每一輸入輸出電源凸塊10的電流曲線取得電源傳輸網路。更詳細地說，電源模組180可基於步驟250所產生的每一核心電源凸塊20的電流曲線以及步驟270所計算取得的每一入輸出電源凸塊10的電流曲線，採用Z參數或S參數格式取得電源傳輸網路。In step 280 , the power module 180 can obtain the power delivery network based on the current curve of each core power bump 20 and the current curve of each input and output power bump 10 . More specifically, the power module 180 may use the Z parameter or S based on the current curve of each core power bump 20 generated in step 250 and the current curve of each input/output power bump 10 calculated in step 270 . The parameter format obtains the power delivery network.

透過上述步驟，即可考慮不同的SoC應用場景（即不同工作負載）快速構建對應的每一核心電源凸塊20的電流曲線、每一入輸出電源凸塊10的電流曲線以及電源傳輸網路；具有從單一輸入輸出區域到整個SoC級別的可擴展性；且可利用基本單元或更高級別的層次單元（hierarchy cell）的粒度（granularity）調整模擬的速度與準確性，而具有自適應權衡（Adaptive tradeoff）。Through the above steps, the corresponding current curve of each core power bump 20 , the current curve of each input and output power bump 10 , and the power transmission network can be quickly constructed considering different SoC application scenarios (ie, different workloads). It is scalable from a single input and output area to the entire SoC level; and the speed and accuracy of the simulation can be adjusted using the granularity of the basic cell or higher-level hierarchical cells, with adaptive trade-offs ( Adaptive tradeoff).

綜上所述，可知本發明與先前技術之間的差異在於透過基於每一核心區域的閘級網表與工作負載以及每一標準單元在其負載電容下的時間延遲與電流曲線計算出每一標準單元的節點電流曲線；基於該些標準單元與該些核心電源凸塊的對應關係產生每一核心電源凸塊的電流曲線；基於每一輸入輸出緩衝器的資料活動與電流步階響應以及每一輸入輸出電源凸塊與該些輸入輸出緩衝器的電性連接關係計算出每一輸入輸出電源凸塊的電流曲線；以及基於每一核心電源凸塊與每一輸入輸出電源凸塊的電流曲線取得電源傳輸網路，藉由此一技術手段可達到模擬結果精確且模擬速度快之技術功效。From the above, it can be seen that the difference between the present invention and the prior art lies in the calculation of each standard cell based on the gate netlist and workload of each core region and the time delay and current curve of each standard cell under its load capacitance. The node current curve of standard cells; the current curve of each core power bump is generated based on the corresponding relationship between the standard cells and the core power bumps; based on the data activity and current step response of each input and output buffer and each Calculate the current curve of each input and output power bump based on the electrical connection relationship between an input and output power bump and the input and output buffers; and based on the current curve of each core power bump and each input and output power bump The power transmission network is obtained, and the technical effect of accurate simulation results and fast simulation speed can be achieved by this technical means.

雖然本發明以前述之實施例揭露如上，然其並非用以限定本發明，任何熟習相像技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準。Although the present invention is disclosed above by the aforementioned embodiments, it is not intended to limit the present invention. Anyone who is familiar with the similar arts can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of patent protection shall be determined by the scope of the patent application attached to this specification.

10:輸入輸出電源凸塊 20:核心電源凸塊 50A,50B,50C: 標準單元 60A,60B,60C:輸入輸出緩衝器 100:系統單晶片級電源完整性模擬系統 101:處理器 102:記憶體模組 103:匯流排 110:獲取模組 120:分類模組 130:單元電流模組 140:節點電流模組 150:核心電流模組 160:模擬模組 170:輸入輸出電流模組 180:電源模組 300:系統單晶片 310:輸入輸出區域 320:核心區域 X,Y,Z:節點 X’,Y’,Z’:輸入驅動器步驟210:基於每一核心區域的閘級網表與工作負載取得每一核心區域中每一標準單元在二進制模式下的節點活動步驟220:基於每一核心區域的閘級網表與每一核心區域中定義的多個核心電源凸塊，對每一核心區域中的該些標準單元進行分類，以使每一核心區域中的該些標準單元對應到同一核心區域中不同的核心電源凸塊步驟230:基於每一標準單元的負載電容與標準單元庫，取得每一標準單元在其負載電容下的時間延遲與電流曲線步驟240:依據每一標準單元在二進制模式下的節點活動以及每一標準單元在其負載電容下的時間延遲與電流曲線計算出每一標準單元的節點電流曲線步驟250:基於該些標準單元與該些核心電源凸塊的對應關係疊加每一標準單元的節點電流曲線，以產生每一核心電源凸塊的電流曲線步驟260:藉由著重於積體電路之模擬程式模擬每一輸入輸出區域中每一輸入輸出緩衝器的電流步階響應步驟270:基於每一輸入輸出緩衝器的資料活動與電流步階響應以及每一輸入輸出電源凸塊與該些輸入輸出緩衝器的電性連接關係計算出每一輸入輸出電源凸塊的電流曲線步驟280:基於每一核心電源凸塊的電流曲線以及每一輸入輸出電源凸塊的電流曲線取得電源傳輸網路 10: Input and output power bumps 20: Core Power Bumps 50A, 50B, 50C: Standard Unit 60A, 60B, 60C: Input and output buffers 100: System-on-Wafer Level Power Integrity Simulation System 101: Processor 102: Memory module 103: Busbar 110: Get Mods 120: Classification module 130: Unit current module 140: Node Current Module 150: Core current module 160: Simulation Module 170: Input and output current module 180: Power Module 300: SoC 310: Input and output area 320: Core Area X,Y,Z: Node X', Y', Z': input driver Step 210: Obtain the node activity of each standard cell in each core area in binary mode based on the gate-level netlist and workload of each core area Step 220: Classify the standard cells in each core region based on the gate-level netlist of each core region and the plurality of core power bumps defined in each core region, so that the These standard cells correspond to different core power bumps in the same core area Step 230: Based on the load capacitance of each standard cell and the standard cell library, obtain the time delay and current curve of each standard cell under its load capacitance Step 240: Calculate the node current curve of each standard cell according to the node activity of each standard cell in the binary mode and the time delay and current curve of each standard cell under its load capacitance Step 250: Superimpose the node current curve of each standard cell based on the corresponding relationship between the standard cells and the core power bumps to generate the current curve of each core power bump Step 260: Simulate the current step response of each I/O buffer in each I/O region by an IC-focused simulation program Step 270: Calculate the current curve of each I/O power bump based on the data activity and current step response of each I/O buffer and the electrical connection relationship between each I/O power bump and the I/O buffers Step 280: Obtain a power transmission network based on the current curve of each core power bump and the current curve of each input and output power bump

第1A圖為本發明系統單晶片級電源完整性模擬系統之一實施例元件示意圖。第1B圖為本發明系統單晶片級電源完整性模擬系統之一實施例系統架構圖。第2圖為第1B圖的系統單晶片級電源完整性模擬系統執行電源完整性模擬程序之一實施例方法流程圖。第3圖為系統單晶片的一實施例示意圖。第4圖為某一核心區域的閘級網表的一實施例示意圖。第5圖為某一輸入輸出電源凸塊及其電性連接多個輸入輸出緩衝器的一實施例示意圖。 FIG. 1A is a schematic diagram of the components of an embodiment of the single-chip level power integrity simulation system of the system of the present invention. FIG. 1B is a system architecture diagram of an embodiment of a single-chip-level power integrity simulation system of the present invention. FIG. 2 is a flowchart of an embodiment of a method for executing a power integrity simulation program in the system-on-wafer-level power integrity simulation system of FIG. 1B . FIG. 3 is a schematic diagram of an embodiment of a system-on-chip. FIG. 4 is a schematic diagram of an embodiment of a gate-level netlist of a certain core area. FIG. 5 is a schematic diagram of an embodiment of an input/output power bump and its electrical connection to a plurality of input/output buffers.

100:系統單晶片級電源完整性模擬系統 110:獲取模組 120:分類模組 130:單元電流模組 140:節點電流模組 150:核心電流模組 160:模擬模組 170:輸入輸出電流模組 180:電源模組 100: System-on-Wafer Level Power Integrity Simulation System 110: Get Mods 120: Classification module 130: Unit current module 140: Node Current Module 150: Core current module 160: Simulation Module 170: Input and output current module 180: Power Module

Claims

一種系統單晶片級電源完整性模擬系統，其包括：一記憶體模組，用以儲存多個指令；以及一處理器，用以執行該記憶體模組所儲存的該些指令，以對一系統單晶片(System on a Chip，SoC)進行一電源完整性模擬程序，該系統單晶片包括多個輸入輸出區域與多個核心區域，該電源完整性模擬程序包括：一獲取模組，用以基於每一該核心區域的一閘級網表(gate level netlist)與一工作負載(workload)取得每一該核心區域中每一標準單元(standard cell)在一二進制模式下的一節點活動；一分類模組，用以基於每一該核心區域的該閘級網表與每一該核心區域中定義的多個核心電源凸塊(core power bumps)，對每一該核心區域中的該些標準單元進行分類，以使每一該核心區域中的該些標準單元對應到同一該核心區域中不同的該核心電源凸塊；一單元電流模組，用以基於每一該標準單元的一負載電容與一標準單元庫(standard cell library)，取得每一該標準單元在其該負載電容下的一時間延遲(cell delay)與一電流曲線(current profile)；一節點電流模組，連接該獲取模組與該單元電流模組，用以依據每一該標準單元在該二進制模式下的該節點活動以及每一該標準單元在其該負載電容下的該時間延遲與該電流曲線計算出每一該標準單元的一節點電流曲線；一核心電流模組，連接該節點電流模組與該分類模組，用以基於該些標準單元與該些核心電源凸塊的對應關係疊加每一該標準單元的該節點電流曲線，以產生每一該核心電源凸塊的一電流曲線；一模擬模組，用以藉由一著重於積體電路之模擬程式(SPICE)模擬出每一該輸入輸出區域中每一輸入輸出緩衝器(I/O buffer)的一電流步階響應；一輸入輸出電流模組，連接該模擬模組，用以基於每一該輸入輸出緩衝器的一資料活動與該電流步階響應以及每一輸入輸出電源凸塊(I/O power bump)與該些輸入輸出緩衝器的電性連接關係計算出每一該輸入輸出電源凸塊的一電流曲線；以及一電源模組，連接該輸入輸出電流模組與該核心電流模組，用以基於該核心電流模組所產生的每一該核心電源凸塊的該電流曲線與該輸入輸出電流模組所計算取得的每一該輸入輸出電源凸塊的該電流曲線，採用Z參數或S參數格式取得一電源傳輸網路(Power Delivery Network，PDN)。 A system-on-chip-level power integrity simulation system, comprising: a memory module for storing a plurality of instructions; and a processor for executing the instructions stored in the memory module for a A system on a chip (SoC) performs a power integrity simulation program. The system single chip includes a plurality of input and output regions and a plurality of core regions. The power integrity simulation program includes: an acquisition module for Based on a gate level netlist and a workload of each core area, a node activity of each standard cell in each core area in a binary mode is obtained; a a classification module for the criteria in each of the core regions based on the gate-level netlist of each of the core regions and a plurality of core power bumps defined in each of the core regions cell classification so that the standard cells in each of the core regions correspond to different core power bumps in the same core region; a cell current module based on a load capacitance of each of the standard cells and a standard cell library (standard cell library) to obtain a time delay (cell delay) and a current profile (current profile) of each standard cell under the load capacitance; a node current module, connected to the acquisition module set and the cell current module for the node activity in the binary mode of each of the standard cells to and the time delay and the current curve of each of the standard cells under the load capacitance to calculate a node current curve of each of the standard cells; a core current module, connecting the node current module and the classification module , for superimposing the node current curve of each standard cell based on the corresponding relationship between the standard cells and the core power bumps to generate a current curve for each core power bump; an analog module, using A current step response of each input and output buffer (I/O buffer) in each input and output area is simulated by a simulation program (SPICE) focusing on integrated circuits; an input and output current module, The analog module is connected to be based on a data activity of each of the I/O buffers and the current step response and the power of each I/O power bump and the I/O buffers A current curve of each of the input and output power bumps is calculated from the sexual connection relationship; A current curve of the core power bump and the current curve of each of the input and output power bumps calculated by the input and output current module, using Z-parameter or S-parameter format to obtain a power delivery network (Power Delivery Network) Network, PDN).

如請求項1所述之系統單晶片級電源完整性模擬系統，其中，該分類模組先基於每一該核心區域的該閘級網表進行自動佈局與佈線(automatic placement and routing，APR)，以取得每一該核心區域的一平面佈置圖；接著，基於每一該核心區域的該平面佈置圖生成對應的一網表文件，每一該網表文件包括多個寄生電容；最後，基於每一該網表文件取得每一該核心電源凸塊對應供電的該標準單元，再對每一該核心區域中的該些標準單元進行分類，以使每一該核心區域中的該些標準單元對應到同一該核心區域中不同的該核心電源凸塊。 The system-on-chip level power integrity simulation system of claim 1, wherein the classification module first performs automatic placement and routing (APR) based on the gate-level netlist of each core region, to get each of the cores A floor plan of the region; then, a corresponding netlist file is generated based on the floor plan of each of the core regions, and each netlist file includes a plurality of parasitic capacitances; finally, based on each of the netlist files, obtain Each of the core power bumps corresponds to the standard cell that supplies power, and then the standard cells in each of the core regions are classified so that the standard cells in each of the core regions correspond to the same core region different for this core power bump.

如請求項1所述之系統單晶片級電源完整性模擬系統，其中，該單元電流模組先取得每一該標準單元的該負載電容，每一該標準單元的該負載電容包括一金屬寄生電容，或者包括該金屬寄生電容與一下一級標準單元的一閘極(gate)的電容；接著，對應到同一該核心電源凸塊的該些標準單元中，當該標準單元為一第一級標準單元時，根據該標準單元庫與該標準單元的該負載電容取得該標準單元的該時間延遲、該電流曲線與一轉換時間(transition time)；以及當該標準單元為一第N級標準單元時，將一第(N-1)級標準單元的該轉換時間作為一輸入特性，並根據該標準單元庫、該第N級標準單元的該負載電容與該輸入特性取得該第N級標準單元的該時間延遲、該電流曲線與該轉換時間，其中，N為正整數，大於或等於2，且小於或等於對應到同一該核心電源凸塊的該些標準單元的數量。 The system-on-chip power integrity simulation system of claim 1, wherein the cell current module first obtains the load capacitance of each of the standard cells, and the load capacitance of each of the standard cells includes a metal parasitic capacitance , or including the metal parasitic capacitance and the capacitance of a gate of the next-level standard cell; then, corresponding to the standard cells of the same core power bump, when the standard cell is a first-level standard cell , obtain the time delay, the current curve and a transition time of the standard cell according to the standard cell library and the load capacitance of the standard cell; and when the standard cell is an Nth-level standard cell, Taking the conversion time of a (N-1)-level standard cell as an input characteristic, and obtaining the N-th-level standard cell according to the standard cell library, the load capacitance of the N-th level standard cell, and the input characteristic The time delay, the current curve and the switching time, wherein N is a positive integer, greater than or equal to 2, and less than or equal to the number of the standard cells corresponding to the same core power bump.

如請求項1所述之系統單晶片級電源完整性模擬系統，其中，該輸入輸出電流模組先基於每一該輸入輸出緩衝器的該資料活動與該電流步階響應取得每一該輸入輸出緩衝器的該電流曲線；再基於與同一該輸入輸出電源凸塊電性連接的該些輸入輸出緩衝器的該些電流曲線計算出每一該輸入輸出電源凸塊的該電流曲線。 The system-on-chip power integrity simulation system of claim 1, wherein the I/O current module first obtains each of the I/O based on the data activity and the current step response of each of the I/O buffers this current curve of the buffer; re-base The current curve of each of the I/O power bumps is calculated from the current curves of the I/O buffers electrically connected to the same I/O power bump.

一種系統單晶片級電源完整性模擬方法，用以對一系統單晶片進行一電源完整性模擬，該系統單晶片包括多個輸入輸出區域與多個核心區域，該系統單晶片級電源完整性模擬方法包括以下步驟：(a)基於每一該核心區域的一閘級網表與一工作負載取得每一該核心區域中每一標準單元在一二進制模式下的一節點活動；(b)基於每一該核心區域的該閘級網表與每一該核心區域中定義的多個核心電源凸塊，對每一該核心區域中的該些標準單元進行分類，以使每一該核心區域中的該些標準單元對應到同一該核心區域中不同的該核心電源凸塊；(c)基於每一該標準單元的一負載電容與一標準單元庫，取得每一該標準單元在其該負載電容下的一時間延遲與一電流曲線；(d)依據每一該標準單元在該二進制模式下的該節點活動以及每一該標準單元在其該負載電容下的該時間延遲與該電流曲線計算出每一該標準單元的一節點電流曲線；(e)基於該些標準單元與該些核心電源凸塊的對應關係疊加每一該標準單元的該節點電流曲線，以產生每一該核心電源凸塊的一電流曲線； (f)藉由一著重於積體電路之模擬程式模擬每一該輸入輸出區域中每一輸入輸出緩衝器的一電流步階響應；(g)基於每一該輸入輸出緩衝器的一資料活動與該電流步階響應以及每一輸入輸出電源凸塊與該些輸入輸出緩衝器的電性連接關係計算出每一該輸入輸出電源凸塊的一電流曲線；以及(h)基於步驟(e)所產生的每一該核心電源凸塊的該電流曲線以及步驟(g)所計算取得的每一該輸入輸出電源凸塊的該電流曲線，採用Z參數或S參數格式取得一電源傳輸網路。 A system single chip level power integrity simulation method is used to perform a power integrity simulation on a system single chip, the system single chip includes a plurality of input and output areas and a plurality of core areas, the system single chip level power integrity simulation The method includes the following steps: (a) obtaining a node activity in a binary mode of each standard cell in each of the core regions based on a gate-level netlist and a workload of each of the core regions; (b) based on each of the core regions A gate-level netlist of the core region and a plurality of core power bumps defined in each of the core regions classify the standard cells in each of the core regions such that the The standard cells correspond to different core power bumps in the same core area; (c) based on a load capacitance of each standard cell and a standard cell library, obtain the load capacitance of each standard cell under its load capacitance a time delay and a current curve of a node current curve of the standard cell; (e) superimposing the node current curve of each standard cell based on the corresponding relationship between the standard cells and the core power bumps to generate a a current curve; (f) simulating a current step response of each I/O buffer in each of the I/O regions by an IC-focused simulation program; (g) based on a data activity of each of the I/O buffers calculating a current curve for each of the I/O power bumps based on the current step response and the electrical connection relationship between each I/O power bump and the I/O buffers; and (h) based on step (e) The generated current curve of each of the core power bumps and the current curve of each of the input and output power bumps calculated in step (g) are used to obtain a power transmission network in Z-parameter or S-parameter format.

如請求項5所述之系統單晶片級電源完整性模擬方法，其中，該步驟(b)還包括：基於每一該核心區域的該閘級網表進行自動佈局與佈線，以取得每一該核心區域的一平面佈置圖；基於每一該核心區域的該平面佈置圖生成對應的一網表文件，每一該網表文件包括多個寄生電容；以及基於每一該網表文件取得每一該核心電源凸塊對應供電的該標準單元，再對每一該核心區域中的該些標準單元進行分類，以使每一該核心區域中的該些標準單元對應到同一該核心區域中不同的該核心電源凸塊。 The SoC-level power integrity simulation method of claim 5, wherein the step (b) further comprises: performing automatic placement and routing based on the gate-level netlist of each of the core regions to obtain each of the a floorplan of the core area; generating a corresponding netlist file based on the floorplan of each core area, each netlist file including a plurality of parasitic capacitances; and obtaining each netlist file based on each of the netlist files The core power bump corresponds to the standard cells that supply power, and then the standard cells in each core area are classified, so that the standard cells in each core area correspond to different ones in the same core area the core power bump.

如請求項5所述之系統單晶片級電源完整性模擬方法，其中，該步驟(c)還包括：取得每一該標準單元的該負載電容，其中，每一該標準單元的該負載電容包括一金屬寄生電容，或者包括該金屬寄生電容與一下一級標準單元的一閘極的電容；以及對應到同一該核心電源凸塊的該些標準單元中，當該標準單元為一第一級標準單元時，根據該標準單元庫與該標準單元的該負載電容取得該標準單元的該時間延遲、該電流曲線與一轉換時間(transition time)；當該標準單元為一第N級標準單元時，將一第(N-1)級標準單元的該轉換時間作為一輸入特性，並根據該標準單元庫、該第N級標準單元的該負載電容與該輸入特性取得該第N級標準單元的該時間延遲、該電流曲線與該轉換時間，其中，N為正整數，大於或等於2，且小於或等於對應到同一該核心電源凸塊的該些標準單元的數量。 The system-on-chip level power integrity simulation method according to claim 5, wherein the step (c) further comprises: Obtain the load capacitance of each of the standard cells, wherein the load capacitance of each of the standard cells includes a metal parasitic capacitance, or includes the metal parasitic capacitance and a capacitance of a gate of the next-level standard cell; and corresponds to the same Among the standard cells of the core power bump, when the standard cell is a first-level standard cell, the time delay and the current curve of the standard cell are obtained according to the standard cell library and the load capacitance of the standard cell and a transition time; when the standard cell is an N-level standard cell, the transition time of a (N-1)-level standard cell is used as an input characteristic, and according to the standard cell library, the The load capacitance and the input characteristic of the Nth level standard cell obtain the time delay, the current curve and the conversion time of the Nth level standard cell, wherein N is a positive integer, greater than or equal to 2, and less than or equal to the corresponding The number of the standard cells to the same core power bump.

如請求項5所述之系統單晶片級電源完整性模擬方法，其中，該步驟(g)還包括：基於每一該輸入輸出緩衝器的該資料活動與該電流步階響應取得每一該輸入輸出緩衝器的一電流曲線；以及基於與同一該輸入輸出電源凸塊電性連接的該些輸入輸出緩衝器的該些電流曲線計算出每一該輸入輸出電源凸塊的該電流曲線。 The system-on-chip level power integrity simulation method of claim 5, wherein the step (g) further comprises: obtaining each of the inputs based on the data activity and the current step response of each of the input and output buffers a current curve of an output buffer; and calculating the current curve of each of the I/O power bumps based on the current curves of the I/O buffers electrically connected to the same I/O power bump.