CN107784136B - Method and system for creating standard cell library - Google Patents
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Abstract
The embodiment of the invention provides a method and a system for creating a standard cell library. Therefore, the scheme reasonably configures each basic logic unit in the standard unit library, can ensure that the balance of chip time sequence and area is effectively realized in the ASIC design process, and avoids the waste of chip area caused by adopting a plurality of unit combinations due to lack of corresponding drive. Besides, the proportion of basic logic units is defined, the unit circuit schematic diagram is convenient to rapidly realize, the design development time of a standard unit library is effectively shortened, the driving consistency is good, the rapid convergence of the chip key path time sequence is facilitated, the invalid iteration times for repairing the time sequence violation in the logic synthesis and layout wiring processes are obviously reduced, and the efficiency of large-scale integrated circuit design is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit design technologies, and in particular, to a method and a system for creating a standard cell library.
Background
The standard cell library is a set of a combinational logic cell, a sequential logic cell and a special cell; the design method comprises data such as a unit netlist, a unit symbol, a unit layout, a logic function model, a comprehensive library model and the like, and is a basic database for large-scale integrated circuit design. The ASIC design based on the standard unit can greatly improve the design efficiency, accelerate the time of products entering the market, and has the advantages of low cost, short period and the like. The performance of the standard cell library determines the characteristics of the chip, such as area, timing, and power consumption. With the increase of the integration level and the operation speed of the monolithic integrated circuit, designing and developing a standard cell library with high integration level and high speed has become a necessary condition for chip design. The driving capability of the basic logic cells in the standard cell library directly affects the timing characteristics of the integrated circuit, including rise delay, fall delay, rise transition time, fall transition time, setup time, hold time, removal time, and reset time.
The determinants of the influence of the standard cell driving capability on the circuit timing characteristics are the input stage capacitance and the external load capacitance of the cell. The input capacitor is mainly an input stage transistor gate capacitor, determines the driving capability in the cell and is also the output load of the previous stage cell; the size of the output stage transistor affects the timing of the cell itself and determines the driving capability of the cell to external loads. Therefore, in the standard cell library design phase, the main influence factors of the driving capability are the input stage transistor size and the output stage transistor size.
In an integrated circuit design, the input capacitance of a succeeding stage unit is the load capacitance of a preceding stage unit. Therefore, the driving capacities of the basic logic cells in a set of standard cell libraries are mutually influenced and restricted, and the consistency of the driving capacities of all the basic logic cells is crucial to the performance of the whole set of cell libraries. If the basic logic cells in the standard cell library have no reasonable driving capacity quantity and type, the waste of chip area is caused; if the cells with different driving capabilities do not have an accurate proportional relationship, the timing of the critical path of the circuit cannot be converged, and the frequency of the chip is reduced as a whole.
The design and development of the existing standard cell library are generally completed by a plurality of engineers of a design team according to the design specification of the standard cell library in a full-custom design mode. The full customization is based on the transistor level, and all circuit schematic diagrams, circuit simulation, device interconnection lines and layouts are designed manually. The method is suitable for general circuit design requiring high integration level, high speed, small area and low power consumption.
The inventor finds that the logic function and the time sequence characteristic of the standard cell are determined by simulation by adopting the existing method, but the quantity distribution of the whole driving capability of the standard cell library and the device size ratio cannot be obtained by circuit simulation. Namely, the driving capability consistency is poor in the development process of the existing standard cell library. How to improve the consistency of the driving capability of the standard cell library becomes a major technical problem to be solved urgently at present.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method and a system for creating a standard cell library, so as to improve the consistency of the driving capability of the standard cell library.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
a method of creating a standard cell library, comprising:
determining the classification of the basic logic unit and generating at least one classification unit;
determining the quantity and the driving capability type of the driving strength of each classification unit;
determining the device size of the basic logic unit.
Preferably, the determining the classification of the basic logical unit and the generating at least one classification unit includes:
dividing the basic logic unit into a basic unit, a simple combinational logic unit, a complex combinational logic unit, a time sequence unit and a special unit according to Boolean logic and the use probability of the basic logic unit;
the base unit includes at least: an inverter and a buffer;
the simple combinational logic unit at least comprises an AND gate, an NAND gate, an OR gate and a NOR gate;
the complex combinational logic unit at least comprises an AND gate, an AND or, an OR or not, an XOR, an adder and a selector;
the timing unit at least comprises: latches, flip-flops, clock gating;
the special unit includes at least: the antenna comprises a substrate connecting unit, a filling unit and an antenna unit.
Preferably, the determining the number of driving strengths of each of the classification units comprises:
calculating the number of the driving strengths of the classification units according to a formula N ═ k ═ i × j;
wherein, N is the number of driving strengths of the sorting unit, k is the number of types of basic logic units in the sorting unit, i is the number of driving strengths, and j is the number of driving capability types.
Preferably, the driving capability category includes: a rise-fall time balance type, a complementary type in which the rise-fall average time is minimized and the average time is minimized, and a rise-fall transit time balance type.
Preferably, the determining the device size of the basic logic unit comprises:
and determining the device size of the basic logic cell according to the driving strength and the driving capability type of the basic logic cell.
Preferably, the determining the device size of the basic logic cell according to the driving strength and the driving capability type of the basic logic cell includes:
defining a P/N ratio as a preset reference value, wherein the P/N ratio is the channel width ratio of a PMOS tube and an NMOS tube of a phase inverter;
determining that the P/N ratios of all basic logic units of the same driving type are the same;
and determining that the device size of each basic logic unit with the same type and different driving strengths is X times of the preset reference value, wherein X is the numerical value of the driving strength of the basic logic unit.
A system for creating a standard cell library, comprising:
the first determining module is used for determining the classification of the basic logic unit and generating at least one classification unit;
a second determination module for determining the number of driving strengths of each of the classification units;
and the third determining module is used for determining the device size of the basic logic unit.
Preferably, the second determining module includes:
the calculation unit is used for calculating the product of the number of the types of the basic logic units, the number of the driving strengths and the number of the driving types in the classification unit;
a defining unit for defining the product as the number of driving strengths of the classifying unit.
Preferably, the third determining module includes:
and the determining unit is used for determining the device size of the basic logic unit according to the driving strength and the driving type of the basic logic unit.
Preferably, the determination unit includes:
the definition subunit is used for defining a P/N ratio as a preset reference value, wherein the P/N ratio is the channel width ratio of a PMOS tube and an NMOS tube of the phase inverter;
the first determining subunit is used for determining that the P/N ratios of all basic logic units in the same classification unit are the same;
and the second determining subunit is used for determining that the device size of each basic logic unit in the same classification unit is X times of the preset reference value, and X is the numerical value of the driving strength of the basic logic unit.
Based on the above technical solution, embodiments of the present invention provide a method and a system for creating a standard cell library, where at least one classification unit is generated by determining a classification of a basic logic unit, then the number of driving strengths and the driving capability types of each classification unit are determined, and finally the device size of the basic logic unit is determined. Therefore, the scheme reasonably configures each basic logic unit in the standard cell library, and improves the consistency of the driving capability of the standard cell library.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1a is a flowchart of a method for creating a standard cell library according to an embodiment of the present invention;
fig. 1b is a schematic structural diagram of a standard cell library creating apparatus according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a classification of a standard cell library according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a basic cell of a standard cell library according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a method for determining a device size of a basic logic unit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a basic logic unit of a standard cell library according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a basic logic unit of a standard cell library according to an embodiment of the present invention;
fig. 7 is a flowchart of a method for creating a standard cell library according to another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall correspond to the protection scope of the present invention.
Fig. 1a is a schematic flowchart of a method for creating a standard cell library according to an embodiment of the present invention, and fig. 1b is a schematic structural diagram of an apparatus for creating a standard cell library according to the embodiment, where the method for creating includes the steps of:
s100: and determining the classification of the basic logic unit and generating at least one classification unit.
Dividing the basic logic unit into a basic unit, a simple combinational logic unit, a complex combinational logic unit, a time sequence unit and a special unit according to Boolean logic and the use probability of the basic logic unit;
referring to fig. 2, the specific division is as follows:
a base unit: the unit logic is simple, the probability of being used in a chip is highest, and the unit logic comprises 2 types of basic logic units of an inverter and a buffer;
simple combinational logic unit: the unit logic is simpler, the probability of being used in a chip is higher, and the unit comprises units such as an AND gate, an NAND gate, an OR gate and an NOR gate, and about 25 logic function units;
complex combinational logic unit: the unit logic is relatively complex, the probability of being used in a chip is moderate, and the unit logic comprises units such as an AND gate, an AND or NOR, an AND or not, an XOR, an adder, a selector and the like, and about 40 basic logic units;
a time sequence unit: the logic of the unit is relatively complex, the unit is mainly used for a clock network in a chip, the used probability is related to the use of the chip, and the unit comprises units such as a latch, a trigger, a clock gate and the like, and about 35 basic logic units;
a special unit: such elements may be relatively special in function, or not logical elements, or may be used only in the physical design phase. The antenna comprises a substrate connecting unit, a filling unit, an antenna unit, a user-defined unit and the like, and about 10 basic logic units.
S110: determining a number of drive strengths for each of the classification units.
And calculating the product of the number of types of basic logic cells, the number of driving strengths and the driving capability type in the classification cells, and defining the product as the number of the driving strengths of the classification cells.
Specifically, the number of the driving strengths refers to the number of the driving strengths such as 0.5 times, 0.6 times, 0.7 times, 0.8 times, 0.9 times, 1 times, 1.2 times, 1.4 times, 1.7 times, 2 times, 2.5 times, 3 times … 64 times, and the like. The driving capability types in the present invention include a rise-fall time balance type (B), a minimum rise-fall average time (a), a complementary type (M) having a minimum average time, a rise-fall transition time balance type (E), and the like. The number of driving strengths N of each type of cell is equal to the cell type (k) multiplied by the number of driving strengths (i) multiplied by the type of driving capability (j), i.e., N ═ k × i × j. The number M of driving capabilities of each cell is equal to the number (i) of driving strengths thereof multiplied by the kind (j) of driving capabilities thereof, i.e., M ═ i × j. The distribution scheme of the number of basic unit driving strengths and the driving capability types is as follows:
the number of the basic unit driving strengths is larger when the scale of the standard unit library is larger, and the number of the basic unit driving strengths is smaller when the scale of the standard unit library is smaller; the simpler the logic equation of the type to which the cell belongs, the greater the number of cell drive strengths, and the more complex the logic equation of the type to which the cell belongs, the fewer the number of cell drive strengths.
The standard cell library has larger scale, so that the variety of basic cell driving capability is more, and the standard cell library has smaller scale, so that the variety of the basic cell driving capability is more; the simpler the logic equation of the type of the cell belongs to, the more the variety of the cell driving capability is, and the more the logic equation of the type of the cell belongs to, the less the variety of the cell driving capability is.
The design of the amount of cell driving capability is described below, taking a standard cell library scale of about 1000 cells as an example, as shown in FIG. 3. The associated data does not form a constraint on the present claims.
The drive strengths of the two basic cells, inverter and buffer, may specifically include, but are not limited to: X0P5, X0P6, X0P7, X0P8, X0P9, X1, X1P2, X1P4, X1P7, X2, X2P5, X3, X4, X5, X6, X7, X9, X11, X13, X16, X24, X32, X48, and X64; meanwhile, 3 driving types are respectively designed for each driving strength: a rise-fall time balance type (B), a complementary type (M) in which the rise-fall average time is the smallest (A) and the average time is the smallest. Therefore, the number of the two kinds of unit driving capacity of the inverter and the buffer is at least more than 60.
And simple logic units such as an and gate, a nand gate, an or gate, and a nor gate, and the like, and specific driving capabilities may include but are not limited to: X0P5, X0P7, X1, X1P4, X2, X3, X4, X6, and X8; 2-3 driving types are respectively designed for each driving strength: a rise-fall time balance type (B), a complementary type (M) in which the rise-fall average time is the smallest (A) and the average time is the smallest. Thereby ensuring that the driving capacity of each simple logic cell is at least more than 18.
And or gate, and or not, or and, or not, and nor, and specific driving capabilities may include but are not limited to: X0P5, X0P7, X1, X1P4, X2, X3, X4, X6, and X8; the drive type of each drive strength is selected to be the smallest rise-fall average time (a) or the complementary type (M) having the smallest average time. The number of driving capabilities of each complex combination cell is about 9.
Timing units such as latches, flip-flops, clock gating, and the like, specific driving capabilities may include, but are not limited to: x1, X2, X3 and X4; the driving type of each driving intensity is a complementary type (M) with the smallest average time. The number of driving capabilities of each sequential cell is about 4.
The substrate connecting unit, the filling unit, the antenna unit and other special units have no logic function and do not need various driving capabilities, and the corresponding unit widths are designed according to different physical characteristics.
The number of the basic units, the simple combinational logic units, the complex combinational logic units and the actual driving capability of the sequential cells can be calculated in equal proportion according to the scale and the number of types of the cell library.
S120: determining the device size of the basic logic unit.
And determining the device size of the basic logic unit according to the driving strength and the driving type of the basic logic unit. Specifically, as shown in fig. 4, the method is implemented by the following steps:
defining a P/N ratio as a preset reference value, wherein the P/N ratio is the channel width ratio of a PMOS tube and an NMOS tube of a phase inverter;
determining that the P/N ratios of all basic logic units of the same driving type are the same;
and determining that the device size of each basic logic unit with the same type and different driving strengths is X times of the preset reference value, wherein X is the numerical value of the driving strength of the basic logic unit.
For example:
the P/N ratio of the input stage and the P/N ratio of the output stage of the unit with the same type and different driving strengths keep a relatively constant value; as shown in fig. 5, the P/N ratio of the 1-time drive strength rising and falling time balance type inverter INV _ X1B is the same as the P/N ratio of the 8-time drive strength rising and falling time balance type inverter INV _ X8B.
The unit of the same type and different driving strengths has the output stage device size of n times of the driving strength unit which is n times of 1 time of the driving strength. For example, after the two-input NAND gate NAND2_ X1A with 1 time of driving strength rising and falling average time being the smallest is sized, the channel widths of the output end devices PMOS and NMOS of the two-input NAND gate NAND2_ X4A unit of 4 times of driving strength rising and falling time balance type are 4 times of that of the NAND2_ X1A unit.
The channel width of a PMOS tube and an NMOS tube of the inverter is the geometric mean of the channel width of a subsequent device and the inverter with the minimum driving strength, so as to ensure smaller input capacitance and enough driving capability of the subsequent device; the output stage in the logic unit circuit is provided with an inverter, and the channel width of a PMOS tube and the channel width of an NMOS tube of the inverter are the same as that of the inverter with the same driving strength, so that the accurate driving strength is ensured.
A circuit schematic of the input stage and the output stage being inverters is shown in fig. 6. For example, the buffer BUF _ X16B of the 16-times driving strength rise-fall time balance type has the channel widths of the PMOS transistor and the NMOS transistor: the size of an output stage device is the same as that of a 16-time drive strength rising and falling time balance type inverter INV _ X16B unit, and the size of an input stage device is the geometric mean of the channel width of a subsequent stage device and the inverter INV _ X0P5B unit with the minimum drive strength;
the channel width of the MOS transistor in other cases is preliminarily determined according to the P/N ratio of the inverter and the logic effort. According to the specific scheme, the sizes of the MOS tube devices of the input stage and the output stage of all basic logic units can be preliminarily determined.
Therefore, the scheme reasonably configures each basic logic unit in the standard cell library, and improves the consistency of the driving capability of the standard cell library.
As shown in fig. 7, after step S120, the method may further include the steps of:
s130: and designing a schematic diagram of the cell circuit according to the design specifications of the standard cell library and the device size ratio of the basic logic cell determined in the step S120. The difference with the traditional process is that in the design process of the unit circuit schematic diagram, the device sizes of the unit input stage and the unit output stage have initial guide values, so that the design of the unit circuit schematic diagram is conveniently and rapidly completed, and the consistency of the driving capability of all basic units is ensured.
The method can also comprise the following steps: pre-simulation of cell circuit function and timing. If the post-simulation result does not meet the requirements of functions and time sequences, returning to the step S130 to modify the circuit structure and the device size; if the post-simulation result meets the functional and timing requirements, go to step 207.
S140: and (5) designing a unit layout. And an engineer designs a layout according to the circuit structure and the size of the device, and completes physical verification, including design rule check, layout schematic diagram comparison check and parasitic parameter extraction.
S150: post-simulation of cell circuit function and timing. If the post-simulation result does not meet the requirements of functions and time sequences, returning to the step S140 to modify the layout and interconnection lines of the unit layout; if the post-simulation result meets the functional and timing requirements, the process proceeds to step S160.
S160: and performing characteristic modeling on the standard cell library to form a standard cell library design kit. And (4) extracting the characteristics of time sequence, area, power consumption, noise and the like for the standard unit completed in the steps, and establishing a perfect characterization model.
In addition, the present embodiment further provides a system for creating a standard cell library, including:
the first determining module is used for determining the classification of the basic logic unit and generating at least one classification unit;
a second determination module for determining the number of driving strengths of each of the classification units;
and the third determining module is used for determining the device size of the basic logic unit.
Preferably, the second determining module includes:
the calculation unit is used for calculating the product of the number of the types of the basic logic units, the number of the driving strengths and the number of the driving types in the classification unit;
a defining unit for defining the product as the number of driving strengths of the classifying unit.
Preferably, the third determining module includes:
and the determining unit is used for determining the device size of the basic logic unit according to the driving strength and the driving type of the basic logic unit.
Preferably, the determination unit includes:
the definition subunit is used for defining a P/N ratio as a preset reference value, wherein the P/N ratio is the channel width ratio of a PMOS tube and an NMOS tube of the phase inverter;
the first determining subunit is used for determining that the P/N ratios of all basic logic units in the same classification unit are the same;
and the second determining subunit is used for determining that the device size of each basic logic unit in the same classification unit is X times of the preset reference value, and X is the numerical value of the driving strength of the basic logic unit.
The principle of the standard cell library creation system is the same as the method embodiment.
In summary, embodiments of the present invention provide a method and a system for creating a standard cell library, which generate at least one classification unit by determining a classification of a basic logic unit, then determine a driving strength number of each classification unit, and finally determine a device size of the basic logic unit. Therefore, the scheme reasonably configures each basic logic unit in the standard unit library, can ensure that the balance of chip time sequence and area is effectively realized in the ASIC design process, and avoids the waste of chip area caused by adopting a plurality of unit combinations due to lack of corresponding drive. Besides, the proportion of basic logic units is defined, the unit circuit schematic diagram is convenient to rapidly realize, the design development time of a standard unit library is effectively shortened, the driving consistency is good, the rapid convergence of the chip key path time sequence is facilitated, the invalid iteration times for repairing the time sequence violation in the logic synthesis and layout wiring processes are obviously reduced, and the efficiency of large-scale integrated circuit design is improved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. A method for creating a standard cell library, comprising:
determining the classification of the basic logic unit and generating at least one classification unit;
determining the quantity and the driving capability type of the driving strength of each classification unit;
determining the device size of the basic logic unit;
the determining the number of driving strengths of each of the classification units comprises:
calculating the number of the driving strengths of the classification units according to a formula N ═ k ═ i × j;
wherein N is the number of driving strengths of the classification units, k is the number of types of basic logic units in the classification units, i is the number of the driving strengths, and j is the number of the driving capability types;
determining the device size of the basic logic cell according to the driving strength and the driving capability type of the basic logic cell comprises:
defining a P/N ratio as a preset reference value, wherein the P/N ratio is the channel width ratio of a PMOS tube and an NMOS tube of a phase inverter;
determining that the P/N ratios of the basic logic units of the same driving capability type are the same;
and determining that the device size of each basic logic unit of the same type with different driving strengths is X times of the preset reference value, wherein X is the number of the driving strengths of the basic logic units.
2. The method of creating a standard cell library of claim 1, wherein determining a classification of the base logical unit and generating at least one classified unit comprises:
dividing the basic logic unit into a basic unit, a simple combinational logic unit, a complex combinational logic unit, a time sequence unit and a special unit according to Boolean logic and the use probability of the basic logic unit;
the base unit includes at least: an inverter and a buffer;
the simple combinational logic unit at least comprises an AND gate, an NAND gate, an OR gate and a NOR gate;
the complex combinational logic unit at least comprises an AND gate, an AND or, an OR or not, an XOR, an adder and a selector;
the timing unit at least comprises: latches, flip-flops, clock gating;
the special unit includes at least: the antenna comprises a substrate connecting unit, a filling unit and an antenna unit.
3. The method of creating a standard cell library of claim 1, wherein the driving capability category comprises: a rise-fall time balance type, a complementary type in which the rise-fall average time is minimized and the average time is minimized, and a rise-fall transit time balance type.
4. The method of claim 3, wherein said determining the device size of the basic logic cell comprises:
and determining the device size of the basic logic cell according to the driving strength and the driving capability type of the basic logic cell.
5. A system for creating a standard cell library, comprising:
the first determining module is used for determining the classification of the basic logic unit and generating at least one classification unit;
a second determining module, configured to determine the driving strength number and the driving capability type of each of the classification units;
a third determining module, configured to determine a device size of the basic logic unit;
the second determining module includes:
the calculation unit is used for calculating the product of the number of types of basic logic units, the number of driving strengths and the number of driving capability types in the classification unit;
a defining unit for defining the product as the number of driving strengths of the classifying unit;
the third determining module includes:
the determining unit is used for determining the device size of the basic logic unit according to the driving strength and the driving capability type of the basic logic unit; the determination unit includes:
the definition subunit is used for defining a P/N ratio as a preset reference value, wherein the P/N ratio is the channel width ratio of a PMOS tube and an NMOS tube of the phase inverter;
the first determining subunit is used for determining that the P/N ratios of all basic logic units of the same driving capability type are the same;
and the second determining subunit is used for determining that the device size of each basic logic unit of the same type with different driving strengths is X times of the preset reference value, wherein X is the number of the driving strengths of the basic logic units.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610721546.5A CN107784136B (en) | 2016-08-24 | 2016-08-24 | Method and system for creating standard cell library |
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| CN108563899B (en) * | 2018-04-26 | 2022-02-22 | 武汉新芯集成电路制造有限公司 | Simulation system and method for standard cell |
| CN110888038B (en) * | 2018-09-11 | 2021-12-14 | 中芯国际集成电路制造(上海)有限公司 | Standard unit test circuit layout, optimization method thereof and standard unit test structure |
| CN109635436B (en) * | 2018-12-12 | 2023-08-18 | 上海华力集成电路制造有限公司 | Circuit structure |
| CN111241771B (en) * | 2019-01-29 | 2023-12-01 | 叶惠玲 | Method and system for establishing standard cell library, chip design method and system |
| CN111241768B (en) * | 2019-01-29 | 2023-06-30 | 叶惠玲 | Method and system for establishing standard cell library, chip design method and system |
| CN109948226B (en) * | 2019-03-13 | 2020-12-25 | 上海安路信息科技有限公司 | Method and system for processing drive information |
| CN112100158B (en) * | 2020-09-21 | 2022-11-22 | 海光信息技术股份有限公司 | Standard cell library establishing method and device, electronic equipment and storage medium |
| US20220253282A1 (en) * | 2021-02-11 | 2022-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | New low power adder tree structure |
| CN113158618A (en) * | 2021-05-25 | 2021-07-23 | 杨家奇 | Method for generating standard cell library layout |
| CN114707443B (en) * | 2022-05-23 | 2023-01-10 | 北京芯愿景软件技术股份有限公司 | Method and device for simplifying basic unit library |
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