TWI755741B - 用於高速資料傳輸的半導體封裝及其製造方法 - Google Patents
用於高速資料傳輸的半導體封裝及其製造方法 Download PDFInfo
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- TWI755741B TWI755741B TW109117536A TW109117536A TWI755741B TW I755741 B TWI755741 B TW I755741B TW 109117536 A TW109117536 A TW 109117536A TW 109117536 A TW109117536 A TW 109117536A TW I755741 B TWI755741 B TW I755741B
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- conductive
- waveguide
- conductive member
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Abstract
本發明實施例係關於一種半導體結構及其形成方法。一種製造該半導體結構之方法包含:提供一基板;在該基板上方沈積一第一介電層;將一波導附接至該第一介電層;沈積一第二介電層以橫向包圍該波導;及在該第二介電層及該波導上方形成一第一導電部件及一第二導電部件,其中該第一導電部件及該第二導電部件與該波導接觸。該波導經組態以在該第一導電部件與該第二導電部件之間傳輸一電磁信號。
Description
本發明實施例係有關用於高速資料傳輸的半導體封裝及其製造方法。
使用半導體裝置之電子設備對於諸多現代應用而言係必不可少的。隨著電子技術之進步,半導體裝置之大小持續變小,同時具有更大功能及更多積體電路量。歸因於半導體裝置之小型化尺度,一基板上晶圓上晶片(CoWoS)廣泛用於藉由貫穿基板通路(TSV)將若干晶片整合至一單一半導體裝置中。在CoWoS操作期間,將諸多晶片組裝於一單一半導體裝置上。此外,在小半導體裝置內實施諸多製造操作。
然而,半導體裝置之製造操作涉及小而薄之半導體裝置上之諸多步驟及操作。小型化尺度之半導體裝置之製造變得更複雜。製造半導體裝置之複雜性增加會引起諸如不良結構組態及組件分層之缺陷以導致半導體裝置顯著良率損失及製造成本增加。因而,修改半導體裝置之一結構及改良製造操作存在諸多挑戰。
根據本發明的一實施例,一種製造一半導體結構之方法包括:提供一基板;在該基板上方沈積一第一介電層;將一波導附接至該第一介電層;沈積一第二介電層以橫向包圍該波導;及在該第二介電層及該波導上方形成一第一導電部件及一第二導電部件,該第一導電部件及該第二導電部件與該波導接觸,其中該波導經組態以在該第一導電部件與該第二導電部件之間傳輸一電磁信號。
根據本發明的一實施例,一種製造一半導體結構之方法包括:在一基板上方沈積一介電層;在該介電層上方形成一第一導電部件及一第二導電部件;將一波導之一第一端及一第二端分別接合至該第一導電部件及該第二導電部件;及形成分別接觸該波導之該第一端及該第二端的一第三導電部件及一第四導電部件。
根據本發明的一實施例,一種半導體結構包括:一基板;一重佈層,其安置於該基板上方且包括:一第一介電層,其在該基板上方;一第一導電部件及一第二導電部件,其等在該第一介電層內;一波導,其在該第一介電層上方且接合至該第一導電部件及該第二導電部件;一第二介電層,其橫向包圍該波導;一第三導電部件及一第四導電部件,其等耦合至該波導;及一第五導電部件,其在該第一介電層內且位於該第一導電部件與該基板之一表面之間;及一半導體晶粒,其在該重佈層上方且電連接至該第一導電部件。
以下揭露提供用於實施所提供標的之不同特徵之諸多不同實施例或實例。下文將描述組件及配置之特定實例以簡化本揭露。當然,此等僅為實例且不意在限制。例如,在以下描述中,在一第二構件上方或一第二構件上形成一第一構件可包含其中形成直接接觸之第一構件及第二構件的實施例,且亦可包含其中可在第一構件與第二構件之間形成額外構件使得第一構件及第二構件可不直接接觸的實施例。另外,本揭露可在各個實例中重複參考元件符號及/或字母。此重複係為了簡單及清楚且其本身不指示所討論之各種實施例及/或組態之間的一關係。
此外,為便於描述,諸如「下面」、「下方」、「下」、「上方」、「上」及其類似者之空間相對術語在本文中可用於描述一元件或構件與另一(些)元件或構件之關係,如圖中所繪示。除圖中所描繪之定向之外,空間相對術語亦意欲涵蓋裝置在使用或操作中之不同定向。設備可依其他方式定向(旋轉90度或依其他定向)且亦可因此解譯本文中所使用之空間相對描述詞。
儘管闡述本揭露之廣泛範疇的數值範圍及參數係近似值,但要儘可能精確報告具體實例中所闡述之數值。然而,任何數值固有地含有由各自測試量測中常見之偏差必然所致之某些誤差。而且,如本文中所使用,術語「約」、「實質」及「實質上」一般意謂在一給定值或範圍之10%、5%、1%或0.5%內。替代地,如由一般技術者所考量,術語「約」、「實質」及「實質上」意謂在平均值之一可接受標準誤差內。除在操作/工作實例中之外,或除非另有明確說明,否則本文中所揭露之所有數值範圍、數量、值及百分比(諸如材料數量、持續時間、溫度、操作條件、數量比及其類似者之數值範圍、數量、值及百分比)應被理解為在所有例項中由術語「約」、「實質」及「實質上」修飾。因此,除非指示相反,否則本揭露及所附申請專利範圍中所闡述之數值參數係可根據需要變動之近似值。最後,至少應鑑於報告有效數位數及藉由應用一般捨入技術來解釋各數值參數。範圍在本文中可表示為自一端點至另一端點或在兩個端點之間。除非另有說明,否則本文中所揭露之所有範圍包含端點。
藉由數個操作來製造包含各種半導體晶片之一電子裝置。在製程期間,具有不同功能及尺寸之半導體晶片整合至一單一模組中。整合半導體晶片之電路且使其透過導電跡線連接。半導體晶片藉由透過導電跡線將一電信號自一裝置傳輸至另一裝置來彼此通信。然而,半導體晶片之間的此傳輸無法滿足半導體晶片之間的高速通信要求。因此,電子裝置之效能無法達到所要位準。
在本揭露中,揭露一種半導體結構及一種形成該半導體結構之方法。該半導體結構包含:一基板;一互連結構,其安置或沈積於該基板上方且包含該基板上方之一介電層;一第一導電部件及一第二導電部件,該第一導電構件安置於該介電層內,該第二導電構件安置或形成於該介電層內;一波導,其安置或製造於該介電層內;一第一晶粒,其安置於該互連結構上方且電連接至該第一導電部件;及一第二晶粒,其安置於該互連結構上方且電連接至該第二導電部件,其中該波導耦合至該第一導電部件及該第二導電部件。
使一電信號自該第一晶粒傳輸至該第一導電部件,且將該電信號轉換為一電磁信號。該電磁信號自該第一導電部件透過該波導傳輸至該第二導電部件。當該電磁信號由該第二導電部件接收時,將該電磁信號經轉換為一電信號。接著,使該電信號自該第二導電部件傳輸至該第二晶粒。該電磁信號係不可見輻射(例如無線電波、微波、毫米波或其類似者)以沿該波導提供一高資料傳送速率(例如,實質上大於10十億位元/秒或大於100十億位元/秒),且可在傳輸期間最小化歸因於波導之電磁信號之能量損失。
圖1係根據本發明之各種實施例之一半導體結構100之一示意性橫截面圖。在一些實施例中,半導體結構100包含一基板101、一互連結構102、一波導103、一第一晶粒104及一第二晶粒105。
在一些實施例中,半導體結構100係一半導體封裝。在一些實施例中,半導體結構100係一積體扇出(InFO)封裝,其中第一晶粒104或第二晶粒105之I/O端子經扇出且以一更大面積重佈於第一晶粒104或第二晶粒105之一表面上方。在一些實施例中,半導體結構100係一基板上晶圓上晶片(CoWoS)封裝結構。在一些實施例中,半導體結構100係三維積體電路(3D IC)。在一些實施例中,半導體結構100經組態以在半導體結構100內執行一超高速信號傳輸,例如實質上等於或大於100十億位元/秒(Gbps)之一速率之一信號傳輸。在一些實施例中,半導體結構100經組態以在半導體結構100內執行一高頻超高速信號傳輸,例如實質上大於約100十億赫茲(GHz)之一頻率之一信號傳輸。
在一些實施例中,基板101係一半導電基板。在一些實施例中,基板101包含半導電材料,諸如矽、鍺、鎵、砷或其等之一組合。在一些實施例中,基板101係一中介層或其類似者。在一些實施例中,基板101係由塊狀矽形成之矽基板或矽中介層。在一些實施例中,基板101包含諸如陶瓷、玻璃、聚合物或其類似者之一材料。在一些實施例中,基板101包含一有機材料。在一些實施例中,基板101具有四邊形、矩形、正方形、多邊形或任何其他適合形狀。
在一些實施例中,基板101包含一第一表面101a及與第一表面101a對置之一第二表面101b。在一些實施例中,一通路101c在基板101中延伸穿過基板101之至少一部分。在一些實施例中,通路101c在第一表面101a與第二表面101b之間延伸。在一些實施例中,通路101c經形成為一導電通路且包含諸如銅、銀、金、鋁、鎢、鈦、其等之一組合或其類似者之一導電材料。在一些實施例中,通路101c係延伸穿過基板101之厚度的一貫穿矽通路(TSV)。
在一些實施例中,一第一墊101d安置於通路101c下面且電連接至通路101c。在一些實施例中,第一墊101d安置於基板101之第二表面101b上方。在一些實施例中,第一墊101d包含金屬或金屬合金。在一些實施例中,第一墊101d包含鉻、銅、金、鈦、銀、鎳、鈀、鎢或其類似者。在一些實施例中,第一墊101d係一可焊接表面且用作用於接收一焊接材料且將基板101之一電路電連接至一外部組件或電路的一平台。
在一些實施例中,一第一導電凸塊101e安置或製造於基板101下面。在一些實施例中,第一導電凸塊101e製造於基板101之第二表面101b上方。在一些實施例中,第一導電凸塊101e製造於第一墊101d下面且電連接至第一墊101d。在一些實施例中,第一導電凸塊101e電連接至通路101c。在一些實施例中,第一導電凸塊101e具有一圓柱形、球形或半球形形狀。在一些實施例中,第一導電凸塊101e係一焊料接頭、一焊料凸塊、一焊球、一球柵陣列(BGA)球、一受控塌陷晶片連接(C4)凸塊或其類似者。在一些實施例中,第一導電凸塊101e係一導電柱或支柱。在一些實施例中,第一導電凸塊101e包含諸如鉛、錫、銅、金、鎳、其等之一組合或其類似者之金屬。
在一些實施例中,互連結構102安置或沈積於基板101上方。在一些實施例中,互連結構102沈積於基板101之第一表面101a上方。在一些實施例中,互連結構102包含沈積於基板101上方之一介電層102a、安置或形成於介電層102a內之若干導電部件102b及安置或形成於介電層102a內之若干導電通路102c。
在一些實施例中,介電層102a包含一或多個介電層,例如彼此上下堆疊之一第一層102a-1、一第二層102a-2及一第三層102a-3。在一些實施例中,介電層102a包含二氧化矽、摻氟二氧化矽、摻碳二氧化矽、多孔二氧化矽、具有一低介電常數(低K)之一介電材料、具有一超低介電常數(ULK)之一介電材料、具有實質上小於二氧化矽之一介電常數之一介電常數的一介電材料或具有實質上小於4之一介電常數的一介電材料。
在一些實施例中,導電部件102b及導電通路102c經組態以電連接至通路101c或第一導電凸塊101e。在一些實施例中,導電部件102b及導電通路102c電連接至安置於基板101上方或基板101內之一電路。在一些實施例中,導電部件102b電耦合至對應導電通路102c。在一些實施例中,導電部件102b係導線且在介電層102a-1、102a-2或102a-3內橫向延伸,且導電通路102c在介電層102a-2或102a-3內垂直延伸以使上覆及下伏導電部件102b互連。在一些實施例中,導電部件102b及導電通路102c包含諸如金、銀、銅、鎳、鎢、鋁、錫、其等之一合金或其類似者之導電材料。
在一些實施例中,導電部件102b包含一第一導電部件102b-1及一第二導電部件102b-2。導電部件102b-1及102b-2可呈一碟、線、條、多邊形或其類似者之一形狀。在一些實施例中,第一導電部件102b-1及第二導電部件102b-2形成或安置於介電層102a之第三層102a-3上方。在一些實施例中,第一導電部件102b-1及第二導電部件102b-2彼此相鄰形成。在一些實施例中,第一導電部件102b-1及第二導電部件102b-2由一介電材料分離。在一些實施例中,第一導電部件102b-1與第二導電部件102b-2水平對準。在一些實施例中,第一導電部件102b-1及第二導電部件102b-2電連接至對應導電通路102c。在一些實施例中,通路101c透過導電通路102c電連接至第一導電部件102b-1、第二導電部件102b-2、第三導電部件102b-3或第四導電部件102b-4。
在一些實施例中,第一導電部件102b-1經組態以將一電信號轉換為一電磁信號或將一電磁信號轉換為一電信號。在一些實施例中,第一導電部件102b-1經組態以將電磁信號傳輸至第二導電部件102b-2或自第二導電部件102b-2接收電磁信號。在一些實施例中,第二導電部件102b-2經組態以自第一導電部件102b-1接收電磁信號或將電磁信號傳輸至第一導電部件102b-1。在一些實施例中,第二導電部件102b-2經組態以將電磁信號轉換為一電信號或將一電信號轉換為一電磁信號。在一些實施例中,電磁信號係諸如微波、無線電波、毫米波或其類似者之一不可見波長輻射。在一些實施例中,電磁信號係一不可見光。
在一些實施例中,導電部件102b包含一第三導電部件102b-3及一第四導電部件102b-4。導電部件102b-3及102b-4可呈一碟、線、條、多邊形或其類似者之一形狀。在一些實施例中,第三導電部件102b-3及第四導電部件102b-4安置或形成於介電層102a之第二層102a-2內。在一些實施例中,第三導電部件102b-3及第四導電部件102b-4彼此相鄰形成。在一些實施例中,第三導電部件102b-3與第四導電部件102b-4水平對準。在一些實施例中,第三導電部件102b-3及第四導電部件102b-4電連接至對應導電通路102c。
在一些實施例中,第三導電部件102b-3經組態以將一電信號轉換為一電磁信號或將一電磁信號轉換為一電信號。在一些實施例中,第三導電部件102b-3經組態以將電磁信號傳輸至第二導電部件102b-2或第四導電部件102b-4或自第二導電部件102b-2或第四導電部件102b-4接收電磁信號。在一些實施例中,第四導電部件102b-4經組態以將電磁信號轉換為一電信號或將一電信號轉換為一電磁信號。在一些實施例中,第四導電部件102b-4經組態以自第一導電部件102b-1或第三導電部件102b-3接收電磁信號或將電磁信號傳輸至第一導電部件102b-1或第三導電部件102b-3。
在一些其他實施例中,第一導電部件102b-1及第三導電部件102b-3安置於波導103之一相同側上,例如參考圖3B所描述。類似地,在一些其他實施例中,第二導電部件102b-2及第四導電部件102b-4安置於波導103之一相同側上。
在一些實施例中,第一導電部件102b-1及第二導電部件102b-2分別經組態為一第一傳輸電極及一第一接收電極或分別經組態為一第一接收電極及一第一傳輸電極。在一些實施例中,第三導電部件102b-3及第四導電部件102b-4分別經組態為一第二傳輸電極及一第二接收電極或分別經組態為一第二接收電極及一第二傳輸電極。在一些實施例中,第三導電部件102b-3安置於與第一導電部件102b-1對置之波導103之一側上,且第四導電部件102b-4安置於與第二導電部件102b-2對置之波導103之一側上。在一些實施例中,第一導電部件102b-1具有類似於第三導電部件102b-3之組態的一組態,且第二導電部件102b-2具有類似於第四導電部件102b-4之組態的一組態。
在一些實施例中,第一導電部件102b-1及第三導電部件102b-3可成對操作,其中對之一者用作用於傳輸或接收電磁信號之一信號端子且另一者接地。在一些實施例中,第二導電部件102b-2及第四導電部件102b-4可成對操作,其中對之一者用作用於傳輸或接收電磁信號之一信號端子且另一者接地。
在一些實施例中,波導103安置於互連結構102中之介電層102a之第三層102a-3內。在一些實施例中,波導103安置於導電部件102b之兩者之間。在一些實施例中,波導103安置於第一導電部件102b-1與第二導電部件102b-2之間或第三導電部件102b-3與第四導電部件102b-4之間。在一些實施例中,波導103耦合至第一導電部件102b-1及第二導電部件102b-2。在一些實施例中,波導103耦合至第三導電部件102b-3及第四導電部件102b-4。
在一些實施例中,波導103包含一第一端103a及與第一端103a對置之一第二端103b。在一些實施例中,第一端103a耦合至第一導電部件102b-1或第三導電部件102b-3,且第二端103b耦合至第二導電部件102b-2或第四導電部件102b-4。在一些實施例中,第一端103a由第一導電部件102b-1及第三導電部件102b-3包圍,且第二端103b由第二導電部件102b-2及第四導電部件102b-4包圍。
在一些實施例中,波導103係介電的且經組態以將一電磁信號自導電部件102b之一者傳輸至導電部件102b之另一者。在一些實施例中,電磁信號在波導103內傳輸。在一些實施例中,波導103經組態以透過波導103將一電磁信號自第一導電部件102b-1傳輸至第二導電部件102b-2或自第三導電部件102b-3傳輸至第四導電元件102b-4。
在一些實施例中,第一導電部件102b-1及第三導電部件102b-3經組態為經組態以傳輸或接收電磁信號之一對天線板,其中天線板之一者用作一信號埠且另一者接地。類似地,第二導電部件102b-2及第四導電部件102b-4經組態為經組態以傳輸或接收電磁信號之一對天線板,其中天線板之一者用作一信號埠且另一者接地。在一些實施例中,第一導電部件102b-1與第三導電部件102b-3之間的波導103之至少一部分(諸如第一端103a)經形成為一諧振腔且結合第一導電部件102b-1及第三導電部件102b-3進行電磁信號與一電信號之間的轉換。在一些實施例中,電磁輻射之駐波形成於波導103內,其中駐波之諧振頻率由波導103之幾何形狀(諸如波導103之寬度及高度)判定。在一些實施例中,第二導電部件102b-2與第四導電部件102b-4之間的波導103之至少一部分(諸如第二端103b)經形成為一諧振腔且結合第二導電部件102b-2及第四導電部件102b-4進行電磁信號與一電信號之間的轉換。
在一些實施例中,將來自第一導電部件102b-1之一電信號轉換為一電磁信號,電磁信號在波導103內自第一端103a傳輸至第二端103b,且電磁信號在第二導電部件102b-2處轉換為一電信號。因而,電信號自第一導電部件102b-1透過波導103傳輸至第二導電部件102b-2。在一些實施例中,電磁信號之一傳輸速率實質上大於10或100十億位元/秒(Gbps)。自第二導電部件102b-2傳輸至第一導電部件102b-1之電信號依一類似方式進行。
在一些實施例中,波導103具有一平板、一稜柱、一長方體、一碟、一板、一切片或其他適合形式之一形狀。在一些實施例中,波導103在介電層102a-3內橫向延伸。在一些實施例中,波導103之一高度係在約1 μm至約20 μm之間。在一些實施例中,波導103之一寬度係在約10 μm至約200 μm之間。在一些實施例中,波導103之寬度係波導103之高度之約10倍。在一些實施例中,波導103之長度係在約0.01 cm至約1 cm之間。
在一些實施例中,波導103之一介電常數實質上大於介電層102a (例如第一層102a-1、第二層102a-2或第三層102a-3)之介電常數。在一些實施例中,波導103之一介電常數係介電層102a之介電常數之至少10倍。由於波導103之介電常數實質上大於介電層102a之介電常數,因此波導103引起進入波導103之電磁信號藉由全內反射來反射於波導103內,使得電磁信號可在波導103之第一端103a與第二端103b之間或第一導電部件102b-1與第二導電部件102b-2之間傳輸。
在一些實施例中,波導103之介電常數實質上大於二氧化矽之一介電常數。在一些實施例中,波導103之介電常數實質上大於4。在一些實施例中,波導103之介電常數實質上大於7。在一些實施例中,波導103之介電常數實質上大於13。在一些實施例中,波導103之介電常數實質上大於100。在一些實施例中,波導103之介電常數實質上大於200。在一些實施例中,波導103之介電常數實質上大於500。
在一些實施例中,波導103包含氮化矽或碳化矽。在一些其他實施例中,波導103包含藉由任何適合沈積方法(諸如化學汽相沈積(CVD)、電漿增強CVD (PECVD)、次大氣壓CVD (SACVD)、大氣壓CVD (APCVD)、有機金屬CVD (MOCVD)、雷射CVD (LCVD)或其類似者)所沈積之二氧化矽(CVD-SiO2
)、氮化矽(SiNx)或氮氧化矽(SiOxNy)。在一些實施例中,波導103包含藉由LCVD、物理汽相沈積(PVD)、電子束(例如電子槍)蒸鍍或其類似者所沈積之低溫二氧化鈦(TiO2
)。在一些實施例中,波導103包含低溫高k介電材料,諸如二氧化鋯(ZrO2
)、氧化鋁(Al2
O3
)、氧化鉿(HfOx)、矽酸鉿(HfSiOx)、鈦酸鋯(ZrTiOx)、氧化鉭(TaOx)或其類似者。在一些實施例中,波導103包含鈦酸鍶(具有約83至約100之介電常數(k)之SrTiO3
)或鈦酸鋇(具有約500之介電常數(k)之BaTiO3
)。在一些實施例中,波導103包含高於氧化鋁(Al2
O3
)之一介電常數的一介電常數,例如約9。
在一些實施例中,上文所提及之波導103之介電材料使用一低溫沈積程序製造,低溫沈積程序使用CVD、PVD或其他沈積操作。在一些實施例中,低溫沈積程序以小於約400°C之一溫度執行。在一些實施例中,低溫沈積程序以小於約300°C之一溫度執行。在一些實施例中,低溫沈積程序以小於約250°C之一溫度執行。例如,在約180°C使用CVD形成二氧化矽,可在約240°C使用PVD形成二氧化鈦,且可在約210°C使用CVD形成高k介電材料。使用基於沈積之操作所製造之波導103可共用用於半導體結構100之其他部分之工具及程序以藉此節省時間及成本。在一些實施例中,形成波導103之操作溫度類似於形成半導體結構100之其他部分(諸如互連結構102之組件)之操作溫度。
在一些實施例中,使用一高溫操作(諸如粉末冶金)形成用於上文所提及之波導103之介電材料。例如,可在大於約400°C、大於約600°C、大於約800°C或大於約1000°C之一溫度使用粉末冶金形成二氧化鈦。在一些實施例中,使用基於非沈積之操作(例如冶金)所製造之波導103不與半導體結構100之其他部分共用工具及程序(歸因於不同程序溫度要求),且可在安置於半導體結構100中之前製備或製造。使用基於冶金之操作所製造之波導103可經製成為(例如)具有大於約50、大於約100、大於約500或大於約1000之一介電常數(k),即,大於使用一基於沈積之操作所製成之波導103之介電常數。因此,可增大波導103之傳輸頻寬及資料傳送速率且可進一步減小波導103之所需厚度。
在一些實施例中,導電部件102b進一步包含一或多個第五導電部件102b-5。第五導電部件102b-5可安置或製造於通路101c與第三導電部件102b-3之間或通路101c與第四導電部件102b-4之間。在一些實施例中,第五導電部件102b-5可安置或製造於基板101之第一表面101a與第三導電部件102b-3或第四導電部件102b-4之間。在一些實施例中,第五導電部件102b-5形成於與波導103對置之第三導電部件102b-3或第四導電部件102b-4之側上。在一些實施例中,第五導電部件102b-5接地或電連接至一接地端子且經組態以向波導103提供電屏蔽以免受外部雜訊及干擾。在一些實施例中,第五導電部件102b-5呈水平延伸且與整個波導103、第一導電部件102b-1、第二導電部件102b-2、第三導電部件102b-3及第四導電部件102b-4重疊之一碟或平板之一形狀。在一些實施例中,第五導電部件102b-5係呈一矩形形狀,其中第五導電部件102b-5彼此間隔開且彼此平行,且在一相同方向上延伸,例如垂直於波導103延伸之方向。
在一些實施例中,第一晶粒104安置於互連結構102上方。在一些實施例中,第一晶粒104安置於第一導電部件102b-1或第三導電部件102b-3上方。在一些實施例中,第一晶粒104經製造成在第一晶粒104內具有一預定功能電路。在一些實施例中,第一晶粒104藉由一機械或雷射刀自一半導體晶圓單粒化。在一些實施例中,單粒化第一晶粒104電連接至第一導電部件102b-1或第三導電部件102b-3。
在一些實施例中,第二晶粒105安置於互連結構102上方。在一些實施例中,第二晶粒105安置成相鄰於第一晶粒104。在一些實施例中,第二晶粒105安置於第二導電部件102b-2或第四導電部件102b-4上方。在一些實施例中,第二晶粒105經製造成在第二晶粒105內具有一預定功能電路。在一些實施例中,第二晶粒105藉由一機械或雷射刀自一半導體晶圓單粒化。在一些實施例中,單粒化第二晶粒105電連接至第二導電部件102b-2或第四導電部件102b-4。
在一些實施例中,第一晶粒104或第二晶粒105包括適合於一特定應用之各種電路。電路可包含諸如電晶體、電容器、電阻器、二極體或其類似者之各種裝置。在一些實施例中,電路包含經組態以產生用於透過波導103傳輸之高頻寬電信號的一振盪器。在一些實施例中,電路包含電連接至波導103且用於組態電磁信號之傳輸及接收的電晶體(圖1中未展示,但在圖3A中繪示為電路301及305及在圖3B中繪示為電路311及315)。
在一些實施例中,第一晶粒104或第二晶粒105係一晶粒、一晶片或一封裝。在一些實施例中,第一晶粒104或第二晶粒105係一邏輯裝置晶粒、一中央處理單元(CPU)晶粒、一圖形處理單元(GPU)晶粒、一行動電話應用處理(AP)晶粒、一單晶片系統(SoC)(其可將多個電子組件整合至一單一晶粒中)或一高頻寬記憶體(HBM)晶粒。在所描繪之實例中,第一晶粒104係一CPU晶粒,而第二晶粒105係一HBM晶粒。在一些實施例中,自一俯視視角看,第一晶粒104或第二晶粒105係呈四邊形、矩形或正方形形狀。
第二晶粒105可與第一晶粒104成對操作。在一些實施例中,第一晶粒104係一傳輸器晶粒或一驅動器晶粒且第二晶粒105係一接收晶粒或一接收器晶粒。在一些其他實施例中,第二晶粒105係一傳輸器晶粒或一驅動器晶粒且第一晶粒104係一接收晶粒或一接收器晶粒。在一些實施例中,傳輸器晶粒包含經組態以產生一電信號之一傳輸器電路。在一些實施例中,接收晶粒包含經組態以接收電信號之一接收電路。在一些實施例中,將由第一晶粒104 (或第二晶粒105)產生之電信號轉換為一電磁信號,且使電磁信號自第一晶粒104 (或第二晶粒105)透過波導103傳輸至第二導電部件102b-2 (或第一導電部件102b-1)或第四導電部件102b-4 (或第三導電部件102b-3),且將電磁信號轉換為由第二晶粒105 (或第一晶粒104)接收之一電信號,使得來自第一晶粒104 (或第二晶粒105)之電信號透過波導103傳輸至第二晶粒105 (或第一晶粒104)。
在一些實施例中,第一晶粒104透過一重佈層(RDL) 106及一第二導電凸塊107電連接至第一導電部件102b-1或第三導電部件102b-3。在一些實施例中,RDL 106安置或形成於互連結構102上方。在一些實施例中,RDL 106經組態以使電路之一路徑自第一晶粒104重新路由至導電部件102b以重佈第一晶粒104之I/O端子。在一些實施例中,RDL 106用作互連結構102之一最頂層。
在一些實施例中,RDL 106包含一第二介電層106a及一第二墊106b。在一些實施例中,第二介電層106a安置或沈積於介電層102a之第三層102a-3上方,且第二介電層106a亦可指稱介電層102a之一第四層102a-4。在一些實施例中,第二墊106b透過第二介電層106a部分暴露。在一些實施例中,第二墊106b電連接至導電通路102c或導電部件102b。在一些實施例中,第二墊106b延伸至第二介電層106a中。在一些實施例中,第二墊106b之一部分由第二介電層106a包圍。在一些實施例中,第二介電層106a包含諸如氧化矽、氮化矽、碳化矽、氮氧化矽或其類似者之介電材料。在一些實施例中,第二墊106b包含諸如金、銀、銅、鎳、鎢、鋁、鈀及/或其合金之導電材料。
在一些實施例中,一或多個第二導電凸塊107安置或製造於互連結構102與第一晶粒104之間。在一些實施例中,第二導電凸塊107安置於RDL 106與第一晶粒104之間。在一些實施例中,第一晶粒104透過第二導電凸塊107電連接至導電部件102b或第二墊106b。在一些實施例中,第二導電凸塊107係呈一圓柱形、球形或半球形形狀。在一些實施例中,第二導電凸塊107係一焊料接頭、一焊料凸塊、一焊球、一球柵陣列(BGA)球、一受控塌陷晶片連接(C4)凸塊或其類似者。在一些實施例中,第二導電凸塊107係一導電柱或支柱。在一些實施例中,第二導電凸塊107包含諸如鉛、錫、銅、金、鎳或其類似者之金屬。
在一些實施例中,第二晶粒105透過重佈層(RDL) 106及第二導電凸塊107電連接至第二導電部件102b-2或第四導電部件102b-4。在一些實施例中,第二晶粒105透過第二導電凸塊107電連接至RDL 106之第二墊106b。在一些實施例中,第二導電凸塊107安置於互連結構102與第二晶粒105之間。在一些實施例中,導電凸塊107安置於RDL 106與第二晶粒105之間。在一些實施例中,第二晶粒105安置於第二導電部件102b-2上方。
在一些實施例中,一底膠材料108安置或施配於RDL 106、互連結構102及基板101上方。在一些實施例中,底膠材料108包圍第二導電凸塊107。在一些實施例中,底膠材料108填充兩個相鄰第二導電凸塊107之間的空間。在一些實施例中,第一晶粒104之一側壁或第二晶粒105之一側壁與底膠材料108接觸。在一些實施例中,底膠材料108係用於保護第二導電凸塊107或固定第一晶粒104與RDL 106之間或第二晶粒105與RDL 106之間的一接合之一電絕緣黏著劑。在一些實施例中,底膠材料108包含環氧樹脂、樹脂、環氧模塑料或其類似者。
在一些實施例中,一模塑料109安置於RDL 106、互連結構102及基板101上方。在一些實施例中,模塑料109包圍第一晶粒104及第二晶粒105。在一些實施例中,模塑料109覆蓋底膠材料108。在一些實施例中,模塑料109之一部分安置於第一晶粒104與第二晶粒105之間。在一些實施例中,模塑料109之部分安置於波導103上方。在一些實施例中,第一晶粒104之一表面或第二晶粒105之一表面透過模塑料109暴露。在一些實施例中,模塑料109與第一晶粒104之側壁或第二晶粒105之側壁接觸。在一些實施例中,模塑料109可為一單層膜或一複合堆疊。在一些實施例中,模塑料109包含諸如模製底膠、環氧樹脂、樹脂或其類似者之各種介電材料。在一些實施例中,模塑料109具有一高導熱率、一低吸濕率及一高抗彎強度。
圖2係根據本發明之各種實施例之半導體結構200之一示意性橫截面圖。在一些實施例中,半導體結構200包含一基板101、一互連結構102、一波導103、一第一晶粒104及一第二晶粒105,其等具有類似於上文所描述或圖1中所繪示之類似組件之組態的組態。在一些實施例中,通路101c進一步由介電層102a (例如介電層102a之一第五層102a-5)橫向包圍。在一些實施例中,介電層102a之第五層102a-5安置或沈積於通路101c與基板101之間。在一些實施例中,第五層102a-5之組態、材料及形成方法類似於介電層102a之其他層之組態、材料及形成方法,且為簡潔起見,省略其重複描述。
在一些實施例中,半導體結構200包含一第二基板201及安置或形成於第二基板201上方之一接合墊201a。在一些實施例中,基板101安置於第二基板201上方。在一些實施例中,第一導電凸塊101e安置或製造於接合墊201a上方。在一些實施例中,接合墊201a電耦合至第一導電凸塊101e。在一些實施例中,第一晶粒104及第二晶粒105透過第一導電凸塊101e電連接至第二基板201。
在一些實施例中,第二基板201經製造成在其上具有一預定功能電路。在一些實施例中,第二基板201包含安置於第二基板201內之導電跡線及電組件,諸如電晶體、電容器及二極體。在一些實施例中,第二基板201包含諸如矽之半導電材料。在一些實施例中,第二基板201係一矽基板。在一些實施例中,第二基板201係一印刷電路板(PCB)。在一些實施例中,接合墊201a包含諸如金、銀、銅、鎳、鎢、鋁、鈀及/或其合金之導電材料。
圖3A係根據本發明之一些實施例之半導體結構100之一部分之一示意圖。在一些實施例中,半導體結構100包含一第一電路301及一第二電路305。在一些實施例中,第一電路301係安置於第一晶粒104中之一傳輸電路,且第二電路305係安置於第二晶粒105中之一接收電路。替代地,在一些實施例中,第二電路305係安置於第二晶粒105中之一傳輸電路,且第一電路301係安置於第一晶粒104中之一接收電路。在一些實施例中,波導103係連接至第一電路301及第二電路305之四埠波導。
在一些實施例中,傳輸電路301係一驅動器電路。在一些實施例中,傳輸電路301係一電晶體且包含一第一源極端子S1、一第一汲極端子D1及一第一閘極端子G1。在一些實施例中,第一源極端子S1電接地。在一些實施例中,傳輸電路301經組態以接收一輸入信號IN至第一閘極端子G1且使一電信號自第一汲極端子D1透過一傳輸線302輸出至一傳輸耦合元件303a。在一些實施例中,傳輸耦合元件303a包含一第一傳輸耦合元件303a-1及一第二傳輸耦合元件303a-2。在一些實施例中,傳輸耦合元件303a包含諸如金、銀、銅、鎳、鎢、鋁、鈀及/或其合金之一導電材料。在一些實施例中,第一傳輸耦合元件303a-1及第二傳輸耦合元件303a-2彼此對置安置。在一些實施例中,傳輸耦合元件303a-1及303a-2分別對應於圖1中之第一導電部件102b-1及第三導電部件102b-3。在一些實施例中,傳輸耦合元件303a-1及303a-2分別對應於圖1中之第三導電部件102b-3及第一導電部件102b-1。在一些實施例中,第一傳輸耦合元件303a-1及第二傳輸耦合元件303a-2之一者經組態以接收電信號,而另一者電接地。在一些實施例中,波導103之第一端103a由傳輸耦合元件303a包圍。在一些實施例中,自傳輸線302傳輸至第一傳輸耦合元件303a-1之電信號產生對應於電信號之一電磁信號,且電磁信號自波導103之第一端103a傳輸至第二端103b。
在一些實施例中,接收電路305係一接收器電路。在一些實施例中,接收電路305係一電晶體且包含一第二源極端子S2、一第二汲極端子D2及一第二閘極端子G2。在一些實施例中,第二源極端子S2電接地。在一些實施例中,接收電路305經組態以在第二閘極端子G2處接收來自一接收耦合元件303b之電信號;接收電路305進一步經組態以在第二汲極端子D2處提供一輸出信號OUT。在一些實施例中,接收耦合元件303b包含一第一接收耦合元件303b-1及一第二接收耦合元件303b-2。在一些實施例中,接收耦合元件303b包含諸如金、銀、銅、鎳、鎢、鋁、鈀及/或其合金之一導電材料。在一些實施例中,第一接收耦合元件303b-1及第二接收耦合元件303b-2彼此對置安置。在一些實施例中,第一接收耦合元件303b-1及第二接收耦合元件303b-2分別對應於第二導電部件102b-2及第四導電部件102b-4。在一些實施例中,第一接收耦合元件303b-1及第二接收耦合元件303b-2分別對應於第四導電部件102b-4及第二導電部件102b-2。在一些實施例中,第一接收耦合元件303b-1及第二接收耦合元件303b-2之一者經組態以輸出電信號,而另一者電接地。在一些實施例中,波導103之第二端103b由接收耦合元件303b包圍。在一些實施例中,沿波導103傳輸之電磁信號在接收耦合元件303b處轉換為電信號,且電信號透過傳輸線304傳輸至第二閘極端子G2。
圖3B係根據本發明之一些實施例之半導體結構100之一部分之一示意圖。在一些實施例中,圖3B中所展示之半導體結構100之部分類似於圖3A中所展示之半導體結構之部分,只是圖3B中所展示之部分包含第一電路311 (其包含第一電路311a、311b及311c)及第二電路315 (其包含第二電路315a、315b及315c)。在一些實施例中,第一電路311係安置於第一晶粒104中之傳輸電路,且第二電路315係安置於第二晶粒105中之接收電路。在一些實施例中,第一電路311係安置於第一晶粒104中之接收電路,且第二電路315係安置於第二晶粒105中之傳輸電路。在一些實施例中,波導103係六埠波導,其包含耦合至第一電路311及第二電路315之導電部件321及325。在一些實施例中,導電部件321及325包含諸如金、銀、銅、鎳、鎢、鋁、鈀及/或其合金之一導電材料。
在一些實施例中,傳輸電路311共同形成一驅動器電路。在一些實施例中,傳輸電路311之各者係一電晶體且分別包含一第一源極端子S1、一第一汲極端子D1及一第一閘極端子G1。在一些實施例中,第一電路311之各者之第一源極端子S1電接地。在一些實施例中,一傳輸耦合元件303a包含導電部件321a、321b及321c。在一些實施例中,傳輸電路311a經組態以在其第一閘極端子G1處接收一輸入信號IN且使一電信號自其第一汲極端子D1透過一傳輸線312a輸出至導電部件321a。在一些實施例中,導電部件321b透過傳輸電路311b之第一汲極端子D1及第一閘極端子G1及傳輸線312b接地,且導電部件321c透過傳輸電路311c之第一汲極端子D1及第一閘極端子G1及傳輸線312c接地。在一些實施例中,導電部件321a包含於圖1之第一導電部件102b-1中。在一些實施例中,導電部件321b或321c包含於圖1之第三導電部件102b-3中。在一些實施例中,儘管圖1中未明確繪示,但導電部件321a、321b及321c安置於波導103之一相同側上。
在一些實施例中,接收電路315共同形成一接收器電路。在一些實施例中,接收電路315之各者係一電晶體且包含一第二源極端子S2、一第二汲極端子D2及一第二閘極端子G2。在一些實施例中,第二電路315之各者之第二源極端子S2電接地。在一些實施例中,一接收耦合元件303b包含導電部件325a、325b及325c。在一些實施例中,導電部件325a經組態以接收一電磁信號,其經轉換為一電信號,電信號透過接收電路315a之第二閘極端子G2及一傳輸線314a提供至接收電路315a之第二汲極端子D2。在一些實施例中,導電部件325b透過傳輸電路315b之第二汲極端子D2及第二閘極端子G2及傳輸線314b接地,而導電部件325c透過傳輸電路315c之第二汲極端子D2及第二閘極端子G2及傳輸線314c接地。在一些實施例中,導電部件325a包含於圖1之第三導電部件102b-3中。在一些實施例中,導電部件325b或325c包含於圖1之第三導電部件102b-3中。在一些實施例中,儘管圖1中未明確繪示,但導電部件325a、325b及325c安置於波導103之一相同側上。
在本揭露中,亦揭露一種製造一半導體結構(100或200)之方法。在一些實施例中,半導體結構(100或200)由一方法400形成。方法400包含數個操作且描述及繪示不被視為限制操作序列。圖4係製造半導體結構(100或200)之方法400之一實施例。方法400包含數個操作(401、402、403、404、405、406及407)。圖4及圖4A至圖4P中所繪示之方法係例示性的。下文將提及之階段之修改(諸如階段順序改變、階段劃分及階段刪除或添加)係在本揭露之考量範疇內。
在操作401中,提供或接收基板101,如圖4A及圖4B中所展示。在一些實施例中,基板101係一半導電基板。在一些實施例中,基板101係一矽基板或一矽中介層。在一些實施例中,基板101包含一第一表面101a及與第一表面101a對置之一第二表面101b。在一些實施例中,基板101具有類似於上文所描述或參考圖1或圖2所繪示之基板之組態的一組態。
在一些實施例中,形成延伸穿過基板101之至少一部分的一通路101c。在一些實施例中,通路101c在第一表面101a與第二表面101b之間延伸。在一些實施例中,通路101c係一貫穿矽通路(TSV)。在一些實施例中,藉由移除基板101之一部分以形成第一凹槽110 (如圖4A中所展示)且在第一凹槽110中形成一導電材料以形成通路101c (如圖4B中所展示)來形成通路101c。在一些實施例中,移除基板101之部分包含光微影、蝕刻或任何其他適合操作。在一些實施例中,形成導電材料包含濺鍍、電鍍或任何其他適合操作。在一些實施例中,通路101c具有類似於上文所描述或參考圖1或圖2所繪示之通路101c之組態的一組態。在一些實施例中,在使導電材料形成至第一凹槽110中之前,在基板101上方且沿第一凹槽110之一側壁沈積一介電材料(例如圖2中之介電層102a之第五層102a-5)。在一些實施例中,介電材料包圍通路101c。在一些實施例中,將介電材料沈積於通路101c與基板101之間。在一些實施例中,將基板101上方之通路101c之一水平部分實施為互連結構102之導電部件102b之部分,例如圖1中所展示之第五導電部件102b-5。
在操作402中,將介電層102a之一第一層102a-1及一第二層102a-2相繼沈積於基板101上方,如圖4C中所展示。在一些實施例中,介電層102a之第一層102a-1或第二層102a-2係一低介電常數層。在一些實施例中,介電層102a之第一層102a-1包含二氧化矽、摻氟二氧化矽、摻碳二氧化矽、多孔二氧化矽、具有一低介電常數(低K)的一介電材料、具有一超低介電常數(ULK)的一介電材料、具有實質上小於二氧化矽之一介電常數之一介電常數的一介電材料或具有實質上小於4之一介電常數的一介電材料。在一些實施例中,藉由旋塗、化學汽相沈積(CVD)、電漿增強CVD (PECVD)、高密度電漿CVD (HDPCVD)或任何其他適合操作來沈積介電層102a之第一層102a-1或第二層102a-2。在一些實施例中,在形成第一層102a-1之後執行一平坦化操作(諸如研磨、化學機械平坦化(CMP)或其類似者)以提供第一層102a-1之一平坦化表面,其與通路101c之一上表面共面。亦可在形成第二層102a-2之後執行平坦化操作以提供第二層102a-2之一平坦表面。
在一些實施例中,在形成介電層102a之第二層102a-2之後形成導電通路102c。在一些實施例中,藉由移除介電層102a之第二層102a-2之一部分且在其內形成一導電材料來形成導電通路102c。在一些實施例中,移除介電層102a中之第二層102a-2之部分包含光微影、蝕刻或任何其他適合操作。在一些實施例中,形成導電材料包含濺鍍、電鍍或任何其他適合操作。在一些實施例中,導電通路102c具有類似於上文所描述或參考圖1或圖2所繪示之導電通路之組態的一組態。在一些實施例中,單獨或同時形成導電部件102b及一些導電通路102c。
在一些實施例中,在沈積導電通路102c之後形成導電部件102b。在一些實施例中,導電部件102b及導電通路102c形成於介電層102a之第二層102a-2內。在一些實施例中,形成包含一第三導電部件102b-3及一第四導電部件102b-4之導電部件102b。在一些實施例中,藉由移除介電層102a之第二層102a-2之一部分且安置一導電材料來形成導電部件102b。在一些實施例中,移除介電層102a中之第二層102a-2之部分包含光微影、蝕刻或任何其他適合操作以暴露導電通路102c之上表面。在一些實施例中,形成導電材料包含濺鍍、電鍍或任何其他適合操作。在一些實施例中,導電部件102b具有類似於上文所描述或參考圖1或圖2所繪示之導電部件之組態的一組態。在一些實施例中,執行導電通路102c及導電部件102b-3及102b-4之蝕刻操作,接著進行導電材料之一單一沈積操作。在一些實施例中,執行一平坦化操作(諸如研磨、化學機械平坦化(CMP)或其類似者)以移除導電部件102b之過量材料且提供與第三導電部件102b-3及第四導電部件102b-4齊平之第二層102a-2之一平坦化表面。
在操作403中,在介電層102a之第二層102a-2上方附接或形成一波導103,如圖4D至圖4H中所展示。在一些實施例中,波導103形成於導電部件102b或導電通路102c上方。在一些實施例中,波導103沈積於第三導電部件102b-3及第四導電部件102b-4上方。在一些實施例中,波導103形成於第三導電部件102b-3與第四導電部件102b-4之間。在一些實施例中,波導103耦合至第三導電部件102b-3及第四導電部件102b-4。在一些實施例中,波導103與第三導電部件102b-3及第四導電部件102b-4完全或部分重疊。
在一些實施例中,藉由將一製造波導附接至介電層102a之第二層102a-2來形成波導103,如圖4D中所展示。在一些實施例中,將波導103製造於不同於用於製造半導體結構100之剩餘部分(例如互連結構102之第二層102a-2及導電部件102b)之腔室的一腔室中。在一些實施例中,在單獨腔室中同時執行波導103及介電層102a之第二層102a-2之製造。可使用粉末冶金來形成波導103。在一些實施例中,用於製造波導103之粉末冶金方案可涉及以下操作之至少一者:製備基質粉末;將基質粉末與添加劑混合或摻合;壓實粉末;燒結;及修整壓實粉末。在一些實施例中,以高於一預定溫度(例如約400°C)之一溫度T1執行波導103之形成,其中預定溫度高於可將半導體結構100之其他部分製造成具有所要功能之溫度。在一些實施例中,溫度T1高於約600°C、高於800°C或高於約1000°C。在附接至介電層102a之前,可以一瓦片、一稜柱、一長方體、一碟、一板、一餅片或其他適合組態之一形狀製造所製造之波導103。
在一些實施例中,使用一取放(PNP)操作將波導103附接至半導體結構100。拾取所製造之波導103且藉由一黏著層422將其附接至載體420。在一些實施例中,載體420由玻璃、陶瓷、矽基板或其他適合材料製成。在一些實施例中,黏著層422包含可藉由使紫外(UV)光照射載體420來脫離載體420之一光敏材料。例如,黏著層422可為一光熱轉換(LTHC)離型膜、環氧樹脂、UV膠或其類似者。
在經拾取且附接至載體420之後,波導103在介電層102a之第二層102a-2上方移動且在一位置(例如第三導電部件102b-3與第四導電部件102b-4之間的一中心位置)處對準。使用一接合工具來使載體420與波導103一起在介電層102a之第二層102a-2上方移動且使波導103與介電層102a之第二層102a-2對準。當波導103與第二層102a-2對準時,接合工具可引起波導103接近第二層102a-2且使波導103與介電層102a之第二層102a-2之一上表面接合。波導103可與第三導電部件102b-3及第四導電部件102b-4接觸。波導103可與第三導電部件102b-3及第四導電部件102b-4完全或部分重疊。在一些實施例中,可在其上製造半導體結構100之一晶圓上及載體420上形成對準標記以促進接合工具之對準操作。
圖4E繪示半導體結構100上之一熱操作430。熱操作430可增加波導103與半導體結構100之間的接合強度。熱操作430可包含例如爐退火或快速熱退火(RTA)之退火。在一些實施例中,以約250°C之一溫度執行熱操作430達少於30分鐘,諸如約10分鐘。在一些實施例中,原位執行圖4D中所繪示之熱操作430及接合操作。
在將波導103接合至介電層102a之第二層102a-2之後,使載體420自波導103及半導體結構100釋離或脫離,如圖4F中所展示。在一些實施例中,在移除載體420期間移除或蝕刻黏著層422。圖4G繪示半導體結構100上之一熱操作440。熱操作440可在波導103與半導體結構100之間提供比由熱操作430提供之接合強度更大之永久接合強度。熱操作440可包含例如爐退火或快速熱退火(RTA)之退火。在一些實施例中,以約250°C之一溫度執行熱操作440達大於30分鐘之一時段,諸如約2小時。在一些實施例中,執行熱操作440且原位執行圖4D中所繪示之接合操作。在一些實施例中,波導103具有類似於上文所描述或圖1、圖2或圖3中所繪示之波導之組態的一組態。
在一些實施例中,將介電層102a之第三層102a-3沈積於基板101上方以橫向包圍波導103,如圖4H中所展示。在一些實施例中,形成介電層102a之第三層102a-3包含旋塗、化學汽相沈積(CVD)、電漿增強CVD (PECVD)、高密度電漿CVD (HDPCVD)、次大氣壓CVD (SACVD)、大氣壓CVD (APCVD)、有機金屬CVD (MOCVD)、雷射CVD (LCVD)、電子束(例如電子槍)蒸鍍或任何其他適合操作。波導103可具有大於介電層102a之第三層102a-3之介電常數的一介電常數。介電層102a之第三層102a-3可具有相同或不同於介電層102a之第一層102a-1或第二層102a-2之材料的一材料。圖4I繪示介電層102a之第三層102a-3上之一蝕刻操作。使介電層102a之第三層103a變薄以暴露波導103之一上表面。蝕刻操作可包含諸如化學機械拋光(CMP)、乾式蝕刻、濕式蝕刻、雷射蝕刻或任何其他適合操作之一平坦化。
在一些實施例中,在形成第三層102a-3之後,在介電層102a之第三層102a-3中形成導電通路102c。在一些實施例中,藉由移除介電層102a之第三層102a-3之一部分且在其內形成一導電材料來形成導電通路102c。在一些實施例中,移除介電層102a中之第三層102a-3之部分包含光微影、蝕刻或任何其他適合操作。在一些實施例中,形成導電材料包含濺鍍、電鍍或任何其他適合操作。在一些實施例中,執行一平坦化操作以自第三層102a-3之上表面移除導電材料之過量部分且提供與導電通路102c之上表面共面之第三層102a-3之一表面。在一些實施例中,導電通路102c具有類似於參考圖1或圖2所描述之導電通路之組態的一組態。
在操作404中,在介電層102a之第三層102a-3上方形成一第一導電部件102b-1或一第二導電部件102b-2,如圖4J中所展示。在一些實施例中,形成包含一第一導電部件102b-1及一第二導電部件102b-2之導電部件102b。在一些實施例中,波導103安置於第一導電部件102b-1與第二導電部件102b-2之間。在一些實施例中,波導103連接至第一導電部件102b-1及第二導電部件102b-2。在一些實施例中,波導103與第一導電部件102b-1及第二導電部件102b-2完全或部分重疊。
在一些實施例中,第一導電部件102b-1或第二導電部件102b-2藉由沈積一導電材料來形成於介電層102a之平坦化第三層102a-3上。在一些實施例中,安置導電材料包含濺鍍、電鍍或任何其他適合操作。在一些實施例中,第一導電部件102b-1及第二導電部件102b-2具有類似於參考圖1或圖2所描述之導電部件之組態的組態。因此,在基板101上方形成包含介電層102a、導電部件102b及導電通路102c之一互連結構102。在一些實施例中,波導103亦安置於互連結構102內。在一些實施例中,在放置波導103之前或放置波導103之後形成波導103上方之導電部件102b或導電通路102c。
在一些實施例中,在形成波導103之後,在互連結構102上方形成一RDL 106,如圖4K中所展示。在一些實施例中,形成包含第二介電層106a及第二墊106b之RDL 106。在一些實施例中,第二墊106b形成於導電部件102b上方且電連接至導電部件102b。在一些實施例中,藉由在介電層102a及導電部件102b上方安置一導電材料來形成第二墊106b。在一些實施例中,藉由濺鍍、電鍍或任何其他適合操作來形成第二墊106b。
在一些實施例中,第二介電層106a安置於介電層102a上方。在一些實施例中,藉由旋塗、化學汽相沈積(CVD)、電漿增強CVD (PECVD)、高密度電漿CVD (HDPCVD)或任何其他適合操作來沈積第二介電層106a。在一些實施例中,移除第二介電層106a之部分以至少部分暴露第二墊106b。在一些實施例中,藉由光微影、蝕刻或任何其他適合操作來移除第二介電層106a之部分。在一些實施例中,第二介電層106a及第二墊106b具有類似於參考圖1或圖2所描述之介電層及墊之組態的組態。
在一些實施例中,在第二墊106b上方製造一或多個第二導電凸塊107,如圖4K中所展示。在一些實施例中,第二導電凸塊107接合至各自第二墊106b。在一些實施例中,藉由落球、焊料粘貼、模版印刷或任何其他適合操作來製造第二導電凸塊107。在一些實施例中,在沈積之後回焊第二導電凸塊107。
在操作405中,在RDL 106上方形成及安置一第一晶粒104,如圖4L中所展示。在一些實施例中,第一晶粒104接合至基板101。在一些實施例中,第一晶粒104係一傳輸晶粒或一驅動器晶粒。在一些實施例中,第一晶粒104包含一傳輸電路或一傳輸器。在一些實施例中,第一晶粒104之傳輸電路經組態以產生一電信號。在一些實施例中,第一晶粒104電連接至第一導電部件102b-1或第三導電部件102b-3。在一些實施例中,電信號自第一晶粒104傳輸至第一導電部件102b-1或第三導電部件102b-3,參考圖3A或圖3B。在一些實施例中,第一晶粒104具有類似於參考圖1或圖2所描述之第一晶粒之組態的一組態。
在一些實施例中,第一晶粒104透過第二導電凸塊107電連接至導電部件102b或導電通路102c。在一些實施例中,第二導電凸塊107安置於第一晶粒104與RDL 106之間以將第一晶粒104電連接至第一導電部件102b-1或第三導電部件102b-3。在一些實施例中,第二導電凸塊107接合至第二墊106b,使得第一晶粒104電連接至通路101c、導電部件102b或導電通路102c。在一些實施例中,電信號自第一晶粒104透過第二導電凸塊107傳輸至第一導電部件102b-1或第三導電部件102b-3。
在操作406中,在RDL 106上方形成及安置一第二晶粒105,如圖4L中所展示。在一些實施例中,第二晶粒105安置成相鄰於第一晶粒104且與第一晶粒104間隔開。在一些實施例中,第二晶粒105係一接收晶粒或一接收器晶粒。在一些實施例中,第二晶粒105包含一接收電路或一接收器。在一些實施例中,第二晶粒105之接收電路經組態以接收電信號。在一些實施例中,第二晶粒105電連接至第二導電部件102b-2或第四導電部件102b-4。在一些實施例中,將自第一晶粒104產生之電信號轉換為一電磁信號,且使電磁信號自第一晶粒104透過波導103傳輸至第二導電部件102b-2或第四導電部件102b-4。接著,將電磁信號轉換為由第二晶粒105接收之一電信號,使得電信號自第一晶粒104透過波導103傳輸至第二晶粒105。在一些實施例中,第二晶粒105具有類似於參考圖1或圖2所描述之第二晶粒之組態的一組態。
在一些實施例中,第二晶粒105透過第二導電凸塊107電連接至導電部件102b或導電通路102c。在一些實施例中,第二導電凸塊107安置於第二晶粒105與RDL 106之間以將第二晶粒105電連接至第二導電部件102b-2或第四導電部件102b-4。在一些實施例中,第二導電凸塊107接合至第二墊106b,使得第二晶粒105電連接至通路101c、導電部件102b或導電通路102c。在一些實施例中,由第二晶粒105透過第二導電凸塊107接收透過波導103、第三導電部件102b-3或第四導電部件102b-4所傳輸之電信號。
在一些實施例中,在安置第一晶粒104及第二晶粒105之後,安置包圍第二導電凸塊107之一底膠材料108,如圖4M中所展示。在一些實施例中,底膠材料108包圍第一晶粒104及第二晶粒105且填充相鄰第二導電凸塊107之間的間隙。在一些實施例中,藉由流動、注射或任何其他適合操作來安置底膠材料108。在一些實施例中,底膠材料108具有類似於參考圖1或圖2所描述之底膠材料之組態的一組態。
在操作407中,形成一模塑料109,如圖4N中所展示。在一些實施例中,模塑料109形成於RDL 106、互連結構102及基板101上方。在一些實施例中,模塑料109包圍第一晶粒104、第二晶粒105、底膠材料108及第二導電凸塊107。在一些實施例中,藉由轉移模製、注射模製、包覆模製或任何其他適合操作形成模塑料109。在一些實施例中,研磨模塑料109以暴露第一晶粒104或第二晶粒105之一表面。在一些實施例中,藉由研磨、平坦化、化學機械拋光(CMP)或任何其他適合操作研磨模塑料109。在一些實施例中,模塑料109具有類似於參考圖1或圖2所描述之模塑料之組態的一組態。
在一些實施例中,自第二表面101b研磨基板101以暴露通路101c,如圖4O中所展示。在一些實施例中,第二表面101b經研磨以變成一新第二表面101b'。在一些實施例中,由一黏著劑將一載體暫時附接至第一晶粒104、第二晶粒105及模塑料109,且接著自第二表面101b研磨基板101。在一些實施例中,載體包含矽或玻璃。在一些實施例中,黏著劑係一光熱轉換(LTHC)釋離膜、UV膠、環氧樹脂或其類似者。在一些實施例中,藉由背面研磨、CMP或任何其他適合操作來研磨基板101。
在一些實施例中,在基板101上方形成一第一墊101d,如圖4P中所展示。在一些實施例中,第一墊101d形成於基板101之新第二表面101b'上方。在一些實施例中,第一墊101d形成於對應通路101c上方且電連接至對應通路101c。在一些實施例中,藉由在基板101上方安置一導電材料來形成第一墊101d。在一些實施例中,形成導電材料包含濺鍍、電鍍或任何其他適合操作。在一些實施例中,第一墊101d具有類似於參考圖1或圖2所描述之墊之組態的組態。
在一些實施例中,在基板101上方製造一或多個第一導電凸塊101e。在一些實施例中,第一導電凸塊101e透過通路101c電連接至導電部件102b。在一些實施例中,第一導電凸塊101e透過通路101c電連接至第一導電部件102b-1、第二導電部件102b-2、第三導電部件102b-3或第四導電部件102b-4。在一些實施例中,第一導電凸塊101e安置於第一墊101d上方。在一些實施例中,在形成波導103之前或形成波導103之後安置第一導電凸塊101e。在一些實施例中,在安置第一晶粒104及第二晶粒105之前安置第一導電凸塊101e。在一些實施例中,藉由落球、焊料粘貼、模版印刷或任何其他適合操作製造第一導電凸塊101e。在一些實施例中,在製造之後回焊第一導電凸塊101e。在一些實施例中,第一導電凸塊101e具有類似於參考圖1或圖2所描述之第一導電凸塊之組態的組態。在一些實施例中,執行一切割操作以將半導體結構100分成個別晶粒。切割或單粒化操作可由一雷射刀或其類似者執行。在一些實施例中,形成一半導體結構100,其中半導體結構100具有類似於參考圖1所描述之半導體結構之組態的一組態。
亦可包含其他構件及程序。例如,可包含測試結構來輔助3D封裝或3DIC裝置之驗證測試。測試結構可包含(例如)形成於一重佈層中或一基板上之測試墊,其允許測試3D封裝或3DIC、使用探針及/或探針卡及其類似者。可對中間結構及最終結構執行驗證測試。另外,本文中所揭露之結構及方法可與併入已知良好晶粒之中間驗證之測試方法結合使用以提高良率及降低成本。
根據一實施例,一種製造一半導體結構之方法包含:提供一基板;在該基板上方沈積一第一介電層;將一波導附接至該第一介電層;沈積一第二介電層以橫向包圍該波導;及在該第二介電層及該波導上方形成一第一導電部件及一第二導電部件,其中該第一導電部件及該第二導電部件與該波導接觸。該波導經組態以在該第一導電部件與該第二導電部件之間傳輸一電磁信號。
根據一實施例,一種製造一半導體結構之方法包含:在一基板上方沈積一介電層;在該介電層上方形成一第一導電部件及一第二導電部件;將一波導之一第一端及一第二端分別接合至該第一導電部件及該第二導電部件;及形成分別接觸該波導之該第一端及該第二端的一第三導電部件及一第四導電部件。
根據一實施例,一種半導體結構包含一基板及安置於該基板上方之一重佈層。該重佈層包括:一第一介電層,其在該基板上方;一第一導電部件及一第二導電部件,其等在該第一介電層內;一波導,其在該第一介電層上方且接合至該第一導電部件及該第二導電部件;一第二介電層,其橫向包圍該波導;一第三導電部件及一第四導電部件,其等耦合至該波導;及一第五導電部件,其在該第一介電層內且位於該第一導電部件與該基板之一表面之間。該半導體結構進一步包含在該重佈層上方且電連接至該第一導電部件之一半導體晶粒。
上文已概述若干實施例之特徵,使得熟習技術者可較佳理解本揭露之態樣。熟習技術者應瞭解,其可易於將本揭露用作設計或修改其他程序及結構以實施相同於本文中所引入之實施例之目的及/或達成相同於本文中所引入之實施例之優點的一基礎。熟習技術者亦應認識到,此等等效建構不應背離本揭露之精神及範疇,且其可在不背離本揭露之精神及範疇的情況下對本文作出各種改變、替換及變更。
100:半導體結構
101:基板
101a:第一表面
101b:第二表面
101b':新第二表面
101c:通路
101d:第一墊
101e:第一導電凸塊
102:互連結構
102a:介電層
102a-1:第一層/介電層
102a-2:第二層/介電層
102a-3:第三層/介電層
102a-4:第四層
102a-5:第五層
102b:導電部件
102b-1:第一導電部件
102b-2:第二導電部件
102b-3:第三導電部件
102b-4:第四導電部件
102b-5:第五導電部件
102c:導電通路
103:波導
103a:第一端
103b:第二端
104:第一晶粒
105:第二晶粒
106:重佈層(RDL)
106a:第二介電層
106b:第二墊
107:第二導電凸塊
108:底膠材料
109:模塑料
110:第一凹槽
200:半導體結構
201:第二基板
201a:接合墊
301:第一電路/傳輸電路
302:傳輸線
303a:傳輸耦合元件
303a-1:第一傳輸耦合元件
303a-2:第二傳輸耦合元件
303b:接收耦合元件
303b-1:第一接收耦合元件
303b-2:第二接收耦合元件
304:傳輸線
305:第二電路/接收電路
311:第一電路/傳輸電路
311a:第一電路/傳輸電路
311b:第一電路/傳輸電路
311c:第一電路/傳輸電路
312a:傳輸線
312b:傳輸線
312c:傳輸線
314a:傳輸線
314b:傳輸線
314c:傳輸線
315:第二電路/接收電路
315a:第二電路/接收電路
315b:第二電路/接收電路
315c:第二電路/接收電路
321:導電部件
321a:導電部件
321b:導電部件
321c:導電部件
325:導電部件
325a:導電部件
325b:導電部件
325c:導電部件
400:方法
401:操作
402:操作
403:操作
404:操作
405:操作
406:操作
407:操作
420:載體
422:黏著層
430:熱操作
440:熱操作
D1:第一汲極端子
D2:第二汲極端子
G1:第一閘極端子
G2:第二閘極端子
IN:輸入信號
OUT:輸出信號
S1:第一源極端子
S2:第二源極端子
自結合附圖閱讀之以下詳細描述最佳理解本揭露之態樣。應注意,根據行業標準做法,各種構件未按比例繪製。實際上,為使討論清楚,可任意增大或減小各種構件之尺寸。
圖1係根據本發明之一些實施例之一半導體結構之一示意性橫截面圖。
圖2係根據本發明之一些實施例之一半導體結構之一示意性橫截面圖。
圖3A係繪示根據本發明之一些實施例之一傳輸電路、一接收電路及一波導的一示意圖。
圖3B係繪示根據本發明之一些實施例之一傳輸電路、一接收電路及一波導的一示意圖。
圖4係根據本發明之一些實施例之製造一半導體結構之一方法之一流程圖。
圖4A至圖4P係根據本發明之一些實施例之藉由圖4之一方法製造一半導體結構之示意圖。
100:半導體結構
101:基板
101a:第一表面
101b':新第二表面
101c:通路
101d:第一墊
101e:第一導電凸塊
102:互連結構
102a-1:第一層/介電層
102a-2:第二層/介電層
102a-3:第三層/介電層
102b-1:第一導電部件
102b-2:第二導電部件
102b-3:第三導電部件
102b-4:第四導電部件
102b-5:第五導電部件
102c:導電通路
103:波導
103a:第一端
103b:第二端
104:第一晶粒
105:第二晶粒
106:重佈層(RDL)
106a:第二介電層
106b:第二墊
107:第二導電凸塊
108:底膠材料
109:模塑料
Claims (10)
- 一種製造一半導體結構之方法,其包括:提供一基板;在該基板上方沈積一第一介電層;透過粉末冶金方式製備一波導;將該波導附接至該第一介電層;沈積一第二介電層以橫向包圍該波導;及在該第二介電層及該波導上方形成一第一導電部件及一第二導電部件,該第一導電部件及該第二導電部件與該波導接觸,其中該波導經組態以在該第一導電部件與該第二導電部件之間傳輸一電磁信號。
- 如請求項1之方法,其進一步包括在將該波導附接至該第一介電層之前,將該波導附接至一載體且使該波導對準於該第一導電部件與該第二導電部件之間的一位置。
- 如請求項2之方法,其進一步包括使該載體脫離該波導且在該脫離之後對該半導體結構執行一熱操作。
- 如請求項1之方法,其進一步包括在將該波導附接至該第一介電層之後,使該半導體結構退火。
- 如請求項1之方法,其進一步包括在將該波導附接至該第一介電層之前,在不同於用於沈積該第一介電層之一第二腔室的一第一腔室中製造該波導。
- 如請求項1之方法,其進一步包括形成分別與該第一導電部件及該第二導電部件對準之一第三導電部件及一第四導電部件,其中該第三導電部件及該第四導電部件與該波導接觸。
- 一種製造一半導體結構之方法,其包括:在一基板上方沈積一介電層;在該介電層上方形成一第一導電部件及一第二導電部件;透過粉末冶金方式製備一波導;將該波導之一第一端及一第二端分別接合至該第一導電部件及該第二導電部件;及形成分別接觸該波導之該第一端及該第二端的一第三導電部件及一第四導電部件。
- 如請求項7之方法,其進一步包括:形成延伸穿過該基板之至少一部分的一導電通路;及在該基板上方安置一導電凸塊以藉由該導電通路將該第一導電部件或該第二導電部件電連接至該導電凸塊。
- 如請求項7之方法,其進一步包括: 分別在該第一導電部件及該第二導電部件上方安置一第一晶粒及一第二晶粒;及在該第一晶粒與該介電層之間或該第二晶粒與該介電層之間形成將該第一晶粒電連接至該第一導電部件或將該第二晶粒電連接至該第二導電部件之一導電凸塊。
- 一種半導體結構,其包括:一基板;一重佈層,其安置於該基板上方且包括:一第一介電層,其在該基板上方;一第一導電部件及一第二導電部件,其等在該第一介電層內;一波導,具有大於500之介電常數,其在該第一介電層上方且接合至該第一導電部件及該第二導電部件;一第二介電層,其橫向包圍該波導,其中該第二介電層的介電材料不同於該第一介電層的介電材料;一第三導電部件及一第四導電部件,其等耦合至該波導;及一第五導電部件,其在該第一介電層內且位於該第一導電部件與該基板之一表面之間;及一半導體晶粒,其在該重佈層上方且電連接至該第一導電部件。
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