TWI754821B - Common voltage decoupling circuit, touch display integrated driver using the same, and touch display device - Google Patents
Common voltage decoupling circuit, touch display integrated driver using the same, and touch display device Download PDFInfo
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Abstract
一種共通電壓解耦合電路,應用於一觸控顯示整合驅動器中,其包括:一遲滯比較器,具有一正輸入端、一負輸入端、用以輸出一第一比較信號的一第一輸出端及用以輸出一第二比較信號的一第二輸出端,其中該正輸入端與該負輸入端對應耦接一共通電壓與一共通參考電壓;一PMOS電晶體,以其閘極和源極對應耦接該遲滯比較器的該第一輸出端和一直流供電壓;以及一NMOS電晶體,以其閘極和源極對應耦接該遲滯比較器的該第二輸出端和一地電壓;其中,該PMOS電晶體的汲極與該NMOS電晶體的汲極耦接於一共接點以提供一共通電壓輸出端。A common voltage decoupling circuit, applied in a touch display integrated driver, comprises: a hysteresis comparator, which has a positive input terminal, a negative input terminal, and a first output terminal for outputting a first comparison signal and a second output terminal for outputting a second comparison signal, wherein the positive input terminal and the negative input terminal are correspondingly coupled to a common voltage and a common reference voltage; a PMOS transistor, with its gate and source correspondingly coupled to the first output terminal of the hysteresis comparator and a DC supply voltage; and an NMOS transistor, the gate and source of which are correspondingly coupled to the second output terminal of the hysteresis comparator and a ground voltage; Wherein, the drain electrode of the PMOS transistor and the drain electrode of the NMOS transistor are coupled to a common contact to provide a common voltage output terminal.
Description
本發明係關於觸控顯示整合驅動電路之技術領域,尤指設置在觸控顯示面板一觸控接收端的一種共通電壓解耦合電路。 The present invention relates to the technical field of integrated driving circuits for touch display, and more particularly, to a common voltage decoupling circuit disposed at a touch receiving end of a touch display panel.
隨著行動裝置的蓬勃發展和普及,觸控顯示裝置已經成為其中不可缺乏的零組件之一。在傳統的觸控顯示裝置之系統架構中,其觸控與顯示功能係分別由一組觸控晶片與一組顯示晶片獨立控制。然而,隨著科技之發展,應用於行動裝置之觸控顯示裝置的架構亦逐步發展為嵌入式(in-cell)架構。因此,為了使得觸控驅動電路與顯示驅動電路的電路結構及設計能夠更為簡化,近年來係發展出同時具有觸控驅動功能與顯示驅動功能之觸控顯示整合驅動積體電路(Touch And Display Driver Integration,TDDI)。 With the vigorous development and popularization of mobile devices, touch display devices have become one of the indispensable components. In the system architecture of the conventional touch display device, the touch and display functions are independently controlled by a set of touch chips and a set of display chips. However, with the development of technology, the architecture of the touch display device applied to the mobile device is gradually developed into an in-cell architecture. Therefore, in order to simplify the circuit structure and design of the touch driving circuit and the display driving circuit, in recent years, a touch and display integrated circuit (Touch And Display Integrated Circuit) with both touch driving function and display driving function has been developed. Driver Integration, TDDI).
圖1顯示一習知觸控面板之示意圖。如圖1所示,由於一面板20’上的各觸控接收點21’和一觸控顯示整合驅動積體電路10’之間有大小不一的路徑阻抗22’(由走線和開關通道構成),因此觸控顯示整合驅動積體電路10’所輸出的共通電壓VCOM對面板20’上各觸控接收點21’之驅動力會不一致。請同時參照圖2,其繪示圖1之觸控顯示整合驅動積體電路10’工作在一顯示模式時之一共通電壓驅動等效電路圖。如圖1與圖2所示,在畫面顯示期間,一共通電壓驅動器11’提供一共通電壓源以直接驅動各觸控接收點21’。然而,由於觸控顯示整合驅動積體電路10’內部有金屬走線和開關連接,因此,相鄰任二觸控接收點21’之間存在由走線和開關通道構成的路徑阻抗12’。
FIG. 1 shows a schematic diagram of a conventional touch panel. As shown in FIG. 1 , since there are
當畫素資料(SD1、SD2、SD3)改變時,各畫素資料所對應的一畫素驅動單元(未示於圖中)會輸出一步階電壓Vstep,而該步階電壓Vstep會經由一寄生電容23’和一路徑阻抗22’耦合到一個觸控接收點21’;此時,在寄生
電容23’和路徑阻抗22’之間會產生一突波電壓Vimp1且在所述觸控接收點21’會產生另一突波電壓Vimp。然而,受到路徑阻抗22’和突波電壓Vimp的影響,部分的觸控接收點21’無法在有限的充電時間內被拉到共通電壓VCOM_REF的準位,導致面板20的顯示畫面產生橫紋或豎紋。
When the pixel data (SD1, SD2, SD3) is changed, a pixel driving unit (not shown in the figure) corresponding to each pixel data will output a step voltage Vstep, and the step voltage Vstep will pass through a parasitic The capacitor 23' and a path impedance 22' are coupled to a touch receiving point 21'; at this time, the parasitic
A surge voltage Vimp1 will be generated between the capacitor 23' and the path impedance 22', and another surge voltage Vimp will be generated at the touch receiving point 21'. However, affected by the
目前,觸控顯示整合驅動積體電路之製造商已經針對上述問題提出了一解決方案。圖3顯示一改良的觸控顯示整合驅動積體電路10a工作在一顯示模式時之一共通電壓驅動等效電路圖。相較於圖2所示之觸控顯示整合驅動積體電路10’,圖3所示之改良的觸控顯示整合驅動積體電路10a更包括複數個NMOS電晶體10N’與複數個PMOS電晶體10P’;其中,各所述NMOS電晶體10N’的汲極、閘極和源極對應耦接一直流供電壓IOVCC、一共通電壓VCOM_REF和一觸控接收點21’。並且,各所述PMOS電晶體10P’的汲極、閘極和源極對應耦接一地電壓VCL、該共通電壓VCOM_REF和該觸控接收點21’。值得特別說明的是,在一畫面顯示期間,該觸控接收點21’係由該共通電壓驅動器11’驅動,使得一畫素驅動單元(未繪示於圖中)之一步階電壓Vstep經由一寄生電容23’耦合至該觸控接收點21’而在該觸控接收點21’產生一突波電壓Vimp時,若該突波電壓Vimp具有足以導通該PMOS電晶體10P’之一向上脈衝,則該PMOS電晶體10P’會提供一快速的放電路徑以縮短該突波電壓的暫態時間。相反地,若該突波電壓Vimp具有足以導通該NMOS電晶體10N’之一向下脈衝,則該NMOS電晶體10N’會提供一快速的充電路徑以縮短該突波電壓Vimp的暫態時間。依此,該觸控接收點21’即可在短時間內回到共通電壓VCOM_REF的準位。
At present, manufacturers of integrated driving ICs for touch display have proposed a solution to the above problem. FIG. 3 shows an equivalent circuit diagram of a common voltage driving when the improved touch display integrated driving IC 10a operates in a display mode. Compared with the touch display integrated driving
由上述說明可知,於改良的觸控顯示整合驅動積體電路10a之中,各所述觸控接收點21’皆耦接彼此串接(Cascade)的一NMOS電晶體10N’與一PMOS電晶體10P’;依此設計,即可藉由導通NMOS電晶體10N’的方式快速上拉該觸控接收點21’之準位至共通電壓VCOM_REF,且藉由導通PMOS電晶體10P’的方式快速下拉該觸控接收點21’之準位至共通電壓VCOM_REF。然而,當觸控接收點21’和共通電壓VCOM_REF之間的電壓差
小於一臨界電壓(Vth)時,NMOS電晶體10N’與/或PMOS電晶體10P’對於該觸控接收點21’之準位的上拉與/或下拉的效果會變得不理想。另一方面,由於NMOS電晶體10N’的基極(Body)與PMOS電晶體10P’的基極必須對應耦接低電位與高電位,導致NMOS電晶體10N’與PMOS電晶體10P’的串接結構會衍生嚴重的基極效應(Body effect)。
As can be seen from the above description, in the improved touch display integrated driving
因此,本領域亟需一種新穎的共通電壓解耦合電路。 Therefore, there is an urgent need in the art for a novel common voltage decoupling circuit.
本發明之一目的在於提供一種共通電壓解耦合電路,其可藉由一簡潔且可靠的電路設計以有效減少一觸控面板的各觸控接收點所受到的電容性脈衝干擾耦合(couple)量,以達到快速回穩一共通電壓準位的功效。 An object of the present invention is to provide a common voltage decoupling circuit, which can effectively reduce the amount of capacitive pulse interference coupled to each touch receiving point of a touch panel through a simple and reliable circuit design , in order to achieve the effect of quickly stabilizing the common voltage level.
本發明之另一目的在於提供一種共通電壓解耦合電路,其能夠顯著縮短一共通電壓信號的安定時間(Settling time)。 Another object of the present invention is to provide a common voltage decoupling circuit, which can significantly shorten the settling time of a common voltage signal.
為達成上述目的,一種共通電壓解耦合電路乃被提出,其包括:一遲滯比較器,具有一正輸入端、一負輸入端、用以輸出一第一比較信號的一第一輸出端及用以輸出一第二比較信號的一第二輸出端,其中該正輸入端與該負輸入端對應耦接一共通電壓與一共通參考電壓;一PMOS電晶體,以其閘極和源極對應耦接該遲滯比較器的所述第一輸出端和一直流供電壓;以及一NMOS電晶體,以其閘極和源極對應耦接該遲滯比較器的所述第二輸出端和一地電壓;其中,該PMOS電晶體的汲極與該NMOS電晶體的汲極耦接於一共接點,且該共接點係作為所述共通電壓解耦合電路的一共通電壓輸出端。 In order to achieve the above object, a common voltage decoupling circuit is proposed, which includes: a hysteresis comparator, which has a positive input terminal, a negative input terminal, a first output terminal for outputting a first comparison signal, and a A second output terminal for outputting a second comparison signal, wherein the positive input terminal and the negative input terminal are correspondingly coupled to a common voltage and a common reference voltage; a PMOS transistor, with its gate and source correspondingly coupled the first output terminal of the hysteresis comparator and the DC supply voltage; and an NMOS transistor, the gate and the source of which are correspondingly coupled to the second output terminal of the hysteresis comparator and a ground voltage; The drain electrode of the PMOS transistor and the drain electrode of the NMOS transistor are coupled to a common point, and the common point is used as a common voltage output terminal of the common voltage decoupling circuit.
在一實施例中,當該共通電壓低於該共通參考電壓的差值超過一第一偏移電壓時,該遲滯比較器透過該第一輸出端所輸出的該第一比較信號為低準位,以導通該PMOS電晶體而對該共通電壓輸出端的一輸出電壓執行一準位上拉操作。 In one embodiment, when the difference between the common voltage and the common reference voltage exceeds a first offset voltage, the first comparison signal output by the hysteresis comparator through the first output terminal is at a low level , to turn on the PMOS transistor to perform a level pull-up operation on an output voltage of the common voltage output terminal.
在一實施例中,當該共通電壓高於該共通參考電壓的差值超過一 第二偏移電壓時,該遲滯比較器透過該第二輸出端所輸出的該第二比較信號為高準位,以導通該NMOS電晶體而對該共通電壓輸出端的該輸出電壓執行一準位下拉操作。 In one embodiment, when the difference between the common voltage and the common reference voltage exceeds one At the second offset voltage, the second comparison signal output by the hysteresis comparator through the second output terminal is at a high level, so as to turn on the NMOS transistor and perform a level on the output voltage of the common voltage output terminal Pull down action.
在一實施例中,該共通電壓輸出端耦接一多工器的一輸入端,且該多工器的一輸出端耦接一觸控面板的一觸控接收點。 In one embodiment, the common voltage output terminal is coupled to an input terminal of a multiplexer, and an output terminal of the multiplexer is coupled to a touch receiving point of a touch panel.
另外,本發明同時提出一種觸控顯示整合驅動器,其具有如前所述之共通電壓解耦合電路。 In addition, the present invention also provides an integrated touch display driver, which has the common voltage decoupling circuit as described above.
另外,本發明又提出一種觸控顯示裝置,其包括一觸控顯示面板及耦接該觸控顯示面板的一觸控顯示整合驅動器,其中該觸控顯示整合驅動器具有如前述之共通電壓解耦合電路。 In addition, the present invention further provides a touch display device, which includes a touch display panel and a touch display integrated driver coupled to the touch display panel, wherein the touch display integrated driver has the common voltage decoupling as described above. circuit.
在可能的實施例中,所述之觸控顯示裝置可為液晶觸控顯示裝置、LED觸控顯示裝置或OLED觸控顯示裝置。 In a possible embodiment, the touch display device may be a liquid crystal touch display device, an LED touch display device or an OLED touch display device.
10:觸控顯示整合驅動器 10: Touch display integrated driver
20:面板 20: Panel
21:觸控接收點 21: Touch receiving point
22:路徑阻抗 22: Path Impedance
1:共通電壓解耦合電路 1: Common voltage decoupling circuit
11:遲滯比較器 11: Hysteresis comparator
11P:PMOS電晶體 11P: PMOS transistor
11N:NMOS電晶體 11N: NMOS transistor
CP:共接點 CP: Common Contact
3:多工器模組 3: Multiplexer module
31:多工器 31: Multiplexer
10’:觸控顯示整合驅動積體電路 10': touch display integrated driver IC
20’:面板 20': Panel
21’:觸控接收點 21': touch receiving point
22’:路徑阻抗 22': path impedance
23’:寄生電容 23': Parasitic capacitance
11’:共通電壓驅動器 11': Common voltage driver
12’:路徑阻抗 12': path impedance
10a:改良的觸控顯示整合驅動積體電路 10a: Improved touch display integrated driver IC
10N’:NMOS電晶體 10N': NMOS transistor
10P’:PMOS電晶體 10P': PMOS transistor
圖1為一習知觸控面板之示意圖;圖2為圖1之觸控顯示整合驅動積體電路工作在一顯示模式時之一共通電壓驅動等效電路圖;圖3為一改良的觸控顯示整合驅動積體電路工作在一顯示模式時之一共通電壓驅動等效電路圖;圖4顯示包含本發明之共通電壓解耦合電路的一觸控顯示裝置的示意圖;圖5繪示圖4之多個共通電壓解耦合電路、一個多工器模組及一個面板的電路架構圖;圖6繪示由圖5之共通電壓解耦合電路的共通電壓輸出端所輸出的一共通電壓VCOM的信號波形圖;以及圖7顯示圖5電路中用以輸入各個觸控接收點的共通電壓VCOM之信號波形圖。 FIG. 1 is a schematic diagram of a conventional touch panel; FIG. 2 is an equivalent circuit diagram of a common voltage driving when the integrated driving IC of FIG. 1 operates in a display mode; FIG. 3 is an improved touch display An equivalent circuit diagram of a common voltage driving when the integrated driving IC works in a display mode; FIG. 4 shows a schematic diagram of a touch display device including the common voltage decoupling circuit of the present invention; FIG. A circuit structure diagram of a common voltage decoupling circuit, a multiplexer module and a panel; FIG. 6 shows a signal waveform diagram of a common voltage VCOM output by the common voltage output terminal of the common voltage decoupling circuit of FIG. 5; And FIG. 7 shows a signal waveform diagram of the common voltage VCOM used to input each touch receiving point in the circuit of FIG. 5 .
為使 貴審查委員能進一步瞭解本發明之結構、特徵、目的、與 其優點,茲附以圖式及較佳具體實施例之詳細說明如後。 In order to enable your examiners to further understand the structure, features, purposes, and Its advantages are attached with drawings and detailed descriptions of preferred embodiments as follows.
圖4顯示包含本發明之共通電壓解耦合電路的一觸控顯示裝置的示意圖,其中,該觸控顯示裝置可為液晶觸控顯示裝置、LED(light emitting diode;發光二極體)觸控顯示裝置和OLED(organic light emitting diode;有機發光二極體)觸控顯示裝置。如圖4所示,該觸控顯示裝置的一面板20上的各觸控接收點21和一觸控顯示整合驅動器10之間有大小不一的路徑阻抗22(由走線和開關通道構成),因此,本發明將複數個所述共通電壓解耦合電路1整合於所述觸控顯示整合驅動器10之中,使得該觸控顯示整合驅動器10能夠藉由各所述共通電壓解耦合電路1提供穩定且一致的共通電壓VCOM至面板20上各個觸控接收點21。
4 shows a schematic diagram of a touch display device including the common voltage decoupling circuit of the present invention, wherein the touch display device can be a liquid crystal touch display device, an LED (light emitting diode; light emitting diode) touch display Device and OLED (organic light emitting diode; organic light emitting diode) touch display device. As shown in FIG. 4 , between each
請同時參照圖5,其繪示圖4之多個共通電壓解耦合電路1、一多工器模組3及面板20的電路架構圖。如圖4與圖5所示,本發明之共通電壓解耦合電路1包括:一遲滯比較器11、一PMOS電晶體11P以及一NMOS電晶體11N,其中遲滯比較器11具有一正輸入端、一負輸入端、用以輸出一第一比較信號PG的一第一輸出端及用以輸出一第二比較信號NG的一第二輸出端,且該正輸入端與該負輸入端對應耦接一共通電壓VCOM與一共通參考電壓VCOM_REF。另一方面,該PMOS電晶體11P以其閘極和源極對應耦接該遲滯比較器11的該第一輸出端和一直流供電壓IOVCC,且該NMOS電晶體11N以其閘極和源極對應耦接該遲滯比較器11的該第二輸出端和一地電壓VCL。
Please refer to FIG. 5 at the same time, which shows a circuit structure diagram of a plurality of common
另外,PMOS電晶體11P的汲極與NMOS電晶體11N的汲極耦接於一共接點CP,且共接點CP係作為共通電壓解耦合電路1的一共通電壓輸出端。並且,由圖4與圖5亦可知,包括複數個多工器31的一多工器模組3係耦接於面板20的一觸控接收點與觸控顯示整合驅動器10之間,使得各所述共通電壓輸出端(亦即,共接點CP)皆耦接一多工器31的一輸入端,且各多工器31的一輸出端均耦接觸控面板20的一觸控接收點21。
In addition, the drain of the
繼續地參閱圖4和圖5,並請同時參閱圖6,其繪示由圖5之共通電壓解耦合電路1的共通電壓輸出端(亦即,共接點CP)所輸出的一共通電壓
VCOM的信號波形圖。由圖6所示的共通電壓VCOM之信號波形可以發現,當一偏置的共通電壓VCOM低於所述共通參考電壓VCOM_REF的差值超過一第一偏移OS-電壓時,該遲滯比較器11透過其第一輸出端所輸出的第一比較信號PG會走向低準位(go low),使得PMOS電晶體11P被導通而對該共通電壓輸出端的一輸出電壓(亦即,共通電壓VCOM)執行一準位上拉,加速透過該共通電壓輸出端輸出的該共通電壓VCOM的準位上升至該共通參考電壓VCOM_REF的準位;相反地,當一偏置的共通電壓VCOM高於該共通參考電壓VCOM_REF的差值超過一第二偏移OS+電壓時,該遲滯比較器11透過其第二輸出端所輸出的該第二比較信號NG會走向高準位(go high),使得該NMOS電晶體11N被導通而對該共通電壓輸出端的該輸出電壓執行一準位下拉。
Continue to refer to FIGS. 4 and 5 , and please refer to FIG. 6 at the same time, which illustrates a common voltage output from the common voltage output terminal (ie, the common contact CP) of the common
圖7顯示圖5電路中用以輸入各個觸控接收點21的共通電壓VCOM之信號波形圖。於圖7中,深灰色的信號曲線用以表示習知技術(如圖2所示)之共通電壓VCOM的信號波形,而黑色的信號曲線則用以表示本發明之共通電壓解耦合電路1所輸出的共通電壓VCOM的信號波形。比較深灰色的信號曲線和黑色的信號曲線可以輕易地發現,本發明之共通電壓解耦合電路1所輸出的共通電壓VCOM受到電容性干擾脈衝之耦合(couple)量有明顯減少,同時其安定時間(Settling time)也相較於習知技術(如圖2所示)之共通電壓信號來的更短。因此,本發明之共通電壓解耦合電路1非常適用於現有的觸控顯示整合驅動器(TDDI driver IC)中,以及各種容易被耦合又需要快速回復穩壓準位的電路中。
FIG. 7 shows a signal waveform diagram of the common voltage VCOM used to input each
如此,依上述之說明,本發明的技術方案乃可應用於一觸控顯示整合驅動器中,且可進一步應用於一觸控顯示裝置之中。並且,依據前述所揭露的本發明之共通電壓解耦合電路1的有關設計,可以得知本發明乃具有以下的優點:
Thus, according to the above description, the technical solution of the present invention can be applied to a touch display integrated driver, and can be further applied to a touch display device. Moreover, according to the related design of the common
(1)本發明之共通電壓解耦合電路1可藉由一簡潔且可靠的電路設計有效減少輸入各觸控接收點21的共通電壓信號受到電容性干擾脈衝之耦合(couple)量,以達到快速回穩該共通電壓信號之電壓準位的功效。
(1) The common
(2)同時,本發明之共通電壓解耦合電路1還能夠顯著縮短所述共通電壓信號的安定時間(Settling time)。
(2) Meanwhile, the common
必須加以強調的是,前述本案所揭示者乃為較佳實施例,舉凡局部之變更或修飾而源於本案之技術思想而為熟習該項技藝之人所易於推知者,俱不脫本案之專利權範疇。 It must be emphasized that the above-mentioned disclosure in this case is a preferred embodiment, and any partial changes or modifications originating from the technical ideas of this case and easily inferred by those who are familiar with the art are within the scope of the patent of this case. category of rights.
綜上所陳,本案無論目的、手段與功效,皆顯示其迥異於習知技術,且其首先發明合於實用,確實符合發明之專利要件,懇請 貴審查委員明察,並早日賜予專利俾嘉惠社會,是為至禱。 To sum up, regardless of the purpose, means and effect of this case, it shows that it is completely different from the conventional technology, and its first invention is suitable for practical use, and indeed meets the patent requirements of the invention. Society is to pray for the best.
1:共通電壓解耦合電路 1: Common voltage decoupling circuit
11:遲滯比較器 11: Hysteresis comparator
11P:PMOS電晶體 11P: PMOS transistor
11N:NMOS電晶體 11N: NMOS transistor
20:面板 20: Panel
21:觸控接收點 21: Touch receiving point
22:路徑阻抗 22: Path Impedance
3:多工器模組 3: Multiplexer module
31:多工器 31: Multiplexer
CP:共接點 CP: Common Contact
Claims (7)
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