TWI750797B - Single-ended successive approximation register analog-to-digital converter - Google Patents

Single-ended successive approximation register analog-to-digital converter Download PDF

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TWI750797B
TWI750797B TW109130577A TW109130577A TWI750797B TW I750797 B TWI750797 B TW I750797B TW 109130577 A TW109130577 A TW 109130577A TW 109130577 A TW109130577 A TW 109130577A TW I750797 B TWI750797 B TW I750797B
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digital
capacitor
analog converter
analog
converter
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TW202211635A (en
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馬兆賢
張順志
吳皓昇
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財團法人成大研究發展基金會
奇景光電股份有限公司
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Abstract

A single-ended successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) having a first capacitor associated with a most significant bit (MSB) of the output code, and a second capacitor associated with other bit or bits of the output code; and a second DAC having a first capacitor associated with a MSB of the output code, and a second capacitor associated with other bit or bits of the output code. A bottom plate of the first capacitor of the second DAC is connected to a negative reference voltage in all phases.

Description

單端循續漸近式類比至數位轉換器Single-Ended Asymptotic Analog-to-Digital Converter

本發明係有關一種循續漸近式(SAR)類比至數位轉換器(ADC)，特別是關於一種可切換操作於單端模式或差動模式的循續漸近式類比至數位轉換器。The present invention relates to a successive asymptotic (SAR) analog-to-digital converter (ADC), and more particularly, to a successive asymptotic analog-to-digital converter switchable to operate in a single-ended mode or a differential mode.

循續漸近式類比至數位轉換器(successive approximation register analog-to-digital converter, SAR ADC)為類比至數位轉換器(ADC)的一種，用以等效轉換類比信號為數位信號。循續漸近式類比至數位轉換器藉由比較與搜尋所有可能的量化階層以執行轉換，用以得到數位輸出。相較於一般的類比至數位轉換器，循續漸近式類比至數位轉換器使用較少的電路面積與功率消耗。A successive approximation register analog-to-digital converter (SAR ADC) is a kind of analog-to-digital converter (ADC), which is used for equivalently converting an analog signal into a digital signal. A progressive analog-to-digital converter performs the conversion by comparing and searching all possible quantization levels to obtain a digital output. Compared with the general analog-to-digital converter, the progressive analog-to-digital converter uses less circuit area and power consumption.

差動(differential)循續漸近式類比至數位轉換器為循續漸近式類比至數位轉換器的一種，用以將差動類比輸入電壓數位化。單端(single-ended)循續漸近式類比至數位轉換器為另一種循續漸近式類比至數位轉換器，用以將相對於地的單一類比輸入電壓數位化。單端循續漸近式類比至數位轉換器可簡化類比至數位轉換器驅動器的要求，以降低複雜度與功耗。但是，相對於差動循續漸近式類比至數位轉換器，具有較窄的動態範圍與較差的信號雜訊比(SNR)效能。A differential DAC is a type of DAC used to digitize a differential analog input voltage. A single-ended A/D converter is another type of A/D converter that digitizes a single analog input voltage relative to ground. A single-ended progressive analog-to-digital converter simplifies the analog-to-digital converter driver requirements to reduce complexity and power consumption. However, it has a narrower dynamic range and poorer signal-to-noise ratio (SNR) performance than a differential sequential analog-to-digital converter.

由於缺少明確的電壓源，單端循續漸近式類比至數位轉換器通常遭受不當的比較基準(comparison benchmark)，因而產生不正確的輸出碼。因此亟需提出一種新穎機制，以克服傳統單端循續漸近式類比至數位轉換器的缺失。Due to the lack of a well-defined voltage source, single-ended asymptotic analog-to-digital converters often suffer from inappropriate comparison benchmarks, resulting in incorrect output codes. Therefore, there is an urgent need to propose a novel mechanism to overcome the lack of traditional single-ended step-by-step analog-to-digital converters.

鑑於上述，本發明實施例的目的之一在於提出一種單端循續漸近式類比至數位轉換器，可藉由自電荷重分配(self-charge redistribution)以自行產生比較基準。In view of the above, one of the objectives of the embodiments of the present invention is to provide a single-ended successive asymptotic analog-to-digital converter, which can generate a comparison reference by itself through self-charge redistribution.

根據本發明實施例，單端循續漸近式類比至數位轉換器包含第一數位至類比轉換器、第二數位至類比轉換器、比較器及循續漸近式控制器。第一數位至類比轉換器藉由第一取樣開關以接收輸入電壓。第二數位至類比轉換器藉由第二取樣開關以接收地電壓。比較器之正輸入節點接收第一數位至類比轉換器的第一輸出電壓，負輸入節點接收第二數位至類比轉換器的第二輸出電壓。循續漸近式控制器根據比較器的比較輸出以控制第一數位至類比轉換器與第二數位至類比轉換器的切換，用以產生輸出碼。第一數位至類比轉換器包含第一電容器與第二電容器，該第一電容器關聯於輸出碼的最高有效位元，該第二電容器關聯於輸出碼的其他位元；且第二數位至類比轉換器包含第一電容器與第二電容器，該第一電容器關聯於輸出碼的最高有效位元，該第二電容器關聯於輸出碼的其他位元。第二數位至類比轉換器的第一電容器的下板於所有時期連接至負參考電壓。According to an embodiment of the present invention, the single-ended progressive analog-to-digital converter includes a first digital-to-analog converter, a second digital-to-analog converter, a comparator, and a progressive-to-analog controller. The first digital-to-analog converter receives the input voltage through the first sampling switch. The second digital-to-analog converter receives the ground voltage through the second sampling switch. The positive input node of the comparator receives the first output voltage of the first digital-to-analog converter, and the negative input node receives the second output voltage of the second digital-to-analog converter. The successive asymptotic controller controls the switching of the first digital-to-analog converter and the second digital-to-analog converter according to the comparison output of the comparator, so as to generate an output code. The first digital-to-analog converter includes a first capacitor and a second capacitor, the first capacitor is associated with the most significant bit of the output code, the second capacitor is associated with other bits of the output code; and the second digital-to-analog conversion The device includes a first capacitor associated with the most significant bit of the output code and a second capacitor associated with the other bits of the output code. The lower plate of the first capacitor of the second digital-to-analog converter is connected to the negative reference voltage at all times.

第一A圖顯示本發明實施例之單端(single-ended)循續漸近式(SAR)類比至數位轉換器(ADC)100的方塊圖，第一B圖顯示第一A圖之單端循續漸近式類比至數位轉換器100的詳細電路圖。The first diagram A shows a block diagram of a single-ended successive asymptotic (SAR) analog-to-digital converter (ADC) 100 according to an embodiment of the present invention, and the first B diagram shows the single-ended loop of the first A diagram. A detailed circuit diagram of the asymptotic analog-to-digital converter 100 continues.

在本實施例中，單端循續漸近式類比至數位轉換器(以下簡稱類比至數位轉換器)100可包含第一數位至類比轉換器(DAC)11A，藉由第一取樣(sampling)開關SW1，於其輸入節點接收輸入電壓V i。輸入電壓V i可介於滿格(full-scale)電壓(例如1伏特)與地電壓(例如0伏特)之間。類比至數位轉換器100可包含第二數位至類比轉換器11B，藉由第二取樣開關SW2，於其輸入節點接收地電壓。 In this embodiment, the single-ended progressive analog-to-digital converter (hereinafter referred to as the analog-to-digital converter) 100 may include a first digital-to-analog converter (DAC) 11A through a first sampling switch SW1 receives the input voltage V i at its input node. The input voltage V i may be between a full-scale voltage (eg, 1 volt) and a ground voltage (eg, 0 volt). The analog-to-digital converter 100 may include a second digital-to-analog converter 11B that receives a ground voltage at its input node through a second sampling switch SW2.

本實施例之類比至數位轉換器100可包含比較器12，其正輸入節點接收第一數位至類比轉換器11A(之輸出節點)的第一輸出電壓V o1，其負輸入節點接收第二數位至類比轉換器11B(的輸出節點)的第二輸出電壓V o2。本實施例之類比至數位轉換器100可包含第一提升(boost)開關SW b1，連接於比較器12之正輸入節點與共模(common mode)提升電壓V com_boost之間，且包含第二提升開關SW b2，連接於比較器12之負輸入節點與共模提升電壓V com_boost之間。第一提升開關SW b1與第二提升開關SW b2可提升比較器12的共模電壓。 The analog-to-digital converter 100 of this embodiment may include a comparator 12 whose positive input node receives the first output voltage V o1 of the (output node of) the first digital-to-analog converter 11A, and whose negative input node receives the second digital to the second output voltage V o2 of (the output node of) the analog converter 11B. The analog-to-digital converter 100 of the present embodiment may include a first boost switch SW b1 connected between the positive input node of the comparator 12 and the common mode boost voltage V com_boost and include a second boost switch SW b1 The switch SW b2 is connected between the negative input node of the comparator 12 and the common mode boost voltage V com_boost . The first boost switch SW b1 and the second boost switch SW b2 can boost the common mode voltage of the comparator 12 .

本實施例之類比至數位轉換器100可包含循續漸近式(SAR)控制器13，根據比較器12的比較輸出以控制第一數位至類比轉換器11A與第二數位至類比轉換器11B的切換，用以依序從最高有效位元(MSB)至最低有效位元(LSB)產生輸出碼(code)。循續漸近式控制器13可根據模式信號S m以進入單端模式或差動模式。以下實施例係以單端模式作為說明。 The analog-to-digital converter 100 of the present embodiment may include a successive approximation (SAR) controller 13 for controlling the output of the first digital-to-analog converter 11A and the second digital-to-analog converter 11B according to the comparison output of the comparator 12 The switch is used to generate an output code (code) sequentially from the most significant bit (MSB) to the least significant bit (LSB). The progressive controller 13 can enter the single-ended mode or the differential mode according to the mode signal S m. The following embodiments are illustrated in single-ended mode.

第一數位至類比轉換器11A可包含第一電容器C T1、第二電容器C T2及(可選的)冗餘(redundant)電容器C redun。第一電容器C T1關聯於輸出碼的最高有效位元，第二電容器C T2則關聯於輸出碼的其他位元。在本實施例中，第二電容器C T2可代表複數併聯的電容器。第一電容器C T1、第二電容器C T2及冗餘電容器C redun的上板連接至第一數位至類比轉換器11A的輸入節點。第一電容器C T1、第二電容器C T2及冗餘電容器C redun的下板可切換至正參考電壓V refp(例如1伏特)與負參考電壓V refn(例如0伏特)。第一數位至類比轉換器11A可包含提升電容器C com_boost，連接於第一數位至類比轉換器11A的輸入節點與輸出節點之間，用以提升比較器12的共模電壓。 The first digital-to-analog converter 11A may include a first capacitor C T1 , a second capacitor C T2 and an (optional) redundant capacitor C redun . The first capacitor C T1 is associated with the most significant bit of the output code, and the second capacitor C T2 is associated with the other bits of the output code. In this embodiment, the second capacitor C T2 may represent a plurality of capacitors connected in parallel. The upper plates of the first capacitor C T1 , the second capacitor C T2 and the redundant capacitor C redun are connected to the input node of the first digital-to-analog converter 11A. The lower plates of the first capacitor C T1 , the second capacitor C T2 and the redundant capacitor C redun can be switched to a positive reference voltage V refp (eg, 1 volt) and a negative reference voltage V refn (eg, 0 volt). The first digital-to-analog converter 11A may include a boost capacitor C com_boost connected between the input node and the output node of the first digital-to-analog converter 11A for boosting the common-mode voltage of the comparator 12 .

在一實施例中，第一數位至類比轉換器11A可包第一寄生(parasitic)電容器C para1，其上板連接至第一數位至類比轉換器11A的輸入節點，其下板接收寄生電壓V para。第一數位至類比轉換器11A可包第二寄生電容器C para2，其上板連接至第一數位至類比轉換器11A的輸出節點，其下板接收寄生電壓V para。 In one embodiment, the first digital-to-analog converter 11A may include a first parasitic capacitor C para1 , the upper plate of which is connected to the input node of the first digital-to-analog converter 11A, and the lower plate of which receives the parasitic voltage V para . The first digital-to-analog converter 11A may include a second parasitic capacitor C para2 , the upper plate of which is connected to the output node of the first digital-to-analog converter 11A, and the lower plate of which receives the parasitic voltage V para .

類似的情形，第二數位至類比轉換器11B可包含第一電容器C T1、第二電容器C T2及(可選的)冗餘電容器C redun。第一電容器C T1關聯於輸出碼的最高有效位元，第二電容器C T2則關聯於輸出碼的其他位元。在本實施例中，第二電容器C T2可代表複數併聯的電容器。第一電容器C T1、第二電容器C T2及冗餘電容器C redun的上板連接至第二數位至類比轉換器11B的輸入節點。第一電容器C T1、第二電容器C T2及冗餘電容器C redun的下板可切換至正參考電壓V refp(例如1伏特)與負參考電壓V refn(例如0伏特)。第二數位至類比轉換器11B可包含提升電容器C com_boost，連接於第二數位至類比轉換器11B的輸入節點與輸出節點之間。 Similarly, the second digital-to-analog converter 11B may include a first capacitor C T1 , a second capacitor C T2 and (optionally) a redundant capacitor C redun . The first capacitor C T1 is associated with the most significant bit of the output code, and the second capacitor C T2 is associated with the other bits of the output code. In this embodiment, the second capacitor C T2 may represent a plurality of capacitors connected in parallel. The upper plates of the first capacitor C T1 , the second capacitor C T2 and the redundant capacitor C redun are connected to the input node of the second digital-to-analog converter 11B. The lower plates of the first capacitor C T1 , the second capacitor C T2 and the redundant capacitor C redun are switchable to a positive reference voltage V refp (eg, 1 volt) and a negative reference voltage V refn (eg, 0 volt). The second digital-to-analog converter 11B may include a boost capacitor C com_boost connected between the input node and the output node of the second digital-to-analog converter 11B.

在一實施例中，第二數位至類比轉換器11B可包第一寄生電容器C para1，其上板連接至第二數位至類比轉換器11B的輸入節點，其下板接收寄生電壓V para。第二數位至類比轉換器11B可包第二寄生電容器C para2，其上板連接至第二數位至類比轉換器11B的輸出節點，其下板接收寄生電壓V para。 In one embodiment, the second digital-to-analog converter 11B may include a first parasitic capacitor C para1 , the upper plate of which is connected to the input node of the second digital-to-analog converter 11B, and the lower plate of which receives the parasitic voltage V para . The second digital-to-analog converter 11B may include a second parasitic capacitor C para2 , the upper plate of which is connected to the output node of the second digital-to-analog converter 11B, and the lower plate of which receives the parasitic voltage V para .

第二A圖至第二C圖分別顯示類比至數位轉換器100於取樣前時期(或前一轉換時期的末端)、取樣時期及上板位準轉移(top-plate level shifting)時期的配置。第三圖例示(第一/第二)數位至類比轉換器11A/11B的輸入節點與輸出節點的波形。The second diagram A to the second diagram C show the configuration of the analog-to-digital converter 100 in the pre-sampling period (or the end of the previous conversion period), the sampling period and the top-plate level shifting period, respectively. The third graph illustrates the waveforms of the input nodes and output nodes of the (first/second) digital-to-analog converters 11A/11B.

於取樣時期(如第二B圖所示)，開啟(亦即，導通)第一取樣開關SW1與第二取樣開關SW2，以分別取樣輸入電壓V i與地電壓，且關閉(亦即，斷開)第一提升開關SW b1與第二提升開關SW b2。根據本實施例的特徵之一，於每一週期的所有時期，第二數位至類比轉換器11B的第一電容器C T1的下板連接至負參考電壓V refn(例如0伏特)。 During the sampling period (as shown in the second figure B), the first sampling switch SW1 and the second sampling switch SW2 are turned on (ie, turned on) to sample the input voltage V i and the ground voltage, respectively, and turned off (ie, turned off). ON) the first lift switch SW b1 and the second lift switch SW b2 . According to one of the features of this embodiment, the lower plate of the first capacitor C T1 of the second digital-to-analog converter 11B is connected to the negative reference voltage V refn (eg, 0 volts) during all periods of each cycle.

根據本實施例的另一特徵，於取樣時期，第一數位至類比轉換器11A的第一電容器C T1、第二電容器C T2及冗餘電容器C redun以及第二數位至類比轉換器11B的冗餘電容器C redun連接正參考電壓V refp，而二數位至類比轉換器11B的第二電容器C T2則連接負參考電壓V refn。在一實施例中，N-位元類比至數位轉換器100的正參考電壓V refp可表示如下： V refp=(2 N-1+C para1+C redun+(C com_boost‖C para2))/2 N-1 According to another feature of this embodiment, during the sampling period, the first capacitor C T1 , the second capacitor C T2 and the redundant capacitor C redun of the first digital-to-analog converter 11A and the redundant capacitor C redun of the second digital-to-analog converter 11B The residual capacitor C redun is connected to the positive reference voltage V refp , and the second capacitor C T2 of the DAC 11B is connected to the negative reference voltage V refn . In one embodiment, N- bit analog to digital converter is the reference voltage V refp 100 can be expressed as follows: V refp = (2 N- 1 + C para1 + C redun + (C com_boost ‖C para2)) / 2 N-1

於上板位準轉移時期(如第二C圖所示)，關閉(亦即，斷開)第一取樣開關SW1與第二取樣開關SW2，且維持關閉(亦即，斷開)第一提升開關SW b1與第二提升開關SW b2。根據本實施例的特徵之一，於上板位準轉移時期，第一數位至類比轉換器11A的第一電容器C T1、第二電容器C T2及冗餘電容器C redun以及第二數位至類比轉換器11B的冗餘電容器C redun維持連接正參考電壓V refp，第二數位至類比轉換器11B的第一電容器C T1維持連接負參考電壓V refn，但是第二數位至類比轉換器11B的第二電容器C T2連接正參考電壓V refp。跟隨在上板位準轉移時期之後的是轉換時期與預充電(pre-charging)時期。 During the transition period of the upper plate level (as shown in the second diagram C), the first sampling switch SW1 and the second sampling switch SW2 are turned off (ie, turned off), and the first boost switch is kept turned off (ie, turned off). The switch SW b1 and the second lift switch SW b2 . According to one of the features of the present embodiment, during the upper board level transition period, the first capacitor C T1 , the second capacitor C T2 and the redundant capacitor C redun of the first digital-to-analog converter 11A and the second digital-to-analog converter The redundant capacitor C redun of the converter 11B remains connected to the positive reference voltage V refp , the first capacitor C T1 of the second digital-to-analog converter 11B remains connected to the negative reference voltage V refn , but the second digital-to-analog converter 11B’s second The capacitor C T2 is connected to the positive reference voltage V refp . Following the upper plate level transfer period is a transition period and a pre-charging period.

在本實施例中，根據正參考電壓V refp的擺動，可正確產生第二數位至類比轉換器11B之輸入節點的比較基準。該比較基準係根據第二數位至類比轉換器11B之第一電容器C T1、第二電容器C T2及冗餘電容器C redun的分壓(voltage division)而產生的。 In this embodiment, according to the swing of the positive reference voltage V refp , the comparison reference of the input node of the second digital-to-analog converter 11B can be correctly generated. The comparison reference is generated according to the voltage division of the first capacitor C T1 , the second capacitor C T2 and the redundant capacitor C redun of the second digital-to-analog converter 11B.

於差動模式，差動輸入電壓(未顯示)藉由第一取樣開關SW1與第二取樣開關SW2而分別受到第一數位至類比轉換器11A與第二數位至類比轉換器11B的取樣。此外，根據循續漸近式控制器13之控制，第二數位至類比轉換器11B的第一電容器C T1的下板連接至正參考電壓V refp或負參考電壓V refn。 In the differential mode, the differential input voltage (not shown) is sampled by the first digital-to-analog converter 11A and the second digital-to-analog converter 11B through the first sampling switch SW1 and the second sampling switch SW2, respectively. In addition, according to the control of the progressive progressive controller 13, the lower plate of the first capacitor C T1 of the second digital-to-analog converter 11B is connected to the positive reference voltage V refp or the negative reference voltage V refn .

以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍內。The above descriptions are only preferred embodiments of the present invention and are not intended to limit the scope of the patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed in the invention shall be included in the following within the scope of the patent application.

100:單端循續漸近式類比至數位轉換器 11A:第一數位至類比轉換器 11B:第二數位至類比轉換器 12:比較器 13:循續漸近式控制器 SW1:第一取樣開關 SW2:第二取樣開關 SW b1:第一提升開關 SW b2:第二提升開關 S m:模式信號 C T1:第一電容器 C T2:第二電容器 C redun:冗餘電容器 C para1:第一寄生電容器 C para2:第二寄生電容器 C com_boost:提升電容器 V i:輸入電壓 V o1:第一輸出電壓 V o2:第二輸出電壓 V com_boost:共模提升電壓 V refp:正參考電壓 V refn:負參考電壓 V para:寄生電壓 100: single-ended progressive analog-to-digital converter 11A: first digital-to-analog converter 11B: second digital-to-analog converter 12: comparator 13: progressive asymptotic controller SW1: first sampling switch SW2 : second sampling switch SW b1: a first lifting switch SW b2: second lift switch S m: Tl mode signal C: a first capacitor C T2: second capacitor C redun: redundant capacitor C para1: a first parasitic capacitor C para2 : second parasitic capacitor C com_boost : boost capacitor V i : input voltage V o1 : first output voltage V o2 : second output voltage V com_boost : common mode boost voltage V refp : positive reference voltage V refn : negative reference voltage V para : parasitic voltage

第一A圖顯示本發明實施例之單端循續漸近式(SAR)類比至數位轉換器(ADC)的方塊圖。 第一B圖顯示第一A圖之單端循續漸近式類比至數位轉換器的詳細電路圖。 第二A圖至第二C圖分別顯示類比至數位轉換器於取樣前時期、取樣時期及上板位準轉移時期的配置。 第三圖例示數位至類比轉換器的輸入節點與輸出節點的波形。 The first Figure A shows a block diagram of a single-ended successive asymptotic (SAR) analog-to-digital converter (ADC) according to an embodiment of the present invention. Figure 1 B shows a detailed circuit diagram of the single-ended progressive analog-to-digital converter of Figure 1 A. The second diagram A to the second diagram C show the configuration of the analog-to-digital converter in the pre-sampling period, the sampling period, and the upper-board level transfer period, respectively. The third figure illustrates the waveforms of the input and output nodes of the digital-to-analog converter.

100:單端循續漸近式類比至數位轉換器 100: Single-Ended Asymptotic Analog-to-Digital Converter

11A:第一數位至類比轉換器 11A: First digital to analog converter

11B:第二數位至類比轉換器 11B: Second digital to analog converter

12:比較器 12: Comparator

13:循續漸近式控制器 13: Step-by-step controller

SW1:第一取樣開關 SW1: The first sampling switch

SW2:第二取樣開關 SW2: Second sampling switch

SWb1:第一提升開關 SW b1 : The first lift switch

SWb2:第二提升開關 SW b2 : Second lift switch

Sm:模式信號 S m : mode signal

Vi:輸入電壓 V i : input voltage

Vo1:第一輸出電壓 V o1 : the first output voltage

Vo2:第二輸出電壓 V o2 : the second output voltage

Vcom_boost:共模提升電壓 V com_boost : Common mode boost voltage

Claims (9)

一種單端循續漸近式類比至數位轉換器，包含：一第一數位至類比轉換器，藉由一第一取樣開關以接收輸入電壓；一第二數位至類比轉換器，藉由一第二取樣開關以接收地電壓；一比較器，其正輸入節點接收該第一數位至類比轉換器的第一輸出電壓，其負輸入節點接收該第二數位至類比轉換器的第二輸出電壓；及一循續漸近式控制器，根據該比較器的比較輸出以控制該第一數位至類比轉換器與該第二數位至類比轉換器的切換，用以產生輸出碼；其中該第一數位至類比轉換器包含第一電容器與第二電容器，該第一電容器關聯於該輸出碼的最高有效位元，該第二電容器關聯於該輸出碼的其他位元；及該第二數位至類比轉換器包含第一電容器與第二電容器，該第一電容器關聯於該輸出碼的最高有效位元，該第二電容器關聯於該輸出碼的其他位元；其中該第二數位至類比轉換器的第一電容器的下板於所有時期連接至負參考電壓；其中該第一數位至類比轉換器更包含冗餘電容器，其上板連接至該第一數位至類比轉換器的輸入節點，其下板可切換至正參考電壓與負參考電壓；且該第二數位至類比轉換器更包含冗餘電容器，其上板連接至該第二數位至類比轉換器的輸入節點，其下板可切換至正參考電壓與負參考電壓；其中於取樣時期，該第一數位至類比轉換器之冗餘電容器與該第二數位至類比轉換器之冗餘電容器切換至正參考電壓。 A single-ended progressive analog-to-digital converter, comprising: a first digital-to-analog converter through a first sampling switch to receive input voltage; a second digital-to-analog converter through a second a sampling switch to receive a ground voltage; a comparator, the positive input node of which receives the first output voltage of the first digital-to-analog converter, and the negative input node of which receives the second output voltage of the second digital-to-analog converter; and an asymptotic controller for controlling the switching of the first digital-to-analog converter and the second digital-to-analog converter according to the comparison output of the comparator to generate an output code; wherein the first digital-to-analog converter The converter includes a first capacitor and a second capacitor, the first capacitor is associated with the most significant bit of the output code, the second capacitor is associated with other bits of the output code; and the second digital-to-analog converter includes a first capacitor and a second capacitor, the first capacitor is associated with the most significant bit of the output code, the second capacitor is associated with other bits of the output code; wherein the second digital-to-analog converter is a first capacitor The lower plate of the is connected to a negative reference voltage at all times; wherein the first digital-to-analog converter further includes redundant capacitors, its upper plate is connected to the input node of the first digital-to-analog converter, and its lower plate is switchable to positive reference voltage and negative reference voltage; and the second digital-to-analog converter further includes redundant capacitors, the upper plate of which is connected to the input node of the second digital-to-analog converter, and the lower plate of which can be switched to the positive reference voltage and the a negative reference voltage; wherein during the sampling period, the redundant capacitor of the first digital-to-analog converter and the redundant capacitor of the second digital-to-analog converter are switched to a positive reference voltage. 如請求項1之單端循續漸近式類比至數位轉換器，更包含：一第一提升開關，連接於該比較器之正輸入節點與共模提升電壓之間；及一第二提升開關，連接於該比較器之負輸入節點與該共模提升電壓之間。 The single-ended progressive analog-to-digital converter of claim 1, further comprising: a first boost switch connected between the positive input node of the comparator and the common-mode boost voltage; and a second boost switch, is connected between the negative input node of the comparator and the common mode boost voltage. 如請求項1之單端循續漸近式類比至數位轉換器，其中該循續漸近式控制器根據模式信號以進入單端模式或差動模式，其中於該差動模式，一差動輸入電壓藉由該第一取樣開關與該第二取樣開關而分別受到該第一數位至類比轉換器與該第二數位至類比轉換器的取樣，且根據該循續漸近式控制器之控制，該第二數位至類比轉換器的第一電容器的下板連接至正參考電壓或該負參考電壓。 The single-ended asymptotic analog-to-digital converter of claim 1, wherein the step-by-step controller enters a single-ended mode or a differential mode according to a mode signal, wherein in the differential mode, a differential input voltage The first sampling switch and the second sampling switch are sampled by the first digital-to-analog converter and the second digital-to-analog converter, respectively, and according to the control of the successive asymptotic controller, the first The lower plate of the first capacitor of the two digital-to-analog converter is connected to the positive reference voltage or the negative reference voltage. 如請求項1之單端循續漸近式類比至數位轉換器，其中該第一數位至類比轉換器之第一電容器與第二電容器的上板連接至該第一數位至類比轉換器的輸入節點，該第二數位至類比轉換器之第一電容器與第二電容器的上板連接至該第二數位至類比轉換器的輸入節點，該第一數位至類比轉換器之第一電容器與第二電容器的下板可切換至正參考電壓與負參考電壓，且該第二數位至類比轉換器之第一電容器與第二電容器的下板可切換至正參考電壓與負參考電壓。 The single-ended progressive analog-to-digital converter of claim 1, wherein upper plates of the first capacitor and the second capacitor of the first digital-to-analog converter are connected to the input node of the first digital-to-analog converter , the upper plates of the first capacitor and the second capacitor of the second digital-to-analog converter are connected to the input node of the second digital-to-analog converter, and the first capacitor and the second capacitor of the first digital-to-analog converter The lower plate of the second digital-to-analog converter can be switched to a positive reference voltage and a negative reference voltage, and the lower plates of the first capacitor and the second capacitor of the second digital-to-analog converter can be switched to a positive reference voltage and a negative reference voltage. 如請求項1之單端循續漸近式類比至數位轉換器，其中該第一數位至類比轉換器更包含提升電容器，連接於該第一數位至類比轉換器的輸入節點與輸出節點之間，且該第二數位至類比轉換器更包含提升電容器，連接於該第二數位至類比轉換器的輸入節點與輸出節點之間。 The single-ended progressive analog-to-digital converter of claim 1, wherein the first digital-to-analog converter further comprises a boost capacitor connected between the input node and the output node of the first digital-to-analog converter, And the second digital-to-analog converter further includes a boost capacitor connected between the input node and the output node of the second digital-to-analog converter. 如請求項1之單端循續漸近式類比至數位轉換器，其中該第一數位至類比轉換器更包含：一第一寄生電容器，其上板連接至該第一數位至類比轉換器的輸入節點，其下板接收寄生電壓；及一第二寄生電容器，其上板連接至該第一數位至類比轉換器的輸出節點，其下板接收寄生電壓。 The single-ended progressive analog-to-digital converter of claim 1, wherein the first digital-to-analog converter further comprises: a first parasitic capacitor, the upper plate of which is connected to the input of the first digital-to-analog converter node, the lower plate of which receives the parasitic voltage; and a second parasitic capacitor, the upper plate of which is connected to the output node of the first digital-to-analog converter, and the lower plate of which receives the parasitic voltage. 一種單端循續漸近式類比至數位轉換器，包含：一第一數位至類比轉換器，藉由一第一取樣開關以接收輸入電壓；一第二數位至類比轉換器，藉由一第二取樣開關以接收地電壓；一比較器，其正輸入節點接收該第一數位至類比轉換器的第一輸出電壓，其負輸入節點接收該第二數位至類比轉換器的第二輸出電壓；及一循續漸近式控制器，根據該比較器的比較輸出以控制該第一數位至類比轉換器與該第二數位至類比轉換器的切換，用以產生輸出碼；其中該第一數位至類比轉換器包含第一電容器與第二電容器，該第一電容器關聯於該輸出碼的最高有效位元，該第二電容器關聯於該輸出碼的其他位元；及該第二數位至類比轉換器包含第一電容器與第二電容器，該第一電容器關聯於該輸出碼的最高有效位元，該第二電容器關聯於該輸出碼的其他位元；其中該第二數位至類比轉換器的第一電容器的下板於所有時期連接至負參考電壓；其中於取樣時期，該第一數位至類比轉換器的第一電容器與第二電容器連接正參考電壓，且該第二數位至類比轉換器的第二電容器連接負參考電壓；其中於取樣時期，開啟該第一取樣開關與該第二取樣開關，以分別取樣輸入電壓與地電壓。 A single-ended progressive analog-to-digital converter, comprising: a first digital-to-analog converter through a first sampling switch to receive input voltage; a second digital-to-analog converter through a second a sampling switch to receive a ground voltage; a comparator, the positive input node of which receives the first output voltage of the first digital-to-analog converter, and the negative input node of which receives the second output voltage of the second digital-to-analog converter; and an asymptotic controller for controlling the switching of the first digital-to-analog converter and the second digital-to-analog converter according to the comparison output of the comparator to generate an output code; wherein the first digital-to-analog converter The converter includes a first capacitor and a second capacitor, the first capacitor is associated with the most significant bit of the output code, the second capacitor is associated with other bits of the output code; and the second digital-to-analog converter includes a first capacitor and a second capacitor, the first capacitor is associated with the most significant bit of the output code, the second capacitor is associated with other bits of the output code; wherein the second digital-to-analog converter is a first capacitor The lower plate of the DAC is connected to the negative reference voltage at all periods; wherein in the sampling period, the first capacitor and the second capacitor of the first digital-to-analog converter are connected to the positive reference voltage, and the second digital-to-analog converter of the second The capacitor is connected to the negative reference voltage; in the sampling period, the first sampling switch and the second sampling switch are turned on to sample the input voltage and the ground voltage respectively. 如請求項7之單端循續漸近式類比至數位轉換器，其中於取樣時期之後的上板位準轉移時期，該第二數位至類比轉換器的第二電容器連接正參考電壓。 The single-ended asymptotic analog-to-digital converter of claim 7, wherein the second capacitor of the second digital-to-analog converter is connected to the positive reference voltage during the upper plate level transfer period after the sampling period. 如請求項8之單端循續漸近式類比至數位轉換器，其中於上板位準轉移時期，關閉該第一取樣開關與該第二取樣開關。 The single-ended asymptotic analog-to-digital converter of claim 8, wherein the first sampling switch and the second sampling switch are turned off during the upper board level transition period.
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