CN114244368A - Single-ended progressive analog-to-digital converter - Google Patents
Single-ended progressive analog-to-digital converter Download PDFInfo
- Publication number
- CN114244368A CN114244368A CN202010942403.3A CN202010942403A CN114244368A CN 114244368 A CN114244368 A CN 114244368A CN 202010942403 A CN202010942403 A CN 202010942403A CN 114244368 A CN114244368 A CN 114244368A
- Authority
- CN
- China
- Prior art keywords
- digital
- analog converter
- capacitor
- analog
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000750 progressive effect Effects 0.000 title claims abstract description 46
- 239000003990 capacitor Substances 0.000 claims abstract description 107
- 238000005070 sampling Methods 0.000 claims description 37
- 230000003071 parasitic effect Effects 0.000 claims description 19
- 230000007704 transition Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention relates to a single-ended progressive analog-to-digital converter, which comprises a first digital-to-analog converter, a second digital-to-analog converter and a control circuit, wherein the first digital-to-analog converter is provided with a first capacitor which is related to the most significant bit of an output code, and is provided with a second capacitor which is related to other bits of the output code; and a second digital-to-analog converter having a first capacitor associated with the most significant bit of the output code and a second capacitor associated with the other bits of the output code. The lower plate of the first capacitor of the second DAC is connected to the negative reference voltage at all times.
Description
Technical Field
The present invention relates to a progressive analog-to-digital converter (ADC), and more particularly, to a progressive ADC switchable between a single-ended mode and a differential mode.
Background
A progressive analog-to-digital converter (SAR ADC) is one type of analog-to-digital converter (ADC) for equivalently converting an analog signal into a digital signal. The progressive adc performs the conversion by comparing and searching all possible quantization levels to obtain a digital output. Compared with a general analog-to-digital converter, the progressive analog-to-digital converter uses less circuit area and power consumption.
A differential (differential) sequential analog-to-digital converter is one of sequential analog-to-digital converters for digitizing a differential analog input voltage. Single-ended (single-ended) progressive adc is another type of progressive adc for digitizing a single analog input voltage with respect to ground. The single-ended progressive adc simplifies the requirements of the adc driver to reduce complexity and power consumption. However, compared to the differential progressive adc, the dynamic range is narrower and the signal-to-noise ratio (SNR) performance is worse.
Due to the lack of a well-defined voltage source, single-ended progressive analog-to-digital converters typically suffer from improper comparison reference (compare benchmark), thus producing incorrect output codes. Therefore, a novel mechanism is needed to overcome the shortcomings of the conventional single-ended progressive adc.
Disclosure of Invention
In view of the foregoing, an objective of the present invention is to provide a single-ended progressive adc that can generate a comparison reference by self-charge redistribution (self-charge redistribution).
According to an embodiment of the present invention, the single-ended progressive adc includes a first digital-to-analog converter, a second digital-to-analog converter, a comparator and a progressive controller. The first digital-to-analog converter receives an input voltage through the first sampling switch. The second digital-to-analog converter receives the ground voltage through the second sampling switch. The positive input node of the comparator receives a first output voltage of the first digital-to-analog converter, and the negative input node receives a second output voltage of the second digital-to-analog converter. The progressive controller controls the switching of the first digital-to-analog converter and the second digital-to-analog converter according to the comparison output of the comparator to generate an output code. The first digital-to-analog converter comprises a first capacitor and a second capacitor, wherein the first capacitor is associated with the most significant bit of the output code, and the second capacitor is associated with other bits of the output code; and the second digital-to-analog converter includes a first capacitor associated with the most significant bit of the output code and a second capacitor associated with the other bits of the output code. The lower plate of the first capacitor of the second digital-to-analog converter is connected to a negative reference voltage at all times.
Preferably, the method further comprises: a first boost switch connected between the positive input node of the comparator and the common-mode boost voltage; and a second boost switch connected between the negative input node of the comparator and the common mode boost voltage.
Preferably, the progressive controller enters a single-ended mode or a differential mode according to a mode signal, wherein in the differential mode, a differential input voltage is sampled by the first digital-to-analog converter and the second digital-to-analog converter through the first sampling switch and the second sampling switch, respectively, and a lower plate of the first capacitor of the second digital-to-analog converter is connected to a positive reference voltage or the negative reference voltage according to the control of the progressive controller.
Preferably, wherein the upper plates of the first and second capacitors of the first digital-to-analog converter are connected to the input node of the first digital-to-analog converter, the upper plates of the first and second capacitors of the second digital-to-analog converter are connected to the input node of the second digital-to-analog converter, the lower plates of the first and second capacitors of the first digital-to-analog converter are switchable to positive and negative reference voltages, and the lower plates of the first and second capacitors of the second digital-to-analog converter are switchable to positive and negative reference voltages.
Preferably, wherein the first digital-to-analog converter further comprises a redundancy capacitor whose upper plate is connected to an input node of the first digital-to-analog converter and whose lower plate is switchable to a positive reference voltage and a negative reference voltage; and the second digital-to-analog converter further includes a redundancy capacitor having an upper plate connected to an input node of the second digital-to-analog converter and a lower plate switchable to a positive reference voltage and a negative reference voltage.
Preferably, during the sampling period, the redundancy capacitor of the first digital-to-analog converter and the redundancy capacitor of the second digital-to-analog converter are switched to the positive reference voltage.
Preferably, the first digital-to-analog converter further comprises a boost capacitor connected between the input node and the output node of the first digital-to-analog converter, and the second digital-to-analog converter further comprises a boost capacitor connected between the input node and the output node of the second digital-to-analog converter.
Preferably, the first digital-to-analog converter further comprises: a first parasitic capacitor whose upper plate is connected to an input node of the first digital-to-analog converter and whose lower plate receives a parasitic voltage; and a second parasitic capacitor whose upper plate is connected to an output node of the first digital-to-analog converter and whose lower plate receives a parasitic voltage.
Preferably, during the sampling period, the first capacitor and the second capacitor of the first digital-to-analog converter are connected with a positive reference voltage, and the second capacitor of the second digital-to-analog converter is connected with a negative reference voltage.
Preferably, in the sampling period, the first sampling switch and the second sampling switch are turned on to sample the input voltage and the ground voltage, respectively.
Preferably, the second capacitor of the second digital-to-analog converter is connected to a positive reference voltage during an upper plate level transition period after the sampling period.
Preferably, the first sampling switch and the second sampling switch are turned off during the upper plate level transition period.
By means of the technical scheme, the invention at least has the following advantages and effects: the single-ended progressive analog-to-digital converter can generate the comparison reference by self charge redistribution.
Drawings
FIG. 1A shows a block diagram of a single-ended progressive (SAR) analog-to-digital converter (ADC) according to an embodiment of the invention.
FIG. 1B shows a detailed circuit diagram of the single-ended progressive ADC of FIG. 1A.
Fig. 2A to 2C show the arrangement of the adc at the pre-sampling period, the sampling period, and the stage of the upper plate level shift, respectively.
Fig. 3 illustrates waveforms of an input node and an output node of the digital-to-analog converter.
[ description of main element symbols ]
100 single-ended progressive ADC 11A first DAC
11B second digital-to-analog converter 12 comparator
13 progressive controller SW1 first sampling switch
SW2 second sampling switch SWb1A first lifting switch
SWb2The second lifting switch SmMode signal
CT1A first capacitor CT2A second capacitor
CredunRedundancy capacitor Cpara1A first parasitic capacitor
Cpara2A second parasitic capacitor Ccom_boostHoisting capacitor
ViInput voltage Vo1A first output voltage
Vo2A second output voltage Vcom_boostCommon mode boost voltage
VrefpA positive reference voltage VrefnNegative reference voltage
VparaParasitic voltage
Detailed Description
Fig. 1A shows a block diagram of a single-ended (single-ended) progressive (SAR) analog-to-digital converter (ADC)100 according to an embodiment of the present invention, and fig. 1B shows a detailed circuit diagram of the single-ended progressive ADC 100 of fig. 1A.
In the present embodiment, the single-ended progressive analog-to-digital converter (adc)100 may include a first digital-to-analog converter (DAC)11A receiving an input voltage V at an input node thereof via a first sampling switch SW1i. Input voltage ViMay be between a full-scale voltage (e.g., 1 volt) and a ground voltage (e.g., 0 volts). The adc 100 may include a second dac 11B receiving a ground voltage at an input node thereof through a second sampling switch SW 2.
The adc 100 of the present embodiment may include a comparator 12 having a positive input node receiving the first output voltage V of the first digital-to-analog converter 11Ao1A negative input node thereof receives the second output voltage V of (the output node of) the second digital-to-analog converter 11Bo2. The analog-to-digital converter 100 of the present embodiment may include a first boost (boost) switch SWb1A positive input node connected to the comparator 12 and a common mode boost voltage Vcom_boostAnd includes a second boost switch SWb2Connected to the negative input node of the comparator 12 and the common-mode boost voltage Vcom_boostIn the meantime. First lift switch SWb1And a second boost switch SWb2The common mode voltage of the comparator 12 can be boosted.
The analog-to-digital converter 100 of the present embodiment may include a progressive (SAR) controller 13 for controlling the switching of the first digital-to-analog converter 11A and the second digital-to-analog converter 11B according to the comparison output of the comparator 12 to sequentially generate the output codes (codes) from the Most Significant Bit (MSB) to the Least Significant Bit (LSB). Progressive typeThe controller 13 can be controlled according to the mode signal SmTo enter single-ended mode or differential mode. The following examples are illustrated in single ended mode.
The first digital-to-analog converter 11A may include a first capacitor CT1A second capacitor CT2And (optional) redundant capacitor Credun. A first capacitor CT1Associated with the most significant bit of the output code, a second capacitor CT2The other bits of the output code are associated. In the present embodiment, the second capacitor CT2May represent a plurality of capacitors in parallel. A first capacitor CT1A second capacitor CT2And a redundant capacitor CredunIs connected to the input node of the first digital-to-analog converter 11A. A first capacitor CT1A second capacitor CT2And a redundant capacitor CredunCan be switched to a positive reference voltage Vrefp(e.g., 1 volt) and a negative reference voltage Vrefn(e.g., 0 volts). The first digital-to-analog converter 11A may include a boost capacitor Ccom_boostConnected between the input node and the output node of the first digital-to-analog converter 11A, for boosting the common mode voltage of the comparator 12.
In one embodiment, the first digital-to-analog converter 11A may include a first parasitic (parasitic) capacitor Cpara1An upper plate thereof connected to an input node of the first digital-to-analog converter 11A, and a lower plate thereof receiving a parasitic voltage Vpara. The first digital-to-analog converter 11A may include a second parasitic capacitor Cpara2An upper plate thereof connected to an output node of the first digital-to-analog converter 11A, and a lower plate thereof receiving a parasitic voltage Vpara。
Similarly, the second digital-to-analog converter 11B may include a first capacitor CT1A second capacitor CT2And (optional) redundant capacitor Credun. A first capacitor CT1Associated with the most significant bit of the output code, a second capacitor CT2The other bits of the output code are associated. In the present embodiment, the second capacitor CT2May represent a plurality of capacitors in parallel. A first capacitor CT1A second capacitor CT2And a redundant capacitor CredunIs connected to the input node of the second digital-to-analog converter 11B. A first capacitor CT1A second capacitor CT2And a redundant capacitor CredunCan be switched to a positive reference voltage Vrefp(e.g., 1 volt) and a negative reference voltage Vrefn(e.g., 0 volts). The second digital-to-analog converter 11B may include a boost capacitor Ccom_boostAnd is connected between the input node and the output node of the second digital-to-analog converter 11B.
In one embodiment, the second DAC 11B may include a first parasitic capacitor Cpara1An upper plate connected to an input node of the second digital-to-analog converter 11B, and a lower plate receiving a parasitic voltage Vpara. The second digital-to-analog converter 11B may include a second parasitic capacitor Cpara2An upper plate connected to an output node of the second digital-to-analog converter 11B, and a lower plate receiving a parasitic voltage Vpara。
Fig. 2A to 2C respectively show the configuration of the adc 100 during the pre-sampling period (or the end of the pre-conversion period), the sampling period, and the top-plate level shifting period. Fig. 3 illustrates waveforms of input nodes and output nodes of the (first/second) digital-to-analog converters 11A/11B.
During the sampling period (as shown in FIG. 2B), the first sampling switch SW1 and the second sampling switch SW2 are turned on (i.e., turned on) to respectively sample the input voltage ViTo ground voltage, and turns off (i.e., opens) the first boost switch SWb1And a second boost switch SWb2. According to one of the features of this embodiment, the first capacitor C of the second DAC 11B is used during all periods of each cycleT1Is connected to a negative reference voltage Vrefn(e.g., 0 volts).
According to another feature of this embodiment, during the sampling period, the first capacitor C of the first digital-to-analog converter 11AT1A second capacitor CT2And a redundant capacitor CredunAnd redundancy of the second digital-to-analog converter 11BResidual capacitor CredunConnecting a positive reference voltage VrefpAnd a second capacitor C of the two digital-to-analog converter 11BT2Then the negative reference voltage V is connectedrefn. In one embodiment, the positive reference voltage V of the N-bit ADC 100refpCan be expressed as follows:
Vrefp＝(2N-1+Cpara1+Credun+(Ccom_boost‖Cpara2))/2N-1
during the upper plate level transition period (as shown in FIG. 2C), the first and second sampling switches SW1 and SW2 are turned off (i.e., turned off), and the first lift switch SW is kept turned off (i.e., turned off)b1And a second boost switch SWb2. According to one feature of this embodiment, during the upper plate level transition period, the first capacitor C of the first DAC 11AT1A second capacitor CT2And a redundant capacitor CredunAnd a redundant capacitor C of the second digital-to-analog converter 11BredunMaintain connection to a positive reference voltage VrefpFirst capacitor C of second digital-to-analog converter 11BT1Maintain connection to negative reference voltage VrefnBut the second capacitor C of the second digital-to-analog converter 11BT2Connecting a positive reference voltage Vrefp. Following the upper plate level transition period is a transition period and a pre-charging period.
In the present embodiment, according to the positive reference voltage VrefpCan correctly generate the comparison reference of the input node of the second digital-to-analog converter 11B. The comparison reference is based on the first capacitor C of the second digital-to-analog converter 11BT1A second capacitor CT2And a redundant capacitor CredunPartial pressure (voltage division).
In the differential mode, a differential input voltage (not shown) is sampled by the first and second digital-to- analog converters 11A and 11B via the first and second sampling switches SW1 and SW2, respectively. Further, according to the control of the progressive controller 13, the second digital-to-analog converter 11BA capacitor CT1Is connected to a positive reference voltage VrefpOr a negative reference voltage Vrefn。
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (12)
1. A single-ended progressive analog-to-digital converter, comprising:
a first digital-to-analog converter for receiving an input voltage via a first sampling switch;
a second digital-to-analog converter for receiving a ground voltage through a second sampling switch;
a comparator having a positive input node receiving a first output voltage of the first digital-to-analog converter and a negative input node receiving a second output voltage of the second digital-to-analog converter; and
a progressive controller for controlling the switching between the first DAC and the second DAC according to the comparison output of the comparator to generate an output code;
wherein the first digital-to-analog converter comprises a first capacitor associated with a most significant bit of the output code and a second capacitor associated with other bits of the output code; and
the second digital-to-analog converter comprises a first capacitor and a second capacitor, the first capacitor is associated with the most significant bit of the output code, and the second capacitor is associated with other bits of the output code;
wherein the lower plate of the first capacitor of the second digital-to-analog converter is connected to a negative reference voltage at all times.
2. The single-ended progressive analog-to-digital converter of claim 1, further comprising:
a first boost switch connected between the positive input node of the comparator and the common-mode boost voltage; and
and the second lifting switch is connected between the negative input node of the comparator and the common-mode lifting voltage.
3. The single-ended progressive adc of claim 1, wherein the progressive controller enters a single-ended mode or a differential mode according to a mode signal, wherein in the differential mode, a differential input voltage is sampled by the first and second digital-to-analog converters through the first and second sampling switches, respectively, and a lower plate of a first capacitor of the second digital-to-analog converter is connected to a positive reference voltage or the negative reference voltage according to the control of the progressive controller.
4. The single-ended progressive analog-to-digital converter of claim 1, wherein upper plates of first and second capacitors of the first digital-to-analog converter are connected to an input node of the first digital-to-analog converter, upper plates of first and second capacitors of the second digital-to-analog converter are connected to an input node of the second digital-to-analog converter, lower plates of the first and second capacitors of the first digital-to-analog converter are switchable to positive and negative reference voltages, and lower plates of the first and second capacitors of the second digital-to-analog converter are switchable to positive and negative reference voltages.
5. The single-ended progressive analog-to-digital converter of claim 4, wherein the first digital-to-analog converter further comprises a redundancy capacitor having an upper plate connected to an input node of the first digital-to-analog converter and a lower plate switchable to a positive reference voltage and a negative reference voltage; and the second digital-to-analog converter further includes a redundancy capacitor having an upper plate connected to an input node of the second digital-to-analog converter and a lower plate switchable to a positive reference voltage and a negative reference voltage.
6. The single-ended progressive analog-to-digital converter of claim 5, wherein during a sampling period, the redundancy capacitors of the first digital-to-analog converter and the redundancy capacitors of the second digital-to-analog converter are switched to a positive reference voltage.
7. The single-ended progressive analog-to-digital converter of claim 1, wherein the first digital-to-analog converter further comprises a boost capacitor connected between an input node and an output node of the first digital-to-analog converter, and the second digital-to-analog converter further comprises a boost capacitor connected between an input node and an output node of the second digital-to-analog converter.
8. The single-ended progressive analog-to-digital converter of claim 1, wherein the first digital-to-analog converter further comprises:
a first parasitic capacitor whose upper plate is connected to an input node of the first digital-to-analog converter and whose lower plate receives a parasitic voltage; and
a second parasitic capacitor whose upper plate is connected to an output node of the first digital-to-analog converter and whose lower plate receives a parasitic voltage.
9. The single-ended progressive analog-to-digital converter of claim 1, wherein during a sampling period, a first capacitor and a second capacitor of the first digital-to-analog converter are connected to a positive reference voltage, and a second capacitor of the second digital-to-analog converter is connected to a negative reference voltage.
10. The single-ended progressive analog-to-digital converter of claim 9, wherein during a sampling period, the first sampling switch and the second sampling switch are turned on to sample an input voltage and a ground voltage, respectively.
11. The single-ended progressive analog-to-digital converter of claim 9, wherein a second capacitor of the second digital-to-analog converter is connected to a positive reference voltage during an upper plate level transition period after a sampling period.
12. The single-ended progressive analog-to-digital converter of claim 11, wherein the first sampling switch and the second sampling switch are turned off during an upper plate level transition period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010942403.3A CN114244368A (en) | 2020-09-09 | 2020-09-09 | Single-ended progressive analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010942403.3A CN114244368A (en) | 2020-09-09 | 2020-09-09 | Single-ended progressive analog-to-digital converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114244368A true CN114244368A (en) | 2022-03-25 |
Family
ID=80742726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010942403.3A Pending CN114244368A (en) | 2020-09-09 | 2020-09-09 | Single-ended progressive analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114244368A (en) |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030206038A1 (en) * | 2002-05-02 | 2003-11-06 | Michael Mueck | Analog-to-digital converter with the ability to asynchronously sample signals without bias or reference voltage power consumption |
| US20090273501A1 (en) * | 2008-05-01 | 2009-11-05 | Analog Devices, Inc. | Successive approximation register analog to digital converter with improved immunity to time varying noise |
| US20100188278A1 (en) * | 2009-01-28 | 2010-07-29 | Freescale Semiconductor, Inc. | Charge redistribution successive approximation analog-to-digital converter and related operating method |
| US20120112938A1 (en) * | 2010-11-08 | 2012-05-10 | Seiko Epson Corporation | A/d converter circuit, electronic apparatus and a/d conversion method |
| US20120274489A1 (en) * | 2011-04-28 | 2012-11-01 | Ncku Research And Development Foundation | Successive approximation register adc with a window predictive function |
| US20130088375A1 (en) * | 2011-10-07 | 2013-04-11 | Nxp B.V. | Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter |
| US20130249727A1 (en) * | 2012-03-22 | 2013-09-26 | Analog Devices, Inc. | Reference circuit suitable for use with an analog to digital converter and an analog to digital converter including such a reference circuit |
| TW201347417A (en) * | 2012-05-08 | 2013-11-16 | Himax Tech Ltd | Multi-bit per cycle successive approximation register ADC |
| US20150091746A1 (en) * | 2012-12-31 | 2015-04-02 | Silicon Laboratories Inc. | Successive Approximation Register Analog-to-Digital Converter With Single-Ended Measurement |
| US20180091163A1 (en) * | 2016-09-23 | 2018-03-29 | Shenzhen Goodix Technology Co. , Ltd. | Dac capacitor array, sar analog-to-digital converter and method for reducing power consumption thereof |
| US10097198B1 (en) * | 2017-05-02 | 2018-10-09 | SK Hynix Inc. | Sar adc |
| US20190097646A1 (en) * | 2017-09-28 | 2019-03-28 | Taiwan Semiconductor Manufacturing Company Limited | Low Distortion Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) and Associated Methods |
| US20190131986A1 (en) * | 2017-10-30 | 2019-05-02 | Microchip Technology Incorporated | Method and apparatus for offset correction in sar adc with reduced capacitor array dac |
| US20190253062A1 (en) * | 2016-08-30 | 2019-08-15 | Huawei Technologies Co., Ltd. | Analogue to digital converter |
| US10630310B1 (en) * | 2019-07-26 | 2020-04-21 | Nxp B.V. | Analog signal generation by hardware re-use in sampled circuits |
-
2020
- 2020-09-09 CN CN202010942403.3A patent/CN114244368A/en active Pending
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030206038A1 (en) * | 2002-05-02 | 2003-11-06 | Michael Mueck | Analog-to-digital converter with the ability to asynchronously sample signals without bias or reference voltage power consumption |
| US20090273501A1 (en) * | 2008-05-01 | 2009-11-05 | Analog Devices, Inc. | Successive approximation register analog to digital converter with improved immunity to time varying noise |
| US20100188278A1 (en) * | 2009-01-28 | 2010-07-29 | Freescale Semiconductor, Inc. | Charge redistribution successive approximation analog-to-digital converter and related operating method |
| US20120112938A1 (en) * | 2010-11-08 | 2012-05-10 | Seiko Epson Corporation | A/d converter circuit, electronic apparatus and a/d conversion method |
| US20120274489A1 (en) * | 2011-04-28 | 2012-11-01 | Ncku Research And Development Foundation | Successive approximation register adc with a window predictive function |
| US20130088375A1 (en) * | 2011-10-07 | 2013-04-11 | Nxp B.V. | Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter |
| US20130249727A1 (en) * | 2012-03-22 | 2013-09-26 | Analog Devices, Inc. | Reference circuit suitable for use with an analog to digital converter and an analog to digital converter including such a reference circuit |
| TW201347417A (en) * | 2012-05-08 | 2013-11-16 | Himax Tech Ltd | Multi-bit per cycle successive approximation register ADC |
| US20150091746A1 (en) * | 2012-12-31 | 2015-04-02 | Silicon Laboratories Inc. | Successive Approximation Register Analog-to-Digital Converter With Single-Ended Measurement |
| US20190253062A1 (en) * | 2016-08-30 | 2019-08-15 | Huawei Technologies Co., Ltd. | Analogue to digital converter |
| US20180091163A1 (en) * | 2016-09-23 | 2018-03-29 | Shenzhen Goodix Technology Co. , Ltd. | Dac capacitor array, sar analog-to-digital converter and method for reducing power consumption thereof |
| US10097198B1 (en) * | 2017-05-02 | 2018-10-09 | SK Hynix Inc. | Sar adc |
| US20190097646A1 (en) * | 2017-09-28 | 2019-03-28 | Taiwan Semiconductor Manufacturing Company Limited | Low Distortion Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) and Associated Methods |
| US20190131986A1 (en) * | 2017-10-30 | 2019-05-02 | Microchip Technology Incorporated | Method and apparatus for offset correction in sar adc with reduced capacitor array dac |
| US10630310B1 (en) * | 2019-07-26 | 2020-04-21 | Nxp B.V. | Analog signal generation by hardware re-use in sampled circuits |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7965218B2 (en) | Sar adc | |
| US7773024B2 (en) | SAR analog-to-digital converter with large input range | |
| CN108574487B (en) | Successive approximation register analog-to-digital converter | |
| US11418209B2 (en) | Signal conversion circuit utilizing switched capacitors | |
| US9774345B1 (en) | Successive approximation register analog-to-digital converter | |
| US9219489B2 (en) | Successive approximation register analog-to-digital converter | |
| EP2629428A1 (en) | A/D Converter and Method for Calibrating the Same | |
| US8570206B1 (en) | Multi-bit per cycle successive approximation register ADC | |
| US11050431B1 (en) | Single-ended successive approximation register analog-to-digital converter | |
| US20060125676A1 (en) | Analog-to-digital converter in which settling time of amplifier circuit is reduced | |
| US9467161B1 (en) | Low-power, high-speed successive approximation register analog-to-digital converter and conversion method using the same | |
| CN108631778B (en) | Successive approximation analog-to-digital converter and conversion method | |
| US8159383B2 (en) | Switched capacitor circuit and pipelined analog-to-digital conversion circuit with the switched capacitor circuit | |
| CN111371457A (en) | Analog-to-digital converter and three-level switching method applied to SAR ADC | |
| CN111641413A (en) | Capacitive array switching method of high-energy-efficiency SAR ADC | |
| KR20190071536A (en) | Successive approximation register analog digital converter and operating method thereof | |
| JP2000036746A (en) | A/d converter | |
| US10804920B2 (en) | A/D converter | |
| CN110113051B (en) | Analog-to-digital converter error shaping circuit and successive approximation type analog-to-digital converter | |
| CN115473533B (en) | FLASH-SAR ADC conversion method and circuit | |
| CN114244368A (en) | Single-ended progressive analog-to-digital converter | |
| TWI750797B (en) | Single-ended successive approximation register analog-to-digital converter | |
| CN112968704B (en) | Successive approximation type analog-to-digital converter quantization method based on transient capacitance switching mode | |
| CN114401008A (en) | Switched capacitor circuit of differential input SAR ADC and switch control method | |
| CN109039338B (en) | Differential capacitor array and switch switching method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |