TWI749823B - Internal latch circuit and method for generating latch signal thereof - Google Patents
Internal latch circuit and method for generating latch signal thereof Download PDFInfo
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本發明係有關於一種內部鎖存器電路，特別係關於一種內部鎖存器電路及其鎖存信號產生方法。The present invention relates to an internal latch circuit, and particularly relates to an internal latch circuit and a latch signal generation method thereof.
同步動態隨機存取記憶體（Synchronous Dynamic Random Access Memory，SDRAM）係為一種揮發性記憶體，其特點在於SDRAM設計為與中央處理器的計時同步化，使得記憶體控制器能夠掌握準備所要求的資料所需的準確時鐘週期，因此中央處理器不需要延後下一次的資料存取。而雙通道同步動態隨機存取記憶體（Double Data Rate SDRAM，DDR SDRAM）係為新一代的同步動態隨機存取記憶體技術，雙通道同步動態隨機存取記憶體的雙倍數據傳輸率指的就是單一周期內可讀取或寫入2次。在核心時脈不變的情況下，傳輸效率為同步動態隨機存取記憶體的2倍。Synchronous Dynamic Random Access Memory (SDRAM) is a kind of volatile memory. Its characteristic is that SDRAM is designed to synchronize with the timing of the central processing unit, so that the memory controller can master the preparation requirements. The exact clock cycle required for the data, so the central processing unit does not need to postpone the next data access. The dual-channel synchronous dynamic random access memory (Double Data Rate SDRAM, DDR SDRAM) is a new generation of synchronous dynamic random access memory technology. The double data rate of the dual-channel synchronous dynamic random access memory refers to That is, it can be read or written twice in a single cycle. When the core clock is unchanged, the transmission efficiency is twice that of synchronous dynamic random access memory.
其中，在雙倍資料傳輸率同步動態隨機存取記憶體之技術下，選取脈衝信號DQS（data strobe signal）為一重要技術，其係主要用於在一個時鐘周期內準確的區分每個傳輸周期，以便於接收方準確接收資訊。另外，雙倍資料傳輸率同步動態隨機存取記憶體在執行寫入操作時，DQS與寫入信號無法立刻寫入記憶體中，而是需要一段時間的延遲，因而將該延遲的時間週期定義為DQS相對於寫入信號的延遲時間tDQSS（WRITE Command to the first corresponding rising edge of DQS），為了穩定的執行寫入操作，在標準規格下，規定了tDQSS的最小值（tCK x 0.75）和最大值（tCK x 1.25）。Among them, in the double data transfer rate synchronous dynamic random access memory technology, the pulse signal DQS (data strobe signal) is selected as an important technology, which is mainly used to accurately distinguish each transmission cycle within a clock cycle , So that the receiver can accurately receive the information. In addition, when the double data transfer rate synchronous dynamic random access memory is performing a write operation, DQS and write signals cannot be written into the memory immediately, but a delay is required, so the delay time period is defined It is the delay time tDQSS (WRITE Command to the first corresponding rising edge of DQS) of the DQS relative to the write signal. In order to perform the write operation stably, under the standard specifications, the minimum and maximum values of tDQSS (tCK x 0.75) are specified Value (tCK x 1.25).
請參閱圖1及圖2所示，圖1為習用技術之內部鎖存器電路的示意性電路方塊圖；圖2為說明輸入延遲信號的上升邊緣以及下降邊緣的改變示意圖。在雙倍資料傳輸率同步動態隨機存取記憶體之技術下，習用技術會產生鎖存信號以確保寫入操作穩定的執行，然而由於外部環境的溫度或者金屬氧化物半導體場效電晶體（Metal-Oxide-Semiconductor Field-Effect Transistor）之製成技術，會造成輸入延遲信號的延遲時間tDQSS發生變化，更詳而言之，輸入延遲信號的上升邊緣以及下降邊緣由於外部環境的溫度或者製成技術而發生改變。如圖2所示，輸入延遲信號WR_LAT_P1為延遲時間tDQSS在正常情況下之輸入延遲信號，第一輸入延遲信號WR_LAT_P1#1為延遲時間tDQSS過短情況下所產生之輸入延遲信號，第二輸入延遲信號WR_LAT_P1#2為延遲時間tDQSS過長情況下所產生之輸入延遲信號。由於輸入延遲信號WR_LAT_P1的上升邊緣以及下降邊緣發生改變，以致如圖1所示的習用技術之內部鎖存器電路，其係受到延遲信號WR_LAT_P1的上升邊緣以及下降邊緣發生改變的影響，將無法正確的產生鎖存信號，造成雙通道同步動態隨機存取記憶體無法穩定的執行寫入操作。Please refer to FIGS. 1 and 2. FIG. 1 is a schematic circuit block diagram of the internal latch circuit of the conventional technology; FIG. 2 is a schematic diagram illustrating the change of the rising edge and the falling edge of the input delay signal. Under the double data transfer rate synchronous dynamic random access memory technology, the conventional technology will generate a latch signal to ensure the stable execution of the write operation. However, due to the temperature of the external environment or the metal oxide semiconductor field effect transistor (Metal -Oxide-Semiconductor Field-Effect Transistor) manufacturing technology will cause the delay time tDQSS of the input delay signal to change. More specifically, the rising edge and falling edge of the input delay signal are due to the temperature of the external environment or the manufacturing technology And it changes. As shown in Figure 2, the input delay signal WR_LAT_P1 is the input delay signal of the delay time tDQSS under normal conditions, the first input delay
是以，本案發明人在觀察上述缺失後，而遂有本發明之產生。Therefore, after observing the above-mentioned deficiencies, the inventors of the present case came up with the present invention.
本發明的目的係提供一種內部鎖存器電路，其係藉由複數低初始值D型正反器以及複數高初始值D型正反器，基於該內部選取脈衝信號並響應輸入延遲信號，以產生第一內部輸入信號、第一反向內部輸入信號、第二內部輸入信號以及第二反向內部輸入信號，並傳輸至內部鎖存信號產生電路，再藉由該內部鎖存信號產生電路輸出第一反向前輸出信號以及第二反向前輸出信號，最後通過反及閘產生內部鎖存信號，藉此消除輸入延遲信號的延遲時間tDQSS對內部鎖存信號影響，以確保穩定的執行記憶體的寫入操作，並減少延遲時間tDQSS對於對記憶體的寫入操作之影響。The object of the present invention is to provide an internal latch circuit, which uses a complex low initial value D-type flip-flop and a complex high initial value D-type flip-flop based on the internally selected pulse signal and responds to the input delay signal to Generate a first internal input signal, a first inverted internal input signal, a second internal input signal, and a second inverted internal input signal, and transmit them to the internal latch signal generating circuit, and then output by the internal latch signal generating circuit The first output signal before the reverse direction and the second output signal before the reverse direction. Finally, the internal latch signal is generated through the inverter to eliminate the influence of the delay time tDQSS of the input delay signal on the internal latch signal to ensure stable execution memory It also reduces the impact of the delay time tDQSS on the write operation to the memory.
為達上述目的，本發明提供一種內部鎖存器電路，其係包含：一第一延遲電路，其係接收一輸入延遲信號以及一內部選取脈衝信號，並且輸出一第一內部輸入信號，其中該輸入延遲信號響應一時脈信號； 一第二延遲電路，其係耦接該第一延遲電路，該第二延遲電路係接收該內部選取脈衝信號，並且輸出一第一反向內部輸入信號；一第三延遲電路，其係耦接該第二延遲電路，該第三延遲電路係接收該內部選取脈衝信號，並且輸出一第二內部輸入信號；一第四延遲電路，其係耦接該第三延遲電路，該第四延遲電路係接收該內部選取脈衝信號，並且輸出一第二反向內部輸入信號；一內部鎖存信號產生電路，其係耦接該第一延遲電路、該第二延遲電路、該第三延遲電路、以及該第四延遲電路，該內部鎖存信號產生電路依據該第一內部輸入信號以及該第一反向內部輸入信號產生一第一反向前輸出信號，並且依據該第二內部輸入信號以及該第二反向內部輸入信號產生一第二反向前輸出信號；一反及閘，其係耦接該內部鎖存信號產生電路，該反及閘依據該第一反向前輸出信號以及該第二反向前輸出信號產生一內部鎖存信號。To achieve the above objective, the present invention provides an internal latch circuit, which includes: a first delay circuit, which receives an input delay signal and an internal selection pulse signal, and outputs a first internal input signal, wherein the The input delay signal responds to a clock signal; a second delay circuit, which is coupled to the first delay circuit, and the second delay circuit receives the internal selection pulse signal and outputs a first inverted internal input signal; A three delay circuit, which is coupled to the second delay circuit, the third delay circuit receives the internally selected pulse signal, and outputs a second internal input signal; a fourth delay circuit, which is coupled to the third delay circuit Circuit, the fourth delay circuit receives the internal selection pulse signal, and outputs a second inverted internal input signal; an internal latch signal generation circuit, which is coupled to the first delay circuit, the second delay circuit, The third delay circuit and the fourth delay circuit, the internal latch signal generating circuit generates a first pre-reverse output signal according to the first internal input signal and the first reverse internal input signal, and according to the first Two internal input signals and the second reverse internal input signal generate a second pre-reverse output signal; a flip and gate, which is coupled to the internal latch signal generating circuit, the flip and gate according to the first reverse The front output signal and the second reverse front output signal generate an internal latch signal.
較佳地，根據本發明之內部鎖存器電路，其中，該第一延遲電路、該第二延遲電路、該第三延遲電路、以及該第四延遲電路係以D正反器、JK正反器、以及SR正反器的至少其中之一來予以施行。Preferably, according to the internal latch circuit of the present invention, the first delay circuit, the second delay circuit, the third delay circuit, and the fourth delay circuit are D flip-flops, JK positive and negative At least one of the inverter and the SR flip-flop.
較佳地，根據本發明之內部鎖存器電路，其係進一步包含一重置輸入端，其係耦接該第一延遲電路、該第二延遲電路、該第三延遲電路、以及該第四延遲電路，該重置輸入端用於輸入一反向重置信號。Preferably, the internal latch circuit according to the present invention further includes a reset input terminal, which is coupled to the first delay circuit, the second delay circuit, the third delay circuit, and the fourth delay circuit. Delay circuit, the reset input terminal is used to input a reverse reset signal.
進一步地，根據本發明一實施例提供一種內部鎖存器電路，其係具有複數低初始值D型正反器以及複數高初始值D型正反器，該內部鎖存器電路包括：一第一低初始值D型正反器，其係接收一輸入延遲信號以及一內部選取脈衝信號，其中該輸入延遲信號響應一時脈信號；一第二低初始值D型正反器，其係耦接該第一低初始值D型正反器，該第二低初始值D型正反器係接收該內部選取脈衝信號，並且該第二低初始值D型正反器輸出一第一內部輸入信號；一第一高初始值D型正反器，其係耦接該第二低初始值D型正反器，該第一高初始值D型正反器係接收該內部選取脈衝信號；一第三低初始值D型正反器，其係耦接該第一高初始值D型正反器，該第三低初始值D型正反器係接收該內部選取脈衝信號，並且該第三低初始值D型正反器輸出一第一反向內部輸入信號；一第二高初始值D型正反器，其係耦接該第三低初始值D型正反器，該第二高初始值D型正反器係接收該內部選取脈衝信號；一第四低初始值D型正反器，其係耦接該第二高初始值D型正反器，該第四低初始值D型正反器係接收該內部選取脈衝信號，並且該第四低初始值D型正反器輸出一第二內部輸入信號；一第三高初始值D型正反器，其係耦接該第四低初始值D型正反器，該第三高初始值D型正反器係接收該內部選取脈衝信號；一第五低初始值D型正反器，其係耦接該第三高初始值D型正反器，該第五低初始值D型正反器係接收該內部選取脈衝信號，並且該第五低初始值D型正反器輸出一第二反向內部輸入信號；其中，該第一低初始值D型正反器及該第二低初始值D型正反器組成該第一延遲電路，該第一高初始值D型正反器及該第三低初始值D型正反器組成該第二延遲電路，該第二高初始值D型正反器及該第四低初始值D型正反器組成該第三延遲電路，該第三高初始值D型正反器及該第五低初始值D型正反器組成該第四延遲電路。Further, according to an embodiment of the present invention, an internal latch circuit is provided, which has a complex low initial value D-type flip-flop and a complex high initial value D-type flip-flop. The internal latch circuit includes: a first A low-initial D-type flip-flop, which receives an input delay signal and an internal selection pulse signal, wherein the input delay signal responds to a clock signal; a second low-initial D-type flip-flop, which is coupled The first low initial value D-type flip-flop, the second low initial value D-type flip-flop receives the internal selection pulse signal, and the second low initial value D-type flip-flop outputs a first internal input signal ; A first high initial value D-type flip-flop, which is coupled to the second low initial value D-type flip-flop, the first high initial value D-type flip-flop receiving the internally selected pulse signal; The three-low initial value D-type flip-flop, which is coupled to the first high-initial-value D-type flip-flop, the third low-initial-value D-type flip-flop receives the internally selected pulse signal, and the third low The initial value D-type flip-flop outputs a first reverse internal input signal; a second high initial value D-type flip-flop, which is coupled to the third low initial value D-type flip-flop, the second high initial value The value D-type flip-flop receives the internally selected pulse signal; a fourth low-initial-value D-type flip-flop, which is coupled to the second high-initial-value D-type flip-flop, and the fourth low-initial-value D-type The flip-flop receives the internally selected pulse signal, and the fourth low initial value D-type flip-flop outputs a second internal input signal; a third high initial value D-type flip-flop is coupled to the fourth A low-initial D-type flip-flop, the third high-initial-value D-type flip-flop receives the internally selected pulse signal; a fifth-low-initial D-type flip-flop, which is coupled to the third high-initial value D-type flip-flop, the fifth low initial value D-type flip-flop receives the internal selection pulse signal, and the fifth low initial value D-type flip-flop outputs a second reverse internal input signal; wherein, the The first low initial value D-type flip-flop and the second low initial value D-type flip-flop constitute the first delay circuit, the first high initial value D-type flip-flop and the third low initial value D-type flip-flop The inverter constitutes the second delay circuit, the second high initial value D-type flip-flop and the fourth low initial value D-type flip-flop constitute the third delay circuit, and the third high initial value D-type flip-flop And the fifth low initial value D-type flip-flop constitute the fourth delay circuit.
較佳地，根據本發明之內部鎖存器電路，其中，該低初始值D型正反器具有一輸入端、一輸出端、一反向輸出端、以及一內部選取脈衝輸入端。Preferably, according to the internal latch circuit of the present invention, the low initial value D-type flip-flop has an input terminal, an output terminal, a reverse output terminal, and an internal selection pulse input terminal.
較佳地，根據本發明之內部鎖存器電路，其中，該高初始值D型正反器具有一輸入端、一輸出端、一反向輸出端、以及一內部選取脈衝輸入端。Preferably, according to the internal latch circuit of the present invention, the high initial value D-type flip-flop has an input terminal, an output terminal, a reverse output terminal, and an internal selection pulse input terminal.
較佳地，根據本發明之內部鎖存器電路，其中，該第一低初始值D型正反器具有第一輸入端、第一輸出端、第一反向輸出端、以及第一內部選取脈衝輸入端，其中該第一輸入端係接收該輸入延遲信號，該第一內部選取脈衝輸入端接收該內部選取脈衝信號；該第二低初始值D型正反器具有第二輸入端、第二輸出端、第二反向輸出端、以及第二內部選取脈衝輸入端，其中，該第二輸入端係連接該第一輸出端，該第二內部選取脈衝輸入端係接收該內部選取脈衝信號，該第二輸出端輸出該第一內部輸入信號；該第一高初始值D型正反器具有第三輸入端、第三輸出端、第三反向輸出端、以及第三內部選取脈衝輸入端，其中，該第三輸入端係連接該第二反向輸出端，該第三內部選取脈衝輸入端係接收該內部選取脈衝信號；該第三低初始值D型正反器具有第四輸入端、第四輸出端、第四反向輸出端、以及第四內部選取脈衝輸入端，其中，該第四輸入端係連接該第三反向輸出端，該第四內部選取脈衝輸入端係接收該內部選取脈衝信號，該第四反向輸出端輸出該第一反向內部輸入信號；該第二高初始值D型正反器具有第五輸入端、第五輸出端、第五反向輸出端、以及第五內部選取脈衝輸入端，其中，該第五輸入端連接該第四反向輸出端，該第五內部選取脈衝輸入端係接收該內部選取脈衝信號；該第四低初始值D型正反器具有第六輸入端、第六輸出端、第六反向輸出端、以及第六內部選取脈衝輸入端，其中，該第六輸入端係連接該第五反向輸出端，該第六內部選取脈衝輸入端係接收該內部選取脈衝信號，該第六輸出端輸出該第二內部輸入信號；該第三高初始值D型正反器具有第七輸入端、第七輸出端、第七反向輸出端、以及第七內部選取脈衝輸入端，其中，該第七輸入端係連接該第六反向輸出端，該第七內部選取脈衝輸入端係接收該內部選取脈衝信號；該第五低初始值D型正反器具有第八輸入端、第八輸出端、第八反向輸出端、以及第八內部選取脈衝輸入端，其中，該第八輸入端係連接該第七反向輸出端，該第八內部選取脈衝輸入端係接收該內部選取脈衝信號，該第八反向輸出端輸出該第二反向內部輸入信號。Preferably, according to the internal latch circuit of the present invention, the first low initial value D-type flip-flop has a first input terminal, a first output terminal, a first inverted output terminal, and a first internal selection Pulse input terminal, wherein the first input terminal receives the input delay signal, the first internal selection pulse input terminal receives the internal selection pulse signal; the second low initial value D-type flip-flop has a second input terminal, a first Two output terminals, a second inverted output terminal, and a second internal selection pulse input terminal, wherein the second input terminal is connected to the first output terminal, and the second internal selection pulse input terminal receives the internal selection pulse signal , The second output terminal outputs the first internal input signal; the first high initial value D-type flip-flop has a third input terminal, a third output terminal, a third reverse output terminal, and a third internal selection pulse input Terminal, wherein the third input terminal is connected to the second reverse output terminal, the third internal selection pulse input terminal receives the internal selection pulse signal; the third low initial value D-type flip-flop has a fourth input Terminal, a fourth output terminal, a fourth inverted output terminal, and a fourth internally selected pulse input terminal, wherein the fourth input terminal is connected to the third inverted output terminal, and the fourth internally selected pulse input terminal receives The internally selected pulse signal, the fourth reverse output terminal outputs the first reverse internal input signal; the second high initial value D-type flip-flop has a fifth input terminal, a fifth output terminal, and a fifth reverse output Terminal, and a fifth internal selection pulse input terminal, wherein the fifth input terminal is connected to the fourth inverted output terminal, the fifth internal selection pulse input terminal receives the internal selection pulse signal; the fourth low initial value D The type flip-flop has a sixth input terminal, a sixth output terminal, a sixth reverse output terminal, and a sixth internal selection pulse input terminal, wherein the sixth input terminal is connected to the fifth reverse output terminal, and the first The six internal selection pulse input terminal receives the internal selection pulse signal, and the sixth output terminal outputs the second internal input signal; the third highest initial value D-type flip-flop has a seventh input terminal, a seventh output terminal, and a Seven inverted output terminals and a seventh internally selected pulse input terminal, wherein the seventh input terminal is connected to the sixth inverted output terminal, and the seventh internally selected pulse input terminal receives the internally selected pulse signal; The five-low initial value D-type flip-flop has an eighth input terminal, an eighth output terminal, an eighth reverse output terminal, and an eighth internal selection pulse input terminal, wherein the eighth input terminal is connected to the seventh reverse The output terminal, the eighth internal selection pulse input terminal receives the internal selection pulse signal, and the eighth inverted output terminal outputs the second inverted internal input signal.
較佳地，根據本發明之內部鎖存器電路，其中，該時脈信號的週期與該內部選取脈衝信號的週期相等，並且該時脈信號的週期與該內部選取脈衝信號的週期皆為一個時間週期。Preferably, according to the internal latch circuit of the present invention, the period of the clock signal is equal to the period of the internally selected pulse signal, and the period of the clock signal and the period of the internally selected pulse signal are both the same Time period.
較佳地，根據本發明之內部鎖存器電路，其中，該輸入延遲信號的長度為兩個時間週期。Preferably, according to the internal latch circuit of the present invention, the length of the input delay signal is two time periods.
又，為達上述目的，本發明係根據上述內部鎖存器電路為基礎，進一步提供一種執行上述內部鎖存器電路的鎖存信號產生方法，其係包含有：一接收延遲信號步驟，一內部鎖存器電路係接收一輸入延遲信號以及一內部選取脈衝信號；一響應延遲信號步驟，藉由複數低初始值D型正反器以及複數高初始值D型正反器，基於該內部選取脈衝信號並響應該輸入延遲信號，以產生一第一內部輸入信號、一第一反向內部輸入信號、一第二內部輸入信號以及一第二反向內部輸入信號，並傳輸至一內部鎖存信號產生電路；一輸出信號產生步驟，藉由該內部鎖存信號產生電路，其係接收該第一內部輸入信號、第一反向內部輸入信號、一第二內部輸入信號以及一第二反向內部輸入信號，使得該內部鎖存信號產生電路輸出一第一反向前輸出信號以及一第二反向前輸出信號；一生成內部鎖存信號步驟，藉由一反及閘，其係接收該第一反向前輸出信號以及該第二反向前輸出信號，以生成內部鎖存信號。In addition, to achieve the above objective, the present invention is based on the above internal latch circuit, and further provides a latch signal generation method for executing the above internal latch circuit, which includes: a step of receiving a delayed signal, and an internal The latch circuit receives an input delay signal and an internal selection pulse signal; a step of responding to the delay signal is based on the internal selection pulse by a complex low initial value D-type flip-flop and a complex high initial value D-type flip-flop Signal and respond to the input delay signal to generate a first internal input signal, a first inverted internal input signal, a second internal input signal, and a second inverted internal input signal, and transmit to an internal latch signal Generating circuit; an output signal generating step, by the internal latch signal generating circuit, which receives the first internal input signal, the first inverted internal input signal, a second internal input signal and a second inverted internal Input signal so that the internal latch signal generating circuit outputs a first pre-reverse output signal and a second pre-reverse output signal; in a step of generating an internal latch signal, it receives the first output signal through a reverse gate. A pre-reverse output signal and the second pre-reverse output signal are used to generate an internal latch signal.
較佳地，根據本發明之鎖存信號產生方法，其中，該第一延遲電路、該第二延遲電路、該第三延遲電路、以及該第四延遲電路係以D正反器、JK正反器、以及SR正反器的至少其中之一來予以施行。Preferably, according to the latch signal generation method of the present invention, the first delay circuit, the second delay circuit, the third delay circuit, and the fourth delay circuit use D flip-flops, JK positive and negative At least one of the inverter and the SR flip-flop.
較佳地，根據本發明之鎖存信號產生方法，其中，該內部鎖存器電路係進一步包含一重置輸入端，其係耦接該第一延遲電路、該第二延遲電路、該第三延遲電路、以及該第四延遲電路，該重置輸入端用於輸入一反向重置信號。Preferably, according to the latch signal generation method of the present invention, the internal latch circuit further includes a reset input terminal coupled to the first delay circuit, the second delay circuit, and the third delay circuit. In the delay circuit and the fourth delay circuit, the reset input terminal is used to input a reverse reset signal.
較佳地，本發明係根據一較佳實施例之內部鎖存器電路為基礎，根據本發明所提供之鎖存信號產生方法進一步包含有：產生該輸入延遲信號，其係響應該時脈信號；該輸入延遲信號通過該第一低初始值D型正反器以及該第二低初始值D型正反器，並且基於該內部選取脈衝信號，在兩個時間週期後，該第二低初始值D型正反器響應該輸入延遲信號輸出該第一內部輸入信號，該第一內部輸入信號相較於該輸入延遲信號延後兩個時間週期；該輸入延遲信號通過該第一低初始值D型正反器、該第二低初始值D型正反器、該第一高初始值D型正反器以及該第三低初始值D型正反器，並且基於該內部選取脈衝信號，在四個時間週期後，該第三低初始值D型正反器響應該輸入延遲信號輸出該第一反向內部輸入信號，該第一反向內部輸入信號相較於該輸入延遲信號延後四個時間週期並且為反向信號；該輸入延遲信號通過該第一低初始值D型正反器、該第二低初始值D型正反器、該第一高初始值D型正反器、該第三低初始值D型正反器、該第二高初始值D型正反器以及該第四低初始值D型正反器，並且基於該內部選取脈衝信號，在六個時間週期後，該第四低初始值D型正反器響應該輸入延遲信號輸出該第二內部輸入信號，該第二內部輸入信號相較於該輸入延遲信號延後六個時間週期；該輸入延遲信號通過該第一低初始值D型正反器、該第二低初始值D型正反器、該第一高初始值D型正反器、該第三低初始值D型正反器、該第二高初始值D型正反器、該第四低初始值D型正反器、第三高初始值D型正反器以及第五低初始值D型正反器，並且基於該內部選取脈衝信號，在八個時間週期後，該第五低初始值D型正反器響應該輸入延遲信號輸出該第二反向內部輸入信號，該第二反向內部輸入信號相較於該輸入延遲信號延後四個時間週期並且為反向信號；該第一內部輸入信號以及該第一反向內部輸入信號進入該內部鎖存信號產生電路，以產生該第一反向前輸出信號，並且該第二內部輸入信號以及該第二反向內部輸入信號進入該內部鎖存信號產生電路，以產生該第二反向前輸出信號；該第一反向前輸出信號以及該第二反向前輸出信號進入該反及閘，並且產生該內部鎖存信號。Preferably, the present invention is based on an internal latch circuit of a preferred embodiment. The latch signal generating method provided according to the present invention further includes: generating the input delay signal in response to the clock signal The input delay signal passes through the first low initial value D-type flip-flop and the second low initial value D-type flip-flop, and based on the internally selected pulse signal, after two time periods, the second low initial The value D-type flip-flop outputs the first internal input signal in response to the input delay signal. The first internal input signal is delayed by two time periods compared to the input delay signal; the input delay signal passes the first low initial value The D-type flip-flop, the second low initial value D-type flip-flop, the first high initial value D-type flip-flop, and the third low initial value D-type flip-flop, and based on the internally selected pulse signal, After four time periods, the third low initial value D-type flip-flop outputs the first inverted internal input signal in response to the input delay signal, and the first inverted internal input signal is delayed compared to the input delay signal Four time periods and a reverse signal; the input delay signal passes through the first low initial value D-type flip-flop, the second low initial value D-type flip-flop, and the first high initial value D-type flip-flop , The third low initial value D-type flip-flop, the second high initial value D-type flip-flop and the fourth low initial value D-type flip-flop, and based on the internally selected pulse signal, in six time periods Then, the fourth low initial value D-type flip-flop outputs the second internal input signal in response to the input delay signal, and the second internal input signal is delayed by six time periods compared with the input delay signal; the input delay signal Through the first low initial value D-type flip-flop, the second low initial value D-type flip-flop, the first high initial value D-type flip-flop, the third low initial value D-type flip-flop, the The second highest initial value D-type flip-flop, the fourth low initial value D-type flip-flop, the third highest initial value D-type flip-flop, and the fifth lowest initial value D-type flip-flop, and based on the internal selection Pulse signal. After eight time periods, the fifth low initial value D-type flip-flop outputs the second inverted internal input signal in response to the input delay signal, and the second inverted internal input signal is delayed compared to the input The signal is delayed by four time periods and is a reverse signal; the first internal input signal and the first reverse internal input signal enter the internal latch signal generating circuit to generate the first pre-reverse output signal, and the The second internal input signal and the second reverse internal input signal enter the internal latch signal generating circuit to generate the second pre-reverse output signal; the first pre-reverse output signal and the second pre-reverse output The signal enters the inverter and generates the internal latch signal.
較佳地，根據本發明之鎖存信號產生方法，其中，該等低初始值D型正反器以及該等高初始值D型正反器，皆具有一輸入端、一輸出端、一反向輸出端、以及一內部選取脈衝輸入端。Preferably, according to the latch signal generation method of the present invention, the low initial value D-type flip-flops and the high initial value D-type flip-flops all have an input terminal, an output terminal, and a reverser. To the output terminal, and an internal selection pulse input terminal.
較佳地，根據本發明之鎖存信號產生方法，其中，該輸入延遲信號的長度為兩個時間週期，並且該內部鎖存信號的長度為兩個時間週期。Preferably, according to the latch signal generating method of the present invention, the length of the input delay signal is two time periods, and the length of the internal latch signal is two time periods.
較佳地，根據本發明之鎖存信號產生方法，其中，該輸入延遲信號的長度不為兩個時間週期，並且該內部鎖存信號的長度為兩個時間週期。Preferably, according to the latch signal generating method of the present invention, the length of the input delay signal is not two time periods, and the length of the internal latch signal is two time periods.
綜上，本發明所提供之內部鎖存器電路及其鎖存信號產生方法，主要基於該內部選取脈衝信號，並且僅使用輸入延遲信號上升邊緣響應，以產生內部鎖存信號，藉此消除輸入延遲信號對內部鎖存信號的影響，以確保穩定的執行記憶體的寫入操作。In summary, the internal latch circuit and its latch signal generation method provided by the present invention are mainly based on the internal selection pulse signal and only use the rising edge response of the input delay signal to generate the internal latch signal, thereby eliminating the input The delay signal affects the internal latch signal to ensure stable execution of memory write operations.
爲使熟悉該項技藝人士瞭解本發明之目的、特徵及功效，茲藉由下述具體實施例，並配合所附之圖式，對本發明詳加說明如下。In order to enable those skilled in the art to understand the purpose, features and effects of the present invention, the following specific embodiments are used in conjunction with the accompanying drawings to illustrate the present invention in detail as follows.
現在將參照其中示出本發明概念的示例性實施例的附圖 在下文中更充分地闡述本發明概念。以下藉由參照附圖更詳細地闡述的示例性實施例，本發明概念的優點及特徵以及其達成方法將顯而易見。然而，應注意，本發明概念並非僅限於以下示例性實施例，而是可實施為各種形式。因此，提供示例性實施例僅是為了揭露本發明概念並使熟習此項技術者瞭解本發明概念的類別。在圖式中，本發明概念的示例性實施例並非僅限於本文所提供的特定實例且為清晰起見而進行誇大。The inventive concept will now be explained more fully hereinafter with reference to the accompanying drawings in which an exemplary embodiment of the inventive concept is shown. Hereinafter, the advantages and features of the concept of the present invention and the method of achieving the same will be apparent by referring to the exemplary embodiments described in more detail with reference to the accompanying drawings. However, it should be noted that the inventive concept is not limited to the following exemplary embodiments, but can be implemented in various forms. Therefore, the exemplary embodiments are only provided for exposing the concept of the present invention and to enable those skilled in the art to understand the category of the concept of the present invention. In the drawings, the exemplary embodiments of the inventive concept are not limited to the specific examples provided herein and are exaggerated for clarity.
本文所用術語僅用於闡述特定實施例，而並非旨在限制本發明。除非上下文中清楚地另外指明，否則本文所用的單數形式的用語「一(a、an)」及「所述(the)」旨在亦包括複數形式。本文所用的用語「及/或(and/or)」包括相關所列項其中一或多者的任意及所有組合。應理解，當稱元件「連接(connected)」或「耦合(coupled)」至另一元件時，所述元件可直接連接或耦合至所述另一元件或可存在中間元件。The terms used herein are only used to illustrate specific embodiments, and are not intended to limit the present invention. Unless the context clearly indicates otherwise, the singular terms "一 (a, an)" and "the (the)" used herein are intended to also include the plural. The term "and/or" as used herein includes any and all combinations of one or more of the related listed items. It should be understood that when an element is referred to as being “connected” or “coupled” to another element, the element may be directly connected or coupled to the other element or there may be intervening elements.
相似地，應理解，當稱一個元件(例如層、區或基板)位於另一元件「上(on)」時，所述元件可直接位於所述另一元件上，或可存在中間元件。相比之下，用語「直接(directly)」意指不存在中間元件。更應理解，當在本文中使用用語「包括(comprises/comprising)」、「包含(includes及/或including)」時，是表明所陳述的特徵、整數、步驟、操作、元件、及/或組件的存在，但不排除一或多個其他特徵、整數、步驟、操作、元件、組件、及/或其群組的存在或添加。Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as being "on" another element, the element may be directly on the other element, or intervening elements may be present. In contrast, the term "directly" means that there are no intermediate components. It should be understood that when the terms "comprises/comprising" and "includes and/or including" are used in this article, they indicate the stated features, integers, steps, operations, elements, and/or components The existence of, but does not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
此外，將藉由作為本發明概念的理想化示例性圖的剖視圖來闡述詳細說明中的示例性實施例。相應地，可根據製造技術及/或可容許的誤差來修改示例性圖的形狀。因此，本發明概念的示例性實施例並非僅限於示例性圖中所示出的特定形狀，而是可包括可根據製造製程而產生的其他形狀。圖式中所例示的區域具有一般特性，且用於說明元件的特定形狀。因此，此不應被視為僅限於本發明概念的範圍。In addition, the exemplary embodiment in the detailed description will be explained by a cross-sectional view which is an idealized exemplary diagram of the concept of the present invention. Accordingly, the shape of the exemplary figure can be modified according to manufacturing technology and/or allowable errors. Therefore, the exemplary embodiments of the inventive concept are not limited to the specific shapes shown in the exemplary figures, but may include other shapes that can be produced according to the manufacturing process. The regions illustrated in the drawings have general characteristics and are used to illustrate the specific shape of the element. Therefore, this should not be regarded as being limited to the scope of the inventive concept.
亦應理解，儘管本文中可能使用用語「第一(first)」、「第二(second)」、「第三(third)」等來闡述各種元件，然而該些元件不應受限於該些用語。該些用語僅用於區分各個元件。因此，某些實施例中的第一元件可在其他實施例中被稱為第二元件，而此並不背離本發明的教示內容。本文中所闡釋及說明的本發明概念的態樣的示例性實施例包括其互補對應物。本說明書通篇中，相同的參考編號或相同的指示物表示相同的元件。It should also be understood that although the terms "first", "second", "third", etc. may be used in this article to describe various elements, these elements should not be limited to these elements. term. These terms are only used to distinguish each element. Therefore, the first element in some embodiments may be referred to as the second element in other embodiments, and this does not deviate from the teachings of the present invention. The exemplary embodiments of aspects of the inventive concept illustrated and described herein include their complementary counterparts. Throughout this specification, the same reference number or the same indicator represents the same element.
此外，本文中參照剖視圖及/或平面圖來闡述示例性實施例，其中所述剖視圖及/或平面圖是理想化示例性說明圖。因此，預期存在由例如製造技術及/或容差所造成的相對於圖示形狀的偏離。因此，示例性實施例不應被視作僅限於本文中所示區的形狀，而是欲包括由例如製造所導致的形狀偏差。舉例而言，經繪示出為矩形的蝕刻區將通常具有圓形特徵或彎曲特徵。因此，圖中所示的區為示意性的，且其形狀並非旨在說明裝置的區的實際形狀、亦並非旨在限制示例性實施例的範圍。In addition, the exemplary embodiments are described herein with reference to cross-sectional views and/or plan views, where the cross-sectional views and/or plan views are idealized exemplary explanatory diagrams. Therefore, it is expected that there is a deviation from the illustrated shape due to, for example, manufacturing technology and/or tolerances. Therefore, the exemplary embodiments should not be viewed as being limited to the shapes of the regions shown herein, but are intended to include shape deviations caused by, for example, manufacturing. For example, an etched area depicted as a rectangle will generally have round features or curved features. Therefore, the regions shown in the figures are schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor to limit the scope of the exemplary embodiments.
如本發明人(inventive entity)所理解，根據本文所述各種示例性實施例的裝置及形成裝置的方法可被實施於例如積體電路等微電子裝置中，其中根據本文所述各種示例性實施例的多個裝置被整合於同一微電子裝置中。因此，可在所述微電子裝置中在兩個不同方向上複製本文所示的剖視圖，所述兩個不同方向無需為正交的。因此，實施根據本文所述各種示例性實施例的裝置的所述微電子裝置的平面圖可包括基於所述微電子裝置的功能性而呈陣列形式及/或二維圖案形式的多個裝置。As understood by the inventor (inventive entity), the device and the method of forming the device according to the various exemplary embodiments described herein can be implemented in microelectronic devices such as integrated circuits, wherein the various exemplary implementations described herein The multiple devices in the example are integrated into the same microelectronic device. Therefore, the cross-sectional views shown herein can be replicated in two different directions in the microelectronic device, and the two different directions need not be orthogonal. Therefore, a plan view of the microelectronic device implementing the device according to various exemplary embodiments described herein may include a plurality of devices in the form of an array and/or a two-dimensional pattern based on the functionality of the microelectronic device.
因此，本文所示的剖視圖提供對根據本文所述各種示例性實施例的多個裝置的支持，所述多個裝置在平面圖中沿兩個不同方向及/或在立體圖中沿三個不同方向延伸。Therefore, the cross-sectional views shown herein provide support for a plurality of devices according to various exemplary embodiments described herein, the plurality of devices extending in two different directions in plan view and/or in three different directions in perspective view .
請參閱圖3所示，圖3為根據本發明之內部鎖存器電路的示意性電路方塊圖。如圖3所示，根據本發明之內部鎖存器電路100，其係包含有：第一延遲電路1、第二延遲電路2、第三延遲電路3、第四延遲電路4、內部鎖存信號產生電路5、反及閘6。Please refer to FIG. 3, which is a schematic circuit block diagram of the internal latch circuit according to the present invention. As shown in FIG. 3, the
具體地，該第一延遲電路1，其係接收輸入延遲信號WR_LAT_P1以及內部選取脈衝信號INT_DQS，並且輸出第一內部輸入信號DDS_CK_EN1，其中，輸入延遲信號WR_LAT_P1響應於時脈信號CLK。Specifically, the
具體地，該第二延遲電路2，其係耦接第一延遲電路1，該第二延遲電路2接收內部選取脈衝信號INT_DQS，並且輸出第一反向內部輸入信號NOT_DDS_CK_DIS1。Specifically, the
具體地，該第三延遲電路3，其係耦接第二延遲電路2，該第三延遲電路3接收內部選取脈衝信號INT_DQS，並且輸出第二內部輸入信號DDS_CK_EN2。Specifically, the
具體地，該第四延遲電路4，其係耦接第三延遲電路3，該第四延遲電路4接收內部選取脈衝信號INT_DQS，並且輸出第二反向內部輸入信號NOT_DDS_CK_DIS2。Specifically, the
具體地，該內部鎖存信號產生電路5，其係耦接第一延遲電路1、第二延遲電路2、第三延遲電路3、以及第四延遲電路4，該內部鎖存信號產生電路5係接收該第一內部輸入信號DDS_CK_EN1、該第一反向內部輸入信號NOT_DDS_CK_DIS1、該第二內部輸入信號DDS_CK_EN2、以及該第二反向內部輸入信號NOT_DDS_CK_DIS2，並且該內部鎖存信號產生電路5係產生第一反向前輸出信號NOT_PRE_OUT1以及第二反向前輸出信號NOT_PRE_OUT2。Specifically, the internal latch
具體地，該反及閘6，係耦接內部鎖存信號產生電路5，該反及閘6係接收該第一反向前輸出信號NOT_PRE_OUT1以及該第二反向前輸出信號NOT_PRE_OUT2，並且該反及閘6係輸出內部鎖存信號DDS_CK。Specifically, the
具體地，根據上述結構，其中第一延遲電路1、第二延遲電路2、第三延遲電路3、以及第四延遲電路4可以使用D正反器、JK正反器、以及SR正反器的至少其中之一來予以施行。Specifically, according to the above structure, the
具體地，內部鎖存器電路100可以進一步包含重置輸入端7，重置輸入端7係耦接第一延遲電路1、第二延遲電路2、第三延遲電路3、以及第四延遲電路4，重置輸入端7用於輸入一反向重置信號NOT_RST，其中，該重置信號NOT_RST用於重置該等低初始值D型正反器10以及該等高初始值D型正反器20的數值，然而本發明不限於此。Specifically, the
為供進一步瞭解本發明構造特徵、運用技術手段及所預期達成之功效，茲將本發明之實施例加以敘述，相信當可由此而對本發明有更深入且具體瞭解，如下所述：In order to further understand the structural features of the present invention, the technical means used and the expected effects, the embodiments of the present invention are described. It is believed that a more in-depth and specific understanding of the present invention can be obtained from this, as follows:
請參閱圖4，圖4為根據本發明一個或多個示例性實施例之內部鎖存器電路的示意性電路方塊圖。如圖4所示，根據本發明一實施例之內部鎖存器電路100係具有複數低初始值D型正反器10以及複數高初始值D型正反器20，該內部鎖存器電路100包括：第一低初始值D型正反器11、第二低初始值D型正反器12、第一高初始值D型正反器21、第三低初始值D型正反器13、第二高初始值D型正反器22、第四低初始值D型正反器14、第三高初始值D型正反器23、第五低初始值D型正反器15、內部鎖存信號產生電路5、以及反及閘6。Please refer to FIG. 4, which is a schematic circuit block diagram of an internal latch circuit according to one or more exemplary embodiments of the present invention. As shown in FIG. 4, the
具體地，在本實施例中，該第一低初始值D型正反器11係接收輸入延遲信號WR_LAT_P1以及內部選取脈衝信號INT_DQS，其中，輸入延遲信號WR_LAT_P1響應於時脈信號CLK。Specifically, in this embodiment, the first low initial value D-type flip-
具體地，在本實施例中，該第二低初始值D型正反器12係耦接第一低初始值D型正反器11，第二低初始值D型正反器12係接收通過第一低初始值D型正反器11的輸入延遲信號WR_LAT_P1，以及內部選取脈衝信號INT_DQS，並且第二低初始值D型正反器12基於內部選取脈衝INT_DQS並響應輸入延遲信號WR_LAT_P1產生第一內部輸入信號DDS_CK_EN1。藉此，該第二低初始值D型正反器12輸出該第一內部輸入信號DDS_CK_EN1。Specifically, in this embodiment, the second low initial value D-type flip-
具體地，在本實施例中，該第一高初始值D型正反器21係耦接該第二低初始值D型正反器12，該第一高初始值D型正反器21係接收通過該第一低初始值D型正反器11與該第二低初始值D型正反器12的輸入延遲信號WR_LAT_P1，以及內部選取脈衝信號INT_DQS。Specifically, in this embodiment, the first high initial value D-type flip-
具體地，在本實施例中，該第三低初始值D型正反器13係耦接第一高初始值D型正反器21，第三低初始值D型正反器13係接收通過第一低初始值D型正反器11、該第二低初始值D型正反器12、與第一高初始值D型正反器21的輸入延遲信號WR_LAT_P1，以及內部選取脈衝信號INT_DQS，並且第三低初始值D型正反器13基於內部選取脈衝INT_DQS並響應輸入延遲信號WR_LAT_P1產生第一反向內部輸入信號NOT_DDS_CK_DIS1。藉此，該第三低初始值D型正反器13輸出該第一反向內部輸入信號NOT_DDS_CK_DIS1。Specifically, in this embodiment, the third low initial value D-type flip-
具體地，在本實施例中，該第二高初始值D型正反器22係耦接該第三低初始值D型正反器13，該第二高初始值D型正反器22係接收通過該第一低初始值D型正反器、該第二低初始值D型正反器、該第一高初始值D型正反器21、與該第三低初始值D型正反器13的輸入延遲信號WR_LAT_P1，以及內部選取脈衝信號INT_DQS。Specifically, in this embodiment, the second high initial value D-type flip-
具體地，在本實施例中，該第四低初始值D型正反器14係耦接第二高初始值D型正反器22，第四低初始值D型正反器14係接收通過第一低初始值D型正反器11、該第二低初始值D型正反器12、第一高初始值D型正反器21、第三低初始值D型正反器13、與第二高初始值D型正反器22的輸入延遲信號WR_LAT_P1，以及內部選取脈衝信號INT_DQS，並且第四低初始值D型正反器14基於內部選取脈衝INT_DQS並響應輸入延遲信號WR_LAT_P1產生第二內部輸入信號DDS_CK_EN2。藉此，該第四低初始值D型正反器14輸出該第二內部輸入信號DDS_CK_EN2。Specifically, in this embodiment, the fourth low initial value D-type flip-
具體地，在本實施例中，該第三高初始值D型正反器23係耦接該第四低初始值D型正反器14，該第三高初始值D型正反器23係接收通過該第一低初始值D型正反器11、該第二低初始值D型正反器12、第一高初始值D型正反器21、第三低初始值D型正反器13、第二高初始值D型正反器22、與第四低初始值D型正反器14的輸入延遲信號WR_LAT_P1，以及內部選取脈衝信號INT_DQS。Specifically, in this embodiment, the third high initial value D-type flip-
具體地，在本實施例中，該第五低初始值D型正反器15係耦接第三高初始值D型正反器23，第五低初始值D型正反器15係接收通過第一低初始值D型正反器11、該第二低初始值D型正反器12、第一高初始值D型正反器21、第三低初始值D型正反器13、第二高初始值D型正反器22、與第三高初始值D型正反器23的輸入延遲信號WR_LAT_P1，以及內部選取脈衝信號INT_DQS，並且第四低初始值D型正反器14基於內部選取脈衝INT_DQS並響應輸入延遲信號WR_LAT_P1產生第二反向內部輸入信號NOT_DDS_CK_DIS2。藉此，該第五低初始值D型正反器15輸出該第二反向內部輸入信號NOT_DDS_CK_DIS2。Specifically, in this embodiment, the fifth low initial value D-type flip-
具體地，在本實施例中，該內部鎖存信號產生電路5係耦接該第二低初始值D型正反器12、該第三低初始值D型正反器13、該第四低初始值D型正反器14、以及該第五低初始值D型正反器15，該內部鎖存信號產生電路5係接收該第一內部輸入信號DDS_CK_EN1、該第一反向內部輸入信號NOT_DDS_CK_DIS1、該第二內部輸入信號DDS_CK_EN2、以及該第二反向內部輸入信號NOT_DDS_CK_DIS2，並且該內部鎖存信號產生電路5係產生第一反向前輸出信號NOT_PRE_OUT1以及第二反向前輸出信號NOT_PRE_OUT2。Specifically, in this embodiment, the internal latch
具體地，在本實施例中，該反及閘6係耦接內部鎖存信號產生電路5，該反及閘6係接收該第一反向前輸出信號NOT_PRE_OUT1以及該第二反向前輸出信號NOT_PRE_OUT2，並且該反及閘6係輸出內部鎖存信號DDS_CK。Specifically, in this embodiment, the
具體地，在本實施例中，第一低初始值D型正反器11及第二低初始值D型正反器12組成該第一延遲電路1，第一高初始值D型正反器21及第三低初始值D型正反器13組成該第二延遲電路2，第二高初始值D型正反器22及第四低初始值D型正反器14組成第三延遲電路3，第三高初始值D型正反器23及第五低初始值D型正反器15組成該第四延遲電路4。Specifically, in this embodiment, the first low initial value D-type flip-
具體地，在本實施例中，內部鎖存器電路100可以進一步包含重置輸入端7，重置輸入端7係耦接第一低初始值D型正反器11、該第二低初始值D型正反器12、第一高初始值D型正反器21、第三低初始值D型正反器13、第二高初始值D型正反器22、與第三高初始值D型正反器23，重置輸入端7用於輸入一反向重置信號NOT_RST，其中，該重置信號NOT_RST用於重置該等低初始值D型正反器10以及該等高初始值D型正反器20的數值，然而本發明不限於此。Specifically, in this embodiment, the
請參閱圖5及圖6所示，圖5為根據本發明一個或多個示例性實施例之低初始值D型正反器的示意性電路圖；圖6為根據本發明一個或多個示例性實施例之高初始值D型正反器的示意性電路圖。根據本發明之低初始值D型正反器10具有輸入端101、輸出端102、反向輸出端103、以及內部選取脈衝輸入端104，根據本發明之高初始值D型正反器20具有輸入端201、輸出端202、反向輸出端203、以及內部選取脈衝輸入端204，需要進一步說明的是，低初始值D型正反器10以及高初始值D型正反器20的差別在於，在本實施例中，該低初始值D型正反器10的起始值為低值L，該高初始值D型正反器20的起始值為高值H。Please refer to FIG. 5 and FIG. 6. FIG. 5 is a schematic circuit diagram of a low initial value D-type flip-flop according to one or more exemplary embodiments of the present invention; FIG. 6 is a schematic circuit diagram of one or more exemplary embodiments of the present invention. The schematic circuit diagram of the high initial value D-type flip-flop of the embodiment. The low initial value D-type flip-
具體地，在本實施例中，低初始值D型正反器10以及高初始值D型正反器20的作用在於，接收輸入端101以及輸入端201所輸入的信號，並基於內部選取脈衝輸入端104以及內部選取脈衝輸入端204所接收的內部選取脈衝信號INT_DQS，使得接收輸入端101以及輸入端201所輸入的信號與內部選取脈衝信號INT_DQS同步化，然而本發明不限於此。Specifically, in this embodiment, the function of the low initial value D-type flip-
具體地，在本實施例中，第一低初始值D型正反器11具有第一輸入端111、第一輸出端112、第一反向輸出端113、以及第一內部選取脈衝輸入端114，其中該第一輸入端111係接收輸入延遲信號WR_LAT_P1，該第一內部選取脈衝輸入端114接收內部選取脈衝信號INT_DQS，使得第一低初始值D型正反器11基於內部選取脈衝信號INT_DQS並響應輸入延遲信號WR_LAT_P1，以產生第一低初始值D型正反器11的輸出信號，並從第一輸出端112輸出至第二低初始值D型正反器12，其中第一反向輸出端113所輸出的信號與第一輸出端112所輸出的信號為反向的關係。Specifically, in this embodiment, the first low initial value D-type flip-
具體地，在本實施例中，第二低初始值D型正反器12具有第二輸入端121、第二輸出端122、第二反向輸出端123、以及第二內部選取脈衝輸入端124，其中，該第二輸入端121係連接該第一輸出端112，第二輸入端121用於接收通過第一低初始值D型正反器11的輸入延遲信號WR_LAT_P1，第二內部選取脈衝輸入端124用於接收內部選取脈衝信號INT_DQS，使得第二低初始值D型正反器12基於內部選取脈衝INT_DQS並響應輸入延遲信號WR_LAT_P1產生第一內部輸入信號DDS_CK_EN1，並從第二輸出端122輸出該第一內部輸入信號DDS_CK_EN1，第二反向輸出端123輸出與第一內部輸入信號DDS_CK_EN1反向的信號至第三高初始值D型正反器21。Specifically, in this embodiment, the second low initial value D-type flip-
具體地，在本實施例中，第一高初始值D型正反器21具有第三輸入端211、第三輸出端212、第三反向輸出端213、以及第三內部選取脈衝輸入端214，其中，該第三輸入端211係連接該第二反向輸出端124，第三內部選取脈衝輸入端214用於接收內部選取脈衝信號INT_DQS，該第一高初始值D型正反器21接收與第一內部輸入信號DDS_CK_EN1反向的信號後，基於內部選取脈衝信號INT_DQS產生輸出的信號，並從第三反向輸出端213輸出至第三低初始值D型正反器13。Specifically, in this embodiment, the first high initial value D-type flip-
具體地，在本實施例中，第三低初始值D型正反器13具有第四輸入端131、第四輸出端132、第四反向輸出端133、以及第四內部選取脈衝輸入端134，其中，第四輸入端131係連接該第三反向輸出端213，以接收通過第一低初始值D型正反器11、該第二低初始值D型正反器12、與第一高初始值D型正反器21的輸入延遲信號WR_LAT_P1，第四內部選取脈衝輸入端134係接收內部選取脈衝信號INT_DQS，使得第三低初始值D型正反器13基於內部選取脈衝INT_DQS並響應輸入延遲信號WR_LAT_P1，以產生第一反向內部輸入信號NOT_DDS_CK_DIS1，並從第四反向輸出端131輸出該第一反向內部輸入信號NOT_DDS_CK_DIS1。Specifically, in this embodiment, the third low initial value D-type flip-
具體地，在本實施例中，第二高初始值D型正反器22具有第五輸入端221、第五輸出端222、第五反向輸出端223、以及第五內部選取脈衝輸入端224，其中，該第五輸入端221連接該第四反向輸出端133，該第五內部選取脈衝輸入端224係接收該內部選取脈衝信號INT_DQS，該第二高初始值D型正反器22接收該第一反向內部輸入信號NOT_DDS_CK_DIS1後，基於內部選取脈衝信號INT_DQS產生輸出的信號，並從第五反向輸出端223輸出至第四低初始值D型正反器14。Specifically, in this embodiment, the second high initial value D-type flip-
具體地，在本實施例中，第四低初始值D型正反器14具有第六輸入端141、第六輸出端142、第六反向輸出端143、以及第六內部選取脈衝輸入端144，其中，該第六輸入端係141連接該第五反向輸出端223，以接收通過第一低初始值D型正反器11、該第二低初始值D型正反器12、第一高初始值D型正反器21、第三低初始值D型正反器13、與第二高初始值D型正反器22的輸入延遲信號WR_LAT_P1，該第六內部選取脈衝輸入端144係接收該內部選取脈衝信號INT_DQS，使得第四低初始值D型正反器14基於內部選取脈衝INT_DQS並響應輸入延遲信號WR_LAT_P1，以產生第二內部輸入信號DDS_CK_EN2，並從該第六輸出端142輸出該第二內部輸入信號DDS_CK_EN2。Specifically, in this embodiment, the fourth low initial value D-type flip-
具體地，在本實施例中，第三高初始值D型正反器23具有第七輸入端231、第七輸出端232、第七反向輸出端233、以及第七內部選取脈衝輸入端234，其中，該第七輸入端231係連接該第六反向輸出端143，該第七內部選取脈衝輸入端234係接收該內部選取脈衝信號INT_DQS，該第三高初始值D型正反器23接收與第二內部輸入信號DDS_CK_EN2反向的信號後，基於內部選取脈衝信號INT_DQS產生輸出的信號，並從第七反向輸出端233輸出至第五低初始值D型正反器15。Specifically, in this embodiment, the third highest initial value D-type flip-
具體地，在本實施例中，第五低初始值D型正反器15具有第八輸入端151、第八輸出端152、第八反向輸出端153、以及第八內部選取脈衝輸入端154，其中，該第八輸入端151係連接該第七反向輸出端233，以接收通過第一低初始值D型正反器11、該第二低初始值D型正反器12、第一高初始值D型正反器21、第三低初始值D型正反器13、第二高初始值D型正反器22、與第三高初始值D型正反器23的輸入延遲信號WR_LAT_P1，該第八內部選取脈衝輸入端154係接收該內部選取脈衝信號INT_DQS，使得第五低初始值D型正反器15基於內部選取脈衝INT_DQS並響應輸入延遲信號WR_LAT_P1，以產生第二反向內部輸入信號NOT_DDS_CK_DIS2，並從該第八反向輸出端153輸出該第二反向內部輸入信號NOT_DDS_CK_DIS2。Specifically, in this embodiment, the fifth low initial value D-type flip-
具體地，在本實施例中，時脈信號CLK的週期與該內部選取脈衝信號INT_DQS的週期相等，並且該時脈信號的週期與該內部選取脈衝信號的週期皆為一個時間週期tCK，然而本發明不限於此。Specifically, in this embodiment, the period of the clock signal CLK is equal to the period of the internal selection pulse signal INT_DQS, and the period of the clock signal and the period of the internal selection pulse signal are both a time period tCK. The invention is not limited to this.
具體地，在本實施例中，輸入延遲信號WR_LAT_P1的長度為兩個時間週期tCK，然而本發明不限於此。Specifically, in this embodiment, the length of the input delay signal WR_LAT_P1 is two time periods tCK, but the present invention is not limited to this.
如此一來，由上述說明可得知，根據本發明所提供之內部鎖存器電路100，其係接收響應於時脈信號CLK的輸入延遲信號WR_LAT_P1後，藉由該等低初始值D型正反器10以及該等高初始值D型正反器20，基於內部選取脈衝信號INT_DQS並響應輸入延遲信號WR_LAT_P1，以產生第一內部輸入信號DDS_CK_EN1、第一反向內部輸入信號NOT_DDS_CK_DIS1、第二內部輸入信號DDS_CK_EN2、以及第二反向內部輸入信號NOT_DDS_CK_DIS2，並傳輸至內部鎖存信號產生電路5，以藉由內部鎖存信號產生電路5輸出第一反向前輸出信號NOT_PRE_OUT1以及第二反向前輸出信號NOT_PRE_OUT2，最後通過反及閘產生內部鎖存信號DDS_CK。需要進一步說明的是，根據本發明之內部鎖存器電路100，其係基於該內部選取脈衝信號INT_DQS並響應輸入延遲信號WR_LAT_P1，以產生內部鎖存信號DDS_CK，並且在產生內部鎖存信號DDS_CK的過程中，內部鎖存器電路100僅響應該輸入延遲信號WR_LAT_P1的上升邊緣，而不受該輸入延遲信號WR_LAT_P1的下降邊緣影響。In this way, it can be seen from the above description that the
更詳而言之，本發明之內部鎖存器電路100所產生之內部鎖存信號DDS_CK，不會由於外部環境的溫度或者金屬氧化物半導體場效電晶體之製成技術，所造成輸入延遲信號WR_LAT_P1的上升邊緣以及下降邊緣的改變，從而使得雙通道同步動態隨機存取記憶體不能穩定的執行寫入操作。透過本發明之內部鎖存器電路100，使得雙通道同步動態隨機存取記憶體不受製成技術以及外部環境溫度的影響，透過精確的內部鎖存信號DDS_CK，以穩定的執行寫入操作。In more detail, the internal latch signal DDS_CK generated by the
為供進一步瞭解本發明構造特徵、運用技術手段及所預期達成之功效，茲將本發明使用方式加以敘述，相信當可由此而對本發明有更深入且具體瞭解，如下所述：In order to further understand the structural features of the present invention, the technical means used and the expected effects, the use of the present invention is described. It is believed that a more in-depth and specific understanding of the present invention can be obtained from this, as follows:
請參閱圖7，並搭配圖3所示，圖7為說明本發明之鎖存信號產生方法的部分步驟流程圖。本發明進一步提供一種鎖存信號DDS_CK產生方法，係包含下列步驟：Please refer to FIG. 7 in conjunction with FIG. 3. FIG. 7 is a flowchart illustrating partial steps of the latch signal generation method of the present invention. The present invention further provides a method for generating the latch signal DDS_CK, which includes the following steps:
接收延遲信號步驟S1：根據本發明之內部鎖存器電路100係接收輸入延遲信號WR_LAT_P1以及內部選取脈衝信號INT_DQS。Receive delay signal step S1: The
響應延遲信號步驟S2：藉由低初始值D型正反器10以及高初始值D型正反器20，基於內部選取脈衝信號INT_DQS並響應輸入延遲信號WR_LAT_P1，以產生第一內部輸入信號DDS_CK_EN1、第一反向內部輸入信號NOT_DDS_CK_DIS1、第二內部輸入信號DDS_CK_EN2以及第二反向內部輸入信號NOT_DDS_CK_DIS 2，並傳輸至內部鎖存信號產生電路5。Responding to the delay signal step S2: Using the low initial value D-type flip-
輸出信號產生步驟S3，藉由內部鎖存訊號產生電路5，其係接收第一內部輸入信號DDS_CK_EN1、第一反向內部輸入信號NOT_DDS_CK_DIS1、第二內部輸入信號DDS_CK_EN2以及第二反向內部輸入信號NOT_DDS_CK_DIS 2，使得內部鎖存信號產生電路5輸出第一反向前輸出信號以及一第二反向前輸出信號。The output signal generation step S3, through the internal latch
生成內部鎖存信號步驟S4，藉由反及閘6，其係接收第一反向前輸出信號NOT_PRE_OUT1以及第二反向前輸出信號NOT_PRE_OUT2，以生成內部鎖存信號DDS_CK。In step S4 of generating the internal latch signal, the
具體地，根據上述鎖存信號DDS_CK產生方法，其中，第一延遲電路1、第二延遲電路2、第三延遲電路3、以及第四延遲電路4可以使用D正反器、JK正反器、以及SR正反器的至少其中之一來予以施行。Specifically, according to the foregoing latch signal DDS_CK generating method, the
具體地，根據上述鎖存信號DDS_CK產生方法，其中，內部鎖存器電路100可以進一步包含重置輸入端7，重置輸入端7係耦接第一延遲電路1、第二延遲電路2、第三延遲電路3、以及第四延遲電路4，重置輸入端7用於輸入一反向重置信號NOT_RST，其中，該重置信號NOT_RST用於重置該等低初始值D型正反器10以及該等高初始值D型正反器20的數值，然而本發明不限於此。Specifically, according to the foregoing latch signal DDS_CK generating method, the
為供進一步瞭解本發明構造特徵、運用技術手段及所預期達成之功效，茲將本發明之實施例搭配方法加以敘述，相信當可由此而對本發明有更深入且具體瞭解，如下所述：In order to further understand the structural features of the present invention, the technical means used and the expected effects, the embodiments and methods of the present invention are described here. It is believed that a more in-depth and specific understanding of the present invention can be obtained from this, as follows:
請參閱圖8A以及圖8B，並搭配圖4至圖6所示，圖8A為說明執行本發明一個或多個示例性實施例之內部鎖存器電路的鎖存信號產生方法的部分步驟流程圖；圖8B為說明執行本發明一個或多個示例性實施例之內部鎖存器電路的鎖存信號產生方法的部分步驟流程圖。本發明以上述實施例之內部鎖存器電路100為基礎，根據本發明所提供之鎖存信號DDS_CK產生方法進一步包含下列步驟：Please refer to FIG. 8A and FIG. 8B in conjunction with FIG. 4 to FIG. 6. FIG. 8A is a flowchart illustrating partial steps of the latch signal generation method of the internal latch circuit according to one or more exemplary embodiments of the present invention 8B is a flowchart illustrating partial steps of a method for generating a latch signal of an internal latch circuit of one or more exemplary embodiments of the present invention. The present invention is based on the
步驟S1'：響應時脈信號CLK，以產生輸入延遲信號WR_LAT_P1。Step S1': responding to the clock signal CLK to generate an input delay signal WR_LAT_P1.
步驟S2'：輸入延遲信號WR_LAT_P1輸入第一低初始值D型正反器11以及該第二低初始值D型正反器12，並且基於該內部選取脈衝信號INT_DQS，在兩個時間週期tCK後，第二低初始值D型正反器12響應輸入延遲信號WR_LAT_P1以輸出第一內部輸入信號DDS_CK_EN1，該第一內部輸入信號DDS_CK_EN1相較於該輸入延遲信號WR_LAT_P1延後兩個時間週期tCK。Step S2': Input the delay signal WR_LAT_P1 into the first low initial value D-type flip-
步驟S3'：輸入延遲信號WR_LAT_P1輸入第一低初始值D型正反器11、第二低初始值D型正反器12、第一高初始值D型正反器21以及第三低初始值D型正反器13，並且基於該內部選取脈衝信號INT_DQS，在四個時間週期tCK後，第三低初始值D型正反器13響應輸入延遲信號WR_LAT_P1輸出第一反向內部輸入信號NOT_DDS_CK_DIS1，並且該第一反向內部輸入信號NOT_DDS_CK_DIS1相較於該輸入延遲信號WR_LAT_P1延後四個時間週期tCK，並且為反向信號。Step S3': Input the delay signal WR_LAT_P1 into the first low initial value D-type flip-
步驟S4'：輸入延遲信號WR_LAT_P1輸入第一低初始值D型正反器11、該第二低初始值D型正反器12、該第一高初始值D型正反器21、該第三低初始值D型正反器13、該第二高初始值D型正反器22、以及該第四低初始值D型正反器14，並且基於內部選取脈衝信號INT_DQS，在六個時間週期tCK後，第四低初始值D型正反器14響應輸入延遲信號WR_LAT_P1，以輸出該第二內部輸入信號DDS_CK_EN2，該第二內部輸入信號相較於該輸入延遲信號延後六個時間週期tCK。Step S4': Input the delay signal WR_LAT_P1 into the first low initial value D-type flip-
步驟S5'：輸入延遲信號WR_LAT_P1輸入第一低初始值D型正反器11、該第二低初始值D型正反器12、第一高初始值D型正反器21、第三低初始值D型正反器13、第二高初始值D型正反器22、第四低初始值D型正反器14、第三高初始值D型正反器23以及第五低初始值D型正反器15，並且基於內部選取脈衝信號INT_DQS，在八個時間週期tCK後，第五低初始值D型正反器15響應輸入延遲信號WR_LAT_P1，以輸出第二反向內部輸入信號NOT_DDS_CK_DIS2，該第二反向內部輸入信號NOT_DDS_CK_DIS2相較於該輸入延遲信號WR_LAT_P1延後八個時間週期tCK，並且為反向信號。Step S5': Input the delay signal WR_LAT_P1 into the first low initial value D-type flip-
步驟S6'：第一內部輸入信號DDS_CK_EN1以及第一反向內部輸入信號NOT_DDS_CK_DIS1輸入內部鎖存信號產生電路5，以產生第一反向前輸出信號NOT_PRE_OUT1，並且第二內部輸入信號DDS_CK_EN2以及該第二反向內部輸入信號NOT_DDS_CK_DIS2進入內部鎖存信號產生電路5，以產生該第二反向前輸出信號NOT_PRE_OUT2。Step S6': The first internal input signal DDS_CK_EN1 and the first reverse internal input signal NOT_DDS_CK_DIS1 are input to the internal latch
步驟S7'：第一反向前輸出信號NOT_PRE_OUT1以及第二反向前輸出信號NOT_PRE_OUT2輸入反及閘6，並且產生內部鎖存信號DDS_CK。Step S7': The first pre-reverse output signal NOT_PRE_OUT1 and the second pre-reverse output signal NOT_PRE_OUT2 are input to the
舉例而言，請參閱圖9，並且搭配圖4至圖8B所示，圖9為說明執行本發明一個或多個示例性實施例之內部鎖存器電路之鎖存信號產生方法的時序圖。如圖9所示，首先，輸入延遲信號WR_LAT_P1起始值為低值L，並且在時間點A處響應該時脈信號CLK，使輸入延遲信號WR_LAT_P1變為高值H；在兩個時間週期tCK後，由於輸入延遲信號WR_LAT_P1輸入該第一低初始值D型正反器11以及該第二低初始值D型正反器12，第一低初始值D型正反器11基於內部選取脈衝信號INT_DQS並響應輸入延遲信號WR_LAT_P1，使得第二低初始值D型正反器12所輸出之第一內部輸入信號DDS_CK_EN1變為高值H，同時，該第一內部輸入信號DDS_CK_EN1輸入至內部鎖存信號產生電路5，使得第一反向前輸出信號NOT_PRE_OUT1變為低值L，以致鎖存信號DDS_CK變為高值H；在四個時間週期tCK後，由於輸入延遲信號WR_LAT_P1輸入第一低初始值D型正反器11、第二低初始值D型正反器12、第一高初始值D型正反器21以及第三低初始值D型正反器13，使得第三低初始值D型正反器13所輸出之第一反向內部輸入信號NOT_DDS_CK_DIS1變為低值L，同時，該第一內部輸入信號DDS_CK_EN1輸入至內部鎖存信號產生電路5，使得第一反向前輸出信號NOT_PRE_OUT1變為高值H，以致鎖存信號DDS_CK變為低值L；在六個時間週期tCK後，由於輸入延遲信號WR_LAT_P1輸入第一低初始值D型正反器11、該第二低初始值D型正反器12、該第一高初始值D型正反器21、該第三低初始值D型正反器13、該第二高初始值D型正反器22、以及該第四低初始值D型正反器14，使得第四低初始值D型正反器14所輸出之第二內部輸入信號DDS_CK_EN2變為高值H，同時，該第二內部輸入信號DDS_CK_EN2輸入至內部鎖存信號產生電路5，使得第二反向前輸出信號NOT_PRE_OUT2變為低值L，以致鎖存信號DDS_CK變為高值H；在八個時間週期tCK後，由於輸入延遲信號WR_LAT_P1輸入第一低初始值D型正反器11、該第二低初始值D型正反器12、第一高初始值D型正反器21、第三低初始值D型正反器13、第二高初始值D型正反器22、第四低初始值D型正反器14、第三高初始值D型正反器23以及第五低初始值D型正反器15，使得第五低初始值D型正反器153所輸出之第二反向內部輸入信號NOT_DDS_CK_DIS2變為低值L，同時，該第二反向內部輸入信號NOT_DDS_CK_DIS2輸入至內部鎖存信號產生電路5，使得第二反向前輸出信號NOT_PRE_OUT2變為高值H，以致鎖存信號DDS_CK變為低值L。For example, please refer to FIG. 9 in conjunction with FIG. 4 to FIG. 8B. FIG. 9 is a timing diagram illustrating the latch signal generation method of the internal latch circuit according to one or more exemplary embodiments of the present invention. As shown in Figure 9, first, the input delay signal WR_LAT_P1 has a low initial value L, and in response to the clock signal CLK at time point A, the input delay signal WR_LAT_P1 becomes a high value H; in two time periods tCK Later, since the input delay signal WR_LAT_P1 is input to the first low initial value D-type flip-flop 11 and the second low initial value D-type flip-flop 12, the first low initial value D-type flip-flop 11 is based on an internally selected pulse signal INT_DQS responds to the input delay signal WR_LAT_P1, so that the first internal input signal DDS_CK_EN1 output by the second low initial value D-type flip-flop 12 becomes a high value H, and at the same time, the first internal input signal DDS_CK_EN1 is input to the internal latch signal The generating circuit 5 makes the output signal NOT_PRE_OUT1 before the first reversal change to a low value L, so that the latch signal DDS_CK changes to a high value H; after four time periods tCK, the first low initial value D is input due to the input delay signal WR_LAT_P1 Type flip-flop 11, second low initial value D-type flip-flop 12, first high initial value D-type flip-flop 21, and third low initial value D-type flip-flop 13, making the third low initial value D-type The first reverse internal input signal NOT_DDS_CK_DIS1 output by the flip-flop 13 becomes a low value L, and at the same time, the first internal input signal DDS_CK_EN1 is input to the internal latch signal generating circuit 5, so that the first pre-reverse output signal NOT_PRE_OUT1 changes Is a high value H, so that the latch signal DDS_CK becomes a low value L; after six time periods tCK, due to the input delay signal WR_LAT_P1 input to the first low initial value D-type flip-flop 11, the second low initial value D-type The flip-flop 12, the first high initial value D-type flip-flop 21, the third low initial value D-type flip-flop 13, the second high initial value D-type flip-flop 22, and the fourth low initial value The value D-type flip-flop 14 makes the second internal input signal DDS_CK_EN2 output by the fourth low initial value D-type flip-flop 14 change to a high value H, and at the same time, the second internal input signal DDS_CK_EN2 is input to the internal latch signal The generating circuit 5 causes the second pre-reverse output signal NOT_PRE_OUT2 to become a low value L, so that the latch signal DDS_CK becomes a high value H; after eight time periods tCK, the first low initial value D is input due to the input delay signal WR_LAT_P1 Type flip flop 11, the second low initial value D type flip flop 12, the first high initial value D type flip flop 21, the third low initial value D type flip flop 13, the second high initial value D type The flip-flop 22, the fourth low-initial value D-type flip-flop 14, the third high-initial-value D-type flip-flop 23, and the fifth low-initial-value D-type flip-flop 15 make the fifth low-initial value D-type flip-flop The second inverted internal input signal NOT_DDS_CK_DIS2 output by the inverter 153 becomes a low value L, and at the same time, the second inverted internal input signal NOT_DDS_ CK_DIS2 is input to the internal latch signal generating circuit 5, so that the second pre-reverse output signal NOT_PRE_OUT2 becomes a high value H, so that the latch signal DDS_CK becomes a low value L.
值得一提的是，由上述說明可得知，根據本發明之內部鎖存器電路100所產生的鎖存信號DDS_CK，在輸入延遲信號WR_LAT_P1於時間點A處響應該時脈信號CLK開始，並往後四個時間週期tCK之內，該鎖存信號DDS_CK僅由第一低初始值D型正反器11、第二低初始值D型正反器12、第一高初始值D型正反器21、第三低初始值D型正反器13、內部鎖存信號產生電路5以及反及閘6所產生，另外，在時間點A往後四個時間週期tCK開始，並直到往後八個時間週期tCK之內，該鎖存信號DDS_CK僅由第二高初始值D型正反器22、第四低初始值D型正反器14、第三高初始值D型正反器23、第五低初始值D型正反器15、內部鎖存信號產生電路5以及反及閘6所產生，然而本發明不限於此。It is worth mentioning that, according to the above description, the latch signal DDS_CK generated by the
藉此，由上述說明可得知，根據本發明所提供之內部鎖存器電路100並搭配其鎖存信號DDS_CK產生方法，在產生內部鎖存信號DDS_CK的過程中，內部鎖存器電路100僅響應該輸入延遲信號WR_LAT_P1的上升邊緣，而不受該輸入延遲信號WR_LAT_P1的下降邊緣影響，更詳而言之，本發明之內部鎖存器電路100所產生之內部鎖存信號DDS_CK，不會由於外部環境的溫度或者金屬氧化物半導體場效電晶體之製成技術，所造成輸入延遲信號WR_LAT_P1的上升邊緣以及下降邊緣的改變，從而使得雙通道同步動態隨機存取記憶體不能穩定的執行寫入操作。透過本發明之內部鎖存器電路100並搭配其鎖存信號DDS_CK產生方法，使得雙通道同步動態隨機存取記憶體不受製成技術以及外部環境溫度的影響，透過精確的內部鎖存信號DDS_CK，以穩定的執行寫入操作。Therefore, it can be known from the above description that according to the
值得再提的是，在本發明另一實施例中，輸入延遲信號WR_LAT_P1由於外部環境的溫度或者金屬氧化物半導體場效電晶體之製成技術，造成輸入延遲信號WR_LAT_P1的上升邊緣以及下降邊緣的改變，然而使用本發明所提供之內部鎖存器電路100，並搭配其鎖存信號DDS_CK產生方法，依據上述步驟，仍然可以產生正確的鎖存信號DDS_CK，以穩定的執行寫入操作。其中，上述步驟S1'、步驟S2'、步驟S3'、步驟S4'、步驟S5'、步驟S6'、步驟S7'等步驟，該些步驟已描述如前內容，在此不再重複說明。It is worth mentioning that, in another embodiment of the present invention, the input delay signal WR_LAT_P1 due to the temperature of the external environment or the manufacturing technology of the metal oxide semiconductor field effect transistor, causes the rising edge and the falling edge of the input delay signal WR_LAT_P1 However, using the
藉此，本發明具有以下之實施功效及技術功效：Therefore, the present invention has the following implementation effects and technical effects:
其一，藉由本發明之內部鎖存器電路100，並搭配其鎖存信號DDS_CK產生方法，使得雙通道同步動態隨機存取記憶體不受製成技術以及外部環境溫度的影響，透過精確的內部鎖存信號DDS_CK，以穩定的執行寫入操作。First, with the
其二，本發明之內部鎖存器電路100，相較於習用技術之內部鎖存器電路僅增加簡單的元件，使本領域中具有通常知識者可以簡單的實現根據本發明之內部鎖存器電路100，具有簡單實現及低成本等功效。Second, the
其三，藉由本發明之內部鎖存器電路100，並搭配其鎖存信號DDS_CK產生方法，使得雙通道同步動態隨機存取記憶體不受輸入延遲信號的延遲時間tDQSS發生變化的影響，以改善延遲時間tDQSS對於雙通道同步動態隨機存取記憶體執行寫入操作時的影響。Third, with the
以上係藉由特定的具體實施例說明本發明之實施方式，所屬技術領域具有通常知識者可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The above is a description of the implementation of the present invention through specific specific embodiments. Those with ordinary knowledge in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification.
儘管本發明是透過參考附圖中所描繪的實施例進行說明，但其僅為實施例，本領域中具有通常知識者應當理解的是可以對其進行各種改變以及變形。然而，這些改變以及變形不應脫離本發明所保護的範圍。因此，本發明的保護範圍必須被限定於所附的申請專利範圍。Although the present invention is described with reference to the embodiments depicted in the drawings, it is only an embodiment, and a person with ordinary knowledge in the art should understand that various changes and modifications can be made to it. However, these changes and modifications should not depart from the scope of protection of the present invention. Therefore, the scope of protection of the present invention must be limited to the scope of the attached patent application.
100:內部鎖存器電路 1:第一延遲電路10:低初始值D型正反器 101:輸入端 102:輸出端 103:反向輸出端 104:內部選取脈衝輸入端 11:第一低初始值D型正反器 111:第一輸入端 112:第一輸出端 113:第一反向輸出端 114:第一內部選取脈衝輸入端 12:第二低初始值D型正反器 121:第二輸入端 122:第二輸出端 123:第二反向輸出端 124:第二內部選取脈衝輸入端 13:第三低初始值D型正反器 131:第四輸入端 132:第四輸出端 133:第四反向輸出端 134:第四內部選取脈衝輸入端 14:第四低初始值D型正反器 141:第六輸入端 142:第六輸出端 143:第六反向輸出端 144:第六內部選取脈衝輸入端 15:第五低初始值D型正反器 151:第八輸入端 152:第八輸出端 153:第八反向輸出端 154:第八內部選取脈衝輸入端 2:第二延遲電路 20:高初始值D型正反器 201:輸入端 202:輸出端 203:反向輸出端 204:內部選取脈衝輸入端 21:第一高初始值D型正反器 211:第三輸入端 212:第三輸出端 213:第三反向輸出端 214:第三內部選取脈衝輸入端 22:第二高初始值D型正反器 221:第五輸入端 222:第五輸出端 223:第五反向輸出端 224:第五內部選取脈衝輸入端 23:第三高初始值D型正反器 231:第七輸入端 232:第七輸出端 233:第七反向輸出端 234:第七內部選取脈衝輸入端3: 第三延遲電路 4:第四延遲電路 5:內部鎖存信號產生電路 6:反及閘 7:重置輸入端 CLK:時脈信號 DDS_CK:內部鎖存信號 DDS_CK_EN1:第一內部輸入信號 DDS_CK_EN2:第二內部輸入信號 DQS:選取脈衝信號 INT_DQS:內部選取脈衝信號 NOT_DDS_CK_DIS1:第一反向內部輸入信號 NOT_DDS_CK_DIS 2:第二反向內部輸入信號 NOT_PRE_OUT1:第一反向前輸出信號 NOT_PRE_OUT2:第二反向前輸出信號 NOT_RST:反向重置信號 WR_LAT_P1:輸入延遲信號 WR_LAT_P1#1:短輸入延遲信號 WR_LAT_P1#2:長輸入延遲信號 tCK:時間週期 S1:接收延遲訊號步驟 S2:響應延遲信號步驟 S3:輸出信號產生步驟 S4:生成內部鎖存信號步驟 S1':步驟 S2':步驟 S3':步驟 S4':步驟 S5':步驟 S6':步驟 S7':步驟 100: Internal latch circuit 1: First delay circuit 10: Low initial value D-type flip-flop 101: Input 102: output 103: Reverse output 104: Internally select pulse input 11: The first low initial value D-type flip-flop 111: The first input 112: First output 113: The first reverse output terminal 114: The first internal selection pulse input terminal 12: The second lowest initial value D-type flip-flop 121: second input 122: second output 123: The second reverse output terminal 124: The second internal selection pulse input terminal 13: The third lowest initial value D-type flip-flop 131: Fourth input 132: Fourth output 133: Fourth reverse output terminal 134: The fourth internal selection pulse input terminal 14: The fourth lowest initial value D-type flip-flop 141: Sixth input 142: Sixth output 143: The sixth reverse output terminal 144: The sixth internal selection pulse input terminal 15: The fifth lowest initial value D-type flip-flop 151: Eighth input 152: Eighth output 153: Eighth reverse output 154: Eighth internal selection pulse input terminal 2: The second delay circuit 20: High initial value D-type flip-flop 201: Input 202: output 203: Reverse output 204: Internally select pulse input 21: The first high initial value D-type flip-flop 211: Third input 212: third output 213: Third reverse output terminal 214: The third internal selection pulse input terminal 22: The second highest initial value D-type flip-flop 221: Fifth input 222: Fifth output terminal 223: Fifth reverse output terminal 224: Fifth internal selection pulse input terminal 23: The third highest initial value D-type flip-flop 231: seventh input 232: seventh output 233: seventh reverse output 234: The seventh internal selection pulse input terminal 3: The third delay circuit 4: The fourth delay circuit 5: Internal latch signal generation circuit 6: reverse and gate 7: Reset input CLK: clock signal DDS_CK: internal latch signal DDS_CK_EN1: The first internal input signal DDS_CK_EN2: The second internal input signal DQS: select pulse signal INT_DQS: internal selection pulse signal NOT_DDS_CK_DIS1: The first reverse internal input signal NOT_DDS_CK_DIS 2: The second reverse internal input signal NOT_PRE_OUT1: Output signal before the first reverse NOT_PRE_OUT2: Output signal before the second reverse NOT_RST: Reverse reset signal WR_LAT_P1: Input delay signal WR_LAT_P1#1: Short input delay signal WR_LAT_P1#2: Long input delay signal tCK: time period S1: Steps to receive delayed signal S2: Respond to the delayed signal step S3: Output signal generation steps S4: Steps to generate internal latch signal S1': Step S2': Step S3': Step S4': Step S5': Step S6': Step S7': steps
圖1為習用技術之內部鎖存器電路的示意性電路方塊圖； 圖2為說明輸入延遲信號的上升邊緣以及下降邊緣的改變示意圖； 圖3為根據本發明之內部鎖存器電路的示意性電路方塊圖； 圖4為根據本發明一個或多個示例性實施例之內部鎖存器電路的示意性電路方塊圖； 圖5為根據本發明一個或多個示例性實施例之高初始值D型正反器的示意性電路圖； 圖6為根據本發明一個或多個示例性實施例之低初始值D型正反器的示意性電路圖； 圖7為說明本發明之鎖存信號產生方法的部分步驟流程圖； 圖8A為說明執行本發明一個或多個示例性實施例之內部鎖存器電路的鎖存信號產生方法的部分步驟流程圖； 圖8B為說明執行本發明一個或多個示例性實施例之內部鎖存器電路的鎖存信號產生方法的部分步驟流程圖； 圖9為說明執行本發明一個或多個示例性實施例之內部鎖存器電路之鎖存信號產生方法的時序圖。 Figure 1 is a schematic circuit block diagram of the internal latch circuit of the conventional technology; 2 is a schematic diagram illustrating the change of the rising edge and the falling edge of the input delay signal; Figure 3 is a schematic circuit block diagram of an internal latch circuit according to the present invention; 4 is a schematic circuit block diagram of an internal latch circuit according to one or more exemplary embodiments of the present invention; Fig. 5 is a schematic circuit diagram of a high initial value D-type flip-flop according to one or more exemplary embodiments of the present invention; 6 is a schematic circuit diagram of a low initial value D-type flip-flop according to one or more exemplary embodiments of the present invention; FIG. 7 is a flowchart illustrating part of the steps of the latch signal generation method of the present invention; FIG. 8A is a flowchart illustrating partial steps of the latch signal generation method of the internal latch circuit of one or more exemplary embodiments of the present invention; FIG. FIG. 8B is a flowchart illustrating partial steps of the latch signal generation method of the internal latch circuit of one or more exemplary embodiments of the present invention; FIG. FIG. 9 is a timing diagram illustrating a method of generating a latch signal of an internal latch circuit according to one or more exemplary embodiments of the present invention.
100:內部鎖存器電路 100: Internal latch circuit
11:第一低初始值D型正反器 11: The first low initial value D-type flip-flop
111:第一輸入端 111: The first input
112:第一輸出端 112: First output
113:第一反向輸出端 113: The first reverse output terminal
114:第一內部選取脈衝輸入端 114: The first internal selection pulse input terminal
12:第二低初始值D型正反器 12: The second lowest initial value D-type flip-flop
121:第二輸入端 121: second input
122:第二輸出端 122: second output
123:第二反向輸出端 123: The second reverse output terminal
124:第二內部選取脈衝輸入端 124: The second internal selection pulse input terminal
13:第三低初始值D型正反器 13: The third lowest initial value D-type flip-flop
131:第四輸入端 131: Fourth input
132:第四輸出端 132: Fourth output
133:第四反向輸出端 133: Fourth reverse output terminal
134:第四內部選取脈衝輸入端 134: The fourth internal selection pulse input terminal
14:第四低初始值D型正反器 14: The fourth lowest initial value D-type flip-flop
141:第六輸入端 141: Sixth input
142:第六輸出端 142: Sixth output
143:第六反向輸出端 143: The sixth reverse output terminal
144:第六內部選取脈衝輸入端 144: The sixth internal selection pulse input terminal
15:第五低初始值D型正反器 15: The fifth lowest initial value D-type flip-flop
151:第八輸入端 151: Eighth input
152:第八輸出端 152: Eighth output
153:第八反向輸出端 153: Eighth reverse output
154:第八內部選取脈衝輸入端 154: Eighth internal selection pulse input terminal
21:第一高初始值D型正反器 21: The first high initial value D-type flip-flop
211:第三輸入端 211: Third input
212:第三輸出端 212: third output
213:第三反向輸出端 213: Third reverse output terminal
214:第三內部選取脈衝輸入端 214: The third internal selection pulse input terminal
22:第二高初始值D型正反器 22: The second highest initial value D-type flip-flop
221:第五輸入端 221: Fifth input
222:第五輸出端 222: Fifth output terminal
223:第五反向輸出端 223: Fifth reverse output terminal
224:第五內部選取脈衝輸入端 224: Fifth internal selection pulse input terminal
23:第三高初始值D型正反器 23: The third highest initial value D-type flip-flop
231:第七輸入端 231: seventh input
232:第七輸出端 232: seventh output
233:第七反向輸出端 233: seventh reverse output
234:第七內部選取脈衝輸入端 234: The seventh internal selection pulse input terminal
5:內部鎖存信號產生電路 5: Internal latch signal generation circuit
6:反及閘 6: reverse and gate
7:重置輸入端 7: Reset input
DDS_CK:內部鎖存信號 DDS_CK: internal latch signal
DDS_CK_EN1:第一內部輸入信號 DDS_CK_EN1: The first internal input signal
DDS_CK_EN2:第二內部輸入信號 DDS_CK_EN2: The second internal input signal
INT_DQS:內部選取脈衝信號 INT_DQS: internal selection pulse signal
NOT_DDS_CK_DIS1:第一反向內部輸入信號 NOT_DDS_CK_DIS1: The first reverse internal input signal
NOT_DDS_CK_DIS 2:第二反向內部輸入信號 NOT_DDS_CK_DIS 2: The second reverse internal input signal
NOT_PRE_OUT1:第一反向前輸出信號 NOT_PRE_OUT1: Output signal before the first reverse
NOT_PRE_OUT2:第二反向前輸出信號 NOT_PRE_OUT2: Output signal before the second reverse
NOT_RST:反向重置信號 NOT_RST: Reverse reset signal
WR_LAT_P1:輸入延遲信號 WR_LAT_P1: Input delay signal
Claims (10)
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| TW201841159A (en) * | 2017-01-13 | 2018-11-16 | 韓商愛思開海力士有限公司 | Semiconductor devices |
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| TW411465B (en) * | 1998-05-19 | 2000-11-11 | Oki Micro Design Kk | Semiconductor memory device |
| EP1035548A1 (en) * | 1999-03-08 | 2000-09-13 | Kabushiki Kaisha Toshiba | Synchronous semiconductor memory device |
| US20020172090A1 (en) * | 2001-05-15 | 2002-11-21 | Samsung Electronic Co., Ltd. | SDRAM having data latch circuit for outputting input data in synchronization with a plurality of control signals |
| TW200406787A (en) * | 2001-11-07 | 2004-05-01 | Samsung Electronics Co Ltd | Expanded operating frequency synchronous semiconductor memory device having wave pipeline structure and wave pipeline control method thereof |
| TW200414226A (en) * | 2002-08-01 | 2004-08-01 | Samsung Electronics Co Ltd | Semiconductor memory device and associated data read method |
| US7830731B2 (en) * | 2005-09-29 | 2010-11-09 | Hynix Semiconductor Inc. | Circuit for initializing a pipe latch unit in a semiconductor memory device |
| US9613001B2 (en) * | 2013-12-20 | 2017-04-04 | Intel Corporation | Processing device for performing convolution operations |
| TW201841159A (en) * | 2017-01-13 | 2018-11-16 | 韓商愛思開海力士有限公司 | Semiconductor devices |
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| TW202218334A (en) | 2022-05-01 |
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