TWI737084B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI737084B
TWI737084B TW108146311A TW108146311A TWI737084B TW I737084 B TWI737084 B TW I737084B TW 108146311 A TW108146311 A TW 108146311A TW 108146311 A TW108146311 A TW 108146311A TW I737084 B TWI737084 B TW I737084B
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planar transistor
semiconductor device
transistor
gate electrode
field plate
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TW202101600A (zh
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笠原清貴
奥村健祐
山之内智雄
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日商愛德萬測試股份有限公司
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Abstract

本發明提供一種可高速運作的平面型電晶體。於半導體裝置100，積體化有平面型電晶體20。平面型電晶體20包括源電極24、閘電極22、汲電極26及場板28。源電極24與場板28連接於平面型電晶體20的主動區域32外。

Description

半導體裝置
本發明是有關於一種半導體裝置，其包括高電子遷移率電晶體(High Electron Mobility Transistor，HEMT)。
作為現有的矽系半導體器件的代替，正在推進可進行更高耐壓運作、高速運作的氮化物系化合物半導體裝置的開發。
化合物半導體電晶體與現有的Si電晶體同樣，包括平面型電晶體(planar transistor)結構。平面型電晶體藉由施加於閘極與汲極之間的反方向電場集中於閘電極(gate electrode)端部，而限制耐壓。為了緩和此制限，進一步提高耐壓，而設置場板(field plate)。圖1是包括場板的現有的平面型電晶體10的剖面圖。
平面型電晶體10包括磊晶(epitaxial)基板(SUB)、閘電極(G)12、源電極(S)14、汲電極(D)16及場板(FP)18。場板18與閘電極12的一部分重疊(overlap)，從源電極14向汲電極16延伸。
圖1中示出包括場板的電晶體的電場分佈E。藉由設置場板18，電場的強度分佈的波峰分散於閘電極12的端部、及場板18的端部，藉此能提高電晶體的耐壓。
[現有技術文獻] [專利文獻]
[專利文獻1]日本專利特開2015-176981號公報
[專利文獻2]日本專利特開2013-183060號公報
[專利文獻3]日本專利特開2017-107941號公報
[專利文獻4]日本專利特開2017-529706號公報
本發明者對圖1的平面型電晶體10進行研究，結果認識到以下課題。
圖1的器件結構中，閘電極12與場板18重疊。此重疊於電晶體的閘極-源極間導致寄生電容(parasitic capacitance)。此寄生電容為電晶體的輸入電容，成為妨礙高速的切換運作的原因。
本發明是於所述狀況下形成，其某形態的例示性目的之一在於提供一種可高速運作的平面型電晶體。
本發明的某形態的半導體裝置包括平面型電晶體。平面型電晶體包括源電極、閘電極、汲電極以及場板，源電極與場板連接於平面型電晶體的主動區域外。
此形態中，能夠消除場板與閘電極的重疊。另外，將場板與源電極連接的連接配線與閘電極的重疊亦不存在。因此，能夠降低電晶體的輸入電容，可高速運作。另外，於場板與閘電極重疊的結構中，存在場板產生段割(stepped cut)的可能性，或者， 於跨越閘電極而將源電極與場板連接的結構中，存在連接配線產生段割的可能性。根據此形態，可使將場板與源電極連接的配線形成於平坦的區域，因此能夠消除段割，提高可靠性。
平面型電晶體亦可包括多指結構(multifinger structure)。
平面型電晶體亦可為GaN-高電子遷移率電晶體(High Electron Mobility Transistor，HEMT)。GaN-HEMT亦可為金屬絕緣半導體(Metal Insulator Semiconductor，MIS)型。
根據本發明的某形態，能夠提供一種高耐壓且高速的平面型電晶體。
10、20、20A、20B:平面型電晶體
12、22、G:閘電極
14、24、S:源電極
16、26、D:汲電極
18、28、28A、28B、FP:場板
30、30A、30B:連接配線
32:主動區域
50:反相器電路
52:電晶體
54:電阻
60:驅動器
100、100A:半導體裝置
102、SUB:磊晶基板
CTRL-REF:控制訊號
E:電場分佈
Id:漏電流
LS:位準偏移器
Toff:斷開時間
Ton:接通時間
Vdd:電源電壓
Vin:輸入訊號
Vout:輸出電壓
圖1是包括場板的現有的平面型電晶體的剖面圖。
圖2的(a)是實施方式的半導體裝置的剖面圖，圖2的(b)是平面型電晶體的俯視圖。
圖3是用於進行性能比較的電阻負載的反相器電路(inverter circuit)的電路圖。
圖4的(a)、圖4的(b)是表示由圖1的平面型電晶體來構成圖3的反相器電路時、以及由圖2的平面型電晶體來構成圖3的反相器電路時的接通(turn on)運作的圖。
圖5的(a)、圖5的(b)是表示由圖1的平面型電晶體來構 成圖3的反相器電路時、以及由圖2的平面型電晶體來構成圖3的反相器電路時的斷開(turn off)運作的圖。
圖6是表示圖1的平面型電晶體的漏電流(leak current)(i)、及圖2的平面型電晶體的漏電流(ii)的測定結果的圖。
圖7的(a)、圖7的(b)是表示圖1的平面型電晶體、圖2的平面型電晶體的掃描式電子顯微鏡(Scanning Electron Microscope，SEM)剖面圖像的圖。
圖8的(a)是變形例1的半導體裝置的剖面圖，圖8的(b)是表示電場的強度分佈的圖，圖8的(c)是平面型電晶體的俯視圖。
圖9是變形例2的平面型電晶體的俯視圖。
以下，參照圖式，基於較佳的實施方式來對本發明進行說明。對各圖式所示的同一或同等的構成部件、構件、處理，標註同一符號，適當省略重覆的說明。另外，實施方式並不對發明加以限定，而是例示，實施方式中所記述的所有特徵或其組合未必為發明的本質性特徵。
圖式中記載的各構件的尺寸(厚度、長度、寬度等)存在為了容易理解，而適當放大縮小的情況。進而，多個構件的尺寸未必表示他們的大小關係，於圖式上，即便某個構件A描畫得較另一構件B厚，構件A亦可能較構件B薄。
圖2的(a)是實施方式的半導體裝置100的剖面圖， 圖2的(b)是平面型電晶體20的俯視圖。於半導體裝置100，積體化有多個平面型電晶體20，圖1中僅示出一個電晶體20。
平面型電晶體20包括：形成於磊晶(epitaxial)基板102上的閘電極22、源電極24、汲電極26、場板28及連接配線30。平面型電晶體20的種類並無特別限定，例如可為GaN-HEMT或GaAs-HEMT。平面型電晶體20亦可為增強(enhancement)型(常關(normally off))，平面型電晶體20亦可具有於閘電極22與磊晶基板102之間包括絕緣膜的MIS結構。或者平面型電晶體20亦可為下降(depression)型(常開(normally on))，亦可具有閘電極22與磊晶基板102接觸的肖特基結構。
磊晶基板102至少包含電子走行層及電子供給層。作為一例，電子走行層可為GaN層，電子供給層可為AlGaN層。
閘電極22、源電極24、汲電極26、場板28將第一方向(圖中為y軸方向)設為長邊，以源電極24、閘電極22、場板28、汲電極26的順序，於第二方向(圖中為x方向)排列配置。本實施方式中，場板28的高度高於閘電極22的高度。
如圖2的(b)所示，源電極24與場板28於平面型電晶體20的主動區域32外，經由連接配線30而以平面的方式連接。
以上為半導體裝置100的結構。繼而對其效果進行說明。實施方式的半導體裝置100(平面型電晶體20)中，場板28與閘電極22的重疊不存在，另外，連接配線30與閘電極22的重疊亦不存在。因此，與圖1的結構相比，能夠削減閘電極22與連 接配線30之間的寄生電容。藉此能夠削減平面型電晶體20的輸入電容，可高速運作。
實際製作圖1的平面型電晶體10、及圖2的平面型電晶體20，對將性能加以比較的結果進行說明。
圖3是用於進行性能比較的電阻負載的反相器電路的電路圖。反相器電路50包含電晶體52、電阻54。電晶體52的源極接地。於電晶體52的汲極與電源線之間，設置電阻54。電晶體52為常開器件。驅動器60為反轉型的位準偏移器(level shifter)，根據輸入訊號Vin生成控制訊號CTRL-REF，並驅動電晶體52的閘極。在電晶體52與電阻54的連接節點產生輸出電壓Vout。對由圖1的平面型電晶體10來構成圖3的電晶體52的情況、以及由圖2的平面型電晶體20來構成圖3的電晶體52的情況下的他們的響應速度加以比較。
圖4的(a)、圖4的(b)是表示由圖1的平面型電晶體10來構成圖3的反相器電路50時、以及由圖2的平面型電晶體20來構成圖3的反相器電路50時的接通運作的圖。於5V及10V的兩種電源電壓Vdd下進行測定。如圖4的(a)所示，於使用圖1的平面型電晶體10的情況下，接通時間Ton為0.233ms。與此相對，如圖4的(b)所示，於使用圖2的平面型電晶體20的情況下，接通時間Ton為0.146ms，與圖1的平面型電晶體10的情況相比，縮短了0.087ms。
圖5的(a)、圖5的(b)是表示由圖1的平面型電晶 體10來構成圖3的反相器電路50時、以及由圖2的平面型電晶體20來構成圖3的反相器電路50時的斷開運作的圖。如圖5的(a)所示，於使用圖1的平面型電晶體10的情況下，斷開時間Toff為0.272ms。與此相對，如圖5的(b)所示，於使用圖2的平面型電晶體20的情況下，斷開時間Toff成為0.199ms，與圖1的平面型電晶體10的情況相比，縮短了0.073ms。
如上所述，圖2的平面型電晶體10中，閘極源極間電容可削減，因此可高速運作。
圖6是表示圖1的平面型電晶體10的漏電流Id(i)、及圖2的平面型電晶體20的漏電流Id(ii)的測定結果的圖。根據圖6可知，於圖2的平面型電晶體20中，亦獲得與圖1的平面型電晶體10比較而言並不遜色的特性。
圖7的(a)、圖7的(b)是表示圖1的平面型電晶體10、圖2的平面型電晶體20的SEM剖面圖像的圖。此SEM剖面圖像是於電晶體的主動區域內取得。如圖7的(a)所示，圖1的平面型電晶體10中，源電極與場板交叉，成為場板容易於閘電極的端部產生段割的結構。
與此相對，如圖7的(b)所示，圖2的平面型電晶體20中，於主動區域內不存在連接配線30，故而無需擔憂段割，因此能夠提高元件的可靠性。
另外，本實施方式中，亦存在無需於主動區域內形成通孔(via hole)等的優點。
以上，關於本發明，已基於實施方式來進行說明。此實施方式為例示，本領域技術人員可理解，可對這些各構成部件或各處理過程的組合進行各種變形，另外，此種變形例亦處於本發明的範圍內。以下。對此種變形例進行說明。
(變形例1)
圖8的(a)是變形例1的半導體裝置100A的剖面圖，圖8的(b)是表示電場的強度分佈的圖，圖8的(c)是平面型電晶體20A的俯視圖。
半導體裝置100A中，積體化有平面型電晶體20A。平面型電晶體20A包括多個場板28A、28B。即，源電極24、閘電極22、場板28A、場板28B、汲電極26以此順序排列。場板28A與場板28B形成為不同的高度，以使當觀察剖面圖時成為階梯狀。具體而言，隨著從閘電極22遠離，場板28的高度升高。
藉由設置多個場板28A、28B，可使電場集中進一步緩和，能夠進而提高耐壓。
如圖8的(c)所示，於變形例1中，場板28A、場板28B亦於主動區域32的外側，與源電極24連接。將場板28A與源電極24連接的連接配線30A、以及將場板28B與源電極24連接的連接配線30B積層。
此處已對場板為兩個的情況進行說明，但亦可設置三個以上的指板(finger plate)，藉此能夠使電場集中進而緩和。
(變形例2)
圖9是變形例2的平面型電晶體20B的俯視圖。此平面型電晶體20B具有多指結構，對每個指(一對閘電極及源電極)設置場板。
亦可將變形例1與變形例2加以組合。即，於多指結構的平面型電晶體20B中，亦可對每個指設置多個指板。
(變形例3)
實施方式中，已對平面型電晶體20為HEMT的情況加以說明，但並不限定於此，亦可為Si-場效電晶體(Field Effect Transistor，FET)，亦可為SiC-FET，半導體材料或器件結構並未限定。
雖已基於實施方式，對本發明加以說明，但實施方式僅示出本發明的原理、應用，實施方式中，於不脫離申請專利範圍所規定的本發明的思想的範圍內，確認多種變形例或配置的變更。
20:平面型電晶體
22、G:閘電極
24、S:源電極
26、D:汲電極
28、FP:場板
30:連接配線
32:主動區域
100:半導體裝置
102、SUB:磊晶基板

Claims (7)

  1. 一種半導體裝置，包括平面型電晶體，其特徵在於：所述平面型電晶體包括源電極、閘電極、汲電極及多個場板，且所述源電極與所述多個場板連接於所述平面型電晶體的主動區域外，所述多個場板設置為不同的高度，以及多個連接配線重疊形成於所述主動區域外，所述多個連接配線將所述多個場板與所述源電極連接。
  2. 如請求項1所述的半導體裝置，其中所述場板的高度高於所述閘電極的高度。
  3. 如請求項1所述的半導體裝置，其中所述場板的高度隨著從所述閘電極遠離而增高。
  4. 如請求項1至請求項3中任一項所述的半導體裝置，其中所述平面型電晶體包括多指結構。
  5. 如請求項1至請求項3中任一項所述的半導體裝置，其中所述平面型電晶體為氮化鎵-高電子遷移率電晶體、砷化鎵-高電子遷移率電晶體、矽-場效電晶體、碳化矽-場效電晶體中的任一者。
  6. 如請求項1至請求項3中任一項所述的半導體裝置，其中 包括於所述閘電極與磊晶基板之間形成有絕緣膜的金屬絕緣半導體結構。
  7. 如請求項1至第請求項3中任一項所述的半導體裝置，其中包括所述閘電極與磊晶基板接觸的肖特基結構。
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