TWI731025B - 半導體封裝的製造方法 - Google Patents
半導體封裝的製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 239000011347 resin Substances 0.000 claims abstract description 33
- 229920005989 resin Polymers 0.000 claims abstract description 33
- 238000007789 sealing Methods 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 50
- 230000001681 protective effect Effects 0.000 claims description 34
- 238000005520 cutting process Methods 0.000 claims description 14
- 239000007888 film coating Substances 0.000 claims description 6
- 238000009501 film coating Methods 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims 1
- 230000002411 adverse Effects 0.000 abstract description 4
- 239000002390 adhesive tape Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 238000010897 surface acoustic wave method Methods 0.000 description 1
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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Abstract
提供無需採用板金屏蔽即可遮蔽對無線系統造成不良影響的電磁波雜訊之半導體封裝及半導體封裝的製造方法。
提供一種半導體封裝,其具備:基板,在第1面、第2面及內部具有配線圖案;半導體元件,搭載於該基板之第1面上;密封樹脂,對該半導體元件進行密封;複數個外部連接電極,形成於該基板之第2面上;電磁波屏蔽膜,對在該密封樹脂之上面及該密封樹脂與該基板之側面所形成的電磁波進行屏蔽;及接地配線,與該電磁波屏蔽膜被電連接,被形成於該基板。
Description
本發明關於半導體封裝及半導體封裝的製造方法。
近年,攜帶型電話或智慧型手機等之攜帶型無線通信機器中,為求高機能化、高性能化等,構成搭載於機器內的無線系統的SAW元件(表面聲波元件,surface acoustic wave device)或天線元件等之電子元件之數目增加。
另外,機器內所搭載的DRAM或快閃記憶體等之各種半導體封裝之資料傳送速度變快,其結果,存在有各種半導體封裝產生的電磁波成為雜訊而對無線系統帶來不良影響之問題。
現在,作為該對策,使用藉由金屬板將包含產生電磁波雜訊的半導體封裝之電路予以包圍的板金屏蔽(例如參照特開2001-44680號公報及特開2004-72051號公報)。
[專利文獻1]特開2001-44680號公報
[專利文獻2]特開2004-72051號公報
但是,如專利文獻1或專利文獻2之記載般,採用藉由金屬板將包含半導體封裝之電路予以包圍的板金屏蔽構造之情況下,裝配所需面積變大,因此成為阻礙攜帶型電話或智慧型手機等攜帶型無線通信機器之小型化或薄型化之主要原因。
本發明有鑑於此,目的在於提供無需採用板金屏蔽即可遮蔽對無線系統造成不良影響的電磁波雜訊之半導體封裝及半導體封裝的製造方法。
依據請求項1記載之發明,提供一種半導體封裝,其特徵為具備:基板,在第1面、第2面及內部具有配線圖案;半導體元件,搭載於該基板之第1面上;密封樹脂,對該半導體元件進行密封;複數個外部連接電極,形成於該基板之第2面上;電磁波屏蔽膜,形成於該密封樹脂之上面及該密封樹脂與該基板之側面,對電磁波進行屏蔽;及接地配線,與該電磁波屏蔽膜電連接,形成
於該基板。
依據請求項2記載之發明,提供一種半導體封裝的製造方法,係關於請求項1記載之半導體封裝的製造方法,其特徵為具備:封裝基板準備工程,係準備封裝基板,該封裝基板係在以格子狀形成的複數個分割預定劃線所劃分之各區域配設半導體元件以樹脂進行密封,具備在被樹脂密封的第1面及相反側之第2面所形成的複數個外部連接電極者;保護膜被覆工程,在該封裝基板之形成有該外部連接電極的第2面之全面塗布液狀樹脂而形成保護膜;分割工程,藉由切削刃沿著分割預定劃線對該封裝基板進行切削,將該封裝基板分割為各個之半導體封裝;電磁波屏蔽膜形成工程,在被分割的該半導體封裝之該密封樹脂之上面及該半導體封裝之側面被覆金屬膜而形成遮蔽電磁波的屏蔽膜;及保護膜除去工程,將該半導體封裝之形成有該外部連接電極的第2面上所被覆之保護膜予以除去。
依據本發明,在半導體封裝之被實施樹脂密封的上面及包含基板的側面被覆由金屬膜構成的電磁波屏蔽膜,則進一步將半導體封裝裝配於母板時,藉由電磁波屏蔽膜作為接地之構造,據此,可以提供無需使用板金屏蔽且不會對無線系統造成不良影響的半導體封裝。
11‧‧‧封裝基板
13‧‧‧基板
14‧‧‧配線圖案
14a、14b‧‧‧接地用配線
16‧‧‧外部連接電極(凸塊)
17a、17b、17c‧‧‧元件區域
18‧‧‧密封樹脂
19‧‧‧分割預定劃線
20‧‧‧液狀樹脂塗布裝置
21‧‧‧元件配設部
23‧‧‧半導體元件
24‧‧‧保護膜
25‧‧‧凸塊
26‧‧‧切削刃
27‧‧‧半導體封裝
28‧‧‧電磁波屏蔽膜
30‧‧‧雷射加工頭(集光器)
32‧‧‧雷射束
[圖1]圖1(A)係封裝基板之平面圖,圖1(B)係封裝基板之背面圖。
[圖2]封裝基板之一部分擴大斷面圖。
[圖3]保護膜被覆工程之一例的斜視圖。
[圖4]圖4(A)係表示分割工程的封裝基板之一部分擴大斷面圖,圖4(B)係被分割工程分割的半導體封裝之斷面圖。
[圖5]圖5(A)係電磁波屏蔽膜形成工程實施後之半導體封裝之斷面圖,圖5(B)係保護膜除去工程實施後之半導體封裝之斷面圖。
[圖6]圖6(A)係表示一部分保護膜除去工程的封裝基板之一部分擴大斷面圖,圖6(B)係表示一部分保護膜除去工程實施後之分割工程的封裝基板之一部分擴大斷面圖。
[圖7]表示接地構造的半導體封裝之斷面圖。
以下,參照圖面說明本發明實施形態之詳細。參照圖1(A),圖示半導體封裝為BGA(Ball Grid Array)的封裝基板之平面圖。圖1(B)係封裝基板之背面圖。
封裝基板11具有矩形狀之樹脂基板13,在樹
脂基板13之外周過剩區域15及被元件區域15a所圍繞的區域,圖示之例中係存在3個元件區域17a、17b、17c。本實施形態中,基板13由樹脂形成,但可以取代樹脂基板13改用矽基板。
於各元件區域17a、17b、17c中,係在互以正交的方式形成的複數個分割預定劃線19所劃分的各區域形成元件配設部21,如圖2所示,在元件配設部21配設具有複數個凸塊25的半導體元件23。
如圖1(B)所示,與各元件區域17a、17b、17c對應的基板13之第1面13a係藉由密封樹脂(模鑄樹脂)18實施密封。在基板13之第1面13a、第2面13b及其內部形成配線圖案(導體圖案)14。
如圖2之最佳圖示般,在基板13之第2面13b形成與基板13內之配線圖案14連接的複數個外部連接電極(凸塊)16。圖1(A)之最佳圖示般,與各半導體元件23對應地沿著半導體元件23之4邊形成複數個外部連接電極16。
接著,說明本發明實施形態的半導體封裝的製造方法。首先,如圖1所示,實施準備封裝基板11的封裝基板準備工程,該封裝基板11,係在以格子狀形成的複數個分割預定劃線19所劃分的基板上之各區域21配設半導體元件21藉由樹脂18實施密封,且具備在被實施樹脂密封的面及相反側之面被形成的複數個外部連接電極(凸塊)16者。
接著,如圖3所示,由液狀樹脂塗布裝置20在封裝基板11之形成有外部連接電極16的面(第2面)13b之全面塗布液狀樹脂22,如圖4(A)所示,實施在基板13之第2面13b形成保護膜24的保護膜被覆工程。保護膜被覆工程可以藉由習知公知之網版印刷法、噴塗法、層壓法、旋塗法、噴墨法、蒸鍍法等實施。
實施保護膜被覆工程之後,如圖4(A)所示,實施對封裝基板11之密封樹脂18側貼附切割黏帶T1,在切割黏帶T1之外周部貼附未圖示的環狀框架,使封裝基板11透過切割黏帶T1而被環狀框架支撐的封裝基板支撐工程。
接著,實施以下工程:藉由切削裝置之夾頭平台透過切割黏帶T1吸附保持封裝基板11,如圖4(A)所示,藉由切削裝置之切削刃26對朝封裝基板11之縱方向及橫方向延伸的全部分割預定劃線19實施切削,將封裝基板11分割為各個半導體封裝27的分割工程。該分割工程中,使切削刃26沿著分割預定劃線19切入直至切割黏帶T1為止而對封裝基板11進行全切(full cut)。
實施分割工程之後,實施以下工程:使半導體封裝27之上下反轉,如圖4(B)所示,在半導體封裝27之保護膜24側貼附切割黏帶T2,在切割黏帶T2之外周貼附未圖示的框架,透過切割黏帶T2藉由框架對複數個半導體封裝27進行支撐的半導體封裝支撐工程。
實施半導體封裝支撐工程之後,實施以下工程:將被切割黏帶T2支撐之複數個半導體封裝27搬入蒸鍍爐中,藉由CVD(Chemical Vapor Deposition)或PVD(Physical Vapor Deposition),如圖5(A)所示,在半導體封裝27之上面及側面被覆金屬膜而形成遮蔽電磁波的電磁波屏蔽膜28的電磁波屏蔽膜形成工程。
該電磁波屏蔽膜28形成於密封樹脂18之上面以及密封樹脂18及基板13之側面。電磁波屏蔽膜28之厚度,例如較好是2μm~10μm之範圍,更好是3μm~8μm。電磁波屏蔽膜28的金屬,例如可以使用銅,鋁,鎳,不鏽鋼等。
電磁波屏蔽膜形成工程實施後,實施以下工程:將半導體封裝27之形成有外部連接電極16的面(第2面)13b上被被覆的保護膜24予以除去的保護膜除去工程。圖5(B)係保護膜除去工程實施後之半導體封裝27之斷面圖。
該狀態中,圖5(B)雖未特別圖示,但如圖7(A)所示,電磁波屏蔽膜28係與基板13之第2面13b上形成的接地用配線14a電連接。
因此,將半導體封裝27透過外部連接電極16以覆晶方式(Flip-Chip)裝配於母板時,電磁波屏蔽膜28透過接地用配線14a及外部連接電極16與未圖示的母板之接地圖案電連接,電磁波屏蔽膜28成為接地。
接著,參照圖6(A)~圖7(B)說明本發明
第2實施形態的分割工程及電磁波屏蔽膜形成工程。本實施形態的分割工程中,首先如圖6(A)所示,實施由雷射加工裝置之加工頭(集光器)30照射雷射束32,將分割預定劃線19上之保護膜24予以除去的一部分保護膜除去工程。
雷射束32以對保護膜24具有吸收性的波長之雷射束為較佳,例如可以採用YAG雷射之第3高次諧波(波長355nm)。於此,在一部分保護膜除去工程中,需要沿著分割預定劃線19將保護膜24除去比起切削刃26之寬度更寬之寬度,因此使雷射束32沿著分割預定劃線19在其寬度方向移動特定距離之同時,使雷射束32進行多次掃描(multi-pass scan),沿著全部之分割預定劃線19將保護膜除去比起切削刃26之厚度更寬之寬度。
一部分保護膜除去工程實施後,如圖6(B)所示,實施藉由切削刃26沿著封裝基板11之分割預定劃線19對封裝基板11進行切削,將封裝基板11分割為各個半導體封裝27的分割工程。
分割工程實施後,和圖4(B)所示者同樣,實施使半導體封裝27之上下反轉而在封裝基板11之保護膜24側貼附切割黏帶T2,藉由CVD法或PVD法等如圖7(B)所示,對半導體封裝27之已實施樹脂密封的上面及密封樹脂18及基板13之側面進行金屬膜之被覆而形成電磁波屏蔽膜18的電磁波屏蔽膜形成工程。
本實施形態之情況下,藉由圖6(A)所示一
部分保護膜除去工程,沿著分割預定劃線19使特定寬度之保護膜24被除去,因此如圖7(B)所示,電磁波屏蔽膜28形成為繞入到基板13之第2面13b為止。
因此,電磁波屏蔽膜28透過接地用配線14b、外部連接電極16被接地於母板之接地圖案。本實施形態對於接地用配線14b未延伸至基板13之側面的半導體封裝27有效。
13:基板
14:配線圖案
14a、14b:接地用配線
16:外部連接電極(凸塊)
18:密封樹脂
23:半導體元件
25:凸塊
27:半導體封裝
28:電磁波屏蔽膜
Claims (2)
- 一種半導體封裝的製造方法,該半導體封裝具備:基板,在第1面、第2面及內部具有配線圖案;半導體元件,搭載於該基板之第1面上;密封樹脂,對該半導體元件進行密封;複數個外部連接電極,形成於該基板之第2面上;電磁波屏蔽膜,形成在該密封樹脂之上面以及該密封樹脂與該基板之側面且對電磁波進行屏蔽;及接地配線,與該電磁波屏蔽膜電連接,被形成於該基板的第2面;該製造方法的特徵為具備:封裝基板準備工程,係準備封裝基板,該封裝基板係在以形成為格子狀的複數個分割預定劃線所劃分之各區域配設半導體元件並以密封樹脂進行密封,且具備在被樹脂密封的第1面及相反側之第2面上形成的複數個外部連接電極者;保護膜被覆工程,在該封裝基板之形成有該外部連接電極的第2面之全面塗布液狀樹脂而形成保護膜;一部分保護膜除去工程,係沿著該封裝基板之該分割預定劃線,將該分割預定劃線上之該保護膜之一部分予以除去;分割工程,藉由切削刃沿著該分割預定劃線對該封裝基板進行切削,將該封裝基板分割為各個半導體封裝;電磁波屏蔽膜形成工程,在被分割的該半導體封裝之 該密封樹脂之上面及該半導體封裝之側面被覆金屬膜而形成遮蔽電磁波的電磁波屏蔽膜;及保護膜除去工程,將該半導體封裝之形成有該外部連接電極的第2面上被覆之保護膜予以除去。
- 如申請專利範圍第1項之半導體封裝的製造方法,其中在該一部分保護膜除去工程中,係藉由照射雷射束而將保護膜除去比起該切削刃之厚度更寬之寬度。
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- 2016-02-17 JP JP2016028287A patent/JP6679162B2/ja active Active
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2017
- 2017-01-12 TW TW106101033A patent/TWI731025B/zh active
- 2017-01-31 SG SG10201700762PA patent/SG10201700762PA/en unknown
- 2017-02-09 KR KR1020170018241A patent/KR102536434B1/ko active IP Right Grant
- 2017-02-13 US US15/431,171 patent/US10269724B2/en active Active
Patent Citations (5)
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TW201130028A (en) * | 2010-01-27 | 2011-09-01 | Disco Corp | Wafer processing method |
JP2014183181A (ja) * | 2013-03-19 | 2014-09-29 | Tdk Corp | 電子部品モジュール及びその製造方法 |
CN104347533A (zh) * | 2013-08-01 | 2015-02-11 | 日月光半导体制造股份有限公司 | 半导体封装件及其制造方法 |
US20160035680A1 (en) * | 2014-08-01 | 2016-02-04 | Cyntec Co., Ltd. | Semiconductor package with conformal em shielding structure and manufacturing method of same |
TW201637151A (zh) * | 2014-12-22 | 2016-10-16 | 德國艾托特克公司 | 用於主動組件之電磁屏蔽與熱管理之新穎方法 |
Also Published As
Publication number | Publication date |
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TW201740512A (zh) | 2017-11-16 |
KR20170096945A (ko) | 2017-08-25 |
KR102536434B1 (ko) | 2023-05-24 |
SG10201700762PA (en) | 2017-09-28 |
US10269724B2 (en) | 2019-04-23 |
US20170236786A1 (en) | 2017-08-17 |
JP2017147341A (ja) | 2017-08-24 |
JP6679162B2 (ja) | 2020-04-15 |
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