TWI725381B - 用於封裝件之整合緩衝設計 - Google Patents

用於封裝件之整合緩衝設計 Download PDF

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TWI725381B
TWI725381B TW108105390A TW108105390A TWI725381B TW I725381 B TWI725381 B TW I725381B TW 108105390 A TW108105390 A TW 108105390A TW 108105390 A TW108105390 A TW 108105390A TW I725381 B TWI725381 B TW I725381B
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die
device die
layer
dielectric
package
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TW108105390A
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TW202002104A (zh
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陳潔
余振華
陳憲偉
陳明發
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台灣積體電路製造股份有限公司
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Abstract

形成封裝件的方法包括將裝置晶粒接合到中介晶圓，該中介晶圓包括金屬線和通孔，形成介電區以包圍裝置晶粒，並形成穿孔以穿透介電區。穿孔通過中介晶圓中的金屬線和通孔電連接到第一裝置晶粒。該方法還包括在介電區上形成聚合物層，並形成電性連接件。電性連接件通過聚合物層中的導電特徵電耦合到穿孔。中介晶圓被鋸切以將封裝件與其他封裝件分離。

Description

用於封裝件之整合緩衝設計
本發明的實施例是有關於一種半導體裝置及其製造方法，且特別是有關於一種包含緩衝設置的半導體裝置及其製造方法。
隨著半導體技術的演進，半導體晶片/晶粒變得越來越小。同時，半導體晶粒上需要整合的越來越多的功能。因此，半導體晶粒需要在較小的面積上封裝越來越多數目的輸入/輸出(input/output，I/O)接墊，並且I/O接墊的密度隨著時間快速增加。因此，半導體晶粒的封裝變得越加困難，進而不利地影響封裝產量。
習知的封裝技術可分為兩類。在第一類中，晶圓上的晶粒在切割之前先被封裝。此封裝技術具有一些優點特徵，例如較大的生產量與較低成本。再者，需要較少的底膠填充或是模塑化合物。然而，此封裝技術亦有缺點。由於晶粒的尺寸越來越小，因而個別的封裝可僅為扇入型封裝(fan-intype package)，其中各晶粒的I/O接墊被直接侷限在個別晶粒之表面上方的區域。由於 晶粒面積有限，I/O接墊的數目因I/O接墊間隔的限制而受到侷限。如果接墊的間隔增加，則可能會產生焊橋(solder bridge)。此外，在固定的球尺寸需求之下，焊球必須具有某種尺寸，因而限制了在晶粒表面上可封裝的焊球數目。
在另一類封裝中，晶粒在封裝之前被切割。此封裝技術的優點特徵在於可形成扇出封裝(fan-out package)，其係指晶粒上的I/O接墊可分布至比晶粒更大的面積，因而可增加晶粒表面上封裝的I/O接墊數目。此封裝技術的另一優點特徵係封裝「已知的良好晶粒」(known-good-die)，並且丟棄有缺陷的晶粒，因而不會浪費成本與氣力在有缺陷的晶粒上。
本發明的實施例提供一種半導體裝置的製造方法，包括以下步驟。形成第一封裝件，包括下述步驟。接合第一裝置晶粒至中介晶圓，其中中介晶圓包括金屬線和通孔；形成介電區以包圍第一裝置晶粒；形成穿孔以穿透介電區，其中穿孔藉由中介晶圓中的金屬線和通孔電連接到第一裝置晶粒；在介電區上形成聚合物層；形成電性連接件，其中電性連接件藉由聚合物層中的導電特徵電耦合到穿孔；以及鋸切中介晶圓以將第一封裝件與其他的封裝件分離。
本發明的實施例提供一種半導體裝置的製造方法，包括以下步驟。形成第一封裝件以及接合第一封裝件至第二封裝件。 形成第一封裝件包括接合第一裝置晶粒和第二裝置晶粒至中介晶粒；包封第一裝置晶粒和第二裝置晶粒於無機間隙填充材料中；形成穿孔在中介晶粒的金屬接墊上，其中穿孔穿透無機間隙填充材料，並藉由中介晶粒電連接到第一裝置晶粒和第二裝置晶粒；形成介電層在第一裝置晶粒、第二裝置晶粒和穿孔上；形成金屬特徵在介電層中，其中金屬特徵是利用鑲嵌製程而形成；形成聚合物層在金屬特徵上，其中在聚合物層下面的所有介電材料是無機材料；以及形成電性連接件在聚合物層上。電性連接件接合至第二封裝件。
本發明的實施例提供一種半導體裝置，包括第一封裝件。第一封裝件包括不包含主動裝置的中介晶粒；接合至中介晶粒的第一裝置晶粒和第二裝置晶粒；將第一裝置晶粒和第二裝置晶粒包封在其中的無機介電區；穿透無機介電區的第一穿孔，其中第一穿孔藉由中介晶粒電連接第一裝置晶粒和第二裝置晶粒；在第一裝置晶粒、第二裝置晶粒和第一穿孔上的介電層；在介電層上的聚合物層，其中在聚合物層下面的所有介電材料是無機材料；以及在聚合物層上的電性連接件。
2:晶圓
4:中介晶粒/中介層/晶粒
20、44A、44B:基板
24、32、52A、52B、54、56、62、152:介電層
26、48A、48B:內連線結構
28:金屬線
30:通孔
32:IMD層
34:表面介電層
36、36A、36B、50A、50B:接合墊
42A、42B、136:裝置晶粒
44A-BS1、44B-BS1:虛線
46:間隙
54、56:間隙填充層/區
54:蝕刻停止層
54A:頂表面
56:介電區
58:隔離區
59、64、78、130:開口
60:穿孔
66:金屬特徵/金屬線
68:金屬接墊
70:鈍化層
72、76:聚合物層
74、154:重佈線(RDL)
80、156:凸塊下金屬(UBM)
82、158:電性連接件
84:複合晶圓
86:SoIC封裝件
88、160:封裝件
90:底部填充劑區
120:載體
122:離型膜/LTHC塗佈材料
124:聚合物緩衝層
126:金屬晶種層
128:光阻
132、142:金屬柱
138:晶粒貼合膜(DAF)
144:頂部介電層
148:包封材料
150:前側重佈線結構
154:重佈線
162:InFO封裝件
200:製程流程
202、204、206、208、210、212、214、216、218、220、222、230、232、234、236、238、240、242、244:製程
T1、T1A、T1B:厚度
WB:底寬度
WT:頂寬度
當使用附圖閱讀時，從以下詳細描述中可以最好地理解本揭露的方面。應注意，根據產業中的標準實施方式，各種特徵未按比例繪製。實際上，為了清楚起見，可以任意增加或減少各 種特徵的尺寸。
圖1至圖12是根據一些實施例說明形成系統級積體電路裝置(System on Integrate Chip，SoIC)封裝件的中間階段的剖視圖。
圖13至18是根據一些實施例說明形成積體扇出型(Integrated Fan-Out，InFO)封裝件的中間階段的剖視圖。
圖19繪示根據一些實施例的封裝件的剖視圖，該封裝件包括結合到InFO封裝件的SoIC封裝件。
圖20和21繪示根據一些實施例的封裝件的剖視圖，該封裝件包括與InFO封裝件結合的SoIC封裝件。
圖22繪示根據一些實施例用於形成積體封裝件的製程流程，該積體封裝件包括結合到InFO封裝件的SoIC封裝件。
以下揭示內容提供許多不同的實施例或範例，用於實施本申請案之不同特徵。元件與配置的特定範例之描述如下，以簡化本申請案之揭示內容。當然，這些僅為範例，並非用於限制本申請案。例如，以下描述在第二特徵上或上方形成第一特徵可包含形成直接接觸的第一與第二特徵之實施例，亦可包含在該第一與第二特徵之間形成其他特徵的實施例，因而該第一與第二特徵並非直接接觸。此外，本申請案可在不同範例中重複元件符號與/或字母。此重複係為了簡化與清楚之目的，而非支配不同實施例與/或所討論架構之間的關係。
再者，本申請案可使用空間對應語詞，例如「之下」、「低於」、「較低」、「高於」、「較高」等類似語詞之簡單說明，以描述圖式中一元件或特徵與另一元件或特徵的關係。空間對應語詞係用以包括除了圖式中描述的位向之外，裝置於使用或操作中之不同位向。裝置或可被定位(旋轉80度或是其他位向)，並且可相應解釋本申請案使用的空間對應描述。
根據各種實施例提供一種積體封裝件及其形成方法，該積體封裝件包括系統級積體電路裝置(System on Integrate Chip，SoIC)封裝件結合到積體扇出型(Integrated Fan-Out，InFO)封裝件。根據一些實施例說明形成形成封裝件的中間階段。討論了一些實施例的一些變化。在各種圖式和說明性實施例中，相同的元件符號用於表示相同的元件。
圖1至圖12是根據一些實施例說明形成SoIC封裝件的中間階段的剖視圖。圖1至圖12中所示的步驟也在圖17中所示的製程流程200中示意性地反映。
圖1繪示晶圓2形成中的剖視圖。根據本揭露的一些實施例，晶圓2是中介晶圓(interposer wafer)，其中沒有任何主動元件，例如電晶體和/或二極體。根據本揭露的一些實施例，中介晶圓2也沒有諸如電容器、電感器、電阻器或其類似物之類的被動元件。中介晶圓2可以在其中包括多個金屬線和通孔，其中繪示多個中介晶粒(interposer die)4中任一者的一些細節。中介晶粒4在下文中可替代地稱為中介層(interposer)或晶片(chip)。 中介層4用於佈線(routing)，這將在隨後的段落中討論。
晶圓2可以包括基板20和基板20頂表面上的特徵。按照本揭露的一些實施例，基板20是半導體基板。基板20可以由結晶矽、結晶鍺、結晶矽鍺和/或III-V化合物半導體形成，例如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或其類似物。半導體基板20也可以是塊狀矽基板或絕緣層上矽(Silicon-On-Insulator，SOI)基板。根據其中基板20是半導體基板的一些實施例，可以在基板20中形成淺溝渠隔離(Shallow Trench Isolation，STI)區(未示出)以隔離基板20中的一些區域。根據替代實施例，STI區未形成在晶圓2中，因為晶圓2不具有主動元件，因此不需要STI區來彼此隔離主動區。基板20也可以是介電基板，例如可以由氧化矽形成。根據一些實施例，穿孔(未示出)形成為延伸到半導體基板20中，其中穿孔用於在基板20的相對側壁上電氣互耦特徵。根據替代實施例，沒有形成延伸到半導體基板20中的穿孔。
介電層24可以形成在基板20上。根據本揭露的一些實施例，介電層24是層間介電層(Inter-Layer Dielectric，ILD)，其可由氧化矽、磷矽酸鹽玻璃(Phospho Silicate Glass，PSG)、硼矽酸鹽玻璃(Boro Silicate Glass，BSG)、硼摻雜的磷矽酸鹽玻璃(Boron-Doped Phospho Silicate Glass，BPSG)、氟摻雜的矽酸鹽玻璃(Fluorine-Doped Silicate Glass，FSG)、四乙基正矽酸酯(Tetra Ethyl Ortho Silicate，TEOS)或其類似物。介電層24可以用熱氧 化、旋轉塗佈、可流動化學氣相沉積(Flowable Chemical Vapor Deposition，FCVD)、原子層沉積(Atomic Layer Deposition，ALD)、化學氣相沉積(Chemical Vapor Deposition，CVD)、電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition，PECVD)、低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition，LPCVD)或其類似物。
在介電層24上方存在內連線結構26。內連線結構26包括金屬線28和通孔30，它們形成在介電層32中。介電層32或者稱為金屬間介電層(Inter-Metal Dielectric，IMD)，以下稱為IMD層。根據本揭露的一些實施例，介電層32由介電常數(k值)低於3.8的低介電常數介電材料形成。例如介電層32的k值可以低於約3.0或低於約2.5。介電層32可以由黑金剛石(應用材料的註冊商標)、含碳的低介電常數介電材料、氫化矽膠(Hydrogen SilsesQuioxane，HSQ)、甲基矽氧烷(MethylSilsesQuioxane，MSQ)或其類似物形成。根據本揭露的替代實施例，介電層32的一些或全部由非低介電常數介電材料形成，例如氧化矽、碳化矽(SiC)、矽碳氮化物(SiCN)、矽氧碳氮化物(SiOCN)或其類似物。根據本揭露的一些實施例，介電層32的形成包括沉積含致孔劑的介電材料，然後進行固化製程以驅除致孔劑，因此剩餘的介電層32為多孔的。形成蝕刻停止層(未示出)在IMD層32之間，蝕刻停止層可以由碳化矽、氮化矽或其類似物形成，為簡單起見未示出。
金屬線28和通孔30形成在介電層32中。在同一水平高 度的金屬線28在下文中統稱為金屬層。根據本揭露的一些實施例，內連線結構26包括通過穿孔30互連的多個金屬層。金屬線28和通孔30可以由銅或銅合金形成，它們也可以由其他金屬形成。形成製程可包括單鑲嵌和雙鑲嵌製程。在單鑲嵌製程中，先在多個介電層32中的任一者中形成溝渠，然後用導電材料填充溝渠。然後進行平坦化製程，例如化學機械研磨製程，以除去高於IMD層頂表面的導電材料的過量部分，並在溝渠中留下金屬線。在雙鑲嵌製程中，溝渠和通孔開口都形成在IMD層中，其中通孔開口位於溝渠下方並與溝渠空間性的連通。然後將導電材料填充到溝渠和通孔開口中以分別形成金屬線和通孔。導電材料可包括襯在溝渠和通孔上的擴散阻障層和在擴散阻障層上的含銅金屬材料。擴散阻障層可包括鈦、氮化鈦、鉭、氮化鉭或其類似物。
圖1繪示根據本揭露的一些實施例的表面介電層34。表面介電層34由諸如氧化矽的非低介電常數介電材料形成。表面介電層34可替代地稱為鈍化層，因為它具有將下面的低k介電層(若有的話)與有害的化學品和水份的不利影響隔離的功能。表面介電層34也可以具有包含多於一層的複合結構，其可以由氧化矽、氮化矽、未摻雜的矽酸玻璃(Undoped Silicate Glass，USG)或其類似物形成。中介層4還可以包括位於表面介電層34下面的金屬接墊，並且金屬接墊可以包括鋁或鋁銅接墊、保護層內連線(Post-Passivation Interconnect，PPI)或其類似物，為簡單起見其未示出。
在表面介電層34中形成接合墊36A和36B，它們也共同和單獨地稱為接合墊36。根據本揭露的一些實施例，接合墊36A和36B通過單鑲嵌製程形成，並且還可包括阻障層和形成在阻障層上的含銅材料。根據本揭露的替代實施例，接合墊36A和36B通過雙鑲嵌製程形成。一些接合墊36A可以通過金屬線28和通孔30電連接到其他接合墊36A和36B。根據本揭露的一些實施例，每個接合墊36A和接合墊36B通過金屬線28和通孔30電連接到至少一個(或多個)其他的接合墊36A和36B，並且沒有接合墊36A和36B與所有其他的接合墊36A和36B電斷開。
根據本揭露的一些實施例，晶圓2中沒有有機介電材料，例如聚合物、樹脂和模塑化合物。有機介電層通常具有高的熱膨脹係數(Coefficient of Thermal Expansion，CTE)，例如10ppm/。℃或更高。這顯著的大於矽基板(例如基板20)的CTE，其為約3ppm/℃。因此，有機介電層往往會引起晶圓2的翹曲(warpage)。在晶圓2中不包括有機材料有利地減少了晶圓2中的層之間的CTE不匹配，並且導致所得到的SoIC封裝件86的翹曲減少(圖12)。另外，在晶圓2中不包括有機材料，使得可以形成細微間距的金屬線(如圖12中的66)和高密度的接合墊，並改善佈線能力。頂部表面介電層34和接合墊36被平坦化，使得它們的頂表面為共平面，其可藉由在形成接合墊36的過程中的化學機械研磨製程而產生。
接下來，裝置晶粒42A和42B黏合到晶圓2，如圖2所 示。相應的製程在圖22所示的製程流程中被示為製程202。根據本揭露的一些實施例，裝置晶粒42A和42B是記憶體晶粒，如動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)晶粒或靜態隨機存取記憶體(Static Random Access Memory，SRAM)晶粒。裝置晶粒42A和42B中的每一個也可以是中央處理單元(Central Processing Unit，CPU)晶粒、微控制單元(Micro Control Unit，MCU)晶粒、輸入-輸出(input-output，IO)晶粒、基頻(BaseBand，BB)晶粒或應用處理器(Application processor，AP)晶粒。裝置晶粒42A和42B可以是選自上述類型的相同類型或不同類型的晶粒。此外，裝置晶粒42A和42B可以使用不同的技術形成，例如45奈米技術、28奈米技術、20奈米技術等。晶粒4、裝置晶粒42A和裝置晶粒42B功能組合起來作為封裝件，其可以是記憶體封裝件或邏輯封裝件。
裝置晶粒42A和42B分別包括基板44A和44B，其可以是半導體基板，例如矽基板。根據一些實施例，基板44A和44B也稱為半導體基板44A和44B。根據本揭露的一些實施例，裝置晶粒42A和42B中沒有矽穿孔(Through-Silicon Vias，TSV)。此外，裝置晶粒42A和42B分別包括內連線結構48A和48B，用於連接裝置晶粒42A和42B中的主動元件和被動元件。內連線結構48A和48B包括金屬線和通孔，其示意性地示出。基板44A和44B在其中沒有穿孔。因此，裝置晶粒42A和42B的所有外部電氣連接都是通過接合墊50A和50B製成的。
裝置晶粒42A包括在所示底表面處的接合墊50A和介電層52A。接合墊50A的底表面與介電層52A的底表面共平面。裝置晶粒42B包括在所示的底表面處的接合墊50B和介電層52B。接合墊50B的底表面與介電層52B的底表面共平面。根據本揭露的一些實施例，裝置晶粒42A和42B不含有有機介電材料，例如聚合物、樹脂、模塑化合物和其類似者。
裝置晶粒42A和42B與晶圓2的接合可以藉由混合接合(hybrid bonding)來實現。例如接合墊50A和50B與接合墊36A藉由金屬與金屬直接接合(metal-to-metal direct bonding)。根據本揭露的一些實施例，金屬與金屬直接接合是銅與銅直接接合。此外，介電層52A和52B接合到表面介電層34，例如產生熔融接合(可包括Si-O-Si接合)。
為了達成混合接合，藉由將裝置晶粒42A和42B輕輕壓在中介層4上，將裝置晶粒42A和42B首先預接合到表面介電層34和接合墊36A上。雖然繪示兩個裝置晶粒42A和42B，但是混合接合可以在晶圓級執行，並且與所示的晶粒群組(包括裝置晶粒42A和42B)相同的多個裝置晶粒群組被預先接合，並且佈置為行和列。
在所有裝置晶粒42A和42B預接合之後，進行退火(anneal)以引起金屬在接合墊36A和相應的上覆的接合墊50A和50B中的相互擴散。根據一些實施例，退火溫度可以在約200℃和約400℃之間的範圍內，並且可以在約300℃和約400℃之間 的範圍內。根據一些實施例，退火時間在約1.5小時和約3.0小時之間的範圍內，並且可以在約1.5小時和約2.5小時之間的範圍內。通過混合接合，接合墊50A和50B通過金屬相互擴散引起的直接金屬接合而接合到相應的接合墊36A。
表面介電層34也與介電層52A和52B結合，其間形成有鍵合。例如表面介電層34和介電層52A/52B之一中的原子(如氧原子)與表面介電層34和介電層52A/52B的另一個中的原子(如矽原子)形成化學或共價鍵。表面介電層34和介電層52A/52B之間產生的鍵是介電與介電接合。接合墊50A和50B的尺寸可以大於、等於或小於相應的接合墊36A的尺寸。間隙46留在相鄰的裝置晶粒42A和42B之間。
進一步參考圖2，可以執行背面研磨以使裝置晶粒42A和42B變薄到例如厚度在約15μm和約30μm之間。圖2示意性地繪示虛線44A-BS1和44B-BS1，它們分別是在背面研磨之前的裝置晶粒42A和42B的背表面。44A-BS2和44B-BS2分別是背面研磨之後的裝置晶粒42A和42B的背表面。通過裝置晶粒42A和42B的減薄，減小了相鄰的裝置晶粒42A和42B之間的間隙46的深寬比。否則，由於間隙46的深寬比高，間隙填充可能是困難的。根據其他間隙46的深寬比對於間隙填充來說不是太高的實施例，則跳過背面研磨。
圖3繪示間隙填充層/區54和56的形成。相應的製程在圖22所示的製程流程中被示為製程204。根據本揭露的一些實施 例，間隙填充層包括介電層54以及在蝕刻停止層54上方並與蝕刻停止層54接觸的介電層56。介電層54可以使用共形沉積方法沉積，例如原子層沉積(ALD)或化學氣相沉積(CVD)。根據一些實施例，介電層54也稱為蝕刻停止層或介電襯層。介電層56可以使用共形沉積方法或非共形沉積方法形成，例如高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition，HDPCVD)、可流動化學氣相沉積(CVD)、旋轉塗佈或其類似者。根據本揭露的一些實施例，間隙填充層不含有機材料，如聚合物、樹脂、模塑化合物和其類似者。
蝕刻停止層54由介電材料形成，該介電材料對裝置晶粒42A和42B的頂表面和側壁以及表面介電層34和接合墊36B的頂表面具有良好的黏附性。蝕刻停止層54也在裝置晶粒42A和42B的頂表面上延伸。根據本揭露的一些實施例，蝕刻停止層54由含氮化物的材料(如氮化矽)所形成。蝕刻停止層54的厚度T1(包括T1A和T1B)可以在約500埃和約1,000埃之間的範圍內。應理解，整個說明書中引用的值是示例，並且可以使用不同的值。蝕刻停止層54可以是共形層，例如水平部分的厚度T1A和垂直部分的厚度T1B實質上彼此相等，例如差值(T1A-T1B)的絕對值小於兩者的厚度T1A和T1B的約20%或小於兩者的厚度T1A和T1B的約10%。
介電層56由不同於蝕刻停止層54的材料的材料形成。介電層56可以由無機介電材料形成。根據本揭露的一些實施例， 介電層56包括氧化物，例如氧化矽，其可以由TEOS形成，而當介電層56和蝕刻停止層54之間存在足夠的蝕刻選擇性(例如高於約50)時，也可以使用其他介電材料，例如碳化矽、氧氮化矽、矽氧碳氮化物或其類似物。蝕刻選擇性是在後續製程中的蝕刻介電層56時，介電層56的蝕刻速率與蝕刻停止層54的蝕刻速率之比。介電層56完全填充間隙46(圖2)並且還包括一些部分與裝置晶粒42A和42B重疊的。介電層56可以由非共形的形成方法或共形的形成方法來形成。
進行平坦化製程，例如化學機械研磨製程或機械研磨製程，以除去介電層56的多餘部分。根據本揭露的一些實施例，當存在與裝置晶粒42A和42B重疊的介電層56的層時，停止平坦化製程。因此，蝕刻停止層54不被拋光。根據本揭露的替代實施例，使用蝕刻停止層54作為化學機械研磨停止層來進行平坦化製程。因此，當平坦化製程停止時，蝕刻停止層54的頂表面54A被暴露出來，並且存在與裝置晶粒42A和42B重疊的剩餘水平部分。根據本揭露的其他實施例，在裝置晶粒42A的基板44A和裝置晶粒42B的基板44B暴露之後，停止平坦化製程。蝕刻停止層54和介電層56的剩餘部分統稱為(間隙填充)隔離區58。隔離區58也稱為無機間隙填充(或間隙填充)區。
圖4繪示蝕刻介電層56以形成開口59。相應的製程在圖22所示的製程流程中被示為製程206。根據本揭露的一些實施例，形成並圖案化光阻(未示出)，並使用圖案化的光阻作為蝕刻罩幕 以蝕刻介電層56。由此形成開口59，並向下延伸至蝕刻停止層54。根據本揭露的一些實施例，介電層56包括氧化物，並且蝕刻可以通過乾式蝕刻來執行。蝕刻氣體可包括NF3和NH3的混合物或HF和NH3的混合物。使用蝕刻停止層54來停止用於形成開口59的蝕刻，允許同一晶圓2上的多個開口59的向下行進在相同的中間水平高度處同步，使得蝕刻較快的開口59在其再次向下延伸之前會等待蝕刻較慢的開口59。
接下來，對蝕刻停止層54進行蝕刻，使開口59向下延伸到接合墊36B。根據本揭露的一些實施例，蝕刻停止層54包括氮化矽，並且使用乾式蝕刻進行蝕刻。蝕刻氣體可包括CF4、O2和N2的混合物、NF3和O2的混合物、SF6或SF6和O2的混合物。
圖5繪示穿孔60的形成，其填充開口59(圖4)，並連接到接合墊36B。相應的製程在圖22所示的製程流程中被示為製程208。根據本揭露的一些實施例，穿孔60的形成包括執行電鍍製程，例如電化學電鍍製程或無電電鍍製程。穿孔60可包括金屬材料，例如鎢、鋁、銅或其類似物。導電阻障層(例如鈦、氮化鈦、鉭、氮化鉭或其類似物)也可以在金屬材料下面形成。進行平坦化製程，例如化學機械研磨製程，以除去多餘部分的鍍覆金屬材料，金屬材料的剩餘部分形成穿孔60。穿孔60可具有實質上豎直和垂直側壁。再者，穿孔60可以具有錐形輪廓，頂部寬度WT略大於相應的底部寬度WB。根據一些實施例，如圖5所示，形成單穿孔60以接觸每個接合墊36B。根據替代實施例，多個穿 孔60(例如兩個或三個)形成在同一個接合墊36B上並與之接觸。
參考圖6，形成介電層62，其可以是無機層。相應的製程在圖22所示的製程流程中被示為製程210。根據本揭露的一些實施例，介電層62由k值低於3.8的低介電常數介電材料形成，並且k值可例如低於約3.0且低於約2.5。根據替代實施例，介電層62由諸如氧化矽的氧化物、諸如氮化矽的氮化物或其類似物形成。然後，在微影製程中將介電層62圖案化以形成開口64，並暴露穿孔60。
然後，形成金屬特徵66，如圖7所示。在圖22中所示的製程流程中，相應的製程也被示為製程210。金屬特徵66可以包括金屬線和金屬接墊，並且可以使用鑲嵌製程形成，其包括將共形的導電阻障層沉積到開口64(圖6)，電鍍諸如銅或銅合金的金屬材料，並執行平坦化製程以去除金屬特徵66的多餘部分。金屬特徵66可以具有單鑲嵌結構，如圖7所示。根據本揭露的其他實施例，金屬特徵66具有雙鑲嵌結構。
根據本揭露的一些實施例，包含介電層62和所有下伏結構的組合結構不含有機材料(例如聚合物層、模塑化合物、樹脂或其類似物)，因此，用於形成金屬特徵66的製造方法可採用用於形成裝置晶粒的製程，並且使得具有小間距和線寬的細微間距金屬線66成為可能。
圖8繪示金屬接墊68的形成。相應的製程在圖22所示的製程流程中被示為製程212。根據一些實施例，金屬接墊68由 鋁銅形成。形成方式可包括沉積金屬層以及圖案化金屬層。經蝕刻的金屬層的剩餘部分是金屬接墊68。
圖9繪示鈍化層70和聚合物層72的形成。根據一些實施例，鈍化層70形成在介電層62上並與其接觸。鈍化層70可以是單層或複合層，並且可以由非多孔的材料形成。根據本揭露的一些實施例，鈍化層70是包含氧化矽層(未單獨示出)和氧化矽層上的氮化矽層(未單獨示出)的複合層。鈍化層70也可以由其他非多孔的介電材料形成，例如未摻雜的矽酸玻璃(USG)、氧氮化矽和/或其類似物。
接下來，對鈍化層70進行圖案化，使得金屬接墊68的一部分藉由鈍化層70中的開口暴露出來。然後，形成聚合物層72。各個製程在圖22所示的製程流程中被示為製程214。聚合物層72可以由聚酰亞胺(polyimide)、聚苯並噁唑(polybenzoxazole，PBO)或其類似物所形成。聚合物層72也被圖案化以形成開口，金屬接墊68通過該開口被暴露出來。根據一些實施例，聚合物層72具有很大的厚度，其可以在約3μm和約6μm之間的範圍內。
參照圖10，形成重佈線(Redistribution Line，RDL)74，並且重佈線74的通孔部分延伸到聚合物層72(圖9)中的開口，以電連接到金屬接墊68。相應的製程在圖22所示的製程流程中被示為製程216。可以理解，重佈線74可以包括金屬接墊和金屬線，並且可以用於佈線，使得重佈線74中的金屬接墊可以重新路由到與裝置晶粒42A和42B重疊的區域中。
圖11繪示聚合物層76的形成，其可以由聚酰亞胺、PBO或其類似物形成。相應的製程在圖22所示的製程流程中被示為製程218。開口78在聚合物層76中形成，以顯露出重佈線74。根據一些實施例，聚合物層76具有很大的厚度，其可以在約5μm和約10μm之間的範圍內。由於聚合物層72和76具有低的楊氏模數(Young’s modulus)，其遠低於由無機材料形成的下層中的楊氏模數，因此，聚合物層72和76可以吸收所得的封裝件中的應力。聚合物層72和76具有較大的厚度，它們吸收應力的能力得到改善。例如，聚合物層72和76下面的結構(包括晶圓2、裝置晶粒42A和42B以及介電區56)可以包括或不包括聚合物。當下層不包括聚合物時，封裝件可以受益於聚合物層72和76，因為聚合物層72和76具有吸收應力的能力。
參照圖12，形成凸塊下金屬(Under-bump metallurgy，UBM)80且UBM 80延伸到聚合物層76中，以連接到重佈線74。根據本揭露的一些實施例，每個UBM 80包括阻障層(未示出)和阻障層上方的晶種層(未示出)。阻障層可以是鈦層、氮化鈦層、鉭層、氮化鎵層或由鈦合金或鉭合金形成的層。晶種層的材料可包括銅或銅合金。其他金屬如銀、金、鋁、鈀、鎳、鎳合金、鎢合金、鉻、鉻合金及其組合也可包括在UBM 80中。根據一些實施例，UBM 80的形成包括沉積毯覆式阻障層和毯覆式晶種層、在晶種層上形成圖案化的蝕刻罩幕(例如圖案化的光阻)，然後蝕刻毯覆式晶種層和毯覆式阻障層。根據其他實施例，UBM 80的形成 包括沉積毯覆式阻障層和毯覆式晶種層，在毯覆式晶種層上形成圖案化電鍍罩幕(如圖案化的光阻)、在圖案化電鍍罩幕中的開口中電鍍金屬柱、去除圖案化的電鍍罩幕，然後，蝕刻預先由圖案化的電鍍罩幕覆蓋的毯覆式晶種層和毯覆式阻障層的部分。
再如圖12所示，電性連接件82形成在UBM 80上並與其接觸。在圖22所示的製程流程中，相應的製程被示為製程220。電性連接件82可包括金屬柱，焊料區或其類似物。在整個說明書中，圖13中所示的結構稱為複合晶圓84。在複合晶圓84上進行鋸切晶粒(單體化)步驟，以將複合晶圓84分離成多個SoIC封裝件86。相應的製程在圖22所示的製程流程中被示為製程222。
圖13至18根據一些實施例說明形成積體扇出型(InFO)封裝件的中間階段的剖視圖。參照圖13，提供載體120，並且在載體120上形成離型膜122。載體120由透明的材料形成，並且可以是玻璃載體、陶瓷載體、有機載體或其類似物。離型膜122可以由光熱轉換(Light-To-Heat-Conversion，LTHC)塗佈材料形成，光熱轉換塗佈材料可通過塗佈塗覆到載體120上。根據一些實施例，離型膜122也稱為LTHC塗佈材料。根據本揭露的一些實施例，LTHC塗佈材料能夠在光/輻射(例如雷射)的熱量下分解，因此可以從形成於其上的結構釋放載體120。
根據一些實施例，如圖1所示，在LTHC塗佈材料122上形成聚合物緩衝層124。根據一些實施例，聚合物緩衝層124由PBO、聚酰亞胺、苯並環丁烯(benzocyclobutene，BCB)或其 他適用的聚合物形成。
金屬晶種層126例如通過物理氣相沉積(PVD)形成。相應的製程在圖22所示的製程流程中被示為製程230。金屬晶種層126可以與聚合物緩衝層124物理接觸。根據本揭露的一些實施例，金屬晶種層126包括鈦層和在該鈦層上的銅層。根據本揭露的替代實施例，金屬晶種層126包括接觸LTHC塗佈材料122的銅層。
光阻128形成在金屬晶種層126上。在圖22中所示的製程流程中，相應的製程也被示為製程230。然後使用微影罩幕(未示出)在光阻128上執行曝光。在隨後的顯影之後，在光阻128中形成開口130。金屬晶種層126的一些部分藉由開口130暴露出來。接下來，藉由在開口130中鍍覆金屬材料來形成金屬柱(metal post)132。被鍍覆的金屬材料可以是銅或銅合金。相應的製程在圖22所示的製程流程中被示為製程232。
在隨後的步驟中，光阻128被移除，因此金屬晶種層126的下伏部分被暴露出來。然後在蝕刻步驟中去除金屬晶種層126的暴露部分，例如在非等向性或等向蝕刻步驟中。因此，剩餘的金屬晶種層126的邊緣與金屬柱132的相應的上覆部分共同終止。所得的金屬柱132如圖14所示。在整個說明書中，金屬晶種層126的剩餘部分被認為是金屬柱132的部分，並且可以不單獨示出。金屬柱132於俯視圖中的形狀包括但不限於圓形、矩形、六邊形、八邊形和類似者。
圖15繪示裝置晶粒136的放置/附接。在圖22所示的製程流程中，相應的製程被示為製程234。裝置晶粒136通過晶粒貼合膜(Die-Attach Film，DAF)138附著於聚合物緩衝層124，DAF 138是在裝置晶粒136放置在聚合物緩衝層124上之前預先附著在裝置晶粒136上的黏合膜。因此，在附接到聚合物緩衝層124之前，DAF 138和裝置晶粒136是一個整體的組合。裝置晶粒136可包括半導體基板，該半導體基板具有與DAF 138物理接觸的背表面(表面朝下)。裝置晶粒136可包括在半導體基板的前表面(表面朝上)處的積體電路裝置(例如主動裝置，其包括例如未示出的電晶體)。根據本揭露的一些實施例，裝置晶粒136是一個邏輯晶粒，它可以是一個中央處理單元(Central Processing Unit，CPU)晶粒、一個圖形處理單元(Graphic Processing Unit，GPU)晶粒、一個移動應用晶粒、微控制單元(Micro Control Unit，MCU)晶粒、輸入-輸出(input-output，IO)晶粒、基頻(BaseBand，BB)晶粒、應用處理器(Application processor，AP)晶粒或其類似物。由於載體120是晶圓級，儘管繪示一個裝置晶粒136，但也可將多個裝置晶粒136放置在聚合物緩衝層124上，並且可以被分配為包括多個行和多個列的陣列。
根據一些示例性實施例，金屬柱(metal pillar)142(例如銅柱)預先形成為裝置晶粒136的部分，並且金屬柱142電耦合到裝置晶粒136中的積體電路裝置(例如未示出的電晶體)。根據本揭露的一些實施例，諸如聚合物的介電材料填充相鄰的金屬 柱142之間的間隙以形成頂部介電層144。頂部介電層144還可包括覆蓋和保護金屬柱142的部分。頂部介電層144可以是聚合物層，其可以根據本揭露的一些實施例由PBO或聚酰亞胺形成。
接著，將裝置晶粒136和金屬柱132包封在包封材料148中，如圖16所示。相應的製程在圖22所示的製程流程中被示為製程236。包封材料148可包括模塑化合物、模塑底部填充劑、環氧樹脂和/或樹脂。當由模塑化合物形成時，包封材料148可包括基底材料，其可以是聚合物、樹脂、環氧樹脂或其類似物，以及在基底材料中的填料顆粒(未示出)。填料顆粒可以是SiO2、Al2O3、二氧化矽或其類似物的介電顆粒，並且可以具有球形形狀。再者，球形的填料顆粒可具有多種不同的直徑。模塑化合物中的填料顆粒和基底材料均可與聚合物緩衝層124物理接觸。
如所設置的，包封材料148的頂表面高於金屬柱142和金屬柱132的頂端。在隨後的步驟中，如圖16所示，執行平坦化製程，例如化學機械研磨製程或機械研磨製程，以減薄包封材料148和頂部介電層144，直到暴露出金屬柱132和金屬柱142。因為金屬柱132貫穿包封材料148，金屬柱132可選地稱為穿孔(through-vias)132。由於平坦化製程，穿孔132的頂端與金屬柱142的頂表面實質上齊平(共平面)，並且穿孔132的頂端與金屬柱142的頂表面和包封材料148的頂表面實質上共平面。
圖17繪示前側重佈線結構150的形成，其包括介電層152和在介電層152中的重佈線154。相應的製程在圖22所示的製程 流程中被示為製程238。根據本揭露的一些實施例，介電層152由聚合物如PBO、聚酰亞胺或其類似物所形成。根據本揭露的替代實施例，介電層152由無機介電材料形成，例如氮化矽、氧化矽或其類似物。
根據本揭露的一些實施例，介電層152和相應的重佈線154的形成可包括沉積介電層152，在相應的介電層152中形成通孔開口以暴露下面的導電特徵，沉積金屬晶種層(未示出)，在相應的金屬晶種層上形成光阻(未示出)，並在金屬晶種層上鍍金屬材料如銅和/或鋁。然後，去除圖案化的光阻，接著蝕刻先前由圖案化的光阻覆蓋的金屬晶種層的部分。
圖18繪示UBM 156的形成。頂部的介電層152被圖案化以形成開口，並且UBM 156形成為延伸到頂部的介電層152中的開口中以接觸在重佈線154中的金屬接墊。UBM 156可以由鎳、銅、鈦或其多層所形成。根據一些示例性實施例，UBM 156包括鈦層和在該鈦層上的銅層。
然後，形成電性連接件158。相應的製程在圖22所示的製程流程中被示為製程240。電性連接件158的形成可包括將焊球放置在UBM 156的暴露部分上，然後將焊球回焊到焊料區內。在整個說明書中，包括聚合物緩衝層124和上覆結構的結構一起被稱為封裝件160，其是包括多個裝置晶粒136的複合晶圓(以下也稱為複合晶圓160)。接下來，從載體120上卸下複合晶圓160，例如藉由將雷射光束投射到LTHC塗佈材料122上，從而分解 LTHC塗佈材料122，以從載體120釋放複合晶圓160。複合晶圓160包括多個InFO封裝件162在其中。
圖19繪示封裝件88的形成，其包括將SoIC封裝件86接合至InFO封裝件162。相應的製程在圖22所示的製程流程中被示為製程242。根據本揭露的一些實施例，多個SoIC封裝件86接合到複合晶圓160，SoIC封裝件86的電性連接件82穿透InFO封裝件162的聚合物緩衝層124，以接合到穿孔132。底部填充劑區90被分配到SoIC封裝件86和InFO封裝件162之間的間隙中。然後將所得的複合晶圓160單體化，得到多個封裝件88。相應的製程在圖22所示的製程流程中被示為製程244。
圖20和21繪示根據本揭露的一些實施例的封裝件88。根據這些實施例，除了圖19中的一些特徵被省略，封裝件88類似於圖19所示的封裝件88。根據本揭露的一些實施例，可以省略如圖19所示的金屬接墊68和鈍化層70，所得到的圖如圖20所示。根據本揭露的一些其他的實施例，省略了如圖19所示的金屬接墊68、鈍化層70、重佈線74和聚合物層72，所得到的圖如圖21所示。根據本揭露的一些實施例，當省略聚合物層72時，聚合物層76的厚度可以(或可以不)增加，例如增加至約8μm和約16μm，使得聚合物吸收應力的能力得以維持。
在上述實施例中，根據本揭露的一些實施例，討論了一些製程和特徵。其他特徵和製程也可包括在內。例如可以包括測試結構以幫助3D封裝或3DIC元件的驗證測試。測試結構可以包 括，例如在重佈線層或基板上形成的測試接墊，其允許測試3D封裝或3DIC，探針和/或探針卡的使用等。可以在中間結構以及最終結構上執行驗證測試。另外，本文公開的結構和方法可以與包含已知良好晶粒的中間驗證的測試方法結合使用，以增加良率並降低成本。
本揭露的實施例具有一些有利特徵。由於SoIC封裝件的部分(如圖8所示)不含聚合物、樹脂和模塑化合物，因此減少了SoIC封裝件的該部分中的CTE不匹配，並且減少了SoIC封裝件的該部分中內部的應力。因此，由於翹曲的減少，可以形成細微間距的重佈線。一些無機材料很硬並具有高楊氏模數。如果SoIC封裝件中沒有聚合物，SoIC封裝件將具有高硬度值。例如在SoIC封裝件中所使用的氮化矽具有大於100的楊氏模數。另一方面，聚合物如聚酰亞胺和PBO的楊氏模數等於約3.5或更低。因此，所添加的聚合物層可以吸收SoIC封裝件中的硬質無機材料所不能吸收的應力。實驗結果表明，如果SoIC封裝件不含聚合物，則在SoIC封裝件接合到複合晶圓(包括未鋸切的InFO封裝件)後，接合可能會斷裂，並且SoIC封裝件會從複合晶圓上脫落。通過形成聚合物層以吸收應力，SoIC封裝件和複合晶圓之間的接合不會受到應力的損害。
根據本揭露的一些實施例，半導體裝置的製造方法包括形成第一封裝，其包括接合第一裝置晶粒至中介晶圓，其中中介晶圓包括金屬線和通孔；形成間隙填充區以包圍第一裝置晶粒； 形成穿孔以穿透間隙填充區，其中穿孔藉由中介晶圓中的金屬線和通孔電連接到第一裝置晶粒；在間隙填充區上形成聚合物層；形成電性連接件，其中電性連接件通過聚合物層中的導電特徵電耦合到穿孔；以及鋸切中介晶圓以將第一封裝件與其他的封裝件分離。在一實施例中，形成間隙填充區包括在中介晶圓和第一裝置晶粒的表面上形成介電襯層；在介電襯層上填充介電材料；以及平坦化介電材料。在一實施例中，在平坦化之後，介電襯層包括與第一裝置晶粒重疊的部分。在一實施例中，在中介晶圓中沒有主動裝置。在一實施例中，在聚合物層下面的所有介電材料都是無機材料。在一實施例中，該方法還包括形成第二封裝，其包括形成金屬柱並將金屬柱和第二裝置晶粒包封在包封材料中；以及接合第二封裝件到第一封裝件。在一實施例中，該方法還包括接合第二裝置晶粒到中介晶圓，其中金屬線和通孔將第一裝置晶粒電連接到第二裝置晶粒，並且間隙填充區包括將第一裝置晶粒與第二裝置晶粒分離的部分。在一實施例中，間隙填充區由無機介電材料形成。在一實施例中，第一裝置晶粒藉由混合接合到中介晶圓。
根據本揭露的一些實施例，半導體裝置的製造方法包括形成第一封裝，其包括接合第一裝置晶粒和第二裝置晶粒至中介晶粒；包封第一裝置晶粒和第二裝置晶粒於無機間隙填充材料中；在中介晶粒的金屬接墊上形成穿孔，其中穿孔穿透無機間隙填充材料，並藉由中介晶粒電連接到第一裝置晶粒和第二裝置晶粒； 在第一裝置晶粒、第二裝置晶粒和穿孔上形成介電層；在介電層中形成金屬特徵，其中金屬特徵是利用鑲嵌製程而形成的；在金屬特徵上形成聚合物層，其中在聚合物層下面的所有介電材料都是無機材料；及在聚合物層上形成電性連接件；該方法還包括接合第一封裝件到第二封裝件，其中電性連接件接合至第二封裝件。在一實施例中，包封第一裝置晶粒和第二裝置晶粒包括沉積接觸第一裝置晶粒、第二裝置晶粒和中介晶粒的蝕刻停止層；在蝕刻停止層上形成介電材料；以及平坦化介電材料。在一實施例中，第一裝置晶粒和第二裝置晶粒藉由混合接合與中介晶粒接合。在一實施例中，中介晶粒不含主動裝置和被動裝置，所有電氣連接從第一裝置晶粒和第二裝置晶粒到第二封裝件都是藉由中介晶粒。在一實施例中，形成介電層包括形成第一低介電常數介電層。在一實施例中，聚合物層與第一低介電常數介電層物理接觸。在一實施例中，中介晶粒包括第二低介電常數介電層，並且第一低介電常數介電層和第二低介電常數介電層在無機間隙填充材料的相對側上。
根據本揭露的一些實施例，半導體裝置包括第一封裝，所述第一封裝包括沒有主動裝置於其中的中介晶粒；與中介晶粒結合的第一裝置晶粒和第二裝置晶粒；包封第一裝置晶粒和第二裝置晶粒的無機間隙填充區；穿透無機間隙填充區的第一穿孔，其中第一穿孔藉由中介晶粒電連接第一裝置晶粒和第二裝置晶粒；在第一裝置晶粒、第二裝置晶粒和第一穿孔上的介電層；在介電 層上的聚合物層，其中在聚合物層下面的所有介電材料都是無機材料；以及在聚合物層上的電性連接件。在一實施例中，半導體裝置還包括第二封裝件，該第二封裝件在第一封裝件上並且與第一封裝件結合，其中第二封裝件包括第三裝置晶粒；將第三裝置晶粒包封在其中的模塑化合物；以及穿透模塑化合物的第二穿孔，其中第二穿孔中的任一者接合至電性連接件。在一實施例中，第一裝置晶粒的第一介電層接合至中介晶粒的第二介電層，並且第一裝置晶粒的第一接合墊接合至中介晶粒的第二接合墊。在一實施例中，半導體裝置還包括在介電層中的金屬特徵，其中金屬特徵具有鑲嵌結構。在一實施例中，介電層是低介電常數介電層。在一實施例中，無機間隙填充區包括中介晶粒、第一裝置晶粒和第二裝置晶粒的氮化矽層襯裡表面；以及在氮化矽層上的氧化物層，其中氮化矽層和氧化物層均包含與第一裝置晶粒重疊的部分。在一實施例中，第一裝置晶粒和第二裝置晶粒藉由中介晶粒中的導線電互連。
前面概述了幾個實施例的特徵，使得本領域技術人員可以更好地理解本揭露的方面。本領域技術人員應該理解，他們可以容易地使用本揭露作為設計或修改用於載體的其他製程和結構的基礎，出於相同的目的和/或實現本文介紹的實施例的相同優點。本領域技術人員還應該認識到，這樣的等同構造不脫離本揭露的精神和範圍，並且在不脫離本揭露的精神和範圍的情況下，它們可以在本文中進行各種改變，替換和變更。
200‧‧‧製程流程
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Claims (10)

  1. 一種半導體裝置的製造方法，包括：形成第一封裝件，包括：接合第一裝置晶粒至中介晶圓，其中所述中介晶圓包括金屬線和通孔；形成介電區以包圍所述第一裝置晶粒，其中形成所述介電區包括：在所述中介晶圓的第一頂表面上形成介電襯層，其中所述介電襯層進一步在所述第一裝置晶粒的側壁表面和第二頂表面上延伸；在所述介電襯層上填充介電材料；以及平坦化所述介電材料；形成穿孔以穿透所述介電區，其中所述穿孔藉由所述中介晶圓中的所述金屬線和所述通孔電連接到所述第一裝置晶粒；在所述介電區上形成聚合物層；形成電性連接件，其中所述電性連接件藉由所述聚合物層中的導電特徵電耦合到所述穿孔；以及鋸切所述中介晶圓以將所述第一封裝件與其他的封裝件分離。
  2. 如申請專利範圍第1項所述的方法，其中使用共形沉積方法形成所述介電襯層。
  3. 如申請專利範圍第1項所述的方法，其中在所述聚合物層下面的所有介電材料是無機材料。
  4. 如申請專利範圍第1項所述的方法，還包括：形成第二封裝件，包括：形成金屬柱；以及包封所述金屬柱和第二裝置晶粒於包封材料中；以及接合所述第二封裝件到所述第一封裝件。
  5. 如申請專利範圍第1項所述的方法，還包括：接合第二裝置晶粒到所述中介晶圓，其中所述金屬線和所述通孔將所述第一裝置晶粒電連接到所述第二裝置晶粒，並且所述介電區包括將所述第一裝置晶粒與所述第二裝置晶粒分離的部分。
  6. 一種半導體裝置的製造方法，包括：形成第一封裝件，包括：接合第一裝置晶粒和第二裝置晶粒至中介晶粒；包封所述第一裝置晶粒和所述第二裝置晶粒於無機間隙填充材料中；形成穿孔在所述中介晶粒的金屬接墊上，其中所述穿孔穿透所述無機間隙填充材料，並藉由所述中介晶粒電連接到所述第一裝置晶粒和所述第二裝置晶粒；形成介電層在所述第一裝置晶粒、所述第二裝置晶粒和所述穿孔上； 形成金屬特徵在所述介電層中，其中所述金屬特徵是利用鑲嵌製程而形成；形成聚合物層在所述金屬特徵上，其中在所述聚合物層下面的所有介電材料是無機材料；以及形成電性連接件在所述聚合物層上；以及接合所述第一封裝件至第二封裝件，其中所述電性連接件接合至所述第二封裝件。
  7. 如申請專利範圍第6項所述的方法，其中包封所述第一裝置晶粒和所述第二裝置晶粒包括：沉積蝕刻停止層，所述蝕刻停止層接觸所述第一裝置晶粒、所述第二裝置晶粒及所述中介晶粒；形成介電材料在所述蝕刻停止層上；以及平坦化所述介電材料。
  8. 如申請專利範圍第6項所述的方法，其中形成所述介電層包括形成第一低介電常數介電層。
  9. 一種半導體裝置，包括：第一封裝件，包括：中介晶粒，不包含主動裝置；第一裝置晶粒和第二裝置晶粒，接合至所述中介晶粒；無機介電區，將所述第一裝置晶粒和所述第二裝置晶粒包封在其中； 第一穿孔，穿透所述無機介電區，其中所述第一穿孔藉由所述中介晶粒電連接所述第一裝置晶粒和所述第二裝置晶粒；介電層，在所述第一裝置晶粒、所述第二裝置晶粒和所述第一穿孔上；聚合物層，在所述介電層上，其中在所述聚合物層下面的所有介電材料是無機材料；以及電性連接件，在所述聚合物層上。
  10. 如申請專利範圍第9項所述的半導體裝置，還包括：第二封裝件，在所述第一封裝件上並接合至述第一封裝件，其中所述第二封裝件包括：第三裝置晶粒；模塑化合物，將所述第三裝置晶粒包封在其中；以及第二穿孔，穿透所述模塑化合物，其中所述第二穿孔中的任一者接合至所述電性連接件。
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