TW202105626A - 封裝結構及形成封裝結構的方法 - Google Patents

封裝結構及形成封裝結構的方法 Download PDF

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TW202105626A
TW202105626A TW109110777A TW109110777A TW202105626A TW 202105626 A TW202105626 A TW 202105626A TW 109110777 A TW109110777 A TW 109110777A TW 109110777 A TW109110777 A TW 109110777A TW 202105626 A TW202105626 A TW 202105626A
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rewiring
die
package
package component
bridge die
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TW109110777A
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TWI769440B (zh
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余振華
蘇安治
吳集錫
葉德強
林宗澍
葉名世
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台灣積體電路製造股份有限公司
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Abstract

一種結構包含橋接晶粒。橋接晶粒包含：半導體基底；及位於半導體基底上方的內連線結構。內連線結構包含介電層及介電層中的導線；將橋接晶粒包封於其中的包封體；以及位於橋接晶粒上方的重佈線結構。重佈線結構中包含重佈線。第一封裝組件及第二封裝組件接合至重佈線。第一封裝組件及第二封裝組件經由重佈線及橋接晶粒電性互連。

Description

具有用於內連線的橋接晶粒的封裝及形成封裝的方法
隨著積體電路的發展，愈來愈多的功能被內建於積體電路封裝中。因此，對相鄰元件晶粒與封裝之間的區域通信及內連線的要求亦變得要求更高。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。以下描述組件及佈置的具體實例以簡化本揭露。當然，這些組件及佈置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，在第二特徵上方或在第二特徵上形成第一特徵可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含在第一特徵與第二特徵之間可形成額外特徵，使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清楚的目的，且本身並不指示所論述的各種實施例及/或配置之間的關係。
另外，本文中為易於描述可使用諸如「在……之下」、「在……下方」、「下部」、「上覆」、「上部」以及類似者的空間相對術語來描述如圖式中所說明的一個元件或特徵與另一（些）元件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞同樣可相應地進行解釋。
根據一些實施例，提供一種包含用於區域互連的橋接晶粒的封裝及形成所述封裝的方法。根據一些實施例，示出形成封裝的中間階段。論述一些實施例的一些變型。本文中所論述的實施例將提供使得能夠製備或使用本揭露的主題的實例，且所屬技術領域中具有通常知識者將易於理解在屬於不同實施例的所設想範疇內的情況下可進行的修改。貫穿各視圖以及說明性實施例，相同的附圖標號用以指代相同元件。儘管方法實施例可論述為以特定次序執行，但其他方法實施例可以任何邏輯次序執行。根據本揭露的一些實施例，橋接晶粒經包封於包封體中，在所述橋接晶粒上方形成包含重佈線的重佈線結構。兩個封裝組件（諸如元件晶粒）接合至內連線結構，且經由橋接晶粒互連。
圖1至圖7示出根據本揭露的一些實施例的形成封裝的中間階段的橫截面圖。對應製程亦示意性地反映於圖25中所示的製程流程200中。
圖1示出載板20及形成於載板20上的離型膜22。載板20可為玻璃載板、有機載板或類似者。載板20可具有圓形俯視圖形狀，且可具有常見矽晶圓的尺寸。舉例而言，載板20可具有8吋直徑、12吋直徑或類似者。離型膜22可由聚合物類材料（諸如光-熱轉換（Light-To-Heat-Conversion；LTHC）材料）形成，能夠自將在後續步驟中形成的上覆結構移除所述離型膜22以及載板20。根據本揭露的一些實施例，離型膜22由環氧類熱釋放材料形成。離型膜22可塗佈於載板20上。
如圖1中所示，形成金屬支柱24。相應製程在圖25中所示的製程流程中示出為製程202。儘管將一個金屬支柱24示出為實例，但可形成多個金屬支柱24。根據本揭露的一些實施例，形成金屬支柱24包含沈積金屬晶種層（未示出），所述金屬晶種層可包含鈦層及在鈦層上方的銅層。鍍覆罩幕（未示出）（其可為光阻）經塗佈於金屬晶種層上，且接著使其圖案化，使得能夠經由鍍覆罩幕中的多個開口暴露金屬晶種層的一些部分。接著，金屬材料（諸如銅）經鍍覆至開口中且經鍍覆於金屬晶種層的暴露部分上。在鍍覆製程之後，移除鍍覆罩幕，從而暴露出金屬晶種層的下伏部分。接著蝕刻金屬晶種層的暴露部分，從而留下所得金屬支柱24，所述金屬支柱24包含經鍍覆金屬材料及金屬晶種層的未經蝕刻部分。
在形成金屬支柱24之後，將橋接晶粒26放置在載板上方。相應製程在圖25中所示的製程流程中示出為製程204。橋接晶粒26經由作為黏著膜的晶粒貼合膜30貼合至離型膜22。根據本揭露的一些實施例，橋接晶粒26包含半導體基底128、穿孔（亦稱為半導體穿孔或矽穿孔（through-silicon via；TSV））134以及穿孔134上方的內連線結構130。內連線結構130包含電性連接至穿孔134的金屬線以及通孔。金屬柱28位於橋接晶粒26的頂部表面處，且亦電性連接至金屬線、通孔以及穿孔134。
圖22示出根據一些實施例的橋接晶粒26的佈線方案的示意圖。橋接晶粒26具有將隨後接合的封裝組件（諸如圖2中所示出的封裝組件46A及封裝組件46B）互連的功能。根據本揭露的一些實施例，橋接晶粒26包含基底128，所述基底128可為半導體基底（諸如矽基底），或可為由例如氧化矽、氮化矽或類似物形成的介電基底。基底128亦可為由介電材料（諸如氧化矽、氮化矽或類似物）形成的介電基底。
根據本揭露的一些實施例，橋接晶粒26中不含主動元件，諸如電晶體及二極體。根據本揭露的替代性實施例，橋接晶粒26包含可形成於半導體基底128的頂部表面處的主動元件。橋接晶粒26中的相應電路可包含記憶體電路、邏輯電路及/或類似者。根據本揭露的一些實施例，橋接晶粒26包含經示意性地示出的被動元件137，諸如電容器、變壓器、電感器、電阻器及/或類似者。根據本揭露的其它實施例，橋接晶粒26不含被動元件。因此，使用虛線繪示被動元件137以指示被動元件137可或可不存在於橋接晶粒26中。橋接晶粒26中可不含主動元件及被動元件兩者。
橋接晶粒26更包含內連線結構130，所述內連線結構130更包含介電層131以及介電層131中的金屬線及通孔132。介電層131可包含金屬間介電（Inter-Metal Dielectric；IMD）層。根據本揭露的一些實施例，介電層131的一些下部介電層由具有低於約3.0的介電常數（k值）的低k介電材料形成。介電層131可由黑鑽石(Black Diamond)（應用材料公司(Applied Materials)的註冊商標）、含碳低k介電材料、三氧化矽烷（Hydrogen SilsesQuioxane；HSQ）、甲基矽倍半氧烷（MethylSilsesQuioxane；MSQ）或類似物形成。根據本揭露的一些實施例，形成介電層131包含沈積含致孔劑的介電材料，且接著執行固化製程以向外驅動致孔劑，因而剩餘介電層131為多孔的。可由碳化矽、氮化矽或類似物形成的蝕刻終止層（未示出）形成於IMD層131之間，且出於簡單起見並未進行繪示。
金屬線及通孔132形成於介電層131中。形成製程可包含單金屬鑲嵌(single damascene)製程及雙金屬鑲嵌(dual damascene)製程。在實例單金屬鑲嵌製程中，溝渠首先形成於介電層131中的一者中，隨後用導電材料填充所述溝渠。接著執行平坦化製程（諸如化學機械拋光（Chemical Mechanical Polish；CMP）製程）以移除高於對應介電層的頂部表面的導電材料的過量部分，從而在溝渠中留下金屬線。在雙金屬鑲嵌製程中，溝渠以及通孔開口兩者形成於IMD層中，其中通孔開口在溝渠之下且連接至溝渠。接著將導電材料填充至溝渠以及通孔開口中以分別形成金屬線及通孔。導電材料可包含擴散障壁層以及擴散障壁層上方的含銅金屬材料。擴散障壁層可包含鈦、氮化鈦、鉭、氮化鉭或類似物。金屬線及通孔132亦可包括形成於鈍化層中的一些部分。
橋接晶粒26可更包含在低k介電層131上方的鈍化層（亦表示為鈍化層131）。鈍化層具有使下伏低k介電層（若存在）與有害化學物質以及水分隔離的功能。鈍化層可由非低k介電材料（諸如氧化矽、氮化矽、未經摻雜的矽酸鹽玻璃（Undoped Silicate Glass；USG）或類似物）形成。在鈍化層中可存在金屬襯墊，諸如鋁襯墊（其可由例如鋁銅形成）。接合襯墊（或金屬柱）28形成於橋接晶粒26的表面處。金屬柱28可由銅、鋁、鎳、鈀或類似物、其多層或其合金形成。
根據本揭露的一些實施例，一些金屬柱28經由金屬線以及通孔132、金屬襯墊或類似者直接連接至其他金屬柱28。可存在多對金屬柱28，其中所述對中的金屬柱28中的每一者電性連接至所述對中的另一金屬柱28。在整個說明書的描述中，所述對金屬柱28中的一者經表示為金屬柱28A，而另一者經表示為金屬柱28B。當兩個金屬柱28互連時，可不存在連接在金屬柱28A與金屬柱28B之間的任何電阻器、電容器、電感器或類似者。因此，同一對中的金屬柱28A與金屬柱28B彼此電短路。另一方面，若需要，則亦可將被動元件137（諸如電容器、電阻器、電感器或類似者）***在一對中的金屬柱28A與金屬柱28B之間，且被動元件以及金屬柱28A及金屬柱28B可串聯連接。
圖23示出根據本揭露的一些實施例的橋接晶粒26的橫截面圖。可參看圖22找到橋接晶粒26的佈線方案。橫截面圖示出金屬線及通孔132。根據一些實施例，聚合物層29（其可由聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺（polyimide）或類似物形成）可形成於金屬柱28上方。根據替代性實施例，沒有含聚合物的介電層經形成為將金屬柱28嵌入(embed)於其中。
根據本揭露的一些實施例，如圖23中所示，TSV 134經形成為延伸至基底128中。TSV 134中的每一者可由隔離襯裡136環繞，所述隔離襯裡由諸如氧化矽、氮化矽或類似者的介電材料形成。隔離襯裡136使相應TSV 134與半導體基底128隔離。TSV 134及隔離襯裡136自半導體基底128的頂部表面延伸至半導體基底128的頂部表面與底部表面之間的中間層級。根據一些實施例，TSV 134的頂部表面與半導體基底128的頂部表面齊平。根據替代性實施例，TSV 134延伸至介電層131中的一者中，且自對應介電層131的頂部表面朝下延伸至半導體基底128中。
根據本揭露的替代性實施例，不管基底128是否由半導體或介電材料形成，都不存在經形成為穿透基底128的穿孔。對應橋接晶粒26繪示於圖8至圖18中的實施例中。
返回參看圖1，當放置橋接晶粒26時，亦可經由離型膜22上方的DAF膜(Die Attach Film；DAF)放置其他封裝組件，所述其他封裝組件包含但不限於封裝、元件晶粒、獨立被動元件（Independent Passive Devices；IPD）或類似者。舉例而言，封裝組件32可經放置於與橋接晶粒26相同的層級處，且經由DAF 34放置於離型膜22上方。根據其他實施例，不存在經放置於與橋接晶粒26相同的層級處的其他封裝組件，諸如元件晶粒、封裝、IPD或類似者。因此，使用虛線示出封裝組件32以指示可或可不放置所述封裝組件。封裝組件32（若放置）在其表面處包含金屬柱36。根據一些實施例，封裝組件32為或包括記憶體晶粒、邏輯晶粒、封裝、IPD或類似者。
作為實例，圖1示出聚合物層29形成於橋接晶粒26中，而無聚合物經形成為將金屬柱36嵌入於所述聚合物中。應瞭解，放置於離型膜22上方的封裝組件及橋接晶粒中的每一者可或可不包含用於嵌入對應金屬柱的聚合物。
橋接晶粒26及封裝組件32（若放置）包封於包封體38中，所述包封體38可由模製化合物、模製底填充料、環氧樹脂、樹脂或類似物形成或包括模製化合物、模製底填充料、環氧樹脂、樹脂或類似物。相應製程在圖25中所示的製程流程中示出為製程206。包封體38可包含基質材料以及基質材料中的填充劑顆粒，所述基質材料可為樹脂及/或聚合物。填充劑顆粒可由可為球形顆粒的介電材料（諸如二氧化矽或氧化鋁）形成。在包封之後，包封體38覆蓋橋接晶粒26及封裝組件32。接著執行平坦化製程以移除包封體38的過量部分，從而暴露出金屬柱28及金屬柱36。平坦化製程可為化學機械拋光（CMP）製程或機械研磨(mechanical grinding)製程。根據本揭露中金屬柱36不在聚合物層中的一些實施例，包封體38流入金屬柱36之間的空間中。
圖1進一步示出重佈線結構40的形成，所述重佈線結構40包含介電層44及重佈線（Redistribution Line；RDL）42。相應製程在圖25中所示的製程流程中示出為製程208。根據一些實施例，介電層44由聚合物（諸如PBO、聚醯亞胺或類似物）形成。形成方法包含塗佈呈可流動形式的介電層44，且接著使對應介電層固化。根據本揭露的替代性實施例，介電層44由諸如氮化矽、氧化矽、碳化矽、其多層、其組合或類似者的無機介電材料形成。形成方法可包含塗佈、化學氣相沈積（Chemical Vapor Deposition；CVD）、原子層沈積（Atomic Layer Deposition；ALD）、電漿增強型化學氣相沈積（Plasma-Enhanced Chemical Vapor Deposition；PECVD）或其他可適用的沈積法。
RDL 42包含延伸至相應介電層44中的通孔部分以及在相應介電層44上方的跡線部分（trace portions）。形成製程可包含：使相應介電層44圖案化以形成開口；形成毯覆式（blanket）金屬晶種層（未示出）；形成鍍覆罩幕（諸如光阻）且將所述鍍覆罩幕圖案化以顯露金屬晶種層的一些部分；將RDL 42鍍覆在鍍覆罩幕中的開口中；移除鍍覆罩幕；以及蝕刻先前由鍍覆罩幕覆蓋的金屬晶種層的所述部分。根據本揭露的一些實施例，金屬晶種層包含鈦層及鈦層上方的銅層。形成金屬晶種層可包含例如物理氣相沈積（PVD）。根據本揭露的一些實施例，經鍍覆材料包括銅、鋁、鋁銅或銅合金。鍍覆可包含電化學鍍覆或無電式鍍覆。貫穿描述，將介電層44及形成於其中的RDL 42組合地稱為重佈線結構40。可存在所形成的RDL 42的一個層、兩個層或更多個層。RDL 42電性連接至金屬柱28及金屬柱36以及穿孔24。根據一些實施例，接合襯墊或凸塊下金屬（Under-Bump Metallurgies；UBM）形成於重佈線結構40的表面處，且亦經表示為接合襯墊或凸塊下金屬42。
接著，參看圖2，封裝組件46（包含封裝組件46A及封裝組件46B，其共同地及單獨地稱為封裝組件46）例如經由焊料區48接合至重佈線結構40的接合襯墊。相應製程在圖25中所示的製程流程中示出為製程210。封裝組件46A及封裝組件46B中的每一者可為或包括邏輯元件晶粒、記憶體元件晶粒、記憶體堆疊（諸如高頻寬記憶體（High Bandwidth Memory；HBM）堆疊）、IPD或類似者。
根據一些實施例，封裝組件46A及封裝組件46B兩者電性連接至相同橋接晶粒26，且經由橋接晶粒26以及RDL 42中的電路徑互連。舉例而言，如圖22中所示，橋接晶粒26包含多對金屬柱28A及金屬柱28B，其中相同對中的金屬柱28A及金屬柱28B為經導向而電性連接。金屬柱28A可經由上覆RDL 42直接連接至封裝組件46A中的接合襯墊，且金屬柱28B可經由上覆RDL 42直接連接至封裝組件46B中的接合襯墊。因此，圖2及圖22組合地繪示橋接晶粒26將封裝組件46A及封裝組件46B電性互連。使用橋接晶粒26（並非僅使用RDL 42）將封裝組件46A及封裝組件46B互連的有利特徵在於可使用用於形成元件晶粒的相同技術（所述技術包含例如金屬鑲嵌製程）來形成橋接晶粒26中的金屬線及通孔。從而，由於RDL 42的節距及線寬明顯大於橋接晶粒26中的節距及線寬，因此藉由使用橋接晶粒26，交叉點的導線節距及導線長度可為極小的，且可用互連的總數目明顯比僅使用RDL 42來執行互連的情況多。根據一些實施例，封裝組件46A及封裝組件46B的連接路徑內的RDL 42用於自封裝組件46A及封裝組件46B至下伏金屬柱28的豎直連接，且這些RDL 42不具有水平佈線功能。因此，將封裝組件46A及封裝組件46B互連的全部電路徑穿過橋接晶粒。根據本揭露的一些實施例，將封裝組件46A及封裝組件46B互連的一些電路徑在不經過橋接晶粒26的情況下穿過RDL 42，而其他電路徑經過橋接晶粒26。此外，封裝組件46A中的一些接合襯墊及/或封裝組件46B中的一些接合襯墊可電性連接至穿孔134。
在接合之後，底填充料50施配於封裝組件46與重佈線結構40之間，且底填充料50接著被固化。包封體52（諸如模製化合物）接著經包封於封裝組件46A及封裝組件46B上。相應製程在圖25中所示的製程流程中示出為製程212。根據一些實施例，並非分別應用底填充料50與包封體52，而是應用模製底填充料且使其固化。在包封製程之後，執行平坦化製程，諸如化學機械拋光（CMP）製程。當仍存在覆蓋封裝組件46A及封裝組件46B的一層包封體52時，可終止平坦化製程。將一些包封體52留在封裝組件46A及封裝組件46B上方可使所得封裝足夠厚以用於後續製程，且可使封裝組件46A及封裝組件46B的背表面在圖3及圖4中所示的製程中受到保護。
接著執行載板切換（carrier switch），其中如圖2中所示的封裝經由圖3中所示的離型膜56貼合至載板54。相應製程在圖25中所示的製程流程中示出為製程214。接著例如藉由將輻射（諸如雷射光束）投影於離型膜22（圖2）上來將載板20自上覆結構剝離，使得離型膜22經分解，因此釋放載板20。圖3中繪示所得結構。
在後續製程中，執行薄化製程以移除DAF 30，在穿孔134之下的基底128的部分以及絕緣襯裡136（圖23），直至顯露穿孔134的端部為止。亦對包封體38及穿孔24（圖3）的對應部分進行研磨。介電層可（或可不）經形成為覆蓋暴露基底128，且在示出介電層135的情況下，橋接晶粒26及包封體38的相應部分的細節繪示於圖24中。圖4中亦繪示所得結構。
圖4亦示出形成重佈線結構58，所述重佈線結構58包含介電層60及RDL 62。相應製程在圖25中所示的製程流程中示出為製程216。介電層60及RDL 62的形成製程及候選材料類似於介電層44及RDL 42的形成製程及候選材料，因而在本文中不重複這些細節。電連接器64接著形成於RDL 62上方且電性連接至RDL 62。相應製程在圖25中所示的製程流程中亦示出為製程216。電連接器64可包含金屬柱及金屬柱上的預焊料區，或可包含接觸RDL 62的焊料區。貫穿描述，離型膜56上方的特徵統稱為經重構晶圓66。
接著例如藉由將輻射（諸如雷射光束）投影於離型膜56上來將載板54自經重構晶圓66剝離，使得離型膜56經分解，從而釋放載板54。相應製程在圖25中所示的製程流程中示出為製程218。圖5中繪示所得經重構晶圓66。在後續製程中，執行單體化製程（諸如鋸切製程）以將經重構晶圓66分離成多個封裝66'。相應製程在圖25中所示的製程流程中示出為製程220。
參看圖6，封裝66'例如經由焊料接合而接合至封裝基底68。相應製程在圖25中所示的製程流程中示出為製程222。根據本揭露的一些實施例，多個封裝66'接合至作為封裝基底帶（package substrate strip）的積體部件的多個封裝基底68。封裝基底68可為無芯基底（coreless substrate）或有芯基底（cored substrate）。焊料區70可形成於基底68的底部。焊料區70可電性連接至穿孔24及穿孔134，且可電性連接至封裝組件46。施配包封體82，且接著使其固化以將封裝66'包封在其中。包封體82可包括模製化合物、模製底填充料或類似物。接著執行單體化製程以使相應結構單體化且形成多個封裝72。相應製程在圖25中所示的製程流程中亦示出為製程224。
圖7示出根據一些實施例的封裝72，其中，DAF 34可具有最終封裝72中留下的一部分。根據一些實施例，在圖1中所示的結構中，封裝組件32比橋接晶粒26更薄，且DAF 34比DAF 30更厚。因此，在如對圖2中所示的結構執行的薄化製程之後，如圖7中所示，DAF 34具有留下的一些部分。圖7亦示出封裝組件46A為記憶體堆疊，所述記憶體堆疊中包含多個記憶體晶粒46A'。底填充料47可形成於多個記憶體晶粒46A'之間，且包封體49進一步將記憶體晶粒46A'包封於其中。
如圖6及圖7中所示，穿孔24穿透包封體38。在相同封裝中，穿孔134穿透橋接晶粒26的基底128。穿孔24及穿孔134兩者具有將RDL 42及RDL 62互連的功能。應瞭解，穿孔24可佔據封裝72中的相對較小的晶片區域，且使來自RDL 42的訊號遠離橋接晶粒26進行佈線意謂佈線路徑較長。因此，穿孔24用於縮短佈線路徑。
圖8至圖12示出根據本揭露的一些實施例的形成封裝的中間階段的橫截面圖。除了IPD接合至重佈線結構40以及橋接晶粒26中不具有穿孔之外，這些實施例類似於圖1至圖7中所示的實施例。除非另外規定，否則在這些實施例中的組件的材料及形成製程基本上與類似組件相同。所述組件在圖1至圖7中所示的前述實施例中藉由類似附圖標號表示。關於圖8至圖12（以及圖13至圖18）中所示的組件的形成製程及材料的細節可因此在對前述實施例的論述中找到。
參看圖8，重佈線結構58首先形成於在載板20上方的離型膜22上。重佈線結構58包含介電層60以及重佈線62。穿孔24形成於重佈線結構58上方。使用DAF 30將橋接晶粒26放置於離型膜22上方。除了未形成如圖23中所示的穿孔134之外，橋接晶粒26可具有與圖22及圖23中所示的橋接晶粒基本上相同的結構。接著，在平坦化製程中對包封體38進行平坦化，隨後形成重佈線結構40。在後續製程中，封裝組件46A及封裝組件46B例如經由焊料接合而接合至重佈線結構40。封裝組件46A及封裝組件46B亦經由RDL 42以及橋接晶粒26彼此互連。
IPD 74例如經由焊料接合而接合至重佈線結構40的表面。IPD 74可包含電容器、電感器、電阻器或類似者。根據本揭露的一些實施例，IPD 74中的一些或全部可為離散IPD晶粒，所述離散IPD晶粒中可不含主動元件。一些IPD晶粒74中可僅包含單個被動元件。將IPD 74接合至重佈線結構40與習知接合方案中的情況不同，在所述習知接合方案中，IPD接合至封裝基底，例如如圖12中所示的封裝基底68。將IPD晶粒74接合至重佈線結構40使得能夠有效地使用晶片區域，且可減小封裝基底的尺寸，從而使所得封裝的覆蓋面積減小。
參看圖9，施配底填充料50，且封裝組件46及IPD 74包封於包封體52中。接著對包封體52進行平坦化，直至暴露出封裝組件46的頂部表面為止。因此形成經重構晶圓66。接著，執行剝離製程，且將經重構晶圓66自載板20剝離。
圖10示出將經重構晶圓66放置於固定在框架78上的載帶76上。重佈線結構58中的介電層60目前為頂部表面層，接著例如在雷射打孔製程或蝕刻製程中使所述頂部表面層圖案化以顯露RDL 62中的一些接合襯墊。在圖11中，封裝基底68例如經由焊料區接合至經重構晶圓66。儘管示出一個封裝基底68，但存在接合至經重構晶圓66的多個相同封裝基底68。此製程與習知製程不同，其中首先將封裝單體化為離散封裝，且離散封裝接合至包含多個封裝基底的積體封裝基底帶。
圖12示出在封裝基底68上形成電連接器70。接著執行單體化製程以將經重構晶圓66鋸切為多個離散封裝72。亦將經重構晶圓66單體化為封裝66'。離散封裝72中的每一者包含封裝組件46A及封裝組件46B、橋接晶粒26以及封裝基底68。
如圖12中所示，IPD 74並非接合至封裝基底68，而是接合至重佈線結構40。此使得有可能將封裝基底單體化，且接著將單體化的封裝基底接合至（晶圓級）經重構晶圓66。因此，封裝基底68的尺寸可減小為與封裝66'的尺寸相同或小於封裝66'的尺寸。此外，IPD 74接合至重佈線結構40，而非在封裝基底68上，從而進一步使得有可能減小封裝基底68的尺寸。舉例而言，封裝基底68的長度L1（或寬度）可等於或小於封裝66'的長度L2（或寬度）。此與其中封裝基底大於接合至所述封裝基底的封裝的習知封裝不同，此是由於所述封裝為離散封裝且接合至包含多個封裝基底的積體封裝基底帶。
圖13至圖18示出根據替代性實施例的封裝72的形成。除了沒有接合IPD 74之外，這些實施例類似於圖8至圖12中的實施例。此外，與如圖8至圖12中所示的實施例不同，在圖13至圖18中的實施例中，首先形成離散封裝66'，且接著將所述離散封裝66'接合至封裝基底帶。所述製程簡要地論述如下。
參看圖13，重佈線結構58形成於載板20及離型膜22上方。重佈線結構58包含介電層60及延伸至介電層60中的RDL 62。形成製程以及材料可選自分別用於形成如圖1中所示的介電層44以及RDL 42的候選形成製程以及材料。接著，穿孔24形成於重佈線結構58上方，且電性連接至RDL 62。橋接晶粒26經由DAF 30放置於重佈線結構58上方。穿孔24及橋接晶粒26接著包封於包封體38中。接著形成重佈線結構40。重佈線結構40中的RDL 42電性連接至橋接晶粒26及穿孔24。
參看圖14，封裝組件46A及封裝組件46B例如經由焊料接合而接合至重佈線結構40。封裝組件46A及封裝組件46B亦經由RDL 42及橋接晶粒26彼此互連。施配底填充料50，且封裝組件46及封裝組件46B包封於包封體52中。接著對包封體52進行平坦化。根據一些實施例，在平坦化之後，封裝組件46仍然由一些包封體52覆蓋。根據替代性實施例，暴露出封裝組件46A及封裝組件46B中的至少一個（且可能兩者）的背表面。因此形成經重構晶圓66。接著，執行剝離製程，且將經重構晶圓66自載板20剝離。
圖15示出載板切換製程，其中如圖14中所示的載板20經剝離，且經重構晶圓66經由離型膜56貼合至載板54。在如圖16中所示的後續製程中，形成電連接器64。接著將經重構晶圓66自載板54剝離，且圖17中繪示所得經重構晶圓66。接著執行單體化以將經重構晶圓66單體化為封裝66'。
參看圖18，封裝66'例如經由焊料接合而接合至封裝基底68。根據本揭露的一些實施例，多個封裝66'接合至封裝基底帶中的多個封裝基底68。應用包封體82以將多個封裝66'包封於其中。包封體82可包括模製化合物、模製底填充料或類似物。接著將封裝基底帶及包封體82單體化以形成多個封裝72。
圖19示出根據一些實施例的封裝72。除橋接晶粒26及穿孔24以外，存在所示出的額外晶粒。舉例而言，IPD晶粒74'、記憶體晶粒46C（其可為靜態隨機存取記憶體（Static Random Access Memory；SRAM）晶粒、動態隨機存取記憶體（Dynamic Random Access Memory；DRAM）晶粒等）以及輸入/輸出（Input/Output；I/O）晶粒46D亦包封於包封體38中，且電性連接至重佈線結構40。根據一些實施例，封裝組件46A為包含堆疊在一起的多個記憶體晶粒46'的記憶體堆疊。根據本揭露的一些實施例，I/O晶粒46D中包含TSV 134'，所述TSV 134'將重佈線結構40與重佈線結構58電性互連。穿孔24'形成於重佈線結構40上方，且穿透包封體58。封裝86（在其中可包含記憶體晶粒、記憶體堆疊或類似者）例如經由焊料區88接合至穿孔24。
應瞭解，如圖19中所示的IPD晶粒74'、記憶體晶粒46C以及I/O晶粒46D亦可包含於如圖6、圖7、圖12以及圖18中所示的封裝72中。此外，儘管顯示橋接晶粒26位於重佈線結構40下方，且互連封裝組件46A及互連封裝組件46B接合至重佈線結構40，但可採用其他方案。舉例而言，橋接晶粒26可位於重佈線結構40上方且接合至重佈線結構40，而封裝組件46A及封裝組件46B可包封於包封體38中，其中重佈線結構40形成於所述包封體38上。
圖20示出根據一些實施例的封裝72的平面圖。封裝組件46A可具有彼此相同或彼此不同的結構及電路。封裝組件46B可具有彼此相同或彼此不同的結構及電路。多個橋接晶粒26將封裝組件46A接合至對應封裝組件46B。橋接晶粒26中的每一者將至少一對封裝組件46A及封裝組件46B互連。根據一些實施例，如圖20中所示，一個橋接晶粒26可將兩個封裝組件46A連接至相同封裝組件46B。兩個封裝組件46A亦可經由橋接晶粒26彼此互連。此外，橋接晶粒26可將兩個封裝組件46B互連。圖21示出根據一些實施例的封裝72的平面圖。除了橋接晶粒26中的每一者連接至一對封裝組件46之外，這些實施例類似於如圖20中所示的實施例。
在上文所示的實施例中，根據本揭露的一些實施例論述一些製程及特徵以形成三維（three-dimensional；3D）封裝。亦可包含其他特徵及製程。舉例而言，可包含測試結構以輔助對3D封裝或3DIC元件的驗證測試。測試結構可包含例如形成於重佈線層中或形成於基底上的測試襯墊，其允許測試3D封裝或3DIC、使用探針及/或探針卡以及類似者。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合併入有對良裸晶粒的中間驗證的測試方法而使用，以提高良率且降低成本。
本揭露的實施例具有一些有利特徵。藉由使用橋接晶粒將封裝組件互連，相比於僅使用RDL進行互連，可在兩個封裝組件之間建立的可用數目的電性連接顯著增加。此是歸因於橋接晶粒中的連接的較小節距及線寬。形成於橋接晶粒上方的內連線結構亦提供平坦表面以均等橋接晶粒以及其他元件晶粒的不同厚度，使得可在無難度的情況下佈置封裝組件。
根據本揭露的一些實施例，一種結構包括：橋接晶粒，所述橋接晶粒包括：半導體基底；及內連線結構，位於所述半導體基底上方，其中所述內連線結構包括介電層及介電層中的導線；包封體，將所述橋接晶粒包封於其中；重佈線結構，位於所述橋接晶粒上方，其中所述重佈線結構中包括重佈線；以及第一封裝組件及第二封裝組件，接合至所述重佈線，其中所述第一封裝組件及所述第二封裝組件經由所述重佈線以及所述橋接晶粒電性互連。在實施例中，所述橋接晶粒中不含主動元件。在實施例中，所述橋接晶粒更包括穿透所述半導體基底的第一穿孔。在實施例中，結構更包括穿透所述包封體的第二穿孔。在實施例中，結構更包括接合至所述重佈線結構的被動元件晶粒。在實施例中，所述橋接晶粒包括由所述第一封裝組件交疊的第一部分，及由所述第二封裝組件交疊的第二部分。在實施例中，將所述第一封裝組件與所述第二封裝組件互連的全部電路徑皆穿過所述橋接晶粒。在實施例中，結構更包括：封裝基底，位於所述橋接晶粒的與所述第一封裝組件相對的一側上，其中所述封裝基底電性耦接至所述第一封裝組件，且其中所述封裝基底的側壁自所述包封體的相應側壁橫向凹入。
根據本揭露的一些實施例，一種結構包括：第一重佈線結構，所述第一重佈線結構中包括第一重佈線；橋接晶粒，位於所述第一重佈線結構上方，其中所述橋接晶粒包括：半導體基底；及第一穿孔，穿透所述半導體基底；第二穿孔，位於所述第一重佈線結構上方；包封體，將所述橋接晶粒及所述第二穿孔包封於其中；第二重佈線結構，位於所述橋接晶粒上方，且所述第二重佈線結構中包括第二重佈線，其中所述第一重佈線及所述第二重佈線經由所述第一穿孔及所述第二穿孔互連；以及第一封裝組件及第二封裝組件，位於所述第二重佈線結構上方且接合至所述第二重佈線結構，其中所述第一封裝組件及所述第二封裝組件經由所述橋接晶粒電性互連。在實施例中，所述橋接晶粒中不含主動元件及被動元件。在實施例中，結構更包括：元件晶粒；及黏著膜，位於所述元件晶粒與所述第一重佈線結構之間且接觸所述元件晶粒及所述第一重佈線結構。
根據本揭露的一些實施例，一種方法包括：將橋接晶粒包封於包封體中，所述橋接晶粒包括：半導體基底；及內連線結構，位於所述半導體基底上方，其中所述內連線結構包括介電層及所述介電層中的金屬線；在所述橋接晶粒上方形成第一重佈線結構，其中所述第一重佈線結構包括第一重佈線；以及將第一封裝組件及第二封裝組件接合至所述第一重佈線，其中所述第一封裝組件及所述第二封裝組件經由所述第一重佈線及所述橋接晶粒電性互連。在實施例中，所述方法更包括：形成金屬支柱，其中所述金屬支柱由所述包封體包封；以及在所述半導體基底的背側上形成第二重佈線，其中所述第一重佈線及所述第二重佈線經由所述金屬支柱互連。在實施例中，所述橋接晶粒更包括延伸至所述半導體基底中的穿孔，且所述方法更包括：執行背側研磨以顯露所述穿孔，其中所述第一重佈線及所述第二重佈線進一步經由所述穿孔互連。在實施例中，所述方法更包括：對所述包封體及所述第一重佈線結構執行單體化製程以形成多個封裝件；將所述多個封裝件接合至封裝基底帶（package substrate strip）；以及將所述封裝基底帶單體化。在實施例中，所述方法更包括：形成第二重佈線結構，其中所述第一重佈線結構及所述第二重佈線結構位於所述橋接晶粒的相對側上；將多個離散封裝基底接合在所述第二重佈線結構上；以及對所述包封體、所述第一重佈線結構以及所述第二重佈線結構執行單體化製程以形成多個離散封裝。在實施例中，所述方法更包括：將所述橋接晶粒放置於離型膜上方，其中所述離型膜位於載板上方；在形成所述第一重佈線之後，移除所述離型膜及所述載板；以及執行背側研磨製程以顯露所述橋接晶粒中的穿孔。在實施例中，所述方法更包括放置元件晶粒，其中經由黏著膜將所述元件晶粒放置於所述離型膜上，且所述元件晶粒及所述黏著膜包封於所述包封體中，且其中在所述背側研磨製程之後，所述黏著膜的一部分保留在所述包封體中。在實施例中，所述方法更包括將被動元件接合在所述第一重佈線結構上。在實施例中，所述橋接晶粒中不含主動元件。
前文概述若干實施例的特徵，使得所屬技術領域中具有通常知識者可更佳地理解本揭露的態樣。所屬技術領域中具有通常知識者應瞭解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬技術領域中具有通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬技術領域中具有通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中進行各種改變、替代以及更改。
20、54:載板 22、56:離型膜 24:金屬支柱 24'、134、134':穿孔 26:橋接晶粒 28、28A、28B、36:金屬柱 29:聚合物層 30、34:晶粒貼合膜 32、46、46A、46B:封裝組件 38、49、52、82:包封體 40、58:重佈線結構 42、62:重佈線 44、60、131、135:介電層 46A'、46C:記憶體晶粒 46D:輸入/輸出晶粒 47、50:底填充料 48、70、88:焊料區 64:電連接器 66:經重構晶圓 66'、72、86:封裝 68:封裝基底 74:獨立被動元件 74':IPD晶粒 76:載帶 78:框架 128:半導體基底 130:內連線結構 132:通孔 136:隔離襯裡 137:被動元件 204、206、208、210、212、214、216、218、220、222、224:製程 L1、L2:長度
結合隨附圖式閱讀以下詳細描述會最佳地理解本揭露的各態樣。應注意，根據業界中的標準慣例，各種特徵並未按比例繪製。實際上，為了論述清楚起見，可任意地增大或減小各種特徵的尺寸。 圖1至圖7示出根據一些實施例的形成包含橋接晶粒的封裝的中間階段的橫截面圖。 圖8至圖12示出根據一些實施例的形成包含橋接晶粒的封裝的中間階段的橫截面圖。 圖13至圖18示出根據一些實施例的形成包含橋接晶粒的封裝的中間階段的橫截面圖。 圖19示出根據一些實施例的包含橋接晶粒的封裝的橫截面圖。 圖20及圖21示出根據一些實施例的包含橋接晶粒的封裝的平面圖。 圖22示意性地示出根據一些實施例的橋接晶粒的佈線方案。 圖23及圖24示出根據一些實施例的加工包含穿孔的橋接晶粒的中間階段的橫截面圖。 圖25示出根據一些實施例的用於形成封裝的製程流程。
24:金屬支柱
24'、134':穿孔
26:橋接晶粒
28:金屬柱
38、52:包封體
40、58:重佈線結構
46、46A、46B:封裝組件
46A'、46C:記憶體晶粒
46D:輸入/輸出晶粒
64:電連接器
74':IPD晶粒
86:封裝
88:焊料區

Claims (20)

  1. 一種結構，包括： 橋接晶粒，包括： 半導體基底；以及 內連線結構，位於所述半導體基底上方，其中所述內連線結構包括介電層以及所述介電層中的導線； 包封體，將所述橋接晶粒包封於其中； 重佈線結構，位於所述橋接晶粒上方，其中所述重佈線結構中包括重佈線；以及 第一封裝組件及第二封裝組件，接合至所述重佈線，其中所述第一封裝組件及所述第二封裝組件經由所述重佈線及所述橋接晶粒電性互連。
  2. 如請求項1所述的結構，其中所述橋接晶粒中不含主動元件。
  3. 如請求項1所述的結構，其中所述橋接晶粒更包括： 第一穿孔，穿透所述半導體基底。
  4. 如請求項3所述的結構，更包括：第二穿孔，穿透所述包封體。
  5. 如請求項1所述的結構，更包括：被動元件晶粒，接合至所述重佈線結構。
  6. 如請求項1所述的結構，其中所述橋接晶粒包括由所述第一封裝組件交疊的第一部分及由所述第二封裝組件交疊的第二部分。
  7. 如請求項1所述的結構，其中將所述第一封裝組件與所述第二封裝組件互連的全部電路徑皆穿過所述橋接晶粒。
  8. 如申請專利範圍第1項所述的結構，更包括：封裝基底，位於所述橋接晶粒的與所述第一封裝組件相對的一側上，其中所述封裝基底電性耦接至所述第一封裝組件，且其中所述封裝基底的側壁自所述包封體的相應側壁橫向凹入。
  9. 一種結構，包括： 第一重佈線結構，所述第一重佈線結構中包括第一重佈線； 橋接晶粒，位於所述第一重佈線結構上方，其中所述橋接晶粒包括： 半導體基底；以及 第一穿孔，穿透所述半導體基底； 第二穿孔，位於所述第一重佈線結構上方； 包封體，其中包封有所述橋接晶粒及所述第二穿孔； 第二重佈線結構，位於所述橋接晶粒上方，且所述第二重佈線結構中包括第二重佈線，其中所述第一重佈線及所述第二重佈線經由所述第一穿孔及所述第二穿孔互連；以及 第一封裝組件及第二封裝組件，位於所述第二重佈線結構上方且接合至所述第二重佈線結構，其中所述第一封裝組件及所述第二封裝組件經由所述橋接晶粒電性互連。
  10. 如請求項9所述的結構，其中所述橋接晶粒中不含主動元件及被動元件。
  11. 如請求項9所述的結構，更包括： 元件晶粒；以及 黏著膜，位於所述元件晶粒與所述第一重佈線結構之間且接觸所述元件晶粒及所述第一重佈線結構。
  12. 一種方法，包括： 將橋接晶粒包封於包封體中，所述橋接晶粒包括： 半導體基底；以及 內連線結構，位於所述半導體基底上方，其中所述內連線結構包括介電層及所述介電層中的金屬線； 在所述橋接晶粒上方形成第一重佈線結構，其中所述第一重佈線結構包括第一重佈線；以及 將第一封裝組件及第二封裝組件接合至所述第一重佈線，其中所述第一封裝組件及所述第二封裝組件經由所述第一重佈線及所述橋接晶粒電性互連。
  13. 如請求項12所述的方法，更包括： 形成金屬支柱，其中所述金屬支柱由所述包封體包封；以及 在所述半導體基底的背側上形成第二重佈線，其中所述第一重佈線及所述第二重佈線經由所述金屬支柱互連。
  14. 如請求項13所述的方法，其中所述橋接晶粒更包括延伸至所述半導體基底中的穿孔，且所述方法更包括： 執行背側研磨製程以顯露所述穿孔，其中所述第一重佈線及所述第二重佈線進一步經由所述穿孔互連。
  15. 如請求項12所述的方法，更包括： 對所述包封體及所述第一重佈線結構執行單體化製程以形成多個封裝； 將所述多個封裝接合至封裝基底帶（package substrate strip）；以及 將所述封裝基底帶單體化。
  16. 如請求項12所述的方法，更包括： 形成第二重佈線結構，其中所述第一重佈線結構及所述第二重佈線結構位於所述橋接晶粒的相對側上； 將多個離散封裝基底接合在所述第二重佈線結構上；以及 對所述包封體、所述第一重佈線結構以及所述第二重佈線結構執行單體化製程以形成多個離散封裝。
  17. 如請求項12所述的方法，更包括： 將所述橋接晶粒放置於離型膜上方，其中所述離型膜位於載板上方； 在形成所述第一重佈線之後，移除所述離型膜及所述載板；以及 執行背側研磨製程以顯露所述橋接晶粒中的穿孔。
  18. 如請求項17所述的方法，更包括放置元件晶粒，其中經由黏著膜將所述元件晶粒放置於所述離型膜上，且所述元件晶粒及所述黏著膜包封於所述包封體中，且其中在所述背側研磨製程之後，所述黏著膜的一部分保留在所述包封體中。
  19. 如請求項12所述的方法，更包括將被動元件接合在所述第一重佈線結構上。
  20. 如請求項12所述的方法，其中所述橋接晶粒中不含主動元件。
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