TWI720796B - Semiconductor package structure and manufacturing method thereof - Google Patents

Semiconductor package structure and manufacturing method thereof Download PDF

Info

Publication number
TWI720796B
TWI720796B TW109102236A TW109102236A TWI720796B TW I720796 B TWI720796 B TW I720796B TW 109102236 A TW109102236 A TW 109102236A TW 109102236 A TW109102236 A TW 109102236A TW I720796 B TWI720796 B TW I720796B
Authority
TW
Taiwan
Prior art keywords
heat dissipation
substrate
chip
semiconductor package
package structure
Prior art date
Application number
TW109102236A
Other languages
Chinese (zh)
Other versions
TW202129854A (en
Inventor
潘玉堂
Original Assignee
南茂科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南茂科技股份有限公司 filed Critical 南茂科技股份有限公司
Priority to TW109102236A priority Critical patent/TWI720796B/en
Priority to CN202010348023.7A priority patent/CN113224014A/en
Application granted granted Critical
Publication of TWI720796B publication Critical patent/TWI720796B/en
Publication of TW202129854A publication Critical patent/TW202129854A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor package structure includes a substrate, chip, an encapsulant, a heat dissipation component, and a plurality of conductive terminals. The substrate has a first surface and, a second surface opposite to the first surface. The chip is located on the first surface and is electrically connected to the substrate. The encapsulant encapsulates the chip. The heat dissipation component is located on the second surface and part of the heat dissipation component is embedded in the substrate. The orthographic projection of the chip onto the substrate overlaps the heat dissipation component. The conductive terminals are located on the second surface and are electrically connected to the substrate. The conductive terminals surround the heat dissipation component. A manufacturing method of a semiconductor package structure is also provided.

Description

半導體封裝結構及其製造方法Semiconductor packaging structure and manufacturing method thereof

本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種半導體封裝結構及其製造方法。The present invention relates to a packaging structure and a manufacturing method thereof, and particularly relates to a semiconductor packaging structure and a manufacturing method thereof.

為了確保電子產品的持續小型化與多功能性，具有多功能性的半導體封裝受到期待。此外，為了滿足對前述多功能半導體封裝的需求，需進一步增加輸入/輸出(Input/output, I/O)連接端點數量。然而，增加輸入/輸出連接端點數量的同時，會使半導體封裝中的晶片運作時產生的熱能不斷提高，如此一來，晶片可能會因為過熱而導致效能衰減甚至失效。因此，如何降低半導體封裝中的晶片因為過熱而導致效能衰減甚至失效的問題，已成為本領域研究人員的一大挑戰。In order to ensure the continued miniaturization and versatility of electronic products, semiconductor packages with versatility are expected. In addition, in order to meet the demand for the aforementioned multi-functional semiconductor packages, the number of input/output (I/O) connection terminals needs to be further increased. However, increasing the number of input/output connection terminals will increase the heat generated during the operation of the chip in the semiconductor package. As a result, the chip may be overheated and cause performance degradation or even failure. Therefore, how to reduce the performance degradation or even failure of the chip in the semiconductor package due to overheating has become a major challenge for researchers in the field.

本發明提供一種半導體封裝結構及其製造方法，其可以有效提升半導體封裝結構的散熱效率，進而降低半導體封裝結構中的晶片因為過熱而導致效能衰減甚至失效的問題。The present invention provides a semiconductor packaging structure and a manufacturing method thereof, which can effectively improve the heat dissipation efficiency of the semiconductor packaging structure, thereby reducing the problem of performance degradation or even failure of the chips in the semiconductor packaging structure due to overheating.

本發明提供一種半導體封裝結構，包括基板、晶片、封裝膠體、散熱元件以及多個導電端子。基板具有第一表面與相對於第一表面的第二表面。晶片位於第一表面上且與基板電性連接。封裝膠體包封晶片。散熱元件位於第二表面上且部分散熱元件嵌入基板中。晶片於基板的正投影重疊於散熱元件。多個導電端子位於第二表面上且與基板電性連接。多個導電端子圍繞散熱元件。The invention provides a semiconductor packaging structure, which includes a substrate, a chip, a packaging glue, a heat dissipation element and a plurality of conductive terminals. The substrate has a first surface and a second surface opposite to the first surface. The chip is located on the first surface and is electrically connected to the substrate. The encapsulant encapsulates the chip. The heat dissipation element is located on the second surface and part of the heat dissipation element is embedded in the substrate. The orthographic projection of the chip on the substrate overlaps the heat dissipation element. A plurality of conductive terminals are located on the second surface and are electrically connected with the substrate. A plurality of conductive terminals surround the heat dissipation element.

本發明提供一種半導體封裝結構的製造方法，包括提供基板，其中基板具有第一表面與相對於第一表面的第二表面。配置晶片於第一表面上且與基板電性連接。形成封裝膠體以包封晶片。形成散熱元件於第二表面上且部分散熱元件嵌入基板中。晶片於所述基板的正投影重疊於散熱元件。形成多個導電端子於第二表面上且與基板電性連接。多個導電端子圍繞散熱元件。The present invention provides a method for manufacturing a semiconductor package structure, including providing a substrate, wherein the substrate has a first surface and a second surface opposite to the first surface. The chip is arranged on the first surface and is electrically connected to the substrate. An encapsulant is formed to encapsulate the chip. A heat dissipation element is formed on the second surface and part of the heat dissipation element is embedded in the substrate. The orthographic projection of the chip on the substrate overlaps the heat dissipation element. A plurality of conductive terminals are formed on the second surface and electrically connected with the substrate. A plurality of conductive terminals surround the heat dissipation element.

基於上述，本發明嵌入基板中的散熱元件可以構成晶片有效地散熱路徑，以使晶片運作時產生的熱能可以經由散熱元件從基板的第一表面傳遞至第二表面逸散出去，因此可以有效提升半導體封裝結構的散熱效率，進而降低半導體封裝結構中的晶片因為過熱而導致效能衰減甚至失效的問題。Based on the above, the heat dissipation element embedded in the substrate of the present invention can form an effective heat dissipation path for the chip, so that the heat generated during the operation of the chip can be transferred from the first surface to the second surface of the substrate and escape through the heat dissipation element, so it can effectively improve The heat dissipation efficiency of the semiconductor package structure further reduces the problem of performance degradation or even failure of the chip in the semiconductor package structure due to overheating.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

本文所使用之方向用語（例如，上、下、右、左、前、後、頂部、底部）僅作為參看所繪圖式使用且不意欲暗示絕對定向。The directional terms used herein (for example, up, down, right, left, front, back, top, bottom) are only used as a reference drawing and are not intended to imply absolute orientation.

除非另有明確說明，否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。Unless expressly stated otherwise, any method described herein is in no way intended to be construed as requiring its steps to be performed in a specific order.

以下將參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。相同或相似之標號表示相同或相似之元件，以下段落將不再一一贅述。Hereinafter, the present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

圖1A至圖1I是依據本發明一實施例的半導體封裝結構的部分製造方法的部分剖面示意圖。請參考圖1A，首先，提供多層板10，其中多層板10可以是由核心層12以及形成於核心層12上的導電層所構成。舉例而言，導電層可以包括形成於核心層12的上表面12a的第一導電層14以及形成於核心層12的下表面12b的第二導電層16所構成。換句話說，如圖1A所示，多層板110可以是由第二導電層16、核心層12以及第一導電層14依序堆疊的三層結構，但本發明不限於此，多層板的層數與各層的排列方式都可以視實際需求而定。1A to 1I are partial cross-sectional schematic diagrams of a part of a manufacturing method of a semiconductor package structure according to an embodiment of the present invention. Please refer to FIG. 1A. First, a multilayer board 10 is provided. The multilayer board 10 may be composed of a core layer 12 and a conductive layer formed on the core layer 12. For example, the conductive layer may include a first conductive layer 14 formed on the upper surface 12 a of the core layer 12 and a second conductive layer 16 formed on the lower surface 12 b of the core layer 12. In other words, as shown in FIG. 1A, the multilayer board 110 may have a three-layer structure in which the second conductive layer 16, the core layer 12, and the first conductive layer 14 are sequentially stacked, but the present invention is not limited to this. The number and arrangement of each layer can be determined according to actual needs.

在一些實施例中，第一導電層14與第二導電層16的材料可以是導電金屬或合金。舉例而言，第一導電層14與第二導電層16的材料例如是銅、鋁或其合金，但本發明不限於此，第一導電層14與第二導電層16的材料可以是其他適宜的導電材料。In some embodiments, the materials of the first conductive layer 14 and the second conductive layer 16 may be conductive metals or alloys. For example, the materials of the first conductive layer 14 and the second conductive layer 16 are copper, aluminum or alloys thereof, but the present invention is not limited to this, and the materials of the first conductive layer 14 and the second conductive layer 16 may be other suitable materials. Of conductive materials.

請同時參考圖1A與圖1B，移除部分核心層12與部分導電層，以形成貫穿多層板10的開口OP1，其中移除部分導電層可以是移除部分第一導電層14與部分第二導電層16。換句話說，剩餘的核心層112、剩餘的第一導電層1141與剩餘的第二導電層1161可以分別具有位於開口OP1兩側的多個部分。1A and 1B at the same time, remove part of the core layer 12 and part of the conductive layer to form an opening OP1 penetrating through the multilayer board 10, where removing part of the conductive layer may be removing part of the first conductive layer 14 and part of the second Conductive layer 16. In other words, the remaining core layer 112, the remaining first conductive layer 1141, and the remaining second conductive layer 1161 may respectively have multiple portions located on both sides of the opening OP1.

請參考圖1C，填充導熱材料於開口OP1中，以形成散熱塊120，其中散熱塊120可以構成一散熱路徑。舉例而言，導熱材料可以是填滿開口OP1，因此散熱塊120的頂面120a可以與剩餘的第一導電層1141的外表面1141a實質上共面，而散熱塊120的底面120b可以與剩餘的第二導電層1161的外表面1161a實質上共面。在一些實施例中，導熱材料可以是導熱效率較好的金屬或其合金。舉例而言，導熱材料例如是銅。填充導熱材料的方法例如是電鍍。Please refer to FIG. 1C, the opening OP1 is filled with a thermally conductive material to form a heat dissipation block 120, where the heat dissipation block 120 can form a heat dissipation path. For example, the thermally conductive material may fill the opening OP1, so the top surface 120a of the heat dissipation block 120 may be substantially coplanar with the outer surface 1141a of the remaining first conductive layer 1141, and the bottom surface 120b of the heat dissipation block 120 may be the same as the remaining outer surface 1141a. The outer surface 1161a of the second conductive layer 1161 is substantially coplanar. In some embodiments, the thermally conductive material may be a metal or an alloy thereof with good thermal conductivity. For example, the thermally conductive material is copper. The method of filling the thermally conductive material is, for example, electroplating.

請同時參考圖1C與圖1D，對剩餘的導電層進行圖案化製程，以形成圖案化線路層，其中剩餘的核心層112與圖案化線路層構成基板130。舉例而言，對剩餘的第一導電層1141以及剩餘的第二導電層1161進行圖案化製程，以分別形成第一圖案化線路層114以及第二圖案化線路層116。在本實施例中，基板130具有第一表面130a與相對於第一表面130a的第二表面130b，其中第一表面130a可以是第一圖案化線路層114暴露出的表面，而第二表面130b可以是第二圖案化線路層116暴露出的表面，且散熱塊120嵌入基板130中。散熱塊120可以貫穿基板130而顯露於第一表面130a。圖案化製程例如是微影蝕刻製程。Please refer to FIGS. 1C and 1D at the same time to perform a patterning process on the remaining conductive layer to form a patterned circuit layer, wherein the remaining core layer 112 and the patterned circuit layer constitute the substrate 130. For example, a patterning process is performed on the remaining first conductive layer 1141 and the remaining second conductive layer 1161 to form the first patterned circuit layer 114 and the second patterned circuit layer 116, respectively. In this embodiment, the substrate 130 has a first surface 130a and a second surface 130b opposite to the first surface 130a. The first surface 130a may be the exposed surface of the first patterned circuit layer 114, and the second surface 130b It may be the exposed surface of the second patterned circuit layer 116, and the heat sink 120 is embedded in the substrate 130. The heat dissipation block 120 may penetrate the substrate 130 to be exposed on the first surface 130a. The patterning process is, for example, a photolithography process.

另一方面，圖案化線路層可以具有多個開口，以暴露出部分核心層112。舉例而言，第一圖案化線路層114可以具有多個開口OP2，第二圖案化線路層116可以具有多個開口OP3，以分別暴露出部分核心層112。On the other hand, the patterned circuit layer may have multiple openings to expose part of the core layer 112. For example, the first patterned circuit layer 114 may have a plurality of openings OP2, and the second patterned circuit layer 116 may have a plurality of openings OP3 to respectively expose a part of the core layer 112.

應說明的是，本發明的基板130不限制於前述以多層板10的製造方法所製成的基板130，只要基板130的第一表面130a與第二表面130b上具有適宜的導電線路且散熱塊120可以嵌入基板130中，皆屬於本發明的保護範圍。此外，本發明不限制前述開口的形成方法，前述開口可以以適宜的方法所形成。舉例而言，可以藉由蝕刻製程以形成前述開口。It should be noted that the substrate 130 of the present invention is not limited to the substrate 130 made by the manufacturing method of the multilayer board 10, as long as the first surface 130a and the second surface 130b of the substrate 130 have suitable conductive circuits and heat dissipation blocks. 120 can be embedded in the substrate 130, all of which belong to the protection scope of the present invention. In addition, the present invention does not limit the forming method of the aforementioned opening, and the aforementioned opening can be formed by a suitable method. For example, the aforementioned opening can be formed by an etching process.

請參考圖1E，為了避免基板130的第一表面130a與第二表面130b上的導電線路產生短路及氧化，可以於基板130上形成防銲層，以包覆圖案化線路層且部分防銲層可以位於開口。舉例而言，可以於基板130的第一表面130a上形成第一防銲層1421，以包覆第一圖案化線路層114且部分第一防銲層1421位於開口OP2中，可以於基板130的第二表面130b上形成第二防銲層1441，以包覆第二圖案化線路層116部分第二防銲層1441位於開口OP3中。防銲層的材料例如是綠漆，但本發明不限於此。防銲層可以藉由適宜的方法所形成。1E, in order to avoid short circuit and oxidation of the conductive lines on the first surface 130a and the second surface 130b of the substrate 130, a solder mask layer may be formed on the substrate 130 to cover the patterned circuit layer and part of the solder mask layer Can be located in the opening. For example, a first solder mask layer 1421 may be formed on the first surface 130a of the substrate 130 to cover the first patterned circuit layer 114 and a part of the first solder mask layer 1421 is located in the opening OP2, which may be on the substrate 130 A second solder mask 1441 is formed on the second surface 130b to cover a portion of the second patterned circuit layer 116. The second solder mask 1441 is located in the opening OP3. The material of the solder mask is, for example, green paint, but the present invention is not limited to this. The solder mask can be formed by a suitable method.

請同時參考圖1E與圖1F，對防銲層進行圖案化製程，以形成圖案化防銲層。舉例而言，對第一防銲層1421與第二防銲層1441進行圖案化製程，以分別形成第一圖案化防銲層142與第二圖案化防銲層144。圖案化防銲層可以根據實際設計需求而具有不同圖案。舉例而言，第一圖案化防銲層142可以具有至少一開口OP4，其中至少一開口OP4可以暴露出部分第一圖案化線路層114與散熱塊120的頂面120a，而第二圖案化防銲層144可以具有多個開口OP5，其中多個開口OP5暴露出部分第二圖案化線路層116與散熱塊120的底面120b。於本實施例中，更進一步地在後續暴露出的電性接點上進行表面處理(電鍍)。Please refer to FIG. 1E and FIG. 1F at the same time to perform a patterning process on the solder mask to form a patterned solder mask. For example, a patterning process is performed on the first solder resist layer 1421 and the second solder resist layer 1441 to form the first patterned solder resist layer 142 and the second patterned solder resist layer 144, respectively. The patterned solder mask can have different patterns according to actual design requirements. For example, the first patterned solder mask 142 may have at least one opening OP4, wherein at least one of the openings OP4 may expose a part of the first patterned circuit layer 114 and the top surface 120a of the heat sink 120, and the second patterned resist The solder layer 144 may have a plurality of openings OP5, wherein the plurality of openings OP5 expose a part of the second patterned circuit layer 116 and the bottom surface 120b of the heat dissipation block 120. In this embodiment, further surface treatment (electroplating) is performed on the subsequently exposed electrical contacts.

請參考圖1G，於第一表面130a上配置晶片150且晶片150與基板130電性連接，且晶片150於基板130上的正投影與散熱塊120重疊，因此晶片150可以透過嵌入基板130中的散熱塊120進行散熱，將晶片150運作時產生的熱能從基板130的第一表面130a傳遞至第二表面130b。在本實施例中，晶片150可以是位於第一圖案化防銲層142的開口OP4中，且晶片150可以是以覆晶接合的方式配置於第一表面130a上，因此晶片150上具有散熱或接地功能的凸塊可以直接與散熱塊120接觸，以縮短晶片150的散熱路徑，但本發明不限於此。在此，本發明不限制晶片150的種類，可以視實際設計需求而定。1G, the chip 150 is disposed on the first surface 130a and the chip 150 is electrically connected to the substrate 130, and the orthographic projection of the chip 150 on the substrate 130 overlaps with the heat sink 120, so the chip 150 can pass through the embedded substrate 130 The heat sink 120 dissipates heat and transfers the heat generated during the operation of the chip 150 from the first surface 130a of the substrate 130 to the second surface 130b. In this embodiment, the chip 150 may be located in the opening OP4 of the first patterned solder mask 142, and the chip 150 may be disposed on the first surface 130a in a flip chip bonding manner, so that the chip 150 has heat dissipation or The bumps with the grounding function can directly contact the heat dissipation block 120 to shorten the heat dissipation path of the chip 150, but the present invention is not limited to this. Here, the present invention does not limit the type of the chip 150, which can be determined according to actual design requirements.

請參考圖1H，為了防止水氣或外界異物入侵，進而對半導體封裝結構100造成影響，例如鏽蝕、短路或功能失常等，可以形成封裝膠體160以包封晶片150。在本實施例中，部分封裝膠體160可以填充至開口OP4中，因此封裝膠體160可以與部分第一圖案化線路層114直接接觸，但本發明不限於此。封裝膠體160的材料例如是環氧模壓樹脂（Epoxy Molding Compound, EMC），而封裝膠體160例如是藉由模封製程所形成。1H, in order to prevent moisture or foreign matter from invading the semiconductor package structure 100, such as corrosion, short circuit, or malfunction, a package gel 160 can be formed to encapsulate the chip 150. In this embodiment, a part of the encapsulant 160 can be filled into the opening OP4, so the encapsulant 160 can directly contact a part of the first patterned circuit layer 114, but the present invention is not limited to this. The material of the encapsulant 160 is, for example, Epoxy Molding Compound (EMC), and the encapsulant 160 is formed by, for example, a molding process.

請參考圖1I，為使本發明達到更佳的散熱效果，亦可選擇性的接合一散熱模組172於散熱塊120上，其中散熱塊120與散熱模組172構成散熱元件170。舉例而言，散熱模組172可以位於基板130的第二表面130b上，且散熱模組172可以直接連接至嵌入基板130中的散熱塊120以構成散熱元件170。晶片150於基板130的正投影重疊於散熱元件170，且散熱模組172可以是凸設於第一圖案化線路層114。散熱模組172例如是金屬片，其中金屬片可以藉由散熱膠20連接於散熱塊120上，但本發明不限於此。應說明的是，在其他實施例中，散熱模組172可以具有其他不同態樣。Please refer to FIG. 1I, in order to achieve a better heat dissipation effect of the present invention, a heat dissipation module 172 can also be selectively joined to the heat dissipation block 120, wherein the heat dissipation block 120 and the heat dissipation module 172 constitute a heat dissipation element 170. For example, the heat dissipation module 172 may be located on the second surface 130b of the substrate 130, and the heat dissipation module 172 may be directly connected to the heat dissipation block 120 embedded in the substrate 130 to form the heat dissipation element 170. The orthographic projection of the chip 150 on the substrate 130 overlaps the heat dissipation element 170, and the heat dissipation module 172 may be protrudingly provided on the first patterned circuit layer 114. The heat dissipation module 172 is, for example, a metal sheet, where the metal sheet can be connected to the heat dissipation block 120 by the heat dissipation glue 20, but the present invention is not limited to this. It should be noted that in other embodiments, the heat dissipation module 172 may have other different aspects.

嵌入基板130中的散熱元件170可以構成晶片150有效地散熱路徑，如圖1I中的箭頭所示，以使晶片150運作時產生的熱能可以經由散熱元件170從基板130的第一表面130a傳遞至第二表面130b逸散出去，因此可以有效提升半導體封裝結構100的散熱效率，進而降低半導體封裝結構100中的晶片150因為過熱而導致效能衰減甚至失效的問題。The heat dissipation element 170 embedded in the substrate 130 can form an effective heat dissipation path for the chip 150, as shown by the arrow in FIG. 11, so that the heat generated during the operation of the chip 150 can be transferred from the first surface 130a of the substrate 130 through the heat dissipation element 170 The second surface 130b escapes, thereby effectively improving the heat dissipation efficiency of the semiconductor packaging structure 100, thereby reducing the problem of performance degradation or even failure of the chip 150 in the semiconductor packaging structure 100 due to overheating.

請繼續參考圖1I，於第二表面130b上還可以形成多個導電端子180且導電端子180與基板130電性連接，其中導電端子180後續可以進一步與其他元件連接，例如是PCB電路板。在本實施例中，多個導電端子180可以圍繞散熱元件170。換句話說，多個導電端子180可以位於散熱元件170的兩側。導電端子180可以是錫球，但本發明不限於此。在一實施例中，可以對導電端子180進行迴焊製程，以提升導電端子180與基板130之間的黏著力。經過上述製程後即可大致上完成本實施例之半導體封裝結構100的製作。其中，更應說明的是，散熱元件170的下表面可以選擇性的與外部元件(例如電路板)直接接觸，形成熱傳導散熱路徑，或亦可選擇性的與外部元件保持一段間距，利用空氣流通來達到散熱，無論是接觸或是非接觸，均屬於本發明之範圍。Please continue to refer to FIG. 1I, a plurality of conductive terminals 180 may be formed on the second surface 130b, and the conductive terminals 180 are electrically connected to the substrate 130, wherein the conductive terminals 180 may be further connected to other components, such as a PCB circuit board. In this embodiment, a plurality of conductive terminals 180 may surround the heat dissipation element 170. In other words, the plurality of conductive terminals 180 may be located on both sides of the heat dissipation element 170. The conductive terminal 180 may be a solder ball, but the present invention is not limited thereto. In one embodiment, the conductive terminal 180 may be subjected to a reflow process to improve the adhesion between the conductive terminal 180 and the substrate 130. After the above-mentioned manufacturing process, the fabrication of the semiconductor package structure 100 of this embodiment can be substantially completed. It should be noted that the lower surface of the heat dissipating element 170 can selectively directly contact an external element (such as a circuit board) to form a heat conduction and heat dissipation path, or it can also selectively maintain a distance from the external element and use air circulation. To achieve heat dissipation, whether it is contact or non-contact, it belongs to the scope of the present invention.

在此必須說明的是，以下實施例沿用上述實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明，關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。It must be noted here that the following embodiments follow the component numbers and part of the content of the above embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted, and the description of the omitted parts is omitted. Reference may be made to the foregoing embodiment, and the description of the following embodiments will not be repeated.

圖2是依據本發明另一實施例的半導體封裝結構的部分剖面示意圖。請參考圖2，本實施例的半導體封裝結構200類似於上述實施例的半導體封裝結構100，而其差別在於：晶片150以打線接合的方式配置於第一表面130a上。舉例而言，晶片150可以藉由導線L連接第一圖案化線路層114，以形成電性連接。在本實施例中，封裝膠體160的高度可以高於導線L的高度以完全包覆導線L。2 is a schematic partial cross-sectional view of a semiconductor package structure according to another embodiment of the invention. Please refer to FIG. 2, the semiconductor package structure 200 of this embodiment is similar to the semiconductor package structure 100 of the foregoing embodiment, but the difference is that the chip 150 is disposed on the first surface 130a by wire bonding. For example, the chip 150 may be connected to the first patterned circuit layer 114 by the wire L to form an electrical connection. In this embodiment, the height of the encapsulant 160 may be higher than the height of the wire L to completely cover the wire L.

圖3是依據本發明又一實施例的半導體封裝結構的部分剖面示意圖。請參考圖3，本實施例的半導體封裝結構300類似於上述實施例的半導體封裝結構100，而其差別在於：半導體封裝結構300更包括電路板390，且散熱模組372可以是熱導管。舉例而言，電路板390位於散熱元件370與多個導電端子180上，其中多個導電端子180與散熱元件370可以與電路板390直接接觸，以使晶片150運作時產生的熱能可以進一步透過電路板390傳遞出去，因此可以更有效提升半導體封裝結構300的散熱效率，進而降低半導體封裝結構300中的晶片150因為過熱而導致效能衰減甚至失效的問題。3 is a schematic partial cross-sectional view of a semiconductor package structure according to another embodiment of the invention. Referring to FIG. 3, the semiconductor package structure 300 of this embodiment is similar to the semiconductor package structure 100 of the foregoing embodiment, but the difference is that the semiconductor package structure 300 further includes a circuit board 390, and the heat dissipation module 372 may be a heat pipe. For example, the circuit board 390 is located on the heat dissipation element 370 and the plurality of conductive terminals 180, wherein the plurality of conductive terminals 180 and the heat dissipation element 370 can directly contact the circuit board 390, so that the heat generated during the operation of the chip 150 can be further transmitted through the circuit The board 390 is transferred out, so that the heat dissipation efficiency of the semiconductor packaging structure 300 can be more effectively improved, thereby reducing the problem of performance degradation or even failure of the chip 150 in the semiconductor packaging structure 300 due to overheating.

圖4是依據本發明再一實施例的半導體封裝結構的部分剖面示意圖。請參考圖4，本實施例的半導體封裝結構400類似於上述實施例的半導體封裝結構300，而其差別在於：散熱元件470中的散熱模組472可以是水冷式散熱器。在此，水冷式散熱器例如是藉由相變化來達到散熱的功效。4 is a schematic partial cross-sectional view of a semiconductor package structure according to still another embodiment of the present invention. Referring to FIG. 4, the semiconductor package structure 400 of this embodiment is similar to the semiconductor package structure 300 of the foregoing embodiment, but the difference is that the heat dissipation module 472 in the heat dissipation element 470 may be a water-cooled heat sink. Here, the water-cooled radiator achieves heat dissipation effect through phase change, for example.

應說明的是，儘管上述實施例中僅繪示出單獨存在的散熱模組，如圖1I所示的金屬片，圖3所示的熱導管以及圖4所示的水冷式散熱器，然而，本發明不限於此，散熱模組可以是多種散熱構件的組合。舉例而言，散熱模組可以是金屬片、熱導管、水冷式散熱器的組合。It should be noted that although the foregoing embodiment only illustrates a separate heat dissipation module, such as the metal sheet shown in FIG. 1I, the heat pipe shown in FIG. 3, and the water-cooled radiator shown in FIG. 4, however, The present invention is not limited to this, and the heat dissipation module may be a combination of various heat dissipation components. For example, the heat dissipation module can be a combination of metal sheets, heat pipes, and water-cooled radiators.

圖5是依據本發明又再一實施例的半導體封裝結構的部分剖面示意圖。請參考圖5，本實施例的半導體封裝結構500類似於上述實施例的半導體封裝結構100，而其差別在於：散熱元件170與電路板390之間可以藉由如散熱材料592(散熱膏、散熱或錫膏)連接，因此可以更進一步有效提升半導體封裝結構500的散熱效率，進而降低半導體封裝結構500中的晶片150因為過熱而導致效能衰減甚至失效的問題。FIG. 5 is a schematic partial cross-sectional view of a semiconductor package structure according to still another embodiment of the present invention. Please refer to FIG. 5, the semiconductor package structure 500 of this embodiment is similar to the semiconductor package structure 100 of the above-mentioned embodiment, but the difference is that the heat dissipation element 170 and the circuit board 390 can be formed by a heat dissipation material 592 (heat dissipation paste, heat dissipation). (Or solder paste) connection, therefore, the heat dissipation efficiency of the semiconductor packaging structure 500 can be further effectively improved, thereby reducing the problem of performance degradation or even failure of the chip 150 in the semiconductor packaging structure 500 due to overheating.

綜上所述，本發明嵌入基板中的散熱元件可以構成晶片有效地散熱路徑，以使晶片運作時產生的熱能可以經由散熱元件從基板的第一表面傳遞至第二表面逸散出去，因此可以有效提升半導體封裝結構的散熱效率，進而降低半導體封裝結構中的晶片因為過熱而導致效能衰減甚至失效的問題。此外，半導體封裝結構可以更包括位於散熱元件與多個導電端子上的電路板且散熱模組可以具有不同態樣，以更進一步有效提升半導體封裝結構的散熱效率，進而降低半導體封裝結構中的晶片因為過熱而導致效能衰減甚至失效的問題。In summary, the heat dissipation element embedded in the substrate of the present invention can form an effective heat dissipation path for the chip, so that the heat generated during the operation of the chip can be transferred from the first surface to the second surface of the substrate and escape through the heat dissipation element. Effectively improve the heat dissipation efficiency of the semiconductor package structure, thereby reducing the problem of performance degradation or even failure of the chip in the semiconductor package structure due to overheating. In addition, the semiconductor packaging structure may further include a circuit board on the heat dissipation element and the plurality of conductive terminals, and the heat dissipation module may have different configurations, so as to further effectively improve the heat dissipation efficiency of the semiconductor packaging structure, thereby reducing the chip in the semiconductor packaging structure. The problem of performance degradation or even failure due to overheating.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10:多層板 12、112:核心層 12a:上表面 12b:下表面 14、1141:第一導電層 16、1161:第二導電層 20:散熱膠 100、200、300、400、500:半導體封裝結構 114:第一圖案化線路層 116:第二圖案化線路層 1141a、1161a:外表面 120:散熱塊 120a:頂面 120b:底面 130:基板 130a:第一表面 130b:第二表面 142:第一圖案化防銲層 144:第二圖案化防銲層 1421:第一防銲層 1441:第二防銲層 150:晶片 160:封裝膠體 170、370、470:散熱元件 172、372、472:散熱模組 180:導電端子 390:電路板 592:散熱膏 L:導線 OP1、OP2、OP3、OP4、OP5:開口 10: Multilayer board 12, 112: core layer 12a: upper surface 12b: lower surface 14, 1141: the first conductive layer 16, 1161: second conductive layer 20: Thermal glue 100, 200, 300, 400, 500: semiconductor package structure 114: The first patterned circuit layer 116: second patterned circuit layer 1141a, 1161a: outer surface 120: heat sink 120a: top surface 120b: bottom surface 130: substrate 130a: first surface 130b: second surface 142: The first patterned solder mask 144: The second patterned solder mask 1421: The first solder mask 1441: second solder mask 150: chip 160: Encapsulation gel 170, 370, 470: heat dissipation components 172, 372, 472: cooling module 180: conductive terminal 390: circuit board 592: Thermal Grease L: Wire OP1, OP2, OP3, OP4, OP5: opening

圖1A至圖1I是依據本發明一實施例的半導體封裝結構的部分製造方法的部分剖面示意圖。 圖2是依據本發明另一實施例的半導體封裝結構的部分剖面示意圖。 圖3是依據本發明又一實施例的半導體封裝結構的部分剖面示意圖。 圖4是依據本發明再一實施例的半導體封裝結構的部分剖面示意圖。 圖5是依據本發明又再一實施例的半導體封裝結構的部分剖面示意圖。 1A to 1I are partial cross-sectional schematic diagrams of a part of a manufacturing method of a semiconductor package structure according to an embodiment of the present invention. 2 is a schematic partial cross-sectional view of a semiconductor package structure according to another embodiment of the invention. 3 is a schematic partial cross-sectional view of a semiconductor package structure according to another embodiment of the invention. 4 is a schematic partial cross-sectional view of a semiconductor package structure according to still another embodiment of the present invention. FIG. 5 is a schematic partial cross-sectional view of a semiconductor package structure according to still another embodiment of the present invention.

20:散熱膠 20: Thermal glue

100:半導體封裝結構 100: Semiconductor package structure

120:散熱塊 120: heat sink

130:基板 130: substrate

130a:第一表面 130a: first surface

130b:第二表面 130b: second surface

142:第一圖案化防銲層 142: The first patterned solder mask

144:第二圖案化防銲層 144: The second patterned solder mask

150:晶片 150: chip

160:封裝膠體 160: Encapsulation colloid

170:散熱元件 170: heat dissipation element

172:散熱模組 172: Cooling Module

180:導電端子 180: conductive terminal

Claims (8)

一種半導體封裝結構，包括：基板，具有第一表面與相對於所述第一表面的第二表面；晶片，位於所述第一表面上且與所述基板電性連接；封裝膠體，包封所述晶片；散熱元件，位於所述第二表面上且部分所述散熱元件嵌入所述基板中，其中所述晶片於所述基板的正投影重疊於所述散熱元件，其中所述散熱元件包括散熱塊與接合於所述散熱塊的散熱模組，且所述散熱塊貫穿所述基板而顯露於所述第一表面，所述散熱模組凸設於所述第二表面；以及多個導電端子，位於所述第二表面上且與所述基板電性連接，其中所述多個導電端子圍繞所述散熱元件。 A semiconductor packaging structure, comprising: a substrate having a first surface and a second surface opposite to the first surface; a wafer located on the first surface and electrically connected to the substrate; an encapsulation gel, which encapsulates the substrate The chip; a heat dissipation element located on the second surface and part of the heat dissipation element is embedded in the substrate, wherein the orthographic projection of the chip on the substrate overlaps the heat dissipation element, wherein the heat dissipation element includes heat dissipation A block and a heat dissipation module joined to the heat dissipation block, and the heat dissipation block penetrates the substrate to be exposed on the first surface, the heat dissipation module is protrudingly provided on the second surface; and a plurality of conductive terminals , Located on the second surface and electrically connected to the substrate, wherein the plurality of conductive terminals surround the heat dissipation element. 如請求項1所述的半導體封裝結構，其中所述散熱模組包括金屬片、熱導管、水冷式散熱器或其組合。 The semiconductor package structure according to claim 1, wherein the heat dissipation module includes a metal sheet, a heat pipe, a water-cooled heat sink, or a combination thereof. 如請求項1所述的半導體封裝結構，更包括電路板，位於所述散熱元件與所述多個導電端子上，其中所述多個導電端子與所述電路板直接接觸。 The semiconductor package structure according to claim 1, further comprising a circuit board on the heat dissipation element and the plurality of conductive terminals, wherein the plurality of conductive terminals are in direct contact with the circuit board. 如請求項3所述的半導體封裝結構，其中所述散熱元件與所述電路板直接接觸。 The semiconductor package structure according to claim 3, wherein the heat dissipation element is in direct contact with the circuit board. 如請求項3所述的半導體封裝結構，其中所述散熱元件與所述電路板之間藉由散熱膏、散熱膠或錫膏連接。 The semiconductor package structure according to claim 3, wherein the heat dissipating element and the circuit board are connected by heat dissipating paste, heat dissipating glue or solder paste. 一種半導體封裝結構的製造方法，包括： 提供多層板，其中所述多層板包括核心層以及形成於所述核心層上的導電層；移除部分所述核心層與部分所述導電層，以形成貫穿所述多層板的開口；填充導熱材料於所述開口中，以形成散熱塊；對剩餘的所述導電層進行圖案化製程，以形成圖案化線路層，其中剩餘的所述核心層與所述圖案化線路層構成基板，其中所述基板具有第一表面與相對於所述第一表面的第二表面；配置晶片於所述第一表面上且與所述基板電性連接；形成封裝膠體，以包封所述晶片；接合散熱模組於所述散熱塊上，且所述散熱模組凸設於所述圖案化線路層，其中所述散熱塊與所述散熱模組構成所述散熱元件形成於所述第二表面上且部分所述散熱元件嵌入所述基板中，其中所述晶片於所述基板的正投影重疊於所述散熱元件；以及形成多個導電端子於所述第二表面上且與所述基板電性連接，其中所述多個導電端子圍繞所述散熱元件。 A method for manufacturing a semiconductor packaging structure includes: A multilayer board is provided, wherein the multilayer board includes a core layer and a conductive layer formed on the core layer; part of the core layer and part of the conductive layer are removed to form an opening penetrating the multilayer board; Material in the opening to form a heat sink; the remaining conductive layer is subjected to a patterning process to form a patterned circuit layer, wherein the remaining core layer and the patterned circuit layer constitute a substrate, wherein The substrate has a first surface and a second surface opposite to the first surface; disposing a chip on the first surface and electrically connecting with the substrate; forming a packaging glue to encapsulate the chip; bonding and dissipating heat The module is on the heat dissipation block, and the heat dissipation module is protrudingly disposed on the patterned circuit layer, wherein the heat dissipation block and the heat dissipation module constitute the heat dissipation element formed on the second surface and Part of the heat dissipation element is embedded in the substrate, wherein the orthographic projection of the chip on the substrate overlaps the heat dissipation element; and a plurality of conductive terminals are formed on the second surface and electrically connected to the substrate , Wherein the plurality of conductive terminals surround the heat dissipation element. 如請求項6所述的半導體封裝結構的製造方法，其中所述導熱材料填滿所述開口。 The method for manufacturing a semiconductor package structure according to claim 6, wherein the thermally conductive material fills the opening. 如請求項6所述的半導體封裝結構的製造方法，其中所述晶片以覆晶接合或打線接合的方式配置於所述第一表面上。 The method for manufacturing a semiconductor package structure according to claim 6, wherein the chip is arranged on the first surface by flip chip bonding or wire bonding.
TW109102236A 2020-01-21 2020-01-21 Semiconductor package structure and manufacturing method thereof TWI720796B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW109102236A TWI720796B (en) 2020-01-21 2020-01-21 Semiconductor package structure and manufacturing method thereof
CN202010348023.7A CN113224014A (en) 2020-01-21 2020-04-28 Semiconductor package structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW109102236A TWI720796B (en) 2020-01-21 2020-01-21 Semiconductor package structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TWI720796B true TWI720796B (en) 2021-03-01
TW202129854A TW202129854A (en) 2021-08-01

Family

ID=76035822

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109102236A TWI720796B (en) 2020-01-21 2020-01-21 Semiconductor package structure and manufacturing method thereof

Country Status (2)

Country Link
CN (1) CN113224014A (en)
TW (1) TWI720796B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200802764A (en) * 2006-06-02 2008-01-01 Chipmos Technologies Inc Chip package with array pads and method for manufacturing the same
TW200849641A (en) * 2007-06-06 2008-12-16 Chipmos Technologies Inc Light source module and the method for adjusting the brightness thereof
TW201640635A (en) * 2015-05-12 2016-11-16 南茂科技股份有限公司 Package structure and manufactruing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200802764A (en) * 2006-06-02 2008-01-01 Chipmos Technologies Inc Chip package with array pads and method for manufacturing the same
TW200849641A (en) * 2007-06-06 2008-12-16 Chipmos Technologies Inc Light source module and the method for adjusting the brightness thereof
TW201640635A (en) * 2015-05-12 2016-11-16 南茂科技股份有限公司 Package structure and manufactruing method thereof

Also Published As

Publication number Publication date
CN113224014A (en) 2021-08-06
TW202129854A (en) 2021-08-01

Similar Documents

Publication Publication Date Title
US10593656B2 (en) Three-dimensional package structure
JP4746283B2 (en) Method of connecting a heat sink to a circuit assembly and integrated circuit device
US9130064B2 (en) Method for fabricating leadframe-based semiconductor package with connecting pads top and bottom surfaces of carrier
US9496210B1 (en) Stackable package and method
JP6021504B2 (en) Printed wiring board, printed circuit board, and printed circuit board manufacturing method
CN110556369B (en) Electronic module with magnetic device
TWI543314B (en) Semiconductor package
US8304922B2 (en) Semiconductor package system with thermal die bonding
JP2003264265A (en) Power semiconductor device
TWI456708B (en) Top-side cooled semiconductor package with stacked interconnection plates and method
JP2006502595A (en) Semiconductor device package
US5299091A (en) Packaged semiconductor device having heat dissipation/electrical connection bumps and method of manufacturing same
TW202036815A (en) Semiconductor package having an internal heat sink and method of manufacturingthe same
TWI416700B (en) Chip-stacked package structure and method for manufacturing the same
WO2007147366A1 (en) Ic packages with internal heat dissipation structures
CN109801900B (en) Inverter circuit device for electric power
TWI720796B (en) Semiconductor package structure and manufacturing method thereof
JP4919689B2 (en) Module board
TWI660471B (en) Chip package
US11482507B2 (en) Semiconductor package having molding member and heat dissipation member
JP2002151634A (en) Board radiator
TWI576930B (en) Circuit package of circuit component module and its product
JP2003023126A (en) Semiconductor device
TWI820690B (en) Power module and manufacturing method thereof
US20220181238A1 (en) Chip packaging method and chip package unit