TWI717171B - Data reading method, storage controller and storage device - Google Patents

Abstract

A data reading method is provided. The method includes: performing a read operation on a target codeword stored in a target physical page among a plurality of physical pages to obtain a raw codeword; perform, by a first decoder, X first iterative decoding operations on the raw codeword to obtain X first decoded codewords respectively corresponding to the X first iterative decoding operations; in response to determining that performing a plurality of second iterative decoding operation by a second decoder, generating a first soft bit information and a log-likelihood table according to the X first decoded codewords, and performing, by the second decoder, a plurality of second iterative decoding operations according to the genertated first soft bit information and the log-likelihood table to obtain a final decoded codeword.

Description

資料讀取方法、儲存控制器與儲存裝置Data reading method, storage controller and storage device

本發明是有關於一種資料讀取方法，且特別是有關於一種適用於配置有可複寫式非揮發性記憶體模組的儲存裝置及其儲存控制器的資料讀取方法。The present invention relates to a data reading method, and more particularly to a data reading method suitable for a storage device equipped with a rewritable non-volatile memory module and a storage controller thereof.

現有的錯誤檢查與校正電路中可具有兩個一解碼器，一個解碼器具有較低的解碼能力且較低的耗能(耗費較低的電力)，另一個解碼器具有較高的解碼能力且較高的耗能。The existing error checking and correction circuit may have two one-decoders, one decoder has lower decoding capability and lower energy consumption (lower power consumption), and the other decoder has higher decoding capability and Higher energy consumption.

一般來說，當對所讀取的讀取資料(原始碼字)來進行解碼操作時，錯誤檢查與校正電路會先使用較低耗能的解碼器來進行初步的解碼程序。當所述初步的解碼程序失敗後，錯誤檢查與校正電路再使用較高耗能的能力的解碼器來重新進行解碼，以嘗試獲得解碼正確的讀取資料。Generally speaking, when the read data (original codeword) is decoded, the error checking and correction circuit will first use a lower energy-consuming decoder to perform the preliminary decoding process. When the preliminary decoding procedure fails, the error checking and correction circuit uses a decoder with a higher energy consumption capability to re-decode, so as to try to obtain the correctly decoded read data.

然而，由於傳統方法會利用較高耗能的能力的解碼器重新解碼，而導致了整體解碼操作的耗費時間增加，更增加了耗能。However, since the traditional method uses a decoder with a higher energy consumption capability to re-decode, the overall decoding operation consumes more time and energy.

因此，如何增進具有複數種類的解碼器的錯誤檢查與校正電路的解碼效率，提昇解碼操作的性能且增進可複寫式非揮發性記憶體模組的資料讀取效率，是本領域人員研究的課題之一。Therefore, how to improve the decoding efficiency of error checking and correction circuits with plural types of decoders, improve the performance of the decoding operation, and improve the data reading efficiency of the rewritable non-volatile memory module is a topic for those skilled in the art. one.

本發明的一實施例提供適用於配置有一可複寫式非揮發性記憶體模組的一儲存裝置的一種資料讀取方法，其中所述可複寫式非揮發性記憶體模組具有多個字元線，其中所述多個字元線的每一個字元線耦接至多個記憶胞，其中所述多個記憶胞中的每一個記憶胞包括多個實體頁面，並且所述多個實體頁面中的每一個實體頁面用以被程式化為一位元值。所述方法包括：對所述多個實體頁面中的目標實體頁面所儲存的目標碼字執行讀取操作，以獲得原始碼字；經由第一解碼器，對所述原始碼字執行X個第一迭代解碼操作，以獲得分別對應所述X個第一迭代解碼操作的X個第一已解碼碼字與對應所述X個第一已解碼碼字的X個第一校驗子；根據所述X個第一迭代解碼操作來判斷是否經由第二解碼器執行多個第二迭代解碼操作；反應於判定經由所述第二解碼器執行所述多個第二迭代解碼操作，根據所述X個第一已解碼碼字來產生第一軟位元資訊與對數似然比（Log Likelihood Ratio，LLR）表，並且經由所述第二解碼器，根據所產生的所述第一軟位元資訊與所述對數似然比表來執行多個第二迭代解碼操作，以獲得所述最終已解碼碼字；反應於判定不經由所述第二解碼器執行所述多個第二迭代解碼操作，經由所述第一解碼器，對所述X個第一已解碼碼字中的目標第一已解碼碼字執行多個第三迭代解碼操作，以獲得最終已解碼碼字；以及反應於判定所述最終已解碼碼字為正確的，輸出所述最終已解碼碼字以作為對應於所述讀取操作的讀取資料，並且完成所述讀取操作。An embodiment of the present invention provides a data reading method suitable for a storage device equipped with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of characters Line, wherein each of the plurality of character lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells includes a plurality of physical pages, and in the plurality of physical pages Each physical page of is used to be programmed as a one-bit value. The method includes: performing a reading operation on a target codeword stored in a target physical page of the plurality of physical pages to obtain an original codeword; and performing X-th order on the original codeword through a first decoder An iterative decoding operation to obtain X first decoded codewords corresponding to the X first iterative decoding operations and X first syndromes corresponding to the X first decoded codewords; The X first iterative decoding operations are used to determine whether to perform multiple second iterative decoding operations via the second decoder; in response to the determination to perform the multiple second iterative decoding operations via the second decoder, according to the X First decoded codewords to generate first soft bit information and a log likelihood ratio (Log Likelihood Ratio, LLR) table, and through the second decoder, according to the generated first soft bit information Performing multiple second iterative decoding operations with the log-likelihood ratio table to obtain the final decoded codeword; in response to the decision not to perform the multiple second iterative decoding operations via the second decoder, Through the first decoder, perform multiple third iterative decoding operations on the target first decoded codeword among the X first decoded codewords to obtain the final decoded codeword; and respond to the determination The final decoded codeword is correct, the final decoded codeword is output as the reading data corresponding to the reading operation, and the reading operation is completed.

本發明的一實施例提供用於控制配置有可複寫式非揮發性記憶體模組的儲存裝置的一種儲存控制器。所述儲存控制器包括：連接介面電路、記憶體介面控制電路、讀取輔助電路單元、錯誤檢查與校正電路以及處理器。連接介面電路用以耦接至主機系統。記憶體介面控制電路用以耦接至所述可複寫式非揮發性記憶體模組，其中所述可複寫式非揮發性記憶體模組具有多個字元線，其中所述多個字元線的每一個字元線耦接至多個記憶胞，其中所述多個記憶胞中的每一個記憶胞包括多個實體頁面，並且所述多個實體頁面中的每一個實體頁面用以被程式化為一位元值。處理器耦接至所述連接介面電路、所述記憶體介面控制電路、所述讀取輔助電路單元及所述錯誤檢查與校正電路。所述處理器用以對所述多個實體頁面中的目標實體頁面所儲存的目標碼字執行讀取操作，以獲得原始碼字。所述讀取輔助電路單元指示所述第一解碼器，對所述原始碼字執行X個第一迭代解碼操作，以獲得分別對應所述X個第一迭代解碼操作的X個第一已解碼碼字與對應所述X個第一已解碼碼字的X個第一校驗子。此外，所述讀取輔助電路單元根據所述X個第一迭代解碼操作來判斷是否經由第二解碼器執行多個第二迭代解碼操作。反應於判定經由所述第二解碼器執行所述多個第二迭代解碼操作，所述讀取輔助電路單元根據所述X個第一已解碼碼字來產生第一軟位元資訊與對數似然比（Log Likelihood Ratio，LLR）表，並且指示所述第二解碼器，根據所產生的所述第一軟位元資訊與所述對數似然比表來執行多個第二迭代解碼操作，以獲得所述最終已解碼碼字；以及反應於判定不經由所述第二解碼器執行所述多個第二迭代解碼操作，所述讀取輔助電路單元指示所述第一解碼器，對所述X個第一已解碼碼字中的目標第一已解碼碼字執行多個第三迭代解碼操作，以獲得最終已解碼碼字。此外，反應於判定所述最終已解碼碼字為正確的，所述錯誤檢查與校正電路輸出所述最終已解碼碼字以作為對應於所述讀取操作的讀取資料，並且完成所述讀取操作。An embodiment of the present invention provides a storage controller for controlling a storage device equipped with a rewritable non-volatile memory module. The storage controller includes: a connection interface circuit, a memory interface control circuit, a reading auxiliary circuit unit, an error checking and correction circuit, and a processor. The connection interface circuit is used for coupling to the host system. The memory interface control circuit is used for coupling to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of character lines, wherein the plurality of characters Each character line of the line is coupled to a plurality of memory cells, wherein each of the plurality of memory cells includes a plurality of physical pages, and each of the plurality of physical pages is used to be programmed Converted to a one-bit value. The processor is coupled to the connection interface circuit, the memory interface control circuit, the read auxiliary circuit unit, and the error check and correction circuit. The processor is configured to perform a reading operation on the target codeword stored in the target physical page of the plurality of physical pages to obtain the original codeword. The reading auxiliary circuit unit instructs the first decoder to perform X first iterative decoding operations on the original codeword to obtain X first decoded operations corresponding to the X first iterative decoding operations, respectively The codeword and X first syndromes corresponding to the X first decoded codewords. In addition, the read auxiliary circuit unit determines whether to perform multiple second iterative decoding operations via the second decoder according to the X first iterative decoding operations. In response to determining that the plurality of second iterative decoding operations are performed through the second decoder, the read auxiliary circuit unit generates first soft bit information and logarithmic similarity according to the X first decoded code words Likelihood Ratio (Log Likelihood Ratio, LLR) table, and instruct the second decoder to perform multiple second iterative decoding operations according to the generated first soft bit information and the log likelihood ratio table, To obtain the final decoded codeword; and in response to determining not to perform the plurality of second iterative decoding operations via the second decoder, the read auxiliary circuit unit instructs the first decoder to The target first decoded codeword among the X first decoded codewords performs multiple third iterative decoding operations to obtain the final decoded codeword. In addition, in response to determining that the final decoded codeword is correct, the error checking and correction circuit outputs the final decoded codeword as the reading data corresponding to the reading operation, and completing the reading Take operation.

本發明的一實施例提供一種儲存裝置。所述儲存裝置包括可複寫式非揮發性記憶體模組、記憶體介面控制電路及處理器。可複寫式非揮發性記憶體模組具有多個字元線，其中所述多個字元線的每一個字元線耦接至多個記憶胞，其中所述多個記憶胞中的每一個記憶胞包括多個實體頁面，並且所述多個實體頁面中的每一個實體頁面用以被程式化為一位元值。記憶體介面控制電路用以耦接至所述可複寫式非揮發性記憶體模組。處理器耦接至所述記憶體介面控制電路，其中所述處理器載入且執行讀取輔助程式碼模組，以實現資料讀取方法。其中所述處理器載入且執行一讀取輔助程式碼模組，以實現一資料讀取方法。所述資料讀取方法包括下列步驟：對所述多個實體頁面中的目標實體頁面所儲存的目標碼字執行讀取操作，以獲得原始碼字；經由第一解碼器，對所述原始碼字執行X個第一迭代解碼操作，以獲得分別對應所述X個第一迭代解碼操作的X個第一已解碼碼字與對應所述X個第一已解碼碼字的X個第一校驗子；根據所述X個第一迭代解碼操作來判斷是否經由第二解碼器執行多個第二迭代解碼操作；反應於判定經由所述第二解碼器執行所述多個第二迭代解碼操作，根據所述X個第一已解碼碼字來產生第一軟位元資訊與對數似然比（Log Likelihood Ratio，LLR）表，並且經由所述第二解碼器，根據所產生的所述第一軟位元資訊與所述對數似然比表來執行多個第二迭代解碼操作，以獲得所述最終已解碼碼字；反應於判定不經由所述第二解碼器執行所述多個第二迭代解碼操作，經由所述第一解碼器，對所述X個第一已解碼碼字中的目標第一已解碼碼字執行多個第三迭代解碼操作，以獲得最終已解碼碼字；以及反應於判定所述最終已解碼碼字為正確的，輸出所述最終已解碼碼字以作為對應於所述讀取操作的讀取資料，並且完成所述讀取操作。An embodiment of the present invention provides a storage device. The storage device includes a rewritable non-volatile memory module, a memory interface control circuit and a processor. The rewritable non-volatile memory module has a plurality of character lines, wherein each character line of the plurality of character lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells is The cell includes a plurality of physical pages, and each physical page of the plurality of physical pages is used to be programmed as a one-bit value. The memory interface control circuit is used for coupling to the rewritable non-volatile memory module. The processor is coupled to the memory interface control circuit, and the processor loads and executes the reading auxiliary code module to realize the data reading method. Wherein the processor loads and executes a reading auxiliary code module to realize a data reading method. The data reading method includes the following steps: performing a reading operation on the target codeword stored in the target physical page of the plurality of physical pages to obtain the original codeword; Word performs X first iterative decoding operations to obtain X first decoded codewords corresponding to said X first iterative decoding operations and X first codewords corresponding to said X first decoded codewords. Empirical; according to the X first iterative decoding operations to determine whether to perform multiple second iterative decoding operations via the second decoder; in response to the determination to perform the multiple second iterative decoding operations via the second decoder , Generating a first soft bit information and a log likelihood ratio (Log Likelihood Ratio, LLR) table according to the X first decoded codewords, and using the second decoder according to the generated first A soft bit information and the log-likelihood ratio table are used to perform a plurality of second iterative decoding operations to obtain the final decoded codeword; in response to a determination not to execute the plurality of first decoding operations through the second decoder A second iterative decoding operation, through the first decoder, performing multiple third iterative decoding operations on the target first decoded codeword among the X first decoded codewords to obtain a final decoded codeword; And in response to determining that the final decoded codeword is correct, output the final decoded codeword as the read data corresponding to the read operation, and complete the read operation.

基於上述，本發明實施例所提供的資料讀取方法、儲存控制器及儲存裝置，可從目標實體頁面讀取原始碼字後，利用經由第一解碼器對所述原始碼字執行多個第一迭代解碼操作所獲得的多個第一已解碼碼字與對應的多個第一校驗子來判斷是否要進一步經由第二解碼器來執行多個第二迭代解碼操作或經由第一解碼器執行多個第三迭代解碼操作，並且反應於判定經由第二解碼器來執行多個第二迭代解碼操作，根據所述多個第一已解碼碼字來產生第一軟位元資訊與對應的對數似然比表，以有效地利用所述多個第一已解碼碼字來增進第二解碼器所執行的所述多個第二迭代解碼操作的正確率。如此一來，雖然第一解碼器執行多個第一迭代解碼操作的期間會耗費電力與時間，但是經由所述多個第一迭代解碼操作所獲得多個第一已解碼碼字可被利用在後續第二解碼器所執行的第二迭代解碼操作，而改善了傳統作法的第二解碼器因重新利用原始碼字來進行多個迭代解碼操作，而具有較大的耗時與耗能所導致的問題，增進了從目標實體頁面所讀取資料的正確性與可靠度，降低對所讀取資料所執行的解碼操作的負荷，進而增進了資料讀取操作整體的效率。Based on the above, the data reading method, storage controller, and storage device provided by the embodiments of the present invention can read the original codeword from the target physical page, and then execute multiple first decoders on the original codeword through the first decoder. Multiple first decoded codewords obtained by an iterative decoding operation and corresponding multiple first syndromes are used to determine whether to further perform multiple second iterative decoding operations via the second decoder or via the first decoder Perform multiple third iterative decoding operations, and in response to the decision to perform multiple second iterative decoding operations via the second decoder, generate first soft bit information and corresponding information according to the multiple first decoded codewords The log-likelihood ratio table is used to effectively utilize the plurality of first decoded codewords to improve the accuracy of the plurality of second iterative decoding operations performed by the second decoder. In this way, although the first decoder will consume power and time during the multiple first iterative decoding operations, the multiple first decoded codewords obtained through the multiple first iterative decoding operations can be used in The second iterative decoding operation performed by the subsequent second decoder. The second decoder that improves the traditional practice re-uses the original codewords to perform multiple iterative decoding operations, which consumes more time and energy. The problem of improves the accuracy and reliability of the data read from the target physical page, reduces the load of the decoding operation performed on the read data, and thereby improves the overall efficiency of the data reading operation.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

在本實施例中，儲存裝置包括可複寫式非揮發性記憶體模組(rewritable non-volatile memory module)與儲存裝置控制器(亦稱，儲存控制器或儲存控制電路)。此外，儲存裝置是與主機系統一起使用，以使主機系統可將資料寫入至儲存裝置或從儲存裝置中讀取資料。In this embodiment, the storage device includes a rewritable non-volatile memory module and a storage device controller (also referred to as a storage controller or a storage control circuit). In addition, the storage device is used with the host system so that the host system can write data to the storage device or read data from the storage device.

圖1A是根據本發明的一實施例所繪示的主機系統及儲存裝置的方塊示意圖。FIG. 1A is a block diagram of a host system and a storage device according to an embodiment of the invention.

請參照圖1A，主機系統(Host System)10包括處理器(Processor)110、主機記憶體(Host Memory)120及資料傳輸介面電路(Data Transfer Interface Circuit)130。在本實施例中，資料傳輸介面電路130耦接(亦稱，電性連接)至處理器110與主機記憶體120。在另一實施例中，處理器110、主機記憶體120與資料傳輸介面電路130之間利用系統匯流排(System Bus)彼此耦接。1A, the host system (Host System) 10 includes a processor (Processor) 110, a host memory (Host Memory) 120 and a data transfer interface circuit (Data Transfer Interface Circuit) 130. In this embodiment, the data transmission interface circuit 130 is coupled (also referred to as electrically connected) to the processor 110 and the host memory 120. In another embodiment, the processor 110, the host memory 120, and the data transmission interface circuit 130 are coupled to each other by a system bus.

儲存裝置20包括儲存控制器(Storage Controller)210、可複寫式非揮發性記憶體模組(Rewritable Non-Volatile Memory Module)220及連接介面電路(Connection Interface Circuit)230。其中，儲存控制器210包括處理器211、資料管理電路(Data Management Circuit)212與記憶體介面控制電路(Memory Interface Control Circuit)213。The storage device 20 includes a storage controller (Storage Controller) 210, a rewritable non-volatile memory module (Rewritable Non-Volatile Memory Module) 220 and a connection interface circuit (Connection Interface Circuit) 230. The storage controller 210 includes a processor 211, a data management circuit (Data Management Circuit) 212, and a memory interface control circuit (Memory Interface Control Circuit) 213.

在本實施例中，主機系統10是透過資料傳輸介面電路130與儲存裝置20的連接介面電路230耦接至儲存裝置20來進行資料的存取操作。例如，主機系統10可經由資料傳輸介面電路130將資料儲存至儲存裝置20或從儲存裝置20中讀取資料。In this embodiment, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

在本實施例中，處理器110、主機記憶體120及資料傳輸介面電路130可設置在主機系統10的主機板上。資料傳輸介面電路130的數目可以是一或多個。透過資料傳輸介面電路130，主機板可以經由有線或無線方式耦接至儲存裝置20。儲存裝置20可例如是隨身碟、記憶卡、固態硬碟(Solid State Drive，SSD)或無線記憶體儲存裝置。無線記憶體儲存裝置可例如是近距離無線通訊(Near Field Communication，NFC)記憶體儲存裝置、無線傳真(WiFi)記憶體儲存裝置、藍牙(Bluetooth)記憶體儲存裝置或低功耗藍牙記憶體儲存裝置(例如，iBeacon)等以各式無線通訊技術為基礎的記憶體儲存裝置。此外，主機板也可以透過系統匯流排耦接至全球定位系統(Global Positioning System，GPS)模組、網路介面卡、無線傳輸裝置、鍵盤、螢幕、喇叭等各式I/O裝置。In this embodiment, the processor 110, the host memory 120, and the data transmission interface circuit 130 may be disposed on the main board of the host system 10. The number of the data transmission interface circuit 130 may be one or more. Through the data transmission interface circuit 130, the motherboard can be coupled to the storage device 20 in a wired or wireless manner. The storage device 20 may be, for example, a flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device may be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device or a Bluetooth low energy memory storage device Devices (for example, iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be coupled to various I/O devices such as Global Positioning System (GPS) modules, network interface cards, wireless transmission devices, keyboards, screens, speakers, etc. through the system bus.

在本實施例中，資料傳輸介面電路130與連接介面電路230是相容於高速周邊零件連接介面(Peripheral Component Interconnect Express, PCI Express)標準的介面電路。並且，資料傳輸介面電路130與連接介面電路230之間是利用快速非揮發性記憶體介面標準(Non-Volatile Memory express，NVMe)通訊協定來進行資料的傳輸。In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use a non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol for data transmission.

然而，必須瞭解的是，本發明不限於此，資料傳輸介面電路130與連接介面電路230亦可以是符合並列先進附件(Parallel Advanced Technology Attachment，PATA)標準、電氣和電子工程師協會(Institute of Electrical and Electronic Engineers，IEEE)1394標準、序列先進附件(Serial Advanced Technology Attachment，SATA)標準、通用序列匯流排(Universal Serial Bus，USB)標準、SD介面標準、超高速一代(Ultra High Speed-I，UHS-I)介面標準、超高速二代(Ultra High Speed-II，UHS-II)介面標準、記憶棒(Memory Stick, MS)介面標準、多晶片封裝(Multi-Chip Package)介面標準、多媒體儲存卡(Multi Media Card，MMC)介面標準、eMMC介面標準、通用快閃記憶體(Universal Flash Storage，UFS)介面標準、eMCP介面標準、CF介面標準、整合式驅動電子介面(Integrated Device Electronics，IDE)標準或其他適合的標準。此外，在另一實施例中，連接介面電路230可與儲存控制器210封裝在一個晶片中，或者連接介面電路230是佈設於一包含儲存控制器210之晶片外。However, it must be understood that the present invention is not limited to this. The data transmission interface circuit 130 and the connection interface circuit 230 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, serial advanced attachment (Serial Advanced Technology Attachment, SATA) standard, universal serial bus (Universal Serial Bus, USB) standard, SD interface standard, Ultra High Speed-I (UHS- I) Interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, Multi-Chip Package (Multi-Chip Package) interface standard, multimedia memory card ( Multi Media Card (MMC) interface standard, eMMC interface standard, Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or Other suitable standards. In addition, in another embodiment, the connection interface circuit 230 and the storage controller 210 may be packaged in a chip, or the connection interface circuit 230 may be arranged outside a chip including the storage controller 210.

在本實施例中，主機記憶體120用以暫存處理器110所執行的指令或資料。例如，在本範例實施例中，主機記憶體120可以是動態隨機存取記憶體（Dynamic Random Access Memory，DRAM）、靜態隨機存取記憶體(Static Random Access Memory，SRAM)等。然而，必須瞭解的是，本發明不限於此，主機記憶體120也可以是其他適合的記憶體。In this embodiment, the host memory 120 is used to temporarily store commands or data executed by the processor 110. For example, in this exemplary embodiment, the host memory 120 may be a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), etc. However, it must be understood that the present invention is not limited to this, and the host memory 120 may also be other suitable memory.

儲存控制器210用以執行以硬體型式或韌體型式實作的多個邏輯閘或控制指令並且根據主機系統10的指令在可複寫式非揮發性記憶體模組220中進行資料的寫入、讀取與抹除等運作。The storage controller 210 is used to execute a plurality of logic gates or control commands implemented in a hardware type or a firmware type and to write data in the rewritable non-volatile memory module 220 according to the instructions of the host system 10 , Read and erase operations.

更詳細來說，儲存控制器210中的處理器211為具備運算能力的硬體，其用以控制儲存控制器210的整體運作。具體來說，處理器211具有多個控制指令，並且在儲存裝置20運作時，此些控制指令會被執行以進行資料的寫入、讀取與抹除等運作。In more detail, the processor 211 in the storage controller 210 is a hardware capable of computing, which is used to control the overall operation of the storage controller 210. Specifically, the processor 211 has a plurality of control commands, and when the storage device 20 is operating, these control commands are executed to perform operations such as writing, reading, and erasing data.

值得一提的是，在本實施例中，處理器110與處理器211例如是中央處理單元(Central Processing Unit，CPU)、微處理器(micro-processor)、或是其他可程式化之處理單元(Microprocessor)、數位訊號處理器(Digital Signal Processor，DSP)、可程式化控制器、特殊應用積體電路(Application Specific Integrated Circuits，ASIC)、可程式化邏輯裝置(Programmable Logic Device，PLD)或其他類似電路元件，本發明並不限於此。It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor (micro-processor), or other programmable processing units. (Microprocessor), Digital Signal Processor (DSP), Programmable Controller, Application Specific Integrated Circuits (ASIC), Programmable Logic Device (PLD) or other Similar to circuit elements, the present invention is not limited to this.

在一實施例中，儲存控制器210還具有唯讀記憶體(未繪示)及隨機存取記憶體(未繪示)。特別是，此唯讀記憶體具有開機碼(boot code)，並且當儲存控制器210被致能時，處理器211會先執行此開機碼來將儲存於可複寫式非揮發性記憶體模組220中之控制指令載入至儲存控制器210的隨機存取記憶體中。之後，處理器211會運轉此些控制指令以進行資料的寫入、讀取與抹除等運作。在另一實施例中，處理器211的控制指令亦可以程式碼型式儲存於可複寫式非揮發性記憶體模組220的特定區域，例如，可複寫式非揮發性記憶體模組220中專用於存放系統資料的實體儲存單元中。In one embodiment, the storage controller 210 also has a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the storage controller 210 is enabled, the processor 211 will first execute the boot code to store it in the rewritable non-volatile memory module The control command in 220 is loaded into the random access memory of the storage controller 210. After that, the processor 211 runs these control commands to perform data writing, reading, and erasing operations. In another embodiment, the control commands of the processor 211 may also be stored in a specific area of the rewritable non-volatile memory module 220 in the form of program codes, for example, a dedicated area of the rewritable non-volatile memory module 220 In the physical storage unit storing system data.

在本實施例中，如上所述，儲存控制器210還包括資料管理電路212與記憶體介面控制電路213。應注意的是，儲存控制器210各部件所執行的操作亦可視為儲存控制器210所執行的操作。In this embodiment, as described above, the storage controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the components of the storage controller 210 can also be regarded as operations performed by the storage controller 210.

其中，資料管理電路212耦接至處理器211、記憶體介面控制電路213與連接介面電路230。資料管理電路212用以接受處理器211的指示來進行資料的傳輸。例如，經由連接介面電路230從主機系統10(如，主機記憶體120)讀取資料，並且將所讀取的資料經由記憶體介面控制電路213寫入至可複寫式非揮發性記憶體模組220中（如，根據來自主機系統10的寫入指令來進行寫入操作）。又例如，經由記憶體介面控制電路213從可複寫式非揮發性記憶體模組220的一或多個實體單元中讀取資料(資料可讀取自一或多個實體單元中的一或多個記憶胞)，並且將所讀取的資料經由連接介面電路230寫入至主機系統10(如，主機記憶體120)中（如，根據來自主機系統10的讀取指令來進行讀取操作）。在另一實施例中，資料管理電路212亦可整合至處理器211中。The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used for receiving instructions from the processor 211 to transmit data. For example, read data from the host system 10 (eg, the host memory 120) via the connection interface circuit 230, and write the read data to the rewritable non-volatile memory module via the memory interface control circuit 213 220 (for example, a write operation is performed according to a write instruction from the host system 10). For another example, data can be read from one or more physical units of the rewritable non-volatile memory module 220 through the memory interface control circuit 213 (data can be read from one or more of the one or more physical units). Memory cells), and write the read data to the host system 10 (for example, the host memory 120) via the connection interface circuit 230 (for example, perform a read operation according to a read command from the host system 10) . In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

記憶體介面控制電路213用以接受處理器211的指示，配合資料管理電路212來進行對於可複寫式非揮發性記憶體模組220的寫入(亦稱，程式化，Programming)操作、讀取操作或抹除操作。The memory interface control circuit 213 is used to receive instructions from the processor 211, and cooperate with the data management circuit 212 to perform writing (also known as programming) operations and reading to the rewritable non-volatile memory module 220 Operate or erase operation.

舉例來說，處理器211可執行寫入指令序列，以指示記憶體介面控制電路213將資料寫入至可複寫式非揮發性記憶體模組220中；處理器211可執行讀取指令序列，以指示記憶體介面控制電路213從可複寫式非揮發性記憶體模組220的對應讀取指令的一或多個實體單元（亦稱，目標實體單元）中讀取資料；處理器211可執行抹除指令序列，以指示記憶體介面控制電路213對可複寫式非揮發性記憶體模組220進行抹除操作。寫入指令序列、讀取指令序列及抹除指令序列可各別包括一或多個程式碼或指令碼並且用以指示對可複寫式非揮發性記憶體模組220執行相對應的寫入、讀取及抹除等操作。在一實施例中，處理器211還可以下達其他類型的指令序列給記憶體介面控制電路213，以對可複寫式非揮發性記憶體模組220執行相對應的操作。For example, the processor 211 can execute a write instruction sequence to instruct the memory interface control circuit 213 to write data into the rewritable non-volatile memory module 220; the processor 211 can execute a read instruction sequence, To instruct the memory interface control circuit 213 to read data from one or more physical units (also known as target physical units) corresponding to the read instructions of the rewritable non-volatile memory module 220; the processor 211 can execute The erase command sequence instructs the memory interface control circuit 213 to perform an erase operation on the rewritable non-volatile memory module 220. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct to perform corresponding writing, writing, and writing to the rewritable non-volatile memory module 220. Read and erase operations. In one embodiment, the processor 211 may also send other types of instruction sequences to the memory interface control circuit 213 to perform corresponding operations on the rewritable non-volatile memory module 220.

此外，欲寫入至可複寫式非揮發性記憶體模組220的資料會經由記憶體介面控制電路213轉換為可複寫式非揮發性記憶體模組220所能接受的格式。具體來說，若處理器211要存取可複寫式非揮發性記憶體模組220，處理器211會傳送對應的指令序列給記憶體介面控制電路213以指示記憶體介面控制電路213執行對應的操作。例如，這些指令序列可包括指示寫入資料的寫入指令序列、指示讀取資料的讀取指令序列、指示抹除資料的抹除指令序列、以及用以指示各種記憶體操作(例如，改變預設讀取電壓組的多個預設讀取電壓值以進行讀取操作或讀取輔助操作，或執行垃圾回收程序等等)的相對應的指令序列。這些指令序列可包括一或多個訊號，或是在匯流排上的資料。這些訊號或資料可包括指令碼或程式碼。例如，在讀取指令序列中，會包括讀取的辨識碼、記憶體位址等資訊。In addition, the data to be written into the rewritable non-volatile memory module 220 is converted into a format acceptable by the rewritable non-volatile memory module 220 through the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will send a corresponding command sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to execute the corresponding operating. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and various memory operations (for example, changing presets). It is assumed that a plurality of preset read voltage values of the read voltage group are used to perform a read operation or read auxiliary operation, or execute a garbage collection program, etc.). These command sequences can include one or more signals, or data on the bus. These signals or data may include script or program code. For example, in the read command sequence, information such as the read identification code and memory address will be included.

可複寫式非揮發性記憶體模組220是耦接至儲存控制器210（記憶體介面控制電路213）並且用以儲存主機系統10所寫入之資料。可複寫式非揮發性記憶體模組220可以是單階記憶胞(Single Level Cell，SLC)NAND型快閃記憶體模組(即，一個記憶胞中可儲存1個位元的快閃記憶體模組)、多階記憶胞(Multi Level Cell，MLC)NAND型快閃記憶體模組(即，一個記憶胞中可儲存2個位元的快閃記憶體模組)、三階記憶胞(Triple Level Cell，TLC)NAND型快閃記憶體模組(即，一個記憶胞中可儲存3個位元的快閃記憶體模組)、四階記憶胞(Quadruple Level Cell，QLC)NAND型快閃記憶體模組(即，一個記憶胞中可儲存4個位元的快閃記憶體模組)、三維NAND型快閃記憶體模組（3D NAND flash memory module）或垂直NAND型快閃記憶體模組（Vertical NAND flash memory module）等其他快閃記憶體模組或其他具有相同特性的記憶體模組。可複寫式非揮發性記憶體模組220中的記憶胞是以陣列的方式設置。The rewritable non-volatile memory module 220 is coupled to the storage controller 210 (the memory interface control circuit 213) and is used to store data written by the host system 10. The rewritable non-volatile memory module 220 can be a single level cell (SLC) NAND flash memory module (that is, a flash memory that can store 1 bit in a memory cell). Module), Multi Level Cell (MLC) NAND flash memory module (that is, a flash memory module that can store 2 bits in a memory cell), Three-level memory cell ( Triple Level Cell (TLC) NAND flash memory modules (that is, a flash memory module that can store 3 bits in a memory cell), Quadruple Level Cell (QLC) NAND flash memory modules Flash memory module (ie, a flash memory module that can store 4 bits in a memory cell), 3D NAND flash memory module or vertical NAND flash memory Other flash memory modules such as Vertical NAND flash memory module or other memory modules with the same characteristics. The memory cells in the rewritable non-volatile memory module 220 are arranged in an array.

在本實施例中，可複寫式非揮發性記憶體模組220具有多個字元線，其中所述多個字元線的每一個字元線耦接至多個記憶胞。同一條字元線上的多個記憶胞會組成一或多個實體程式化單元。此外，多個實體程式化單元可組成一個實體單元（實體區塊或實體抹除單元）。In this embodiment, the rewritable non-volatile memory module 220 has a plurality of character lines, and each of the plurality of character lines is coupled to a plurality of memory cells. Multiple memory cells on the same character line form one or more physical programming units. In addition, multiple physical programming units can form a physical unit (physical block or physical erase unit).

在本實施例中，是以記憶胞作為寫入(程式化)資料的最小單位。實體單元為抹除之最小單位，即，每一實體單元含有最小數目之一併被抹除之記憶胞。In this embodiment, the memory cell is used as the smallest unit for writing (programming) data. The physical unit is the smallest unit of erasure, that is, each physical unit contains one of the smallest number of memory cells that are erased.

儲存控制器210會配置多個邏輯單元給可複寫式非揮發性記憶體模組220。主機系統10是透過所配置的邏輯單元來存取儲存在多個實體單元中的使用者資料。在此，每一個邏輯單元可以是由一或多個邏輯位址組成。例如，邏輯單元可以是邏輯區塊(Logical Block)、邏輯頁面(Logical Page)或是邏輯扇區(Logical Sector)。一個邏輯單元可以是映射至一或多個實體單元，其中實體單元可以是一或多個實體位址、一或多個實體扇、一或多個實體程式化單元或者一或多個實體抹除單元。在本實施例中，邏輯單元為邏輯區塊，並且邏輯子單元為邏輯頁面。每一邏輯單元具有多個邏輯子單元。The storage controller 210 allocates a plurality of logic units to the rewritable non-volatile memory module 220. The host system 10 accesses user data stored in multiple physical units through configured logical units. Here, each logical unit can be composed of one or more logical addresses. For example, the logical unit may be a logical block (Logical Block), a logical page (Logical Page) or a logical sector (Logical Sector). A logical unit can be mapped to one or more physical units, where the physical unit can be one or more physical addresses, one or more physical sectors, one or more physical programming units, or one or more physical erasures unit. In this embodiment, the logical unit is a logical block, and the logical sub-unit is a logical page. Each logic unit has multiple logic sub-units.

此外，儲存控制器210會建立邏輯轉實體位址映射表(Logical To Physical address mapping table)與實體轉邏輯位址映射表(Physical To Logical address mapping table)，以記錄配置給可複寫式非揮發性記憶體模組220的邏輯單元(如，邏輯區塊、邏輯頁面或邏輯扇區)與實體單元(如，實體抹除單元、實體程式化單元、實體扇區)之間的位址映射關係。換言之，儲存控制器210可藉由邏輯轉實體位址映射表來查找一邏輯單元所映射的實體單元，並且儲存控制器210可藉由實體轉邏輯位址映射表來查找一實體單元所映射的邏輯單元。然而，上述有關邏輯單元與實體單元映射的技術概念為本領域技術人員之慣用技術手段且非本發明所欲闡述的技術方案，不再贅述於此。In addition, the storage controller 210 creates a logical to physical address mapping table (Logical To Physical address mapping table) and a physical to logical address mapping table (Physical To Logical address mapping table) to record the configuration to the rewritable non-volatile The address mapping relationship between logical units (eg, logical blocks, logical pages, or logical sectors) of the memory module 220 and physical units (eg, physical erase units, physical programming units, and physical sectors). In other words, the storage controller 210 can use the logical-to-physical address mapping table to find the physical unit to which a logical unit is mapped, and the storage controller 210 can use the physical-to-logical address mapping table to find the physical unit to which a physical unit is mapped. Logical unit. However, the above-mentioned technical concepts related to the mapping between logical units and physical units are conventional technical means by those skilled in the art and are not technical solutions intended to be described in the present invention, and will not be repeated here.

在本實施例中，錯誤檢查與校正電路214是耦接至處理器211並且用以執行錯誤檢查與校正程序以確保資料的正確性。具體來說，當處理器211從主機系統10中接收到寫入指令時，錯誤檢查與校正電路214會為對應此寫入指令的資料產生對應的錯誤更正碼(error correcting code，ECC)及/或錯誤檢查碼(error detecting code，EDC)，並且處理器211會將對應此寫入指令的資料與對應的錯誤更正碼及/或錯誤檢查碼寫入至可複寫式非揮發性記憶體模組220中。之後，當處理器211從可複寫式非揮發性記憶體模組220中讀取資料時會同時讀取此資料對應的錯誤更正碼及/或錯誤檢查碼，並且錯誤檢查與校正電路214會依據此錯誤更正碼及/或錯誤檢查碼對所讀取的資料執行錯誤檢查與校正程序。此外，在錯誤檢查與校正程序後，若成功解碼所讀取之資料，錯誤檢查與校正電路214可回傳錯誤位元數給處理器211。In this embodiment, the error checking and correcting circuit 214 is coupled to the processor 211 and used to perform error checking and correcting procedures to ensure the correctness of the data. Specifically, when the processor 211 receives a write command from the host system 10, the error checking and correction circuit 214 will generate a corresponding error correcting code (ECC) and/or for the data corresponding to the write command. Or error detecting code (EDC), and the processor 211 will write the data corresponding to the write command and the corresponding error correction code and/or error check code to the rewritable non-volatile memory module 220 in. After that, when the processor 211 reads data from the rewritable non-volatile memory module 220, it will also read the error correction code and/or error check code corresponding to the data, and the error check and correction circuit 214 will follow This error correction code and/or error check code performs error checking and correction procedures on the read data. In addition, after the error checking and correction process, if the read data is successfully decoded, the error checking and correction circuit 214 can return the number of error bits to the processor 211.

在本實施例中，在接收到欲解碼之所述碼字（亦稱，目標碼字或原始碼字）之後，錯誤檢查與校正電路214會開始對所接收的所述碼字進行迭代解碼操作，辨識所接收碼字的多個資料位元，根據所述多個資料位元來查詢對應的對數似然比（Log Likelihood Ratio，LLR）表（亦稱，LLR表）以獲得對應多個資料位元的多個對數似然比值，並且經由所述對數似然比值來對所述碼字執行一輪的迭代解碼操作。In this embodiment, after receiving the codeword to be decoded (also known as the target codeword or the original codeword), the error checking and correction circuit 214 will start to perform an iterative decoding operation on the received codeword , Recognize multiple data bits of the received codeword, and query the corresponding Log Likelihood Ratio (LLR) table (also known as LLR table) according to the multiple data bits to obtain corresponding multiple data A plurality of log-likelihood ratios of bits, and a round of iterative decoding operation is performed on the codeword via the log-likelihood ratio.

圖1B是根據本發明的一實施例所繪示的錯誤檢查與校正電路的方塊示意圖。請參照圖1B，在本實施例中，錯誤檢查與校正電路214包括解碼器與編碼器。解碼器包括第一解碼器2141與第二解碼器2142。編碼器包括第一編碼器2143與第二編碼器2144。所述第一解碼器2141所使用的第一演算法對應於第一編碼器2143所使用的第一演算法，並且所述第二解碼器2142所使用的第二演算法對應於第二編碼器2144所使用的第二演算法。FIG. 1B is a block diagram of an error checking and correction circuit according to an embodiment of the invention. Please refer to FIG. 1B. In this embodiment, the error checking and correction circuit 214 includes a decoder and an encoder. The decoder includes a first decoder 2141 and a second decoder 2142. The encoder includes a first encoder 2143 and a second encoder 2144. The first algorithm used by the first decoder 2141 corresponds to the first algorithm used by the first encoder 2143, and the second algorithm used by the second decoder 2142 corresponds to the second encoder The second algorithm used by 2144.

所述第一演算法例如是位元翻轉(bit flipping)演算法；所述第二演算法例如是最小值-總和演算法(Min-Sum Algorithm)。即，所述第一解碼器為使用位元翻轉演算法的位元翻轉解碼器，並且所述第二解碼器為使用最小值-總和演算法的最小值-總和解碼器外，第二解碼器2142的解碼能力與耗能皆大於第一解碼器2141。The first algorithm is, for example, a bit flipping algorithm; the second algorithm is, for example, a Min-Sum Algorithm. That is, the first decoder is a bit-reversal decoder that uses a bit-reversal algorithm, and the second decoder is a minimum-sum decoder that uses a minimum-sum algorithm. The second decoder The decoding capability and energy consumption of the 2142 are both greater than that of the first decoder 2141.

應注意的是，第一解碼器2141或第二解碼器2142所使用演算法也可以為總和-乘積演算法(Sum-Product Algorithm，SPA)。It should be noted that the algorithm used by the first decoder 2141 or the second decoder 2142 may also be a Sum-Product Algorithm (SPA).

當儲存控制器210從可複寫式非揮發性記憶體模組406中讀取 n個資料位元(形成一個碼字)時，儲存控制器210（或錯誤檢查與校正電路214）也會取得每一個資料位元的通道可靠度資訊。此通道可靠度資訊用以表示對應的資料位元被解碼為位元“1”（亦稱，第一位元值）或是“0”（亦稱，第二位元值）的機率(或稱信心度)。錯誤檢查與校正電路214會通道可靠度資訊來執行解碼操作。在本實施例中，錯誤檢查與校正電路214所執行的解碼操作為迭代解碼(iterative decoding)操作。 When the storage controller 210 reads n data bits (to form a code word) from the rewritable non-volatile memory module 406, the storage controller 210 (or the error checking and correction circuit 214) also obtains each Channel reliability information for one data bit. This channel reliability information is used to indicate the probability that the corresponding data bit is decoded as bit "1" (also known as the first bit value) or "0" (also known as the second bit value) (or Called confidence). The error checking and correction circuit 214 channels the reliability information to perform the decoding operation. In this embodiment, the decoding operation performed by the error checking and correction circuit 214 is an iterative decoding operation.

在本實施例中，可靠度資訊皆是以對數似然比值(Log Likelihood Ratio，LLR)來表示。然而，當採用不同的演算法來進行迭代解碼操作時，儲存控制器210會先產生相應的不同的可靠度資訊表（亦稱，對數似然比值表），以供不同的解碼器來使用/查找。In this embodiment, the reliability information is represented by the Log Likelihood Ratio (LLR). However, when different algorithms are used for iterative decoding operations, the storage controller 210 will first generate corresponding different reliability information tables (also known as log-likelihood ratio tables) for use by different decoders/ Find.

在本實施例中，每當錯誤檢查與校正電路214完成對一筆所述碼字所執行的一輪迭代解碼操作，錯誤檢查與校正電路214可獲得對應所述碼字的已解碼碼字與對應所述已解碼碼字的校驗子。錯誤檢查與校正電路214可根據校驗子來判斷當下所執行的所述迭代解碼操作是解碼成功或解碼失敗。In this embodiment, each time the error checking and correction circuit 214 completes a round of iterative decoding operations performed on a block of the codeword, the error checking and correction circuit 214 can obtain the decoded codeword corresponding to the codeword and the corresponding codeword. Describe the syndrome of the decoded codeword. The error checking and correction circuit 214 can determine whether the iterative decoding operation currently performed is successful or failed according to the syndrome.

若解碼失敗，錯誤檢查與校正電路214可根據所統計的對所述碼字所執行的迭代解碼操作的總次數與預設迭代次數門檻值來判斷是否需再次執行後續的一或多次的迭代操作。若所述總次數達到所述預設迭代次數門檻值，錯誤檢查與校正電路214會判定所述碼字的整體解碼操作（整體解碼操作可包括一或多個迭代解碼操作）是失敗的，並且輸出最後所獲得之已解碼碼字與對應的校驗子（如，反應於所述總次數達到所述預設迭代次數門檻值且最後獲得的校驗子不為零）；若所述總次數不大於所述預設迭代次數門檻值，錯誤檢查與校正電路214會利用所獲得之已解碼碼字與對應的校驗子來再次執行新一輪的迭代解碼操作。廠商可根據需求自行設定預設迭代次數門檻值，本發明不限於此。If the decoding fails, the error checking and correction circuit 214 can determine whether to perform one or more subsequent iterations again according to the total number of iterative decoding operations performed on the codeword and the preset iteration number threshold. operating. If the total number of times reaches the threshold of the preset number of iterations, the error checking and correction circuit 214 will determine that the overall decoding operation of the codeword (the overall decoding operation may include one or more iterative decoding operations) is failed, and Output the decoded codeword and the corresponding syndrome finally obtained (for example, reflecting that the total number of times reaches the threshold of the preset number of iterations and the syndrome finally obtained is not zero); if the total number of times If the number of iterations is not greater than the preset threshold, the error checking and correction circuit 214 will use the obtained decoded codeword and the corresponding syndrome to perform a new round of iterative decoding operation again. The manufacturer can set the threshold value of the preset number of iterations according to requirements, and the present invention is not limited to this.

在每一次（每一輪）的迭代解碼操作的最後，錯誤檢查與校正電路214會計算對應當前最新獲得之已解碼碼字的校驗子，以判斷此次的迭代解碼操作是否成功。若解碼成功（解碼後所產生的碼字為正確，即，有效碼字），則結束本次的迭代操作並且也結束對此碼字的整體解碼操作；若解碼失敗（解碼後所產生的碼字為錯誤，即，無效碼字），則在所述總次數不大於所述預設迭代次數門檻值的情況下，結束本次的迭代操作並且重新開始新的一次（下一輪）的迭代操作。At the end of each iteration (each round) of the iterative decoding operation, the error checking and correction circuit 214 calculates the syndrome corresponding to the decoded codeword that is currently obtained newly to determine whether the iterative decoding operation is successful. If the decoding is successful (the codeword generated after decoding is correct, that is, the valid codeword), the iterative operation is ended and the overall decoding operation for this codeword is also ended; if the decoding fails (the code generated after decoding is If the word is an error, that is, an invalid code word), if the total number of times is not greater than the preset iteration number threshold, the current iteration operation is ended and a new (next round) iteration operation is restarted .

更詳細來說，於每次迭代解碼操作中，錯誤檢查與校正電路214會判斷對應所述已解碼碼字的校驗子的多個位元值是否皆為零。若所述校驗子的多個位元值皆為零（即，“0”），錯誤檢查與校正電路214判定所述已解碼碼字為正確的，完成本次的迭代解碼操作，並且完成對應所述碼字的整體解碼操作。反之，若所述校驗子的所述多個位元值不皆為零（即，具有一或多個“1”），錯誤檢查與校正電路214判定所述已解碼碼字為錯誤的，完成本次的迭代解碼操作，完成所述碼字的整體解碼操作，並且輸出所述已解碼碼字。多個校驗子之間的大小比較，可利用所述多個校驗子所具有的“1”的總數量來判斷。例如，具有4個“1”的校驗子大於具有1個“1”的校驗子。In more detail, in each iterative decoding operation, the error checking and correction circuit 214 determines whether the multiple bit values of the syndrome corresponding to the decoded codeword are all zero. If the multiple bit values of the syndrome are all zero (ie, "0"), the error checking and correction circuit 214 determines that the decoded codeword is correct, completes this iterative decoding operation, and completes Corresponding to the overall decoding operation of the codeword. Conversely, if the multiple bit values of the syndrome are not all zero (ie, have one or more "1"s), the error checking and correction circuit 214 determines that the decoded codeword is wrong, Complete this iterative decoding operation, complete the overall decoding operation of the codeword, and output the decoded codeword. The size comparison between multiple syndromes can be judged by using the total number of "1"s of the multiple syndromes. For example, a syndrome with 4 "1"s is greater than a syndrome with 1 "1".

應注意的是，上述的說明僅用於解釋原始碼字、已解碼碼字與對應的校驗子的對應關係，其他關於低密度奇偶檢查碼演算法的迭代解碼操作、原始碼字、校驗子、已解碼碼字的細節並非本發明的技術方案，不贅述於此。It should be noted that the above description is only used to explain the correspondence between the original codeword, the decoded codeword and the corresponding syndrome, and other iterative decoding operations, the original codeword, and the checksum of the low-density parity check code algorithm. The details of the sub and decoded codewords are not technical solutions of the present invention and will not be repeated here.

在一實施例中，儲存控制器210還包括緩衝記憶體218與電源管理電路219。緩衝記憶體是耦接至處理器211並且用以暫存來自於主機系統10的資料與指令、來自於可複寫式非揮發性記憶體模組220的資料或其他用以管理儲存裝置20的系統資料（如，對數似然比表或軟資訊），以讓處理器211可快速地從緩衝記憶體218中存取所述資料、指令或系統資料。電源管理電路219是耦接至處理器211並且用以控制儲存裝置20的電源。In one embodiment, the storage controller 210 further includes a buffer memory 218 and a power management circuit 219. The buffer memory is coupled to the processor 211 and used to temporarily store data and commands from the host system 10, data from the rewritable non-volatile memory module 220, or other systems for managing the storage device 20 Data (such as a log-likelihood ratio table or soft information) so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 218. The power management circuit 219 is coupled to the processor 211 and used to control the power of the storage device 20.

在本實施例中，讀取輔助電路單元215包括解碼器管理電路2151與對數似然比表管理電路2152（亦稱，LLR表管理電路）。在處理器211執行讀取操作時，處理器211可指示所述讀取輔助電路單元215對所讀取的相應於所述讀取操作的原始碼字來執行讀取輔助操作，以輔助錯誤檢查與校正電路214對於所述原始碼字所進行的解碼操作。In this embodiment, the reading auxiliary circuit unit 215 includes a decoder management circuit 2151 and a log-likelihood ratio table management circuit 2152 (also known as an LLR table management circuit). When the processor 211 performs a read operation, the processor 211 may instruct the read auxiliary circuit unit 215 to perform a read auxiliary operation on the read original codeword corresponding to the read operation to assist in error checking The decoding operation performed by the AND correction circuit 214 on the original codeword.

更具體來說，在本實施例中，解碼器管理電路2151用以指示錯誤檢查與校正電路214去使用第一解碼器2141或第二解碼器2142來執行解碼操作。LLR表管理電路2152用以管理/記錄/查找所產生的對數似然比表。此外，解碼器管理電路2151與LLR表管理電路2152亦可整合在一起，並且解碼器管理電路2151或LLR表管理電路2152更可用以產生軟資訊及暫存所產生的軟資訊。所述軟資訊被輸入至第一解碼器2141或第二解碼器2142，以配合相應的對數似然比表來進行相應的解碼操作。以下利用圖2來說明本發明所提供的資料讀取方法（亦稱，讀取輔助方法）的細節及讀取輔助電路單元215的功能。應注意的是，讀取輔助電路單元215的各元件的運作可被視為讀取輔助電路單元215整體的運作。More specifically, in this embodiment, the decoder management circuit 2151 is used to instruct the error checking and correction circuit 214 to use the first decoder 2141 or the second decoder 2142 to perform the decoding operation. The LLR table management circuit 2152 is used to manage/record/look up the generated log-likelihood ratio table. In addition, the decoder management circuit 2151 and the LLR table management circuit 2152 can also be integrated, and the decoder management circuit 2151 or the LLR table management circuit 2152 can be used to generate soft information and temporarily store the generated soft information. The soft information is input to the first decoder 2141 or the second decoder 2142 to cooperate with the corresponding log-likelihood ratio table to perform the corresponding decoding operation. The following uses FIG. 2 to illustrate the details of the data reading method (also known as the reading auxiliary method) provided by the present invention and the function of the reading auxiliary circuit unit 215. It should be noted that the operation of each element of the reading auxiliary circuit unit 215 can be regarded as the overall operation of the reading auxiliary circuit unit 215.

圖2是根據本發明的一實施例所繪示的資料讀取方法的流程圖。請參照圖2，在步驟S210中，處理器211指示記憶體介面控制電路213對所述多個實體頁面中的目標實體頁面所儲存的目標碼字執行讀取操作，以獲得原始碼字（也稱，硬位元碼字）。所述原始碼字會被傳送至錯誤檢查與校正電路214，以進行解碼操作。在本實施例中，所述原始碼字會先被傳送至具有較低耗能的第一解碼器，以進行多個第一迭代解碼操作。FIG. 2 is a flowchart of a data reading method according to an embodiment of the invention. Referring to FIG. 2, in step S210, the processor 211 instructs the memory interface control circuit 213 to perform a read operation on the target codeword stored in the target physical page of the plurality of physical pages to obtain the original codeword (also Said, hard bit code word). The original codeword is sent to the error checking and correction circuit 214 for decoding operation. In this embodiment, the original codeword is first transmitted to a first decoder with lower energy consumption to perform multiple first iterative decoding operations.

如，在步驟S220，讀取輔助電路單元215（或解碼器管理電路2151）指示第一解碼器2141，對所述原始碼字執行X個第一迭代解碼操作，以獲得分別對應所述X個第一迭代解碼操作的X個第一已解碼碼字與對應所述X個第一已解碼碼字的X個第一校驗子。所述X為大於1的正整數，並且小於預設迭代次數門檻值。應注意的是，在一實施例中，於執行步驟S220的過程中，反應於獲得了正確的第一已解碼碼字（對應的第一校驗子為0），第一解碼器2141會直接輸出所述已解碼碼字，以完成所述讀取操作，並且讀取輔助電路單元215不再執行後續步驟（如，步驟S230～S260）。For example, in step S220, the reading auxiliary circuit unit 215 (or the decoder management circuit 2151) instructs the first decoder 2141 to perform X first iterative decoding operations on the original codewords to obtain the corresponding X The X first decoded codewords of the first iterative decoding operation and the X first syndromes corresponding to the X first decoded codewords. The X is a positive integer greater than 1, and less than the threshold of the preset number of iterations. It should be noted that, in one embodiment, in the process of performing step S220, in response to obtaining the correct first decoded codeword (the corresponding first syndrome is 0), the first decoder 2141 will directly The decoded codeword is output to complete the reading operation, and the reading auxiliary circuit unit 215 does not perform subsequent steps (eg, steps S230 to S260).

接著，在步驟S230中，讀取輔助電路單元215（或解碼器管理電路2151）根據所述X個第一迭代解碼操作來判斷是否經由所述第一解碼器執行多個第二迭代解碼操作。Next, in step S230, the read auxiliary circuit unit 215 (or the decoder management circuit 2151) determines whether to perform multiple second iterative decoding operations via the first decoder according to the X first iterative decoding operations.

具體來說，讀取輔助電路單元215（或解碼器管理電路2151）可根據多個判斷方法中的其中之一來判斷使用第一解碼器2141以執行多個第二迭代解碼操作或使用第二解碼器2142以執行多個第三迭代解碼操作。Specifically, the reading auxiliary circuit unit 215 (or the decoder management circuit 2151) can determine whether to use the first decoder 2141 to perform multiple second iterative decoding operations or to use the second decoder according to one of multiple judgment methods. The decoder 2142 performs multiple third iterative decoding operations.

在本實施例中，所述多個判斷方法包括：(1)根據對應X個第一迭代解碼操作中的X個第一校驗子與校驗子門檻值來進行判斷；(2) 判斷對應X個第一迭代解碼操作中的X個第一校驗子是否收斂；(3)根據多個第一迭代解碼操作各自的翻轉位元總數量與翻轉位元總數量門檻值來進行判斷。In this embodiment, the multiple judgment methods include: (1) judging according to X first syndromes and syndrome thresholds corresponding to X first iterative decoding operations; (2) judging corresponding Whether the X first syndromes in the X first iterative decoding operations converge; (3) The judgment is made according to the total number of flipped bits and the threshold value of the total number of flipped bits of the multiple first iterative decoding operations.

例如，在所述判斷方法(1)中：反應於判定所述X個第一校驗子中的目標校驗子的大小大於校驗子門檻值，讀取輔助電路單元215（或解碼器管理電路2151）判定使用第二解碼器2142以執行多個第三迭代解碼操作；反應於判定所述X個第一校驗子中的目標校驗子的大小不大於校驗子門檻值，讀取輔助電路單元215（或解碼器管理電路2151）判定使用第一解碼器2141以執行多個第二迭代解碼操作。所述目標校驗子可為所述X個第一校驗子中的第一個所獲得的第一校驗子、最終所獲得的第一校驗子或所述多個第一校驗子的平均值。For example, in the judgment method (1): in response to judging that the size of the target syndrome in the X first syndromes is greater than the syndrome threshold, the read auxiliary circuit unit 215 (or decoder management Circuit 2151) determines to use the second decoder 2142 to perform multiple third iterative decoding operations; in response to determining that the size of the target syndrome among the X first syndromes is not greater than the syndrome threshold, read The auxiliary circuit unit 215 (or the decoder management circuit 2151) decides to use the first decoder 2141 to perform multiple second iterative decoding operations. The target syndrome may be the first syndrome obtained by the first one of the X first syndromes, the first syndrome obtained finally, or the multiple first syndromes average value.

又例如，在所述判斷方法(2)中：反應於判定所述X個第一校驗子的大小皆在校驗子範圍內，讀取輔助電路單元215（或解碼器管理電路2151）判定所述X個第一校驗子不收斂，並且使用第二解碼器2142以執行多個第三迭代解碼操作；反應於判定所述X個第一校驗子的其中之一小於所述校驗子範圍，讀取輔助電路單元215（或解碼器管理電路2151）判定所述X個第一校驗子收斂，並且使用第一解碼器2141以執行多個第二迭代解碼操作。For another example, in the judgment method (2): in response to judging that the sizes of the X first syndromes are all within the syndrome range, the reading auxiliary circuit unit 215 (or the decoder management circuit 2151) judges The X first syndromes do not converge, and the second decoder 2142 is used to perform multiple third iterative decoding operations; it is reflected in determining that one of the X first syndromes is smaller than the check In the sub-range, the reading auxiliary circuit unit 215 (or the decoder management circuit 2151) determines that the X first syndromes converge, and uses the first decoder 2141 to perform multiple second iterative decoding operations.

又例如，在所述判斷方法(3)中：反應於判定對應於所述X個第一迭代解碼操作中的X個翻轉位元總數量的其中之一大於所述翻轉位元總數量門檻值，讀取輔助電路單元215（或解碼器管理電路2151）判定使用第二解碼器2142以執行多個第三迭代解碼操作；反應於判定對應於所述X個第一迭代解碼操作中的多個翻轉位元總數量皆不大於所述翻轉位元總數量門檻值，讀取輔助電路單元215（或解碼器管理電路2151）判定使用第一解碼器2141以執行多個第二迭代解碼操作。其中，對應於一個第一迭代解碼操作中的翻轉位元總數量用以表示在所述第一迭代解碼操作中，第一已解碼碼字中的被判定需執行翻轉（“0”翻轉為“1”或“1”翻轉為“0”）的位元值的總數量。此外，在一實施例中，讀取輔助電路單元215（或解碼器管理電路2151）更可計算所述X個翻轉位元總數量的總和。並且，反應於判定所述總和大於一特定門檻值，讀取輔助電路單元215（或解碼器管理電路2151）可判定使用第二解碼器2142以執行多個第三迭代解碼操作。For another example, in the judgment method (3): it is reflected that one of the total numbers of X flipped bits in the X first iterative decoding operations is determined to be greater than the threshold value of the total number of flipped bits , The reading auxiliary circuit unit 215 (or the decoder management circuit 2151) decides to use the second decoder 2142 to perform multiple third iterative decoding operations; in response to the decision that it corresponds to multiple of the X first iterative decoding operations The total number of flipped bits is not greater than the threshold value of the total number of flipped bits, and the read auxiliary circuit unit 215 (or the decoder management circuit 2151) determines to use the first decoder 2141 to perform multiple second iterative decoding operations. Wherein, the total number of flipped bits corresponding to a first iterative decoding operation is used to indicate that in the first iterative decoding operation, it is determined that the first decoded codeword needs to be flipped ("0" flipped to " The total number of bit values of 1" or "1" flipped to "0"). In addition, in an embodiment, the read auxiliary circuit unit 215 (or the decoder management circuit 2151) may further calculate the sum of the total number of the X flipped bits. And, in response to determining that the sum is greater than a specific threshold value, the read auxiliary circuit unit 215 (or the decoder management circuit 2151) may determine to use the second decoder 2142 to perform multiple third iterative decoding operations.

反應於判定經由第二解碼器執行多個第二迭代解碼操作，執行步驟S240；反應於判定不經由第二解碼器執行多個第二迭代解碼操作，執行步驟S250。In response to determining to perform multiple second iterative decoding operations via the second decoder, step S240 is executed; in response to determining not to perform multiple second iterative decoding operations via the second decoder, step S250 is executed.

在步驟S240中，讀取輔助電路單元215（或LLR表管理電路2152）根據所述X個第一已解碼碼字來產生第一軟位元資訊及對應的對數似然比表，並且指示所述第二解碼器2142，根據所產生的所述第一軟位元資訊及對應的所述對數似然比表來執行多個第二迭代解碼操作，以獲得最終已解碼碼字。In step S240, the reading auxiliary circuit unit 215 (or the LLR table management circuit 2152) generates the first soft bit information and the corresponding log-likelihood ratio table according to the X first decoded codewords, and instructs all The second decoder 2142 performs a plurality of second iterative decoding operations according to the generated first soft bit information and the corresponding log-likelihood ratio table to obtain the final decoded codeword.

具體來說，在根據所述X個第一已解碼碼字來產生對數似然比表的運作中，讀取輔助電路單元215（或LLR表管理電路2152）統計所述X個第一已解碼碼字各自的第一位元值總數量以及第二位元值總數量。接著，讀取輔助電路單元215（或LLR表管理電路2152）根據所述第一位元值總數量、第二位元值總數量、對數似然比上限值以及對數似然比下限值來產生對應的所述對數似然比表。Specifically, in the operation of generating the log-likelihood ratio table according to the X first decoded codewords, the reading auxiliary circuit unit 215 (or the LLR table management circuit 2152) counts the X first decoded codewords The total number of first bit values and the total number of second bit values of each codeword. Next, the reading auxiliary circuit unit 215 (or the LLR table management circuit 2152) according to the total number of first bit values, the total number of second bit values, the upper limit of the log likelihood ratio and the lower limit of the log likelihood ratio To generate the corresponding log-likelihood ratio table.

具體來說，讀取輔助電路單元215（或LLR表管理電路2152）根據所述X個第一校驗子，排序對應的所述X個第一已解碼碼字，以產生一第一軟位元資訊。其中，讀取輔助電路單元215（或解碼器管理電路2151）指示所述第二解碼器2142，根據所述對數似然比表對所述第一軟位元資訊執行所述多個第二迭代解碼操作，以獲得分別對應於所述多個第二迭代解碼操作的多個第二已解碼碼字以及對應所述多個第二已解碼碼字的多個第二校驗子。Specifically, the reading auxiliary circuit unit 215 (or the LLR table management circuit 2152) sorts the corresponding X first decoded codewords according to the X first syndromes to generate a first soft bit Meta information. Wherein, the read auxiliary circuit unit 215 (or decoder management circuit 2151) instructs the second decoder 2142 to perform the multiple second iterations on the first soft bit information according to the log likelihood ratio table A decoding operation to obtain a plurality of second decoded codewords respectively corresponding to the plurality of second iterative decoding operations and a plurality of second syndromes corresponding to the plurality of second decoded codewords.

圖3A為根據本發明的一實施例所繪示的根據多個已解碼碼字產生軟資訊的示意圖。圖4A是根據本發明的一實施例所繪示的產生對數似然比表的示意圖。請先參照圖3A，假設從目標實體頁面300所讀取的原始碼字為 “1 1 1 0 0”，並且X被預先設定為4。在執行步驟S220的過程中，如箭頭A31所示，可依序獲得分別對應4個迭代解碼操作的已解碼碼字311“1 0 1 0 0”、 已解碼碼字312“1 1 0 0 0”、 已解碼碼字313 “1 1 0 1 0”、 已解碼碼字314 “1 1 1 0 0”。讀取輔助電路單元215（或LLR表管理電路2152）可根據所述4個已解碼碼字來直接組成4位元軟位元資訊。所述「4位元」用以表示所述軟位元資訊的每個列由4個位元組成，並且亦可反映出所述軟位元資訊的總行數。3A is a schematic diagram of generating soft information based on multiple decoded codewords according to an embodiment of the present invention. 4A is a schematic diagram of generating a log-likelihood ratio table according to an embodiment of the invention. Please refer to FIG. 3A first, assuming that the original codeword read from the target physical page 300 is "1 1 1 0 0", and X is preset to 4. In the process of performing step S220, as indicated by arrow A31, decoded codewords 311 "1 0 1 0 0" and decoded codewords 312 "1 1 0 0 0" corresponding to 4 iterative decoding operations can be sequentially obtained. ", decoded code word 313 "1 1 0 1 0", decoded code word 314 "1 1 1 0 0". The reading auxiliary circuit unit 215 (or the LLR table management circuit 2152) can directly compose 4-bit soft bit information according to the 4 decoded code words. The "4 bits" is used to indicate that each row of the soft bit information is composed of 4 bits, and can also reflect the total number of rows of the soft bit information.

此外，如箭頭A32所示，讀取輔助電路單元215（或LLR表管理電路2152）可進一步統計所述4位元軟位元資訊中的每一列的第一位元值總數量（如，位元值“1”的總數量）以及第二位元值總數量（如，位元值“0”的總數量）。In addition, as indicated by the arrow A32, the read auxiliary circuit unit 215 (or the LLR table management circuit 2152) can further count the total number of first bit values (eg, bit values) of each column in the 4-bit soft bit information. The total number of meta value "1") and the total number of second bit value (for example, the total number of bit value "0").

在本實施例中，所述讀取輔助電路單元215（或LLR表管理電路2152）根據所述X個第一迭代解碼操作的總數量（或第一軟位元資訊的總行數）、對數似然比上限值以及對數似然比下限值來產生對應的所述對數似然比表。In this embodiment, the read auxiliary circuit unit 215 (or the LLR table management circuit 2152) is based on the total number of the X first iterative decoding operations (or the total number of rows of the first soft bit information), logarithmically similar The upper limit value of the likelihood ratio and the lower limit value of the log likelihood ratio are used to generate the corresponding log likelihood ratio table.

請參照圖4A，假設對數似然比上限值為“+7”、對數似然比下限值為“-7”，並且X為4，即，經由所述X個第一迭代解碼操作可獲得4位元軟位元資訊。由於4位元軟位元資訊的總行數為X，即，4。所述4位元軟位元資訊的每一列的第一位元值的總數量的上限與下限、第一位元值的總數量的上限與下限是對應於X與0。基於此事實，所述讀取輔助電路單元215（或LLR表管理電路2152）可根據所述X個第一迭代解碼操作的總數量（即，所對應的所述4位元軟位元資訊的總行數）、對數似然比上限值為“+7”以及對數似然比下限值為“-7”來產生對應的對數似然比表T600。4A, assuming that the upper limit value of the log likelihood ratio is "+7", the lower limit value of the log likelihood ratio is "-7", and X is 4, that is, through the X first iterative decoding operations, Get 4-bit soft bit information. Since the total number of rows of 4-bit soft bit information is X, that is, 4. The upper limit and lower limit of the total number of first bit values, and the upper limit and lower limit of the total number of first bit values in each row of the 4-bit soft bit information correspond to X and 0. Based on this fact, the read auxiliary circuit unit 215 (or the LLR table management circuit 2152) can be based on the total number of the X first iterative decoding operations (that is, the amount of the corresponding 4-bit soft bit information) The total number of rows), the upper limit of the log likelihood ratio is "+7" and the lower limit of the log likelihood ratio is "-7" to generate the corresponding log likelihood ratio table T600.

在所產生的所述對數似然比表T600中，對數似然比值“-7”用以表示所對應的列的位元值為“1”的機率最高；對數似然比值“+7”用以表示所對應的列的位元值為“0”的機率最高；對數似然比值“0”用以表示所對應的列的位元值為“1”或“0”的機率彼此相等；對數似然比值“-3”用以表示所對應的列的位元值為“1”的機率高於為“0”的機率；對數似然比值“+3”用以表示所對應的列的位元值為“0”的機率高於為“1”的機率。In the generated log-likelihood ratio table T600, the log-likelihood ratio "-7" is used to indicate that the bit value of the corresponding column has the highest probability of being "1"; the log-likelihood ratio "+7" is used The probability that the bit value of the corresponding column is "0" is the highest; the log likelihood ratio "0" is used to indicate that the probability of the bit value of the corresponding column is "1" or "0" is equal to each other; logarithm The likelihood ratio "-3" is used to indicate that the probability of the bit value of the corresponding column is "1" is higher than the probability of being "0"; the log likelihood ratio "+3" is used to indicate the bit of the corresponding column The probability of the meta value being "0" is higher than the probability of being "1".

依此類推，所述讀取輔助電路單元215（或LLR表管理電路2152）可根據所對應的軟位元資訊的總行數、對數似然比上限值以及對數似然比下限值來產生其他的對數似然比表。By analogy, the read auxiliary circuit unit 215 (or LLR table management circuit 2152) can generate the corresponding soft bit information according to the total number of rows, the upper limit of the log likelihood ratio, and the lower limit of the log likelihood ratio. Other log-likelihood ratio tables.

圖4B是根據本發明的一實施例所繪示的產生對數似然比表的示意圖。參照圖4B，假設對數似然比上限值為“+5”、對數似然比下限值為“-5”，並且軟位元資訊的總行數為2（2位元軟位元資訊）。所述讀取輔助電路單元215（或LLR表管理電路2152）可根據所述所對應的所述2位元軟位元資訊的總行數（即，2）、對數似然比上限值為“+5”以及對數似然比下限值為“-5”來產生對應的對數似然比表T610。4B is a schematic diagram of generating a log-likelihood ratio table according to an embodiment of the invention. 4B, suppose that the upper limit value of the log likelihood ratio is "+5", the lower limit value of the log likelihood ratio is "-5", and the total number of rows of soft bit information is 2 (2-bit soft bit information) . The reading auxiliary circuit unit 215 (or the LLR table management circuit 2152) can be based on the total number of rows (ie, 2) of the corresponding 2-bit soft bit information and the upper limit value of the log likelihood ratio " +5" and the lower limit of the log likelihood ratio is "-5" to generate the corresponding log likelihood ratio table T610.

在所產生的所述對數似然比表T610中，對數似然比值“-5”用以表示所對應的列的位元值為“1”的機率最高；對數似然比值“+5”用以表示所對應的列的位元值為“0”的機率最高；對數似然比值“0”用以表示所對應的列的位元值為“1”或“0”的機率彼此相等。In the generated log-likelihood ratio table T610, the log-likelihood ratio "-5" is used to indicate that the bit value of the corresponding column has the highest probability; the log-likelihood ratio "+5" is used The probability that the bit value of the corresponding column is "0" is the highest; the log likelihood ratio "0" is used to indicate that the probability of the bit value of the corresponding column is "1" or "0" is equal to each other.

在獲得所產生的第一軟位元資訊後，所述讀取輔助電路單元215（或LLR表管理電路2152）可統計所述第一軟位元資訊中的每一列的第一位元值總數量以及第二位元值總數量，其中所述第一軟位元資訊中的每一列對應至所述原始碼字的每一個位元值。After obtaining the generated first soft bit information, the read auxiliary circuit unit 215 (or LLR table management circuit 2152) can count the total number of first bit values of each row in the first soft bit information And the total number of second bit values, wherein each row in the first soft bit information corresponds to each bit value of the original codeword.

例如，如圖3A中的箭頭A32所示，圖3A中所產生的4位元軟位元資訊中的每一列的第一位元值與第二位元值的總數量皆可經由所述讀取輔助電路單元215（或LLR表管理電路2152）所統計。For example, as shown by the arrow A32 in FIG. 3A, the total number of the first bit value and the second bit value of each row in the 4-bit soft bit information generated in FIG. 3A can be read through the read Take statistics from the auxiliary circuit unit 215 (or the LLR table management circuit 2152).

接著，所述讀取輔助電路單元215指示所述第二解碼器2142，根據所述第一位元值總數量、所述第二位元值總數量以及所述對數似然比表對所述第一軟位元資訊執行所述多個第二迭代解碼操作，以獲得分別對應於所述多個第二迭代解碼操作的多個第二已解碼碼字以及對應所述多個第二已解碼碼字的多個第二校驗子。Then, the read auxiliary circuit unit 215 instructs the second decoder 2142 to compare the total number of first bit values, the total number of second bit values, and the log-likelihood ratio table. The first soft bit information performs the plurality of second iterative decoding operations to obtain a plurality of second decoded codewords respectively corresponding to the plurality of second iterative decoding operations and corresponding to the plurality of second decoded codes Multiple second syndromes of the codeword.

例如，所述第二解碼器2142可經由圖3A所統計的所述第一位元值總數量、所述第二位元值總數量以及圖4A所產生的對應的所述對數似然比表T600來辨識所述原始碼字的各個位元值為第一位元值與第二位元值的機率（可靠度），藉此來執行所述多個第二迭代解碼操作。For example, the second decoder 2142 may use the total number of first bit values, the total number of second bit values calculated in FIG. 3A, and the corresponding log likelihood ratio table generated in FIG. 4A T600 recognizes the probability (reliability) of the first bit value and the second bit value of each bit value of the original codeword, thereby performing the plurality of second iterative decoding operations.

反應於辨識所述多個第二校驗子中的一最終第二校驗子為零，所述錯誤檢查與校正電路判定所述多個第二已解碼碼字中對應所述最終第二校驗子的所述最終已解碼碼字為正確的。In response to identifying that a final second syndrome of the plurality of second syndromes is zero, the error checking and correction circuit determines that the plurality of second decoded codewords corresponds to the final second syndrome The final decoded codeword of the empirical is correct.

請回到圖2，在步驟S250中，讀取輔助電路單元215（或解碼器管理電路2151）指示所述第一解碼器2141，對所述X個第一已解碼碼字中的目標第一已解碼碼字執行多個第三迭代解碼操作，以獲得最終已解碼碼字。Please return to FIG. 2. In step S250, the read auxiliary circuit unit 215 (or decoder management circuit 2151) instructs the first decoder 2141 to perform the first decoding on the target of the X first decoded codewords. The decoded codeword performs multiple third iterative decoding operations to obtain the final decoded codeword.

具體來說，所述目標第一已解碼碼字的目標第一校驗子為所述X個第一校驗子中的最小者。此外，在讀取輔助電路單元215（或解碼器管理電路2151）指示所述第一解碼器2141，對所述X個第一已解碼碼字中的所述目標第一已解碼碼字執行所述多個第三迭代解碼操作，以獲得所述最終已解碼碼字的運作中，所述第一解碼器2141根據所述目標第一已解碼碼字執行多個第三迭代解碼操作，以獲得分別對應於所述多個第三迭代解碼操作的多個第三已解碼碼字以及對應所述多個第三已解碼碼字的多個第三校驗子。其中，反應於辨識所述多個第三校驗子中的一最終第三校驗子為零，所述第一解碼器判定所述多個第三已解碼碼字中對應所述最終第三校驗子的所述最終已解碼碼字為正確的。Specifically, the target first syndrome of the target first decoded codeword is the smallest one of the X first syndromes. In addition, the reading auxiliary circuit unit 215 (or the decoder management circuit 2151) instructs the first decoder 2141 to perform all operations on the target first decoded codeword among the X first decoded codewords. In the operation of the multiple third iterative decoding operations to obtain the final decoded codeword, the first decoder 2141 performs multiple third iterative decoding operations according to the target first decoded codeword to obtain A plurality of third decoded code words corresponding to the plurality of third iterative decoding operations and a plurality of third syndromes corresponding to the plurality of third decoded code words respectively. Wherein, in response to identifying that a final third syndrome among the plurality of third syndromes is zero, the first decoder determines that the plurality of third decoded codewords corresponds to the final third syndrome The final decoded codeword of the syndrome is correct.

在步驟S260中，反應於判定所述最終已解碼碼字為正確的，錯誤檢查與校正電路214（或解碼器）輸出所述最終已解碼碼字以作為對應於所述讀取操作的讀取資料，並且讀取輔助電路單元215完成所述讀取操作。In step S260, in response to determining that the final decoded codeword is correct, the error checking and correction circuit 214 (or decoder) outputs the final decoded codeword as the reading corresponding to the reading operation Data, and the read auxiliary circuit unit 215 completes the read operation.

另一方面，反應於辨識所述多個第三迭代解碼操作的總數量大於迭代解碼門檻值及所述多個第三校驗子中的最終第三校驗子不為零，所述第一解碼器判定所述多個第三已解碼碼字中對應於所述最終第三校驗子的所述最終已解碼碼字為不正確的On the other hand, in response to identifying that the total number of the plurality of third iterative decoding operations is greater than the iterative decoding threshold and the final third syndrome among the plurality of third syndromes is not zero, the first The decoder determines that the final decoded codeword corresponding to the final third syndrome among the plurality of third decoded codewords is incorrect

反應於判定所述多個第三已解碼碼字中對應於所述最終第三校驗子的所述最終已解碼碼字為不正確的，所述讀取輔助電路單元215可使用下列方法(P1)~(P4)的其中之一來進行後續的處理。In response to determining that the final decoded codeword corresponding to the final third syndrome among the plurality of third decoded codewords is incorrect, the read auxiliary circuit unit 215 can use the following method ( One of P1)~(P4) for subsequent processing.

更詳細來說，在方法(P1)中，所述讀取輔助電路單元215將所述原始碼字輸入至所述第二解碼器2142，以經由所述第二解碼器2142，根據預設的對數似然比表對所述原始碼字執行多個迭代解碼操作（亦稱，第四迭代解碼操作），以獲得分別對應於所述多個第四迭代解碼操作的多個第四已解碼碼字以及對應所述多個第四已解碼碼字的多個第四校驗子。其中，反應於辨識所述多個第四校驗子中的一最終第四校驗子為零，所述第二解碼器判定所述多個第四已解碼碼字中對應所述最終第四校驗子的所述最終已解碼碼字為正確的。在另一實施例中，所述讀取輔助電路單元215將所述所述多個第二已解碼碼字中具有最小的校驗子的目標第二已解碼碼字輸入至所述第二解碼器2142，以經由所述第二解碼器2142，根據預設的對數似然比表對所述目標第二已解碼碼字執行多個迭代解碼操作（亦稱，第四迭代解碼操作），以獲得分別對應於所述多個第四迭代解碼操作的多個第四已解碼碼字以及對應所述多個第四已解碼碼字的多個第四校驗子。In more detail, in the method (P1), the read auxiliary circuit unit 215 inputs the original codeword to the second decoder 2142 to pass through the second decoder 2142 according to a preset The log-likelihood ratio table performs multiple iterative decoding operations (also referred to as fourth iterative decoding operations) on the original codeword to obtain multiple fourth decoded codes corresponding to the multiple fourth iterative decoding operations, respectively Word and a plurality of fourth syndromes corresponding to the plurality of fourth decoded code words. Wherein, in response to identifying that a final fourth syndrome among the plurality of fourth syndromes is zero, the second decoder determines that the plurality of fourth decoded codewords corresponds to the final fourth syndrome The final decoded codeword of the syndrome is correct. In another embodiment, the read assist circuit unit 215 inputs the target second decoded codeword with the smallest syndrome among the plurality of second decoded codewords into the second decoded codeword. The second decoder 2142 is configured to perform multiple iterative decoding operations (also referred to as fourth iterative decoding operations) on the target second decoded codeword according to a preset log-likelihood ratio table via the second decoder 2142, to A plurality of fourth decoded codewords corresponding to the plurality of fourth iterative decoding operations and a plurality of fourth syndromes corresponding to the plurality of fourth decoded codewords are obtained.

此外，在方法（P2）中，所述讀取輔助電路單元215執行所述根據所述X個第一已解碼碼字來產生所述對數似然比表，並且經由所述第二解碼器，根據所產生的所述對數似然比表來執行所述多個第二迭代解碼操作，以獲得所述最終已解碼碼字的步驟，即，執行步驟S240。In addition, in the method (P2), the read auxiliary circuit unit 215 executes the generation of the log-likelihood ratio table according to the X first decoded codewords, and via the second decoder, The step of performing the multiple second iterative decoding operations according to the generated log-likelihood ratio table to obtain the final decoded codeword, that is, step S240 is performed.

在方法（P3）中，所述讀取輔助電路單元215根據所述多個第三校驗子，排序對應的所述多個第三已解碼碼字，以產生第二軟位元資訊。此外，所述讀取輔助電路單元215根據所述第二軟位元資訊的總行數來產生另一對數似然比表。In the method (P3), the read auxiliary circuit unit 215 sorts the corresponding plurality of third decoded codewords according to the plurality of third syndromes to generate second soft bit information. In addition, the reading auxiliary circuit unit 215 generates another log likelihood ratio table according to the total number of rows of the second soft bit information.

接著，所述讀取輔助電路單元215統計所述第二軟位元資訊中的每一列的第一位元值總數量以及第二位元值總數量，並且指示所述第二解碼器2142，根據所述第二軟位元資訊中的每一列的所述第一位元值總數量、所述第二位元值總數量以及所述另一對數似然比表對所述第二軟位元資訊執行多個迭代解碼操作（亦稱，第五迭代解碼操作），以獲得分別對應於所述多個第五迭代解碼操作的多個第五已解碼碼字以及對應所述多個第五已解碼碼字的多個第五校驗子。反應於辨識所述多個第五校驗子中的一最終第五校驗子為零，所述第二解碼器判定所述多個第五已解碼碼字中對應所述最終第五校驗子的所述最終已解碼碼字為正確的。Then, the read auxiliary circuit unit 215 counts the total number of first bit values and the total number of second bit values in each column of the second soft bit information, and instructs the second decoder 2142, According to the total number of first bit values, the total number of second bit values, and the other log-likelihood ratio table in each row of the second soft bit information, the second soft bit Meta information performs multiple iterative decoding operations (also known as fifth iterative decoding operations) to obtain multiple fifth decoded codewords corresponding to the multiple fifth iterative decoding operations and corresponding to the multiple fifth Multiple fifth syndromes of the decoded codeword. In response to identifying that a final fifth syndrome among the plurality of fifth syndromes is zero, the second decoder determines that the plurality of fifth decoded codewords corresponds to the final fifth syndrome The final decoded codeword of the child is correct.

方法（P4）近似於方法（P3），其中不同的地方在於：在方法（P3）中的根據所述多個第三校驗子，排序對應的所述多個第三已解碼碼字，以產生所述第二軟位元資訊的運作中，所述讀取輔助電路單元215從所述多個第三已解碼碼字中，選擇多個目標第三已解碼碼字，其中所述多個第三校驗子中對應所述多個目標第三已解碼碼字的多個目標第三校驗子小於所述多個第三校驗子中的其他的第三校驗子。Method (P4) is similar to method (P3), and the difference lies in: in method (P3), according to the plurality of third syndromes, the corresponding plurality of third decoded codewords are sorted to In the operation of generating the second soft bit information, the read auxiliary circuit unit 215 selects a plurality of target third decoded code words from the plurality of third decoded code words, wherein the plurality of The multiple target third syndromes corresponding to the multiple target third decoded codewords in the third syndrome are smaller than the other third syndromes of the multiple third syndromes.

簡單來說，所述讀取輔助電路單元215根據所述多個第三校驗子的大小，選擇所述多個第三校驗子中較小的多個第三校驗子作為多個目標第三校驗子，並且使用對應的多個目標第三已解碼碼字來產生第二軟位元資訊。即，所述讀取輔助電路單元215依據所述多個目標第三校驗子的大小，由大至小，將所述多個目標第三已解碼碼字排序為所述第二軟位元資訊的多個行，其中所述多個目標第三已解碼碼字的總數量等於所述第二軟位元資訊的所述多個行的總數量（總行數），並且所述總數量是預先設定的。所述讀取輔助電路單元215根據所述多個第三校驗子，排序對應的所述多個第三已解碼碼字，以產生第二軟位元資訊。To put it simply, the read assist circuit unit 215 selects the smaller third syndrome among the plurality of third syndromes as the plurality of targets according to the size of the plurality of third syndromes. The third syndrome, and the corresponding multiple target third decoded codewords are used to generate the second soft bit information. That is, the reading auxiliary circuit unit 215 sorts the plurality of target third decoded codewords into the second soft bit according to the size of the plurality of target third syndromes, from large to small Multiple lines of information, wherein the total number of the multiple target third decoded codewords is equal to the total number of the multiple lines of the second soft bit information (total number of lines), and the total number is predefined configuration. The reading auxiliary circuit unit 215 sorts the corresponding plurality of third decoded codewords according to the plurality of third syndromes to generate second soft bit information.

圖3B為根據本發明的一實施例所繪示的根據多個已解碼碼字及多個校驗子產生軟資訊的示意圖。請參照圖3B，假設從目標實體頁面300所讀取的原始碼字為 “1 1 1 0 0”，所述多個第三迭代解碼操作的總數量為4，並且軟位元資訊的總數量被預先設定為2。如箭頭A33所示，可依序獲得分別對應4個第三迭代解碼操作的第三已解碼碼字321“1 0 1 0 0”、 第三已解碼碼字322“1 1 0 0 0”、 第三已解碼碼字323 “1 1 0 1 0”、 第三已解碼碼字324 “1 1 1 0 0”（共4個第三已解碼碼字）。對應所述多個第三已解碼碼字321、322、323、324的多個第三校驗子的大小（亦稱，校驗子大小）如圖3B所示，分別為“4”、“3”、“2”、“1”。3B is a schematic diagram of generating soft information based on multiple decoded codewords and multiple syndromes according to an embodiment of the present invention. Referring to FIG. 3B, assuming that the original codeword read from the target physical page 300 is "1 1 1 0 0", the total number of the plurality of third iterative decoding operations is 4, and the total number of soft bit information It is preset to 2. As shown by arrow A33, the third decoded codeword 321 "1 0 1 0 0", the third decoded code word 322 "1 1 0 0 0", and the third decoded code word 322 "1 1 0 0 0" corresponding to the 4 third iterative decoding operations can be sequentially obtained. The third decoded code word 323 "1 1 0 1 0", the third decoded code word 324 "1 1 1 0 0" (a total of 4 third decoded code words). The sizes (also known as syndrome sizes) of the multiple third syndromes corresponding to the multiple third decoded codewords 321, 322, 323, and 324 are as shown in FIG. 3B, and are respectively "4" and " 3", "2", "1".

讀取輔助電路單元215（或LLR表管理電路2152）可根據所述多個校驗子大小來排序所述多個第三已解碼碼字，並且從所述多個第三已解碼碼字中選擇2個具有較小校驗子大小的第三已解碼碼字來組成2位元軟位元資訊。The read auxiliary circuit unit 215 (or the LLR table management circuit 2152) may sort the plurality of third decoded codewords according to the plurality of syndrome sizes, and select from the plurality of third decoded codewords Two third decoded codewords with a smaller syndrome size are selected to form 2-bit soft bit information.

此外，如箭頭A34所示，讀取輔助電路單元215可進一步統計所述2位元軟位元資訊中的每一列的第一位元值總數量（如，位元值“1”的總數量）以及第二位元值總數量（如，位元值“0”的總數量）。In addition, as indicated by arrow A34, the read auxiliary circuit unit 215 can further count the total number of first bit values in each column of the 2-bit soft bit information (eg, the total number of bit values "1" ) And the total number of second bit values (for example, the total number of bit values "0").

在本實施例中，如，圖4B所示，所述讀取輔助電路單元215根據所述2位元軟位元資訊的總行數、對數似然比上限值以及對數似然比下限值來產生對應的所述對數似然比表610。In this embodiment, as shown in FIG. 4B, the read auxiliary circuit unit 215 uses the total number of rows, the upper limit of the log likelihood ratio, and the lower limit of the log likelihood ratio of the 2-bit soft bit information. To generate the corresponding log-likelihood ratio table 610.

值得一提的是，在上述的多個實施例中，上述讀取輔助電路單元215是以硬體電路的方式來實施，但本發明不限於此。例如，在一實施例中，讀取輔助電路單元215可以軟體的方式實施為具有讀取輔助電路單元215的功能的讀取輔助程式碼模組。讀取輔助程式碼模組可包括解碼器管理程式碼模組與LLR表管理程式碼模組。所述解碼器管理程式碼模組為具有解碼器管理電路2151的功能的程式碼模組；所述LLR表管理程式碼模組為具有LLR表管理電路2152的功能的程式碼模組。所述處理器211可存取且執行讀取輔助程式碼模組（或解碼器管理程式碼模組與LLR表管理程式碼模組）來實施本發明所提供的資料讀取方法（或讀取輔助方法）。It is worth mentioning that, in the above-mentioned multiple embodiments, the above-mentioned reading auxiliary circuit unit 215 is implemented in a hardware circuit, but the present invention is not limited to this. For example, in one embodiment, the reading auxiliary circuit unit 215 can be implemented in software as a reading auxiliary code module having the function of reading the auxiliary circuit unit 215. The reading auxiliary code module may include a decoder management code module and an LLR table management code module. The decoder management program code module is a program code module with the function of the decoder management circuit 2151; the LLR table management program code module is a program code module with the function of the LLR table management circuit 2152. The processor 211 can access and execute reading auxiliary code modules (or decoder management code modules and LLR table management code modules) to implement the data reading method provided by the present invention (or reading Auxiliary method).

綜上所述，本發明實施例所提供的資料讀取方法、儲存控制器及儲存裝置，可從目標實體頁面讀取原始碼字後，利用經由第一解碼器對所述原始碼字執行多個第一迭代解碼操作所獲得的多個第一已解碼碼字與對應的多個第一校驗子來判斷是否要進一步經由第二解碼器來執行多個第二迭代解碼操作或經由第一解碼器執行多個第三迭代解碼操作，並且反應於判定經由第二解碼器來執行多個第二迭代解碼操作，根據所述多個第一已解碼碼字來產生第一軟位元資訊與對應的對數似然比表，以有效地利用所述多個第一已解碼碼字來增進第二解碼器所執行的所述多個第二迭代解碼操作的正確率。如此一來，雖然第一解碼器執行多個第一迭代解碼操作的期間會耗費電力與時間，但是經由所述多個第一迭代解碼操作所獲得多個第一已解碼碼字可被利用在後續第二解碼器所執行的第二迭代解碼操作，而改善了傳統作法的第二解碼器因重新利用原始碼字來進行多個迭代解碼操作，而具有較大的耗時與耗能所導致的問題，增進了從目標實體頁面所讀取資料的正確性與可靠度，降低對所讀取資料所執行的解碼操作的負荷，進而增進了資料讀取操作整體的效率。In summary, the data reading method, storage controller, and storage device provided by the embodiments of the present invention can read the original codeword from the target physical page, and then perform multiple operations on the original codeword through the first decoder. The multiple first decoded codewords obtained by the first iterative decoding operation and the corresponding multiple first syndromes are used to determine whether to further perform multiple second iterative decoding operations through the second decoder or through the first The decoder executes a plurality of third iterative decoding operations, and responds to the decision to execute a plurality of second iterative decoding operations through the second decoder, and generates the first soft bit information according to the plurality of first decoded code words and The corresponding log-likelihood ratio table is used to effectively use the plurality of first decoded codewords to improve the accuracy of the plurality of second iterative decoding operations performed by the second decoder. In this way, although the first decoder will consume power and time during the multiple first iterative decoding operations, the multiple first decoded codewords obtained through the multiple first iterative decoding operations can be used in The second iterative decoding operation performed by the subsequent second decoder. The second decoder that improves the traditional practice re-uses the original codewords to perform multiple iterative decoding operations, which consumes more time and energy. The problem of improves the accuracy and reliability of the data read from the target physical page, reduces the load of the decoding operation performed on the read data, and thereby improves the overall efficiency of the data reading operation.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10:主機系統 20:儲存裝置 110、211:處理器 120:主機記憶體 130:資料傳輸介面電路 210:儲存控制器 212:資料傳輸管理電路 213:記憶體介面控制電路 214:錯誤檢查與校正電路 2141、2142:解碼器 2143、2144:編碼器 215:讀取輔助電路單元 2151:解碼器管理電路 2152:LLR表管理電路 218:緩衝記憶體 219:電源管理電路 220:可複寫式非揮發性記憶體模組 230:連接介面電路 300:目標實體頁面 311～324:已解碼碼字 S210、S220、S230、S240、S250、S260:資料讀取方法的流程步驟 A31～A34:箭頭 T600、T610:表 10: Host system 20: storage device 110, 211: processor 120: host memory 130: data transmission interface circuit 210: storage controller 212: Data Transmission Management Circuit 213: Memory interface control circuit 214: Error checking and correction circuit 2141, 2142: decoder 2143, 2144: encoder 215: Read auxiliary circuit unit 2151: decoder management circuit 2152: LLR table management circuit 218: buffer memory 219: Power Management Circuit 220: rewritable non-volatile memory module 230: connection interface circuit 300: target entity page 311～324: decoded codeword S210, S220, S230, S240, S250, S260: Process steps of the data reading method A31～A34: Arrow T600, T610: table

圖1A是根據本發明的一實施例所繪示的主機系統及儲存裝置的方塊示意圖。 圖1B是根據本發明的一實施例所繪示的錯誤檢查與校正電路的方塊示意圖。 圖2是根據本發明的一實施例所繪示的資料讀取方法的流程圖。 圖3A為根據本發明的一實施例所繪示的根據多個已解碼碼字產生軟資訊的示意圖。 圖3B為根據本發明的一實施例所繪示的根據多個已解碼碼字及多個校驗子產生軟資訊的示意圖。 圖4A是根據本發明的一實施例所繪示的產生對數似然比表的示意圖。 圖4B是根據本發明的一實施例所繪示的產生對數似然比表的示意圖。 FIG. 1A is a block diagram of a host system and a storage device according to an embodiment of the invention. FIG. 1B is a block diagram of an error checking and correction circuit according to an embodiment of the invention. FIG. 2 is a flowchart of a data reading method according to an embodiment of the invention. 3A is a schematic diagram of generating soft information based on multiple decoded codewords according to an embodiment of the present invention. 3B is a schematic diagram of generating soft information based on multiple decoded codewords and multiple syndromes according to an embodiment of the present invention. 4A is a schematic diagram of generating a log-likelihood ratio table according to an embodiment of the invention. 4B is a schematic diagram of generating a log-likelihood ratio table according to an embodiment of the invention.

S210、S220、S230、S240、S250、S260:資料讀取方法的流程步驟 S210, S220, S230, S240, S250, S260: Process steps of the data reading method

Claims (22)

一種資料讀取方法，適用於配置有一可複寫式非揮發性記憶體模組的一儲存裝置，其中所述可複寫式非揮發性記憶體模組具有多個字元線，其中所述多個字元線的每一個字元線耦接至多個記憶胞，其中所述多個記憶胞中的每一個記憶胞包括多個實體頁面，並且所述多個實體頁面中的每一個實體頁面用以被程式化為一位元值，所述方法包括：對所述多個實體頁面中的目標實體頁面所儲存的目標碼字執行讀取操作，以獲得原始碼字；經由第一解碼器，對所述原始碼字執行X個第一迭代解碼操作，以獲得分別對應所述X個第一迭代解碼操作的X個第一已解碼碼字與對應所述X個第一已解碼碼字的X個第一校驗子；根據所述X個第一迭代解碼操作來判斷是否經由第二解碼器執行多個第二迭代解碼操作；反應於判定經由所述第二解碼器執行所述多個第二迭代解碼操作，根據所述X個第一已解碼碼字以產生第一軟位元資訊與對數似然比(Log Likelihood Ratio，LLR)表，並且經由所述第二解碼器，根據所產生的所述第一軟位元資訊與所述對數似然比表以執行所述多個第二迭代解碼操作，以獲得所述最終已解碼碼字；反應於判定不經由所述第二解碼器執行所述多個第二迭代解碼操作，經由所述第一解碼器，對所述X個第一已解碼碼字中的目標第一已解碼碼字執行多個第三迭代解碼操作，以獲得最終已 解碼碼字；以及反應於判定所述最終已解碼碼字為正確的，輸出所述最終已解碼碼字以作為對應於所述讀取操作的讀取資料，並且完成所述讀取操作。 A data reading method is suitable for a storage device equipped with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of character lines, and the plurality of Each character line of the character line is coupled to a plurality of memory cells, wherein each of the plurality of memory cells includes a plurality of physical pages, and each of the plurality of physical pages is used for Is programmed as a one-bit value, and the method includes: performing a reading operation on the target codeword stored in the target physical page of the plurality of physical pages to obtain the original codeword; The original codeword performs X first iterative decoding operations to obtain X first decoded codewords corresponding to the X first iterative decoding operations and X corresponding to the X first decoded codewords. First syndrome; judging whether to perform multiple second iterative decoding operations via the second decoder according to the X first iterative decoding operations; responding to the decision to perform the multiple second iterative decoding operations via the second decoder Two iterative decoding operations, according to the X first decoded codewords to generate first soft bit information and log likelihood ratio (Log Likelihood Ratio, LLR) table, and through the second decoder, according to the generated The first soft bit information and the log-likelihood ratio table are used to perform the plurality of second iterative decoding operations to obtain the final decoded codeword; in response to the decision not to pass the second decoder Perform the plurality of second iterative decoding operations, via the first decoder, perform a plurality of third iterative decoding operations on the target first decoded codeword among the X first decoded codewords to obtain Finally Decoding the codeword; and in response to determining that the final decoded codeword is correct, outputting the final decoded codeword as the reading data corresponding to the reading operation, and completing the reading operation. 如申請專利範圍第1項所述的資料讀取方法，其中根據所述X個第一迭代解碼操作來判斷是否經由所述第二解碼器執行所述多個第二迭代解碼操作的步驟包括以下步驟(1)、步驟(2)及步驟(3)的其中之一：(1)根據對應所述X個第一迭代解碼操作中的所述X個第一校驗子與校驗子門檻值來進行判斷是否經由所述第二解碼器執行所述多個第二迭代解碼操作；(2)判斷對應所述X個第一迭代解碼操作中的所述X個第一校驗子是否收斂來判斷是否經由所述第二解碼器執行所述多個第二迭代解碼操作；(3)根據所述多個第一迭代解碼操作各自的翻轉位元總數量與翻轉位元總數量門檻值來進行判斷是否經由所述第二解碼器執行所述多個第二迭代解碼操作。 According to the data reading method described in item 1 of the scope of patent application, the step of judging whether to perform the plurality of second iterative decoding operations via the second decoder according to the X first iterative decoding operations includes the following One of step (1), step (2), and step (3): (1) According to the X first syndromes and syndrome thresholds corresponding to the X first iterative decoding operations To determine whether to perform the multiple second iterative decoding operations via the second decoder; (2) determine whether the X first syndromes in the X first iterative decoding operations have converged. Determine whether to perform the plurality of second iterative decoding operations via the second decoder; (3) Perform according to the total number of flipped bits and the threshold value of the total number of flipped bits of each of the plurality of first iterative decoding operations Determining whether to perform the plurality of second iterative decoding operations via the second decoder. 如申請專利範圍第1項所述的資料讀取方法，其中所述第一解碼器為使用位元翻轉演算法(Bit-Flipping Algorithm)的位元翻轉解碼器，並且所述第二解碼器為使用最小值-總和演算法(Min-Sum Algorithm)的最小值-總和解碼器。 According to the data reading method described in item 1 of the scope of patent application, the first decoder is a bit-flipping decoder using a bit-flipping algorithm, and the second decoder is Use the minimum-sum decoder of the Min-Sum Algorithm. 如申請專利範圍第3項所述的資料讀取方法，其中根據所述X個第一已解碼碼字以產生所述第一軟位元資訊與所述對數似然比表的步驟包括：根據所述X個第一迭代解碼操作的總數量、對數似然比上限值以及對數似然比下限值以產生對應的所述對數似然比表。 The data reading method described in item 3 of the scope of patent application, wherein the step of generating the first soft bit information and the log likelihood ratio table according to the X first decoded codewords includes: The total number of the X first iterative decoding operations, the upper limit of the log-likelihood ratio, and the lower limit of the log-likelihood ratio are used to generate the corresponding log-likelihood ratio table. 如申請專利範圍第4項所述的資料讀取方法，其中根據所述X個第一已解碼碼字以產生所述第一軟位元資訊與所述對數似然比表的步驟更包括：根據所述X個第一校驗子，排序對應的所述X個第一已解碼碼字，以產生所述第一軟位元資訊；以及統計所述第一軟位元資訊中的每一列的第一位元值總數量以及第二位元值總數量，其中所述第一軟位元資訊中的每一列對應至所述原始碼字的每一個位元值，其中，其中根據所產生的所述第一軟位元資訊與所述對數似然比表以執行所述多個第二迭代解碼操作，以獲得所述最終已解碼碼字的步驟包括：經由所述第二解碼器，根據所述第一位元值總數量、所述第二位元值總數量以及所述對數似然比表對所述第一軟位元資訊執行所述多個第二迭代解碼操作，以獲得分別對應於所述多個第二迭代解碼操作的多個第二已解碼碼字以及對應所述多個第二已解碼碼字的多個第二校驗子；以及反應於辨識所述多個第二校驗子中的一最終第二校驗子為 零，判定所述多個第二已解碼碼字中對應所述最終第二校驗子的所述最終已解碼碼字為正確的。 According to the data reading method described in item 4 of the scope of patent application, the step of generating the first soft bit information and the log likelihood ratio table according to the X first decoded codewords further includes: According to the X first syndromes, sort the corresponding X first decoded code words to generate the first soft bit information; and count each row in the first soft bit information The total number of first bit values and the total number of second bit values of, wherein each row in the first soft bit information corresponds to each bit value of the original codeword, wherein according to the generated The step of performing the plurality of second iterative decoding operations on the first soft bit information and the log-likelihood ratio table to obtain the final decoded codeword includes: via the second decoder, Perform the plurality of second iterative decoding operations on the first soft bit information according to the total number of first bit values, the total number of second bit values, and the log likelihood ratio table to obtain A plurality of second decoded codewords corresponding to the plurality of second iterative decoding operations and a plurality of second syndromes corresponding to the plurality of second decoded codewords; and in response to identifying the plurality of second decoded codewords A final second syndrome in the second syndrome is Zero, determining that the final decoded codeword corresponding to the final second syndrome among the plurality of second decoded codewords is correct. 如申請專利範圍第3項所述的資料讀取方法，其中所述目標第一已解碼碼字的目標第一校驗子為所述X個第一校驗子中的最小者，其中經由所述第一解碼器，對所述X個第一已解碼碼字中的所述目標第一已解碼碼字執行所述多個第三迭代解碼操作，以獲得所述最終已解碼碼字的步驟包括：經由所述第一解碼器，根據所述目標第一已解碼碼字執行多個第三迭代解碼操作，以獲得分別對應於所述多個第三迭代解碼操作的多個第三已解碼碼字以及對應所述多個第三已解碼碼字的多個第三校驗子；反應於辨識所述多個第三校驗子中的一最終第三校驗子為零，判定所述多個第三已解碼碼字中對應所述最終第三校驗子的所述最終已解碼碼字為正確的；以及反應於辨識所述多個第三迭代解碼操作的總數量大於迭代解碼門檻值及所述多個第三校驗子中的最終第三校驗子不為零，判定所述多個第三已解碼碼字中對應於所述最終第三校驗子的所述最終已解碼碼字為不正確的。 The data reading method as described in item 3 of the scope of patent application, wherein the target first syndrome of the target first decoded codeword is the smallest of the X first syndromes, and The first decoder performs the step of performing the plurality of third iterative decoding operations on the target first decoded codeword among the X first decoded codewords to obtain the final decoded codeword The method includes: performing a plurality of third iterative decoding operations according to the target first decoded codeword via the first decoder to obtain a plurality of third decoded operations respectively corresponding to the plurality of third iterative decoding operations Codeword and a plurality of third syndromes corresponding to the plurality of third decoded codewords; in response to identifying that a final third syndrome among the plurality of third syndromes is zero, it is determined that the The final decoded codeword corresponding to the final third syndrome among the plurality of third decoded codewords is correct; and it is reflected in identifying that the total number of the plurality of third iterative decoding operations is greater than the iterative decoding threshold Value and the final third syndrome in the plurality of third syndromes are not zero, and it is determined that the final syndrome corresponding to the final third syndrome among the plurality of third decoded codewords The decoded codeword is incorrect. 如申請專利範圍第6項所述的資料讀取方法，其中反應於判定所述多個第三已解碼碼字中對應於所述最終第三校驗子的所述最終已解碼碼字為不正確的，所述方法更包括：將所述原始碼字輸入至所述第二解碼器，以經由所述第二解 碼器，根據預設的對數似然比表對所述原始碼字執行多個第四迭代解碼操作，以獲得分別對應於所述多個第四迭代解碼操作的多個第四已解碼碼字以及對應所述多個第四已解碼碼字的多個第四校驗子；以及反應於辨識所述多個第四校驗子中的一最終第四校驗子為零，判定所述多個第四已解碼碼字中對應所述最終第四校驗子的所述最終已解碼碼字為正確的。 The data reading method according to item 6 of the scope of the patent application, wherein the response is to determine whether the final decoded codeword corresponding to the final third syndrome among the plurality of third decoded codewords is not Correctly, the method further includes: inputting the original codeword to the second decoder to pass the second solution The encoder performs multiple fourth iterative decoding operations on the original codeword according to a preset log-likelihood ratio table to obtain multiple fourth decoded codewords respectively corresponding to the multiple fourth iterative decoding operations And a plurality of fourth syndromes corresponding to the plurality of fourth decoded codewords; and in response to recognizing that a final fourth syndrome among the plurality of fourth syndromes is zero, determining the plurality of syndromes The final decoded codeword corresponding to the final fourth syndrome among the fourth decoded codewords is correct. 如申請專利範圍第6項所述的資料讀取方法，其中反應於判定所述多個第三已解碼碼字中對應於所述最終第三校驗子的所述最終已解碼碼字為不正確的，所述方法更包括：執行所述根據所述X個第一已解碼碼字以產生所述對數似然比表，並且經由所述第二解碼器，根據所產生的所述對數似然比表以執行所述多個第二迭代解碼操作，以獲得所述最終已解碼碼字的步驟。 The data reading method according to item 6 of the scope of the patent application, wherein the response is to determine whether the final decoded codeword corresponding to the final third syndrome among the plurality of third decoded codewords is not Correctly, the method further includes: executing the log-likelihood ratio table according to the X first decoded codewords, and using the second decoder to generate the log-likelihood ratio table according to the generated log-likelihood Then compare the table to perform the multiple second iterative decoding operations to obtain the final decoded codeword. 如申請專利範圍第6項所述的資料讀取方法，其中反應於判定所述多個第三已解碼碼字中對應於所述最終第二校驗子的所述最終已解碼碼字為不正確的，所述方法更包括：根據所述多個第三校驗子，排序對應的所述多個第三已解碼碼字，以產生第二軟位元資訊；根據所述第二軟位元資訊的總行數以產生另一對數似然比表；統計所述第二軟位元資訊中的每一列的第一位元值總數量以 及第二位元值總數量，經由所述第二解碼器，根據所述第二軟位元資訊中的每一列的所述第一位元值總數量、所述第二位元值總數量以及所述另一對數似然比表對所述第二軟位元資訊執行多個第五迭代解碼操作，以獲得分別對應於所述多個第五迭代解碼操作的多個第五已解碼碼字以及對應所述多個第五已解碼碼字的多個第五校驗子；以及反應於辨識所述多個第五校驗子中的一最終第五校驗子為零，判定所述多個第五已解碼碼字中對應所述最終第五校驗子的所述最終已解碼碼字為正確的。 The data reading method according to item 6 of the scope of patent application, wherein the response is determined by determining that the final decoded codeword corresponding to the final second syndrome among the plurality of third decoded codewords is not To be correct, the method further includes: sorting the corresponding plurality of third decoded codewords according to the plurality of third syndromes to generate second soft bit information; and according to the second soft bit The total number of rows of meta-information to generate another log-likelihood ratio table; the total number of first bit values in each row in the second soft bit information is calculated as And the total number of second bit values, through the second decoder, according to the total number of first bit values and the total number of second bit values in each row in the second soft bit information And the other log-likelihood ratio table performs a plurality of fifth iterative decoding operations on the second soft bit information to obtain a plurality of fifth decoded codes respectively corresponding to the plurality of fifth iterative decoding operations Word and a plurality of fifth syndromes corresponding to the plurality of fifth decoded codewords; and in response to identifying that a final fifth syndrome among the plurality of fifth syndromes is zero, it is determined that the The final decoded codeword corresponding to the final fifth syndrome among the plurality of fifth decoded codewords is correct. 如申請專利範圍第6項所述的資料讀取方法，其中所述根據所述多個第三校驗子，排序對應的所述多個第三已解碼碼字，以產生所述第二軟位元資訊的步驟包括：從所述多個第三已解碼碼字中，選擇多個目標第三已解碼碼字，其中所述多個第三校驗子中對應所述多個目標第三已解碼碼字的多個目標第三校驗子小於所述多個第三校驗子中的其他的第三校驗子；以及依據所述多個目標第三校驗子的大小，由大至小，將所述多個目標第三已解碼碼字排序為所述第二軟位元資訊的多個行，其中所述多個目標第三已解碼碼字的總數量等於所述第二軟位元資訊的所述多個行的總數量，並且所述總數量是預先設定的。 According to the data reading method described in item 6 of the scope of patent application, wherein the corresponding plurality of third decoded codewords are sorted according to the plurality of third syndromes to generate the second soft The step of bit information includes: selecting a plurality of target third decoded code words from the plurality of third decoded code words, wherein the plurality of third syndromes correspond to the plurality of target third The multiple target third syndromes of the decoded codeword are smaller than the other third syndromes of the multiple third syndromes; and according to the size of the multiple target third syndromes, the larger At least, sort the multiple target third decoded codewords into multiple rows of the second soft bit information, wherein the total number of the multiple target third decoded codewords is equal to the second The total number of the multiple rows of soft bit information, and the total number is preset. 一種儲存控制器，用於控制配置有一可複寫式非揮發性記憶體模組的一儲存裝置，所述儲存控制器包括：一連接介面電路，用以耦接至一主機系統；一記憶體介面控制電路，用以耦接至所述可複寫式非揮發性記憶體模組，其中所述可複寫式非揮發性記憶體模組具有多個字元線，其中所述多個字元線的每一個字元線耦接至多個記憶胞，其中所述多個記憶胞中的每一個記憶胞包括多個實體頁面，並且所述多個實體頁面中的每一個實體頁面用以被程式化為一位元值；一讀取輔助電路單元；一錯誤檢查與校正電路，其中所述錯誤檢查與校正電路包括編碼器與解碼器，並且所述解碼器包括第一解碼器以及第二解碼器；以及一處理器，耦接至所述連接介面電路、所述記憶體介面控制電路、所述讀取輔助電路單元及所述錯誤檢查與校正電路，其中所述處理器用以指示所述記憶體介面控制電路對所述多個實體頁面中的目標實體頁面所儲存的目標碼字執行讀取操作，以獲得原始碼字，其中所述讀取輔助電路單元指示所述第一解碼器，對所述原始碼字執行X個第一迭代解碼操作，以獲得分別對應所述X個第一迭代解碼操作的X個第一已解碼碼字與對應所述X個第一已解碼碼字的X個第一校驗子， 其中所述讀取輔助電路單元根據所述X個第一迭代解碼操作來判斷是否經由第二解碼器執行多個第二迭代解碼操作，其中反應於判定經由所述第二解碼器執行所述多個第二迭代解碼操作，所述讀取輔助電路單元根據所述X個第一已解碼碼字以產生第一軟位元資訊與對數似然比(Log Likelihood Ratio，LLR)表，並且指示所述第二解碼器，根據所產生的所述第一軟位元資訊與所述對數似然比表以執行多個第二迭代解碼操作，以獲得所述最終已解碼碼字，其中反應於判定不經由所述第二解碼器執行所述多個第二迭代解碼操作，所述讀取輔助電路單元指示所述第一解碼器，對所述X個第一已解碼碼字中的目標第一已解碼碼字執行多個第三迭代解碼操作，以獲得最終已解碼碼字，其中反應於判定所述最終已解碼碼字為正確的，所述錯誤檢查與校正電路輸出所述最終已解碼碼字以作為對應於所述讀取操作的讀取資料，並且完成所述讀取操作。 A storage controller for controlling a storage device equipped with a rewritable non-volatile memory module. The storage controller includes: a connection interface circuit for coupling to a host system; and a memory interface A control circuit for coupling to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of character lines, and the plurality of character lines Each character line is coupled to a plurality of memory cells, wherein each of the plurality of memory cells includes a plurality of physical pages, and each of the plurality of physical pages is used to be programmed as A bit value; a reading auxiliary circuit unit; an error checking and correcting circuit, wherein the error checking and correcting circuit includes an encoder and a decoder, and the decoder includes a first decoder and a second decoder; And a processor, coupled to the connection interface circuit, the memory interface control circuit, the read auxiliary circuit unit, and the error checking and correction circuit, wherein the processor is used to instruct the memory interface The control circuit performs a reading operation on the target codeword stored in the target physical page among the plurality of physical pages to obtain the original codeword, wherein the read auxiliary circuit unit instructs the first decoder to The original codeword performs X first iterative decoding operations to obtain the X first decoded codewords corresponding to the X first iterative decoding operations and the Xth first decoded codewords corresponding to the X first decoded codewords. A syndrome, The read auxiliary circuit unit determines whether to perform a plurality of second iterative decoding operations via the second decoder according to the X first iterative decoding operations, wherein it is in response to the determination to perform the plurality of second iterative decoding operations via the second decoder. In a second iterative decoding operation, the read auxiliary circuit unit generates first soft bit information and a log likelihood ratio (Log Likelihood Ratio, LLR) table according to the X first decoded codewords, and instructs all The second decoder performs a plurality of second iterative decoding operations according to the generated first soft bit information and the log-likelihood ratio table to obtain the final decoded codeword, wherein the response is determined The plurality of second iterative decoding operations are not performed through the second decoder, and the read auxiliary circuit unit instructs the first decoder to perform first decoding on the target of the X first decoded codewords. The decoded codeword performs a plurality of third iterative decoding operations to obtain the final decoded codeword, wherein in response to determining that the final decoded codeword is correct, the error checking and correction circuit outputs the final decoded code The word is used as the reading data corresponding to the reading operation, and the reading operation is completed. 如申請專利範圍第11項所述的儲存控制器，其中所述讀取輔助電路單元根據對應所述X個第一迭代解碼操作中的所述X個第一校驗子與校驗子門檻值來進行判斷是否經由所述第二解碼器執行所述多個第二迭代解碼操作，或判斷對應所述X個第一迭代解碼操作中的所述X個第一校驗子是否收斂來判斷是否經由所述第二解碼器執行所述多個第二迭代解碼操作，或根據所述多個第一迭代解碼操作各自的翻轉位元總數量與翻轉位元總數量門檻 值來進行判斷是否經由所述第二解碼器執行所述多個第二迭代解碼操作。 The storage controller according to item 11 of the scope of patent application, wherein the read auxiliary circuit unit corresponds to the X first syndromes and syndrome threshold values in the X first iterative decoding operations To determine whether to perform the multiple second iterative decoding operations via the second decoder, or determine whether the X first syndromes in the X first iterative decoding operations have converged to determine whether Perform the plurality of second iterative decoding operations via the second decoder, or according to the total number of flipped bits and the threshold of the total number of flipped bits of each of the plurality of first iterative decoding operations Value to determine whether to perform the plurality of second iterative decoding operations via the second decoder. 如申請專利範圍第11項所述的儲存控制器，其中所述第一解碼器為使用位元翻轉演算法(Bit-Flipping Algorithm)的位元翻轉解碼器，並且所述第二解碼器為使用最小值-總和演算法(Min-Sum Algorithm)的最小值-總和解碼器。 The storage controller according to item 11 of the scope of patent application, wherein the first decoder is a bit flipping decoder using a bit-flipping algorithm (Bit-Flipping Algorithm), and the second decoder is a The minimum-sum decoder of the Min-Sum Algorithm. 如申請專利範圍第13項所述的儲存控制器，其中在根據所述X個第一已解碼碼字以產生所述第一軟位元資訊與所述對數似然比表的運作中，所述讀取輔助電路單元根據所述X個第一迭代解碼操作的總數量、對數似然比上限值以及對數似然比下限值以產生對應的所述對數似然比表。 The storage controller according to item 13 of the scope of patent application, wherein in the operation of generating the first soft bit information and the log likelihood ratio table based on the X first decoded code words, the The reading auxiliary circuit unit generates the corresponding log likelihood ratio table according to the total number of the X first iterative decoding operations, the upper limit value of the log likelihood ratio, and the lower limit value of the log likelihood ratio. 如申請專利範圍第14項所述的儲存控制器，其中在根據所述X個第一已解碼碼字以產生所述第一軟位元資訊與所述對數似然比表的運作中，所述讀取輔助電路單元根據所述X個第一校驗子，排序對應的所述X個第一已解碼碼字，以產生所述第一軟位元資訊，所述讀取輔助電路單元統計所述第一軟位元資訊中的每一列的第一位元值總數量以及第二位元值總數量，其中所述第一軟位元資訊中的每一列對應至所述原始碼字的每一個位元值，其中在根據所產生的所述對數似然比表以執行所述多個第二 迭代解碼操作的運作中，其中所述讀取輔助電路單元指示所述第二解碼器，根據所述第一位元值總數量、所述第二位元值總數量以及所述對數似然比表對所述第一軟位元資訊執行所述多個第二迭代解碼操作，以獲得分別對應於所述多個第二迭代解碼操作的多個第二已解碼碼字以及對應所述多個第二已解碼碼字的多個第二校驗子，其中反應於辨識所述多個第二校驗子中的一最終第二校驗子為零，所述錯誤檢查與校正電路判定所述多個第二已解碼碼字中對應所述最終第二校驗子的所述最終已解碼碼字為正確的。 The storage controller as described in claim 14, wherein in the operation of generating the first soft bit information and the log-likelihood ratio table based on the X first decoded codewords, all The reading auxiliary circuit unit sorts the corresponding X first decoded codewords according to the X first syndromes to generate the first soft bit information, and the reading auxiliary circuit unit counts The total number of first bit values and the total number of second bit values in each row in the first soft bit information, wherein each row in the first soft bit information corresponds to the value of the original codeword For each bit value, where the second plurality is executed according to the generated log-likelihood ratio table In the operation of the iterative decoding operation, wherein the read auxiliary circuit unit instructs the second decoder, according to the total number of first bit values, the total number of second bit values, and the log likelihood ratio The table performs the plurality of second iterative decoding operations on the first soft bit information to obtain a plurality of second decoded codewords respectively corresponding to the plurality of second iterative decoding operations and corresponding to the plurality of The plurality of second syndromes of the second decoded codeword, wherein in response to identifying that a final second syndrome of the plurality of second syndromes is zero, the error checking and correction circuit determines the The final decoded codeword corresponding to the final second syndrome among the plurality of second decoded codewords is correct. 如申請專利範圍第13項所述的儲存控制器，其中所述目標第一已解碼碼字的目標第一校驗子為所述X個第一校驗子中的最小者，其中在經由所述第一解碼器，對所述X個第一已解碼碼字中的所述目標第一已解碼碼字執行所述多個第三迭代解碼操作，以獲得所述最終已解碼碼字的運作中，所述第一解碼器根據所述目標第一已解碼碼字執行多個第三迭代解碼操作，以獲得分別對應於所述多個第三迭代解碼操作的多個第三已解碼碼字以及對應所述多個第三已解碼碼字的多個第三校驗子，其中反應於辨識所述多個第三校驗子中的一最終第三校驗子為零，所述第一解碼器判定所述多個第三已解碼碼字中對應所述最終第三校驗子的所述最終已解碼碼字為正確的，反應於辨識所述多個第三迭代解碼操作的總數量大於迭代解 碼門檻值及所述多個第三校驗子中的最終第三校驗子不為零，所述第一解碼器判定所述多個第三已解碼碼字中對應於所述最終第三校驗子的所述最終已解碼碼字為不正確的。 The storage controller according to item 13 of the scope of patent application, wherein the target first syndrome of the target first decoded codeword is the smallest one of the X first syndromes, wherein The first decoder performs the plurality of third iterative decoding operations on the target first decoded codeword among the X first decoded codewords to obtain the final decoded codeword Wherein, the first decoder performs a plurality of third iterative decoding operations according to the target first decoded codeword to obtain a plurality of third decoded codewords respectively corresponding to the plurality of third iterative decoding operations And a plurality of third syndromes corresponding to the plurality of third decoded codewords, wherein in response to identifying that a final third syndrome of the plurality of third syndromes is zero, the first The decoder determines that the final decoded codeword corresponding to the final third syndrome among the plurality of third decoded codewords is correct, reflecting the identification of the total number of the plurality of third iterative decoding operations Greater than iterative solution The code threshold and the final third syndrome in the plurality of third syndromes are not zero, and the first decoder determines that the plurality of third decoded codewords corresponds to the final third syndrome The final decoded codeword of the syndrome is incorrect. 如申請專利範圍第16項所述的儲存控制器，其中反應於判定所述多個第三已解碼碼字中對應於所述最終第三校驗子的所述最終已解碼碼字為不正確的，所述讀取輔助電路單元將所述原始碼字輸入至所述第二解碼器，以經由所述第二解碼器，根據預設的對數似然比表對所述原始碼字執行多個第四迭代解碼操作，以獲得分別對應於所述多個第四迭代解碼操作的多個第四已解碼碼字以及對應所述多個第四已解碼碼字的多個第四校驗子，其中反應於辨識所述多個第四校驗子中的一最終第四校驗子為零，所述第二解碼器判定所述多個第四已解碼碼字中對應所述最終第四校驗子的所述最終已解碼碼字為正確的。 The storage controller according to item 16 of the scope of patent application, wherein the response is to determine that the final decoded codeword corresponding to the final third syndrome among the plurality of third decoded codewords is incorrect , The reading auxiliary circuit unit inputs the original codeword to the second decoder, so as to perform more on the original codeword according to a preset log-likelihood ratio table via the second decoder. A fourth iterative decoding operation to obtain a plurality of fourth decoded codewords corresponding to the plurality of fourth iterative decoding operations and a plurality of fourth syndromes corresponding to the plurality of fourth decoded codewords , Wherein in response to identifying that a final fourth syndrome among the plurality of fourth syndromes is zero, the second decoder determines that the plurality of fourth decoded codewords corresponds to the final fourth syndrome The final decoded codeword of the syndrome is correct. 如申請專利範圍第16項所述的儲存控制器，其中反應於判定所述多個第三已解碼碼字中對應於所述最終第二校驗子的所述最終已解碼碼字為不正確的，所述讀取輔助電路單元執行所述根據所述X個第一已解碼碼字以產生所述對數似然比表，並且經由所述第二解碼器，根據所產生的所述對數似然比表以執行所述多個第二迭代解碼操作，以獲得所述最終已解碼碼字的步驟。 The storage controller according to item 16 of the scope of patent application, wherein the response is to determine that the final decoded codeword corresponding to the final second syndrome among the plurality of third decoded codewords is incorrect , The read auxiliary circuit unit executes the X first decoded codewords to generate the log likelihood ratio table, and via the second decoder, according to the generated log likelihood Then compare the table to perform the multiple second iterative decoding operations to obtain the final decoded codeword. 如申請專利範圍第16項所述的儲存控制器，其中反應於判定所述多個第三已解碼碼字中對應於所述最終第二校驗子的所述最終已解碼碼字為不正確的，所述讀取輔助電路單元根據所述多個第三校驗子，排序對應的所述多個第三已解碼碼字，以產生第二軟位元資訊，其中所述讀取輔助電路單元根據所述第二軟位元資訊的總行數以產生另一對數似然比表，其中所述讀取輔助電路單元統計所述第二軟位元資訊中的每一列的第一位元值總數量以及第二位元值總數量，其中所述讀取輔助電路單元指示所述第二解碼器，根據所述第二軟位元資訊中的每一列的所述第一位元值總數量、所述第二位元值總數量以及所述另一對數似然比表對所述第二軟位元資訊執行多個第五迭代解碼操作，以獲得分別對應於所述多個第五迭代解碼操作的多個第五已解碼碼字以及對應所述多個第五已解碼碼字的多個第五校驗子，其中反應於辨識所述多個第五校驗子中的一最終第五校驗子為零，所述第二解碼器判定所述多個第五已解碼碼字中對應所述最終第五校驗子的所述最終已解碼碼字為正確的。 The storage controller according to item 16 of the scope of patent application, wherein the response is to determine that the final decoded codeword corresponding to the final second syndrome among the plurality of third decoded codewords is incorrect Preferably, the read auxiliary circuit unit sorts the corresponding plurality of third decoded code words according to the plurality of third syndromes to generate second soft bit information, wherein the read auxiliary circuit The unit generates another log likelihood ratio table according to the total number of rows of the second soft bit information, wherein the read auxiliary circuit unit counts the first bit value of each row in the second soft bit information The total number and the total number of second bit values, wherein the read auxiliary circuit unit instructs the second decoder to use the total number of the first bit values in each row in the second soft bit information , The total number of second bit values and the other log-likelihood ratio table perform a plurality of fifth iteration decoding operations on the second soft bit information to obtain respective fifth iterations The plurality of fifth decoded codewords of the decoding operation and the plurality of fifth syndromes corresponding to the plurality of fifth decoded codewords, wherein the response is to identify a final first of the plurality of fifth syndromes The fifth syndrome is zero, and the second decoder determines that the final decoded codeword corresponding to the final fifth syndrome among the plurality of fifth decoded codewords is correct. 如申請專利範圍第16項所述的儲存控制器，其中在所述根據所述多個第三校驗子，排序對應的所述多個第三已解碼碼字，以產生所述第二軟位元資訊的運作中，所述讀取輔助電路單元從所述多個第三已解碼碼字中，選擇 多個目標第三已解碼碼字，其中所述多個第三校驗子中對應所述多個目標第三已解碼碼字的多個目標第三校驗子小於所述多個第三校驗子中的其他的第三校驗子，其中所述讀取輔助電路單元依據所述多個目標第三校驗子的大小，由大至小，將所述多個目標第三已解碼碼字排序為所述第二軟位元資訊的多個行，其中所述多個目標第三已解碼碼字的總數量等於所述第二軟位元資訊的所述多個行的總數量，並且所述總數量是預先設定的。 The storage controller according to item 16 of the scope of patent application, wherein the corresponding plurality of third decoded code words are sorted according to the plurality of third syndromes to generate the second soft In the operation of bit information, the read auxiliary circuit unit selects from the plurality of third decoded code words Multiple target third decoded codewords, wherein multiple target third syndromes corresponding to the multiple target third decoded codewords in the multiple third syndromes are smaller than the multiple third syndromes The other third syndromes in the empirical test, wherein the read auxiliary circuit unit converts the plurality of target third decoded codes from large to small according to the size of the plurality of target third syndromes The word sequence is a plurality of rows of the second soft bit information, wherein the total number of the plurality of target third decoded code words is equal to the total number of the plurality of rows of the second soft bit information, And the total number is preset. 一種儲存裝置，所述儲存裝置包括：一可複寫式非揮發性記憶體模組，其中所述可複寫式非揮發性記憶體模組具有多個字元線，其中所述多個字元線的每一個字元線耦接至多個記憶胞，其中所述多個記憶胞中的每一個記憶胞包括多個實體頁面，並且所述多個實體頁面中的每一個實體頁面用以被程式化為一位元值；一記憶體介面控制電路，用以耦接至所述可複寫式非揮發性記憶體模組；以及一處理器，耦接至所述記憶體介面控制電路，其中所述處理器載入且執行一讀取輔助程式碼模組，以實現一資料讀取方法，該資料讀取方法包括下列步驟：對所述多個實體頁面中的目標實體頁面所儲存的目標碼字執行讀取操作，以獲得原始碼字；經由第一解碼器，對所述原始碼字執行X個第一迭代解碼操 作，以獲得分別對應所述X個第一迭代解碼操作的X個第一已解碼碼字與對應所述X個第一已解碼碼字的X個第一校驗子；根據所述X個第一迭代解碼操作來判斷是否經由第二解碼器執行多個第二迭代解碼操作；反應於判斷經由所述第二解碼器執行所述多個第二迭代解碼操作，根據所述X個第一已解碼碼字以產生對數似然比(Log Likelihood Ratio，LLR)表，並且經由所述第二解碼器，根據所產生的所述對數似然比表以執行多個第二迭代解碼操作，以獲得所述最終已解碼碼字；反應於判斷不經由所述第二解碼器執行所述多個第二迭代解碼操作，經由所述第一解碼器，對所述X個第一已解碼碼字中的目標第一已解碼碼字執行多個第三迭代解碼操作，以獲得最終已解碼碼字；以及反應於判定所述最終已解碼碼字為正確的，輸出所述最終已解碼碼字以作為對應於所述讀取操作的讀取資料，並且完成所述讀取操作。 A storage device, the storage device comprising: a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of character lines, wherein the plurality of character lines Each character line of is coupled to a plurality of memory cells, wherein each of the plurality of memory cells includes a plurality of physical pages, and each of the plurality of physical pages is used to be programmed Is a one-bit value; a memory interface control circuit for coupling to the rewritable non-volatile memory module; and a processor coupled to the memory interface control circuit, wherein the The processor loads and executes a reading auxiliary code module to implement a data reading method. The data reading method includes the following steps: target codewords stored in the target physical page among the plurality of physical pages Perform a read operation to obtain the original codeword; through the first decoder, perform X first iterative decoding operations on the original codeword To obtain the X first decoded codewords corresponding to the X first iterative decoding operations and the X first syndromes corresponding to the X first decoded codewords; according to the X The first iterative decoding operation is used to determine whether to perform multiple second iterative decoding operations via the second decoder; in response to the determination to perform the multiple second iterative decoding operations via the second decoder, according to the X first The codeword has been decoded to generate a log likelihood ratio (Log Likelihood Ratio, LLR) table, and through the second decoder, a plurality of second iterative decoding operations are performed according to the generated log likelihood ratio table to Obtain the final decoded codeword; in response to determining that the plurality of second iterative decoding operations are not performed through the second decoder, perform the X first decoded codewords through the first decoder Perform multiple third iterative decoding operations on the target first decoded codeword in to obtain the final decoded codeword; and in response to determining that the final decoded codeword is correct, output the final decoded codeword to As the reading data corresponding to the reading operation, and completing the reading operation. 如申請專利範圍第21項所述的儲存裝置，其中根據所述X個第一迭代解碼操作來判斷是否經由所述第二解碼器執行所述多個第二迭代解碼操作的步驟包括以下步驟(1)、步驟(2)及步驟(3)的其中之一：(1)根據對應所述X個第一迭代解碼操作中的所述X個第一校驗子與校驗子門檻值來進行判斷是否經由所述第二解碼器執行所述多個第二迭代解碼操作；(2)判斷對應所述X個第一迭 代解碼操作中的所述X個第一校驗子是否收斂來判斷是否經由所述第二解碼器執行所述多個第二迭代解碼操作；(3)根據所述多個第一迭代解碼操作各自的翻轉位元總數量與翻轉位元總數量門檻值來進行判斷是否經由所述第二解碼器執行所述多個第二迭代解碼操作。 The storage device according to claim 21, wherein the step of judging whether to perform the plurality of second iterative decoding operations via the second decoder according to the X first iterative decoding operations includes the following steps ( 1) One of step (2) and step (3): (1) Perform according to the X first syndromes and syndrome thresholds corresponding to the X first iterative decoding operations Determine whether to perform the multiple second iterative decoding operations via the second decoder; (2) Determine whether the X first iteratives correspond to Determine whether to perform the multiple second iterative decoding operations via the second decoder whether the X first syndromes in the generation decoding operation converge; (3) According to the multiple first iterative decoding operations Each threshold value of the total number of flipped bits and the total number of flipped bits is used to determine whether to perform the plurality of second iterative decoding operations through the second decoder.

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