TWI397076B - Method and system for decoding data in non-volatile storage using reliability metrics based on multiple reads - Google Patents

Description

非揮發性儲存器中利用以多重讀取為基礎之可靠度計量的解碼資料方法及系統Decoded data method and system using multi-read based reliability measurement in non-volatile storage

本發明係關於非揮發性記憶體。This invention relates to non-volatile memory.

本申請案係關於同在申請中的共同讓渡之以下申請案：於2007年3月29日申請之名為"用於在使用以多重讀取為基礎之可靠度計量的非揮發性儲存器中解碼資料之方法(Method for Decoding Data in Non-Volatile Storage Using Reliability Metrics Based On Multiple Reads)"(檔案號碼SAND-1223US0)之美國專利申請案第11/693,649號(於2011年3月8日獲准美國專利第7,904,793號)；於2007年3月29日申請之名為"利用以多重讀取為基礎之可靠度計量來解碼資料之非揮發性儲存器(Non-Volatile Storage With Decoding of Data Using Reliability Metrics Based On Multiple Reads)"(檔案號碼SAND-1223US1)之美國專利申請案第11/693,672號(現已放棄)；於2007年3月29日申請之名為"用於利用預調節波形及經修改可靠度計量來讀取非揮發性儲存器之方法(Method For Reading Non-Volatile Storage Using Pre-Conditioning Waveforms And Modified Reliability Metrics)"(檔案號碼SAND-1224US0)之美國專利申請案第11/693,663號(於2010年9月14日獲准美國專利第7,797,480號)；及於2007年3月29日申請之名為"利用預調節波形及經修改可靠度計量來讀取之非揮發性儲存器(Non-Volatile Storage With Reading Using Pre-Conditioning Waveforms and Modified Reliability Metrics)"(檔案號碼SAND-1224US1)之美國專利申請案第11/693,668號(已放棄)，其中之每一者以引用之方式併入本文中。This application is the following application for co-delivery in the same application: a non-volatile storage for use in the use of multiple reading-based reliability measurements, filed on March 29, 2007 US Patent Application No. 11/693,649 (Method for Decoding Data in Non-Volatile Storage Using Reliability Metrics Based On Multiple Reads) (file number SAND-1223US0) (approved on March 8, 2011) U.S. Patent No. 7,904,793; the application entitled "Non-Volatile Storage With Decoding of Data Using Reliability", which was filed on March 29, 2007. "Metrics Based On Multiple Reads"" (file number SAND-1223US1) US Patent Application No. 11/693,672 (now abandoned); filed on March 29, 2007, entitled "Using Pre-Adjusted Waveforms and Method of Reading Non-Volatile Storage Using Pre-Conditioning Waveforms And Modified Reliability Metrics" (file number SAND-1224US0) US Patent Application No. 11/693,663 (issued US Patent No. 7,797,480 on September 14, 2010); and filed on March 29, 2007 entitled "Using Pre-Adjusted Waveforms and Modified Reliability Metering to Read U.S. Patent Application Serial No. 11/693,668 (Non-Volatile Storage With Reading Using Pre-Conditioning Waveforms and Modified Reliability Metrics) (file number SAND-1224US1), each of which is abandoned One is incorporated herein by reference.

半導體記憶體對於在各種電子設備中之使用已變得愈加風行。舉例而言，非揮發性半導體記憶體用於蜂巢式電話、數位相機、個人數位助理、行動計算設備、非行動計算設備及其他設備中。在最風行之非揮發性半導體記憶體 當中有電可抹除可程式化唯讀記憶體(EEPROM)及快閃記憶體。在快閃記憶體(亦為EEPROM類型)的情況下，與傳統之全特徵化EEPROM對比，可在一個步驟中抹除整個記憶體陣列之內容或記憶體之一部分之內容。Semiconductor memory has become increasingly popular for use in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. The most popular non-volatile semiconductor memory There is an electric eraseable programmable read only memory (EEPROM) and flash memory. In the case of flash memory (also EEPROM type), the content of the entire memory array or the contents of a portion of the memory can be erased in one step as compared to a conventional fully characterization EEPROM.

傳統EEPROM及快閃記憶體均利用浮動閘極，浮動閘極定位於半導體基板中之通道區域上方且與通道區域絕緣。浮動閘極定位於源極區域與汲極區域之間。控制閘極提供於浮動閘極之上且與浮動閘極絕緣。經如此形成之電晶體的臨限電壓(V_TH )受保留於浮動閘極上之電荷量控制。亦即，在開啟電晶體以允許在其源極與汲極之間進行傳導之前必須施加至控制閘極的最小電壓量受浮動閘極上之電荷位準控制。Both conventional EEPROM and flash memory utilize a floating gate that is positioned above the channel region in the semiconductor substrate and insulated from the channel region. The floating gate is positioned between the source region and the drain region. The control gate is provided above the floating gate and insulated from the floating gate. The threshold voltage (V _TH ) of the thus formed transistor is controlled by the amount of charge remaining on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to allow conduction between its source and drain is controlled by the charge level on the floating gate.

一些EEPROM及快閃記憶體設備具有用於儲存兩個電荷範圍之浮動閘極，且因此，記憶體元件可在兩個狀態(例如，經抹除狀態與經程式化狀態)之間進行程式化/抹除。此快閃記憶體設備有時被稱為二元快閃記憶體設備，因為每一記憶體元件均可儲存一個資料位元。Some EEPROM and flash memory devices have floating gates for storing two charge ranges, and thus, memory elements can be programmed between two states (eg, erased and stylized) / erase. This flash memory device is sometimes referred to as a binary flash memory device because each memory element can store one data bit.

多狀態(亦被稱作多級)快閃記憶體設備係藉由識別多個相異的容許/有效經程式化臨限電壓範圍來實施。每一相異臨限電壓範圍對應於記憶體設備中所編碼之資料位元集合之預定值。舉例而言，當每一記憶體元件可置放在對應於四個相異臨限電壓範圍之四個離散電荷帶中之一者中時，該元件可儲存兩個資料位元。Multi-state (also referred to as multi-level) flash memory devices are implemented by identifying a plurality of distinct allowable/effective programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value of the set of data bits encoded in the memory device. For example, when each memory element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges, the element can store two data bits.

通常，在程式操作期間施加至控制閘極之程式電壓V_PGM 作為在量值方面隨著時間而增加之脈衝系列而被施加。在一可能方法中，脈衝之量值隨著每一連續脈衝而增加一預定步長，例如，0.2-0.4 V。可將V_PGM 施加至快閃記憶體元件之控制閘極。在程式脈衝之間的週期中，進行驗證操作。亦即，在連續程式化脈衝之間讀取經並行地程式化之元件群中之每一元件的程式化位準，以判定其是等於還是大於該元件經程式化至之驗證位準。對於多狀態快閃記憶體元件陣列而言，可針對元件之每一狀態來執行驗證步驟，以判定該元件是否已達到其資料關聯驗證位準。舉例而言，能夠在四個狀態中儲存資料之多狀態記憶體元件可能需要針對三個比較點來執行驗證操作。Typically, the program voltage V _PGM applied to the control gate during program operation is applied as a series of pulses that increase in magnitude over time. In one possible approach, the magnitude of the pulse is increased by a predetermined step size, for example, 0.2-0.4 V, with each successive pulse. V _PGM can be applied to the control gate of the flash memory component. The verification operation is performed during the period between the program pulses. That is, the stylized level of each of the components in the parallel stylized component group is read between consecutive stylized pulses to determine whether it is equal to or greater than the verify level to which the component is programmed. For a multi-state flash memory device array, a verification step can be performed for each state of the component to determine if the component has reached its data association verification level. For example, a multi-state memory element capable of storing data in four states may need to perform a verify operation for three comparison points.

此外，當程式化EEPROM或快閃記憶體設備(諸如，NAND串中之NAND快閃記憶體設備)時，通常將V_PGM 施加至控制閘極且使位元線接地，從而導致將來自單元或記憶體元件(例如，儲存元件)之通道的電子注入至浮動閘極中。當電子累積於浮動閘極中時，浮動閘極變得帶負電，且記憶體元件之臨限電壓上升，使得認為記憶體元件處於經程式化狀態。可在名為"Source Side Self Boosting Technique For Non-Volatile Memory"之美國專利6,859,397及2005年2月3日公布的名為"Detecting Over Programmed Memory"之美國專利申請案公開案2005/0024939中找到關於此程式化之更多資訊；其全部內容均以引用的方式併入本文中。In addition, when programming an EEPROM or flash memory device (such as a NAND flash memory device in a NAND string), V _PGM is typically applied to the control gate and the bit line is grounded, resulting in a Electrons of the channels of the memory elements (eg, storage elements) are injected into the floating gates. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory component rises, making the memory component considered to be in a stylized state. It can be found in U.S. Patent No. 6,859,397, entitled "Source Side Self Boosting Technique For Non-Volatile Memory", and U.S. Patent Application Publication No. 2005/0024939, entitled "Detecting Over Programmed Memory", published on February 3, 2005. More information on this stylization; the entire contents of which are incorporated herein by reference.

一旦已程式化非揮發性儲存元件，則重要的係，可以高 可靠度來讀回其程式化狀態。然而，經感測程式化狀態歸因於截獲位點(trap site)雜訊及其他因素而有時可不同於預期程式化狀態。或許，最重要的雜訊源為1/f雜訊(包括隨機電報信號雜訊)，其為電子截獲及去截獲至位於穿隧氧化物或其他地方之截獲位點中的結果。Once the non-volatile storage element has been programmed, the important system can be high Reliability to read back its stylized state. However, the sensed stylized state may sometimes be different from the expected stylized state due to trap site noise and other factors. Perhaps the most important source of noise is 1/f noise (including random telegraph noise), which is the result of electronic interception and de-interception to intercept sites located in tunnel oxides or elsewhere.

本發明藉由提供一種用於利用多重讀取操作來解碼儲存於非揮發性儲存器中之資料的方法來處理以上及其他問題。The present invention addresses these and other problems by providing a method for decoding data stored in non-volatile memory using multiple read operations.

在一實施例中，一種用於解碼非揮發性儲存器中之資料的方法包括對至少一非揮發性儲存元件執行多重感測操作，及利用迭代機率性解碼來判定至少一非揮發性儲存元件之程式化狀態，其中迭代機率性解碼利用以多重感測操作為基礎之可靠度計量。舉例而言，可靠度計量可包括對數概似比。In one embodiment, a method for decoding data in a non-volatile storage device includes performing a multiple sensing operation on at least one non-volatile storage element and utilizing iterative probability decoding to determine at least one non-volatile storage element The stylized state in which iterative probability decoding utilizes reliability metering based on multiple sensing operations. For example, the reliability measure can include a logarithmic approximation ratio.

該方法可進一步包括以多重感測操作為基礎來判定用於迭代機率性解碼中之初始可靠度計量集合。或，迭代機率性解碼可最初利用以第一感測操作為基礎之第一可靠度計量來迭代。第一可靠度計量經調整以在機率性解碼進一步迭代時獲得經調整可靠度計量。接著以後續感測操作為基礎而在機率性解碼進一步迭代時進一步調整經調整可靠度計量。The method can further include determining an initial set of reliability measures for iterative probability decoding based on the multiple sensing operations. Alternatively, iterative probability decoding may initially iterate using a first reliability measure based on the first sensing operation. The first reliability measure is adjusted to obtain an adjusted reliability measure when the probability decoding is further iterated. The adjusted reliability measure is then further adjusted based on subsequent sensing operations while the probability decoding further iterates.

在另一實施例中，一種用於解碼非揮發性儲存器中之資料的方法包括對至少一非揮發性儲存元件執行第一感測操 作、以第一感測操作為基礎來提供第一碼字、利用以第一碼字為基礎之第一可靠度計量集合而針對第一碼字來執行解碼過程，及在解碼過程不滿足第一條件的情況下對至少一非揮發性儲存元件執行第二感測操作且以第二感測操作為基礎來調整解碼過程。舉例而言，第一條件可包括在給定時間週期內或在給定數目之迭代內收斂或滿足給定數目之同位檢查的解碼過程。In another embodiment, a method for decoding data in a non-volatile storage device includes performing a first sensing operation on at least one non-volatile storage element Providing, based on the first sensing operation, the first codeword, performing the decoding process for the first codeword by using the first reliability metering set based on the first codeword, and not satisfying the decoding process The second sensing operation is performed on the at least one non-volatile storage element and the decoding process is adjusted based on the second sensing operation in a condition. For example, the first condition may include a decoding process that converges or satisfies a given number of parity checks within a given time period or within a given number of iterations.

在另一實施例中，一種用於解碼非揮發性儲存器中之資料的方法包括對至少一非揮發性儲存元件執行第一感測操作、以第一感測操作為基礎來提供表示至少一非揮發性儲存元件之經感測程式化狀態的第一資料，及利用以第一資料為基礎之機率計量來開始用於第一資料之迭代解碼過程。該方法進一步包括對至少一非揮發性儲存元件執行第二感測操作、以第二感測操作為基礎來提供表示至少一非揮發性儲存元件之經感測程式化狀態的第二資料，及藉由以第二資料為基礎來調整機率計量之最近利用的值而繼續迭代解碼過程。In another embodiment, a method for decoding data in a non-volatile storage device includes performing a first sensing operation on at least one non-volatile storage element, providing at least one representation based on the first sensing operation The first data of the sensed stylized state of the non-volatile storage element and the probability data based on the first data are used to initiate an iterative decoding process for the first data. The method further includes performing a second sensing operation on the at least one non-volatile storage element, providing a second material indicative of the sensed stylized state of the at least one non-volatile storage element based on the second sensing operation, and The iterative decoding process continues by adjusting the recently utilized value of the probabilistic meter based on the second data.

在另一實施例中，一種用於解碼非揮發性儲存器中之資料的方法包括對至少一非揮發性儲存元件執行第一感測操作、以第一感測操作為基礎來提供表示至少一非揮發性儲存元件之經感測程式化狀態的第一資料、利用以第一資料為基礎之機率計量來開始用於第一資料之迭代解碼過程，及提供指示迭代解碼過程之進度的計量。若計量指示進度不令人滿意，則該方法進一步包括以第二感測操作為基礎 來提供表示至少一非揮發性儲存元件之經感測程式化狀態的第二資料，及利用以第一資料及第二資料為基礎之機率計量來重新開始迭代解碼過程。In another embodiment, a method for decoding data in a non-volatile storage device includes performing a first sensing operation on at least one non-volatile storage element, providing at least one representation based on the first sensing operation The first data of the sensed stylized state of the non-volatile storage element, using the probability data based on the first data to initiate an iterative decoding process for the first data, and providing a measure indicative of the progress of the iterative decoding process. If the measurement indicates that the progress is not satisfactory, the method further includes based on the second sensing operation A second data representative of the sensed stylized state of the at least one non-volatile storage element is provided, and the iterative decoding process is restarted using probability measurements based on the first data and the second data.

在另一實施例中，一種用於操作非揮發性儲存器之方法包括對非揮發性儲存元件集合執行複數個感測操作、以感測操作為基礎來提供可靠度計量集合，及儲存可靠度計量集合以供迭代機率性解碼過程用於以至少第一及第二後續感測操作為基礎來判定非揮發性儲存元件集合中之至少一非揮發性儲存元件的程式化狀態。In another embodiment, a method for operating a non-volatile storage includes performing a plurality of sensing operations on a set of non-volatile storage elements, providing a set of reliability measurements based on sensing operations, and storing reliability The set of measurements is for an iterative probability decoding process for determining a stylized state of at least one non-volatile storage element of the set of non-volatile storage elements based on at least the first and second subsequent sensing operations.

本發明提供一種用於利用多重讀取操作來解碼儲存於非揮發性儲存器中之資料的方法。The present invention provides a method for decoding data stored in a non-volatile storage using multiple read operations.

適用於實施本發明之記憶體系統之一實例利用NAND快閃記憶體結構，其包括在兩個選擇閘極之間串聯地配置多個電晶體。串聯之電晶體及選擇閘極被稱為NAND串。圖1為展示一NAND串之俯視圖。圖2為其等效電路。圖1及圖2中所描繪之NAND串包括串聯且夾於第一選擇閘極120與第二選擇閘極122之間的四個電晶體100、102、104及106。One example of a memory system suitable for use in practicing the present invention utilizes a NAND flash memory structure that includes a plurality of transistors arranged in series between two select gates. The series connected transistors and select gates are referred to as NAND strings. Figure 1 is a top plan view showing a NAND string. Figure 2 is its equivalent circuit. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104, and 106 that are connected in series and sandwiched between a first select gate 120 and a second select gate 122.

選擇閘極120閘控至位元線126之NAND串連接。選擇閘極122閘控至源極線128之NAND串連接。藉由將適當電壓施加至控制閘極120CG來控制選擇閘極120。藉由將適當電壓施加至控制閘極122CG來控制選擇閘極122。電晶體100、102、104及106中之每一者具有控制閘極及浮動閘極。電晶體100包括控制閘極100CG及浮動閘極100FG。電 晶體102包括控制閘極102CG及浮動閘極102FG。電晶體104包括控制閘極104CG及浮動閘極104FG。電晶體106包括控制閘極106CG及浮動閘極106FG。控制閘極100CG連接至字線WL3，控制閘極102CG連接至字線WL2，控制閘極104CG連接至字線WL1，且控制閘極106CG連接至字線WL0。控制閘極亦經提供為字線之部分。在一實施例中，電晶體100、102、104及106各自為儲存元件，亦被稱為記憶體單元。在其他實施例中，儲存元件可包括多個電晶體，或可不同於圖1及圖2中所描繪之儲存元件。選擇閘極120連接至選擇線SGD(汲極選擇閘極)。選擇閘極122連接至選擇線SGS(源極選擇閘極)。The NAND string connection of the gate 120 gate to the bit line 126 is selected. The NAND string connection of the gate 122 gate to the source line 128 is selected. The selection gate 120 is controlled by applying an appropriate voltage to the control gate 120CG. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. The transistor 100 includes a control gate 100CG and a floating gate 100FG. Electricity The crystal 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL0. The control gate is also provided as part of the word line. In one embodiment, transistors 100, 102, 104, and 106 are each a storage element, also referred to as a memory unit. In other embodiments, the storage element may comprise a plurality of transistors, or may be different than the storage elements depicted in Figures 1 and 2. The selection gate 120 is connected to the selection line SGD (drain selection gate). The selection gate 122 is connected to the selection line SGS (source selection gate).

圖3為描繪三個NAND串之電路圖。利用NAND結構之快閃記憶體系統的典型架構將包括若干NAND串。舉例而言，在具有較多NAND串之記憶體陣列中展示三個NAND串320、340及360。NAND串中之每一者包括兩個選擇閘極及四個儲存元件。雖然為了簡單起見而說明四個儲存元件，但現代NAND串可具有(例如)高達32或64個儲存元件。Figure 3 is a circuit diagram depicting three NAND strings. A typical architecture of a flash memory system utilizing a NAND structure would include several NAND strings. For example, three NAND strings 320, 340, and 360 are shown in a memory array with more NAND strings. Each of the NAND strings includes two select gates and four storage elements. Although four storage elements are illustrated for simplicity, modern NAND strings can have, for example, up to 32 or 64 storage elements.

舉例而言，NAND串320包括選擇閘極322及327以及儲存元件323-326，NAND串340包括選擇閘極342及347以及儲存元件343-346，NAND串360包括選擇閘極362及367以及儲存元件363-366。每一NAND串藉由其選擇閘極(例如，選擇閘極327、347或367)而連接至源極線。選擇線SGS用於控制源極側選擇閘極。各種NAND串320、340及360藉由 選擇閘極322、342、362等等中之選擇電晶體而連接至各別位元線321、341及361。此等選擇電晶體受汲極選擇線SGD控制。在其他實施例中，選擇線未必需要共同地在NAND串當中；亦即，可為不同NAND串提供不同選擇線。字線WL3連接至用於儲存元件323、343及363之控制閘極。字線WL2連接至用於儲存元件324、344及364之控制閘極。字線WL1連接至用於儲存元件325、345及365之控制閘極。字線WL0連接至用於儲存元件326、346及366之控制閘極。可看出，每一位元線及各別NAND串包含儲存元件陣列或集合之行。字線(WL3、WL2、WL1及WL0)包含陣列或集合之列。每一字線連接列中之每一儲存元件的控制閘極。或，控制閘極可由字線自身提供。舉例而言，字線WL2提供用於儲存元件324、344及364之控制閘極。實務上，在一字線上可存在數千個儲存元件。For example, NAND string 320 includes select gates 322 and 327 and storage elements 323-326, NAND string 340 includes select gates 342 and 347 and storage elements 343-346, NAND string 360 includes select gates 362 and 367 and storage Elements 363-366. Each NAND string is connected to the source line by its select gate (eg, select gate 327, 347, or 367). The selection line SGS is used to control the source side selection gate. Various NAND strings 320, 340, and 360 by The selection transistors in the gates 322, 342, 362, etc. are selected to be connected to the respective bit lines 321, 341 and 361. These selective transistors are controlled by the drain select line SGD. In other embodiments, the select lines do not necessarily need to be common among the NAND strings; that is, different select lines can be provided for different NAND strings. Word line WL3 is coupled to the control gates for storage elements 323, 343, and 363. Word line WL2 is coupled to control gates for storage elements 324, 344, and 364. Word line WL1 is coupled to control gates for storage elements 325, 345, and 365. Word line WL0 is coupled to control gates for storage elements 326, 346, and 366. It can be seen that each bit line and each NAND string contains a row of storage element arrays or sets. The word lines (WL3, WL2, WL1, and WL0) contain arrays or sets of columns. Each word line connects the control gate of each of the storage elements in the column. Alternatively, the control gate can be provided by the word line itself. For example, word line WL2 provides control gates for storage elements 324, 344, and 364. In practice, there can be thousands of storage elements on a word line.

每一儲存元件可儲存資料。舉例而言，當儲存一個數位資料位元時，將儲存元件之可能臨限電壓(V_TH )之範圍分成兩個範圍，其經指派邏輯資料"1"及"0"。在NAND型快閃記憶體之一實例中，V_TH 在抹除儲存元件之後為負，且經界定為邏輯"1"。程式操作之後的V_TH 為正，且經界定為邏輯"0"。當V_TH 為負且試圖讀取時，儲存元件將開啟以指示邏輯"1"被儲存。當V_TH 為正且試圖讀取操作時，儲存元件將不開啟，此指示邏輯"0"被儲存。儲存元件亦可儲存多個資訊位準，例如，多個數位資料位元。在此狀況下，將V_TH 值之範圍分成資料位準之數目。舉例而言，若儲存 四個資訊位準，則將存在經指派給資料值"11"、"10"、"01"及"00"的四個V_TH 範圍。在NAND型記憶體之一實例中，抹除操作之後的V_TH 為負，且經界定為"11"。正V_TH 值用於狀態"10"、"01"及"00"。經程式化至儲存元件中之資料與元件之臨限電壓範圍之間的特定關係視用於儲存元件之資料編碼機制而定。舉例而言，美國專利第6,222,762號及美國專利申請案公開案2004/0255090(兩者之全部內容均以引用的方式併入本文中)描述用於多狀態快閃儲存元件之各種資料編碼機制。Each storage element can store data. For example, when storing a digital data bit, the range of possible threshold voltages (V _TH ) of the storage elements is divided into two ranges, which are assigned logical data "1" and "0". In one example of a NAND type flash memory, the _VTH is negative after erasing the storage element and is defined as a logical "1". The V _TH after the program operation is positive and is defined as a logic "0". When the _VTH is negative and an attempt is made to read, the storage element will turn on to indicate that the logical "1" is stored. When the _VTH is positive and an attempt is made to read, the storage element will not turn on, indicating that the logic "0" is stored. The storage element can also store multiple information levels, for example, multiple digital data bits. In this case, the range of V _TH values is divided into the number of data levels. For example, if four information levels are stored, there will be four _VTH ranges assigned to the data values "11", "10", "01", and "00". In one example of a NAND type memory, the _VTH after the erase operation is negative and is defined as "11". Positive V _TH values are used for states "10", "01", and "00". The particular relationship between the data programmed into the storage element and the threshold voltage range of the component depends on the data encoding mechanism used to store the component. For example, U.S. Patent No. 6,222,762, and U.S. Patent Application Publication No. 2004/0255090, the entire disclosure of each of which is incorporated herein by reference in its entirety, is incorporated herein.

NAND型快閃記憶體及其操作之相關實例提供於美國專利第5,386,422號、第5,522,580號、第5,570,315號、第5,774,397號、第6,046,935號、第6,456,528號及第6,522,580號中，其中之每一者均以引用的方式併入本文中。Examples of NAND-type flash memory and its operation are provided in U.S. Patent Nos. 5,386,422, 5,522,580, 5,570,315, 5,774,397, 6,046,935, 6,456,528 and 6,522,580, each of which Both are incorporated herein by reference.

當程式化快閃儲存元件時，將程式電壓施加至儲存元件之控制閘極，且使與儲存元件相關聯之位元線接地。將來自通道之電子注入至浮動閘極中。當電子累積於浮動閘極中時，浮動閘極變得帶負電，且儲存元件之V_TH 上升。為了將程式電壓施加至經程式化之儲存元件的控制閘極，將彼程式電壓施加於適當字線上。如上文所論述，NAND串中之每一者之一個儲存元件共用相同字線。舉例而言，當程式化圖3之儲存元件324時，亦將程式電壓施加至儲存元件344及364之控制閘極。When the flash storage component is programmed, a program voltage is applied to the control gate of the storage component and the bit line associated with the storage component is grounded. The electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the _{VTH of the} storage element rises. To apply a program voltage to the control gate of the programmed storage element, the program voltage is applied to the appropriate word line. As discussed above, one of the storage elements of each of the NAND strings shares the same word line. For example, when the storage element 324 of FIG. 3 is programmed, a program voltage is also applied to the control gates of the storage elements 344 and 364.

圖4描繪用於非揮發性儲存器之資料編碼及解碼的系 統。可以減輕雜訊效應之方式來編碼及解碼儲存於非揮發性儲存器中之資料。或許，最重要的雜訊源為1/f雜訊(包括隨機電報信號雜訊)，其為電子截獲及去截獲至位於穿隧氧化物或其他地方之截獲位點中的結果。雜訊並非全然為進入截獲位點中之通道電子之損失的結果，因為其係歸因於以下事實：帶電截獲位點中之電子/電洞藉由帶電截獲位點在其附近施加於通道之區域上的電場來影響通道中之其他電子的流動。此外，通道之在單一截獲位點之影響下的區域將在儲存元件被按比例縮小時形成通道之較大部分。Figure 4 depicts a system for encoding and decoding data in non-volatile storage System. Data stored in non-volatile memory can be encoded and decoded in a manner that mitigates noise effects. Perhaps the most important source of noise is 1/f noise (including random telegraph noise), which is the result of electronic interception and de-interception to intercept sites located in tunnel oxides or elsewhere. The noise is not a complete result of the loss of the channel electrons entering the interception site, because it is due to the fact that the electron/hole in the charged intercept site is applied to the channel in the vicinity by the charged intercept site. The electric field on the area affects the flow of other electrons in the channel. In addition, the area of the channel under the influence of a single intercept site will form a larger portion of the channel as the storage element is scaled down.

許多有雜訊儲存元件經受單一截獲位點，且此結論係以其當前值之二元性質為基礎，亦即，儲存元件在截獲被佔用的情況下具有一當前/V_TH 值且在截獲未被佔用的情況下具有另一相異的當前/V_TH 值。因此，當儲存元件在等效於讀取條件之DC條件下被偏壓時，許多儲存元件展現當前值之雙峰式分布，其中兩個窄分布具有大體上彼此分離之峰值。然而，一些儲存元件經受多於單一有雜訊截獲位點。此外，並非每一截獲位點均可引起有雜訊行為，因為可能存在讀取條件期間一貫地為空或一貫地被佔用之截獲位點。又，與某一電極容易通信且結果在單一整合時間(例如，讀取週期)期間進行為空與被佔用之間的大量轉變之截獲位點將表明少許雜訊或無雜訊，因為其平均效應對於任何整合時間/量測操作而言或多或少為相同的。此可藉由平均化概念或更精確地藉由中央極限定理來解釋。 又，截獲位點之佔用機率可藉由截獲位點使其自身所浸入之電場來調變。另外，對讀取操作更有害的彼等截獲位點為具有較長佔用/不佔用壽命的截獲位點。可將此等截獲位點想作干擾記憶體之正常操作的寄生記憶體設備。寫入/抹除循環可且確實產生額外截獲位點，且導致更多雜訊。Many of the noise storage elements are subject to a single intercept site, and this conclusion is based on the binary nature of their current values, ie, the storage element has a current /V _TH value if the intercept is occupied and is not intercepted. In the case of being occupied, there is another different current /V _TH value. Thus, when the storage element is biased under DC conditions equivalent to the read conditions, many of the storage elements exhibit a bimodal distribution of current values, wherein the two narrow distributions have peaks that are substantially separated from each other. However, some storage elements are subject to more than a single noise interception site. In addition, not every intercepting site can cause noise behavior because there may be intercepting sites that are consistently empty or consistently occupied during reading conditions. Moreover, an interception site that is easily communicable with an electrode and results in a large number of transitions between empty and occupied during a single integration time (eg, read cycle) will indicate little or no noise because of its average effect. More or less the same for any integration time/measurement operation. This can be explained by the averaging concept or more precisely by the central limit theorem. Moreover, the probability of occupancy of the intercepting site can be modulated by the intercepting site to immerse the electric field itself. In addition, those intercepting sites that are more detrimental to the read operation are intercepted sites with longer occupied/non-occupied lifetimes. These intercepting sites can be thought of as parasitic memory devices that interfere with the normal operation of the memory. The write/erase cycle can and does generate additional intercept sites and cause more noise.

結果，讀取操作可受儲存元件中之雜訊影響。儘管錯誤校正編碼及解碼機制可處理由雜訊及其他因素所引起的一些錯誤，但可藉由執行如本文所解釋之多重讀取操作來達成額外優勢。在圖4之編碼/解碼系統中描繪一實例方法，其包括編碼器402、非揮發性儲存器404、LLR(對數概似比)表406及解碼器408。編碼器402接收儲存於非揮發性儲存器404中之資訊位元，亦被稱為使用者資料。資訊位元由矩陣i=[1 0]表示。編碼器402實施錯誤校正編碼過程，其中將同位位元添加至資訊位元以提供由矩陣或碼字v=[1 0 1 0]所表示之資料，此指示兩個同位位元已附加至資料位元。此為導致高同位位元附加項成本之簡化實例。實務上，可利用具有較低附加項之碼。舉例而言，可利用低密度同位檢查(LDPC)碼，亦被稱為界洛格(Gallager)碼。通常將此等碼施加至多個碼字，其跨越許多儲存元件而被編碼，使得同位位元分布於儲存元件當中。關於LDPC之其他資訊可在D. MacKay之Information Theory, Inference and Learning Algorithms(Cambridge University Press 2003，第47章)中找到。可藉由將非揮發性儲存元件程式化至程式化狀態(例如，X=6，其對應於v(見圖9a))來將資料位元映 射至邏輯頁且儲存於非揮發性儲存器404中。在四位元資料矩陣v的情況下，可利用16個程式化狀態。As a result, the read operation can be affected by noise in the storage element. Although error correction coding and decoding mechanisms can handle some of the errors caused by noise and other factors, additional advantages can be achieved by performing multiple read operations as explained herein. An example method is depicted in the encoding/decoding system of FIG. 4, which includes an encoder 402, a non-volatile storage 404, an LLR (Logarithmic Likelihood Ratio) table 406, and a decoder 408. The encoder 402 receives the information bits stored in the non-volatile storage 404, also referred to as user data. The information bits are represented by the matrix i=[1 0]. Encoder 402 implements an error correction encoding process in which a parity bit is added to the information bit to provide data represented by a matrix or codeword v = [1 0 1 0], which indicates that two parity bits have been attached to the data Bit. This is a simplified example of the cost of additional items that result in high parity bits. In practice, codes with lower additional items can be utilized. For example, a low density parity check (LDPC) code, also known as a Gallager code, can be utilized. These codes are typically applied to a plurality of codewords that are encoded across a plurality of storage elements such that the co-located bits are distributed among the storage elements. Additional information about LDPC can be found in D. MacKay's Information Theory, Inference and Learning Algorithms (Cambridge University Press 2003, Chapter 47). Data bits can be mapped by stylizing non-volatile storage elements into a stylized state (eg, X=6, which corresponds to v (see Figure 9a)) The data is directed to the logical page and stored in the non-volatile storage 404. In the case of the four-bit data matrix v, 16 stylized states are available.

隨後，當需要擷取所儲存資料時，讀取非揮發性儲存器。然而，歸因於如所提及之雜訊，讀取狀態有時可被弄錯。在一實例方法中，第一讀取Y1得到由碼字y1=[1 0 1 1]所表示之程式化狀態7，且第二讀取Y2得到由碼字y2=[1 0 1 0]所表示之程式化狀態6。在一可能實施例中，利用迭代機率性解碼過程，其實施對應於編碼器402處之錯誤校正編碼的錯誤校正解碼。關於迭代機率性解碼之其他細節可在上文所提及之D. MacKay本文中找到。迭代機率性解碼試圖藉由將初始機率計量指派給碼字中之每一位元來解碼碼字。機率計量指示每一位元之可靠度，亦即，位元不被弄錯的可能性多大。在一方法中，機率計量為自LLR表406所獲得之對數概似比(LLR)。LLR值為可靠度之量測，吾人利用其而知道自儲存元件所讀取之各種二元位元的值。Then, when it is necessary to retrieve the stored data, the non-volatile storage is read. However, due to the noise as mentioned, the read status can sometimes be mistaken. In an example method, the first read Y1 results in a stylized state 7 represented by the codeword y1=[1 0 1 1], and the second read Y2 is obtained from the codeword y2=[1 0 1 0] Indicates the stylized state 6. In a possible embodiment, a iterative probability decoding process is utilized that implements error correction decoding corresponding to the error correction coding at encoder 402. Additional details regarding iterative probability decoding can be found in the D. MacKay article mentioned above. Iterative probability decoding attempts to decode the codeword by assigning an initial probability measure to each bit in the codeword. The probability measure indicates the reliability of each bit, that is, the probability that the bit is not mistaken. In one method, the probability measure is the log likelihood ratio (LLR) obtained from the LLR table 406. The LLR value is a measure of reliability, which we use to know the values of the various binary bits read from the storage element.

用於位元之LLR係由給出，其中P(v=0│Y)為位元在給定讀取狀態為Y之條件下為0的機率，且P(v=1│Y)為位元在給定讀取狀態為Y之條件下為1的機率。因此，以錯誤校正碼之一或多個同位檢查為基礎，LLR>0指示位元更可能為0而非1，而LLR<0指示位元更可能為1而非0。另外，較大量值指示較大機率或可靠度。因此，具有LLR=20之位元比具有LLR=10之位元更可能為0，且具有LLR=-20之位元比具有LLR=-10之位元更可能為1。 LLR=0指示位元同樣可能為0或1。LLR for bits Given, where P(v=0│Y) is the probability that the bit is 0 given the read state is Y, and P(v=1│Y) is the bit in the given read state. The probability of 1 under the condition of Y. Thus, based on one or more parity checks of the error correction code, LLR > 0 indicates that the bit is more likely to be 0 instead of 1, and LLR < 0 indicates that the bit is more likely to be 1 instead of 0. In addition, a larger magnitude indicates a greater probability or reliability. Therefore, a bit having LLR = 20 is more likely to be 0 than a bit having LLR = 10, and a bit having LLR = -20 is more likely to be 1 than a bit having LLR = -10. LLR=0 indicates that the bit may also be 0 or 1.

可為碼字Y1中之四個位元位置中之每一者提供LLR表406，使得可將LLR分別指派給y1之每一位元1、0、1及1。另外，LLR表可說明多重讀取結果，使得當位元值在不同碼字中為一致時利用具有較大量值之LLR。因此，與僅執行一讀取操作的情況相比，可將具有較大量值之LLR指派給y1中之第一位元。為了說明，y2中之第一位元為1，其與y1中之第一位元一致。同樣地，當位元值在不同碼字中為不一致時利用具有較小量值之LLR。舉例而言，y2中之第四位元為0，其與y1中之第四位元不一致。因此，與僅執行一讀取操作的情況相比，可將具有較小量值之LLR指派給y1中之第四位元。由於自額外讀取操作獲得更多資訊，所以可改良解碼過程，(例如)使得其收斂得更快或在其可能另外在僅進行一讀取操作的情況下不收斂的狀況下收斂。在另一方法中，除非解碼過程(例如)在給定時間量或給定數目之迭代內未成功地收斂，否則不執行第二讀取操作或其他額外讀取操作。The LLR table 406 can be provided for each of the four bit positions in the codeword Y1 such that the LLRs can be assigned to each of the bits 1, 0, 1, and 1 of y1, respectively. In addition, the LLR table can illustrate multiple read results such that LLRs with larger magnitudes are utilized when bit values are consistent across different codewords. Therefore, an LLR having a larger magnitude can be assigned to the first bit in y1 than in the case where only one read operation is performed. To illustrate, the first bit in y2 is 1, which is consistent with the first bit in y1. Similarly, LLRs with smaller magnitudes are utilized when bit values are inconsistent in different codewords. For example, the fourth bit in y2 is 0, which is inconsistent with the fourth bit in y1. Therefore, an LLR having a smaller magnitude can be assigned to a fourth bit in y1 as compared to a case where only one read operation is performed. Since more information is obtained from the extra read operation, the decoding process can be improved, for example, such that it converges faster or converges in situations where it may otherwise not converge with only one read operation. In another approach, the second read operation or other additional read operation is not performed unless the decoding process, for example, does not successfully converge within a given amount of time or a given number of iterations.

解碼器408接收碼字y1及初始LLR。如下文另外進一步所解釋(亦見圖12及圖13)，解碼器408在連續迭代中迭代，其中其判定是否已滿足錯誤編碼過程之同位檢查。若最初滿足所有同位檢查，則解碼過程已收斂且碼字未被弄錯。若尚未滿足一或多個同位檢查，則解碼器將藉由調整與同位檢查不一致之位元中之一或多者的LLR來執行錯誤校正，且接著重新施加同位檢查以判定其是否已被滿足。舉 例而言，可調整LLR之量值及/或極性。若仍不滿足所述之同位檢查，則可在另一迭代中再次調整LLR。調整LLR可導致在一些而非所有狀況下翻轉位元(例如，自0至1或自1至0)。一旦已滿足所述之同位檢查，則在可應用的情況下將下一同位檢查施加至碼字。該過程繼續以試圖滿足所有同位檢查。因此，完成y1之解碼過程以獲得經解碼資訊及同位位元v以及經解碼資訊位元i。The decoder 408 receives the codeword y1 and the initial LLR. As explained further below (see also Figures 12 and 13), decoder 408 iterates in successive iterations, where it determines if the parity check of the error coding process has been met. If all co-location checks are initially satisfied, the decoding process has converged and the codewords have not been mistaken. If one or more parity checks have not been met, the decoder will perform error correction by adjusting the LLR of one or more of the bits that are inconsistent with the parity check, and then reapply the parity check to determine if it has been satisfied. . Lift For example, the magnitude and/or polarity of the LLR can be adjusted. If the co-location check is still not met, the LLR can be adjusted again in another iteration. Adjusting the LLR can cause the bit to be flipped in some, but not all, conditions (eg, from 0 to 1 or from 1 to 0). Once the co-location check has been satisfied, the next parity test is applied to the codeword if applicable. The process continues to attempt to satisfy all co-location checks. Therefore, the decoding process of y1 is completed to obtain decoded information and parity bits v and decoded information bits i.

注意，在所論述之實例中，在來自一或多個後續讀取操作之輔助的情況下解碼來自第一讀取操作之碼字y1。然而，其他方法係可能的。舉例而言，可在來自一或多個先前讀取操作之輔助的情況下解碼來自給定讀取操作之碼字。或，可採取三個讀取操作，其判定兩個一致結果(例如，均為讀取狀態Y1)及一個不一致結果(例如，狀態Y2)，且可在來自不一致結果之輔助的情況下解碼用於一致結果之碼字。可相應地設定LLR表。Note that in the example discussed, the codeword y1 from the first read operation is decoded with assistance from one or more subsequent read operations. However, other methods are possible. For example, a codeword from a given read operation can be decoded with assistance from one or more previous read operations. Alternatively, three read operations can be taken that determine two consistent results (eg, both read state Y1) and an inconsistent result (eg, state Y2), and can be decoded with assistance from inconsistent results. The code word for the consistent result. The LLR table can be set accordingly.

在另一選項中，在無來自不一致結果之輔助的情況下直接解碼用於一致結果之碼字。In another option, the codeword for the consistent result is directly decoded without assistance from the inconsistent result.

因此所論述之實例包括執行兩個或兩個以上讀取以便減輕雜訊效應，及組合此等讀取之結果以修改關於每一儲存元件之狀態的LLR數。當ECC解碼器之迭代過程花費過多時間來達到收斂時，可執行另一讀取操作。在執行額外讀取時，解碼可繼續或可被暫停。或，可自動地執行額外讀取而不管解碼之進度。在第二讀取操作完成之後，可以第二讀取操作為基礎來更新來自第一讀取操作之LLR標誌量 值。在一方法中，可自不同讀取操作添加或另外組合LLR值。舉例而言，針對第一讀取操作及第二讀取操作之給定位元來考慮LLR值為10及-10之有雜訊儲存元件。此表將讀取狀態作為輸入來接收且針對碼字中之每一位元來輸出表示讀取狀態之LLR值。在獲得此等兩個矛盾結果之後，為(例如)0之LLR可用於解碼。解碼引擎將此位元設定為高或低，以便達成收斂。Thus the examples discussed include performing two or more reads to mitigate noise effects, and combining the results of such reads to modify the number of LLRs for each storage element. Another read operation can be performed when the iterative process of the ECC decoder takes too much time to reach convergence. When an additional read is performed, the decoding may continue or may be suspended. Or, additional readings can be performed automatically regardless of the progress of the decoding. After the second read operation is completed, the LLR flag amount from the first read operation may be updated based on the second read operation value. In one method, LLR values can be added or otherwise combined from different read operations. For example, a noise storage element having an LLR value of 10 and -10 is considered for the positioning element of the first read operation and the second read operation. This table receives the read status as an input and outputs an LLR value indicating the read status for each bit in the codeword. After obtaining these two contradictory results, an LLR of, for example, 0 can be used for decoding. The decoding engine sets this bit high or low to achieve convergence.

執行兩個以上讀取操作亦為可能的。一方法係添加或採取來自所有讀取之LLR結果的平均值或平均數。舉例而言，LLR值對於第一、第二及第三讀取操作之給定位元可分別為20、10及-10，在此狀況下，平均值為6.6。此為便利之簡化方法。其他方法可考慮以下事實：為20之LLR與為10之LLR相比指示給定結果之多於兩倍的機率，使得(例如)為10與20之LLR經組合至與10相比更靠近於20的LLR。It is also possible to perform more than two read operations. One method adds or takes an average or average from all read LLR results. For example, the LLR values may be 20, 10, and -10 for the first, second, and third read operations, respectively, in which case the average is 6.6. This is a simplified method of convenience. Other methods may consider the fact that the LLR of 20 indicates more than twice the probability of a given result compared to an LLR of 10, such that LLRs of, for example, 10 and 20 are combined closer to 10 20 LLR.

另一方法以機率密度函數f1(u│X)及f2(v)為基礎來建構LLR值，如下文進一步所描述。Another method constructs the LLR values based on the probability density functions f1(u│X) and f2(v), as further described below.

又，在第二讀取操作之結果已變得可用時，迭代過程可能已推進，且許多LLR值可能已被更新以試圖收斂。第二讀取之結果可因此與當前可用之第一讀取的即時經迭代結果或與第一讀取之原始結果組合，或可利用混合方法。Also, as the results of the second read operation have become available, the iterative process may have advanced and many LLR values may have been updated to attempt to converge. The result of the second reading may thus be combined with the currently available first iterative result of the first reading or with the original result of the first reading, or a hybrid method may be utilized.

另外，若讀取操作中之每一者產生相同結果，則對於給定位元，吾人可為位元指派較高量值LLR。此峰值LLR(LLRpeak)可能稍微高於可自僅單讀取(LLRsingle)所獲得之LLR。若讀取系列得到不同結果，則可產生較低最 終LLR。聚集讀取系列之一方法係採取單讀取LLR之平均值且使其乘以正規化因子(諸如，LLRpeak/LLRsingle)，使得最終LLR=多重讀取之經平均化LLR×│LLRpeak/LLRsingle∣。Additionally, if each of the read operations produces the same result, then for a given location, we can assign a higher magnitude LLR to the bit. This peak LLR (LLRpeak) may be slightly higher than the LLR that can be obtained from a single read (LLRsingle). If the reading series gets different results, it can produce lower and most Final LLR. One of the methods of the aggregated read series is to take a single read LLR average and multiply it by a normalization factor (such as LLRpeak/LLRsingle) so that the final LLR = multi-read averaged LLR × │ LLRpeak / LLRsingle .

在實際實施例中，以第一讀取結果為基礎之用於收斂的迭代可在獲得第二讀取結果之前開始。一旦獲得第二讀取結果及(一般而言)所有後續讀取結果，則用於將後續讀取結果併入至迭代過程中之一策略係假設自儲存元件所讀取之所有原始結果仍可用。在此狀況下，吾人可簡單地中斷當前迭代且重新以如上文所計算之最終LLR而開始。用於聚集LLR值之另一策略係利用當前經迭代LLR值來組合重新獲取之讀取結果。此可(例如)藉由相對於先前結果而用1/(n-1)來加權第n個讀取結果以使得所有讀取結果經同樣加權而完成。In a practical embodiment, the iteration for convergence based on the first read result may begin before the second read result is obtained. Once the second read result and (generally) all subsequent read results are obtained, one of the strategies used to incorporate subsequent read results into the iterative process assumes that all raw results read from the storage element are still available . In this case, we can simply interrupt the current iteration and start again with the final LLR as calculated above. Another strategy for aggregating LLR values is to combine the re-acquired read results with the current iterative LLR values. This can be done, for example, by weighting the nth read result with 1/(n-1) relative to the previous result such that all read results are equally weighted.

可藉由當前迭代進行得有多好來判定哪一策略更適當。It can be determined by how good the current iteration is to determine which strategy is more appropriate.

可藉由一品質計量來量測迭代之"良好性"，諸如，迭代解碼過程是否在給定時間週期及/或給定數目之迭代內接近收斂，及/或已滿足特定數目之同位檢查。另外，計量可在解碼期間用於即時適應性決策過程，例如，藉由選擇繼續當前解碼過程，而不執行額外讀取，在以額外讀取為基礎來調整最近利用之LLR時繼續解碼，或以額外讀取為基礎而利用新的初始LLR來重新開始解碼。The "goodness" of the iterations can be measured by a quality measure, such as whether the iterative decoding process approaches convergence for a given time period and/or a given number of iterations, and/or a certain number of parity checks have been met. In addition, metering can be used for immediate adaptive decision making during decoding, for example, by selecting to continue the current decoding process without performing additional reads, continuing to decode when the recently utilized LLR is adjusted based on additional reads, or The decoding is resumed with the new initial LLR based on the extra read.

可(例如)藉由獲得非揮發性儲存元件集合之經程式化狀態之機率密度函數來開發LLR或其他機率性計量，如下。The LLR or other probabilistic measure can be developed, for example, by obtaining a probability density function of the programmed state of the non-volatile storage element set, as follows.

圖5a為用於針對非揮發性儲存元件集合來獲得第一機率密度函數f1之過程的流程圖。步驟500包括將隨機資料程式化至M個儲存元件之集合中之所有儲存元件。亦即，假設儲存元件為具有n個級或程式化狀態之多級儲存元件，在程式化之後，儲存元件中之約M/n個經程式化至第一狀態，M/n個經程式化至第二狀態，等等。舉例而言，在一可能方法中，n=16個狀態，其中每一狀態由四位元碼字表示。在步驟502處，將表示第k個程式化狀態之索引k初始化為零。步驟506包括針對經寫入至狀態k之每一儲存元件來進行V_TH 之N個重複量測，其中N為諸如100之大數目。Figure 5a is a flow diagram of a process for obtaining a first probability density function f1 for a non-volatile storage element set. Step 500 includes staging the random data to all of the storage elements in the set of M storage elements. That is, assuming that the storage element is a multi-level storage element having n stages or stylized states, after programming, about M/n of the storage elements are programmed to the first state, and M/n are stylized. To the second state, and so on. For example, in one possible approach, n = 16 states, each of which is represented by a four-bit codeword. At step 502, the index k representing the kth stylized state is initialized to zero. Step 506 includes performing N repeated measurements of the _VTH for each of the storage elements that are written to state k, where N is a large number such as 100.

此等為在測試環境中在與在儲存設備之生產利用期間所利用之精確度相比為更高精確度上所進行的量測。These are measurements made in the test environment at a higher accuracy compared to the accuracy utilized during production utilization of the storage device.

步驟508包括藉由平均化用於每一儲存元件之N個量測而針對每一儲存元件來獲得無雜訊V_TH 。無雜訊V_TH 指代本質上無在讀取操作期間特定地招致之雜訊的臨限電壓。此導致儲存元件集合上的約M/n個無雜訊V_TH 值。舉例而言，圖6a描繪電壓臨限值讀數之分布。對於(例如)狀態0而言，直方圖600展示落入用於實例第一儲存元件之V_TH 之不同範圍或桶形之讀數的數目。直方圖602係針對用於實例第二儲存元件之狀態1，且直方圖604係針對用於實例第三儲存元件之狀態15。未描繪用於中間狀態之直方圖。圖6b描繪無雜訊電壓臨限值讀數。舉例而言，V_TH-NF0 、V_TH-NF1 、…、V_TH-NF15 分別表示用於實例第一、第二及第三儲存元件之狀態0、1、…、15之無雜訊電壓臨限值讀數。注意，亦可 平均化原始V_TH 讀數來代替利用圖6a之直方圖。另外，可利用除了平均化以外之統計技術。Step 508 includes obtaining a noise free _VTH for each storage element by averaging N measurements for each storage element. The no-noise _VTH refers to a threshold voltage that is essentially free of noise that is specifically incurred during a read operation. This results in approximately M/n non-noise _VTH values on the set of storage elements. For example, Figure 6a depicts the distribution of voltage threshold readings. For, for example, state 0, histogram 600 shows the number of readings that fall into different ranges or buckets of the _VTH for the first storage element of the example. The histogram 602 is for state 1 for the example second storage element and the histogram 604 is for state 15 for the example third storage element. A histogram for the intermediate state is not depicted. Figure 6b depicts the noise-free threshold reading. For example, V _TH-NF0 , V _TH-NF1 , ..., V _TH-NF15 represent the noise-free voltages of states 0, 1, ..., 15 for the first, second, and third storage elements, respectively. Limit reading. Note that the original _VTH reading can also be averaged instead of using the histogram of Figure 6a. In addition, statistical techniques other than averaging can be utilized.

步驟510(圖5a)包括利用來自每一儲存元件之無雜訊V_TH 來建構無雜訊V_TH 跨越集合中經程式化至狀態k之所有儲存元件之分布的直方圖。舉例而言，圖6c描繪無雜訊電壓臨限值讀數(例如，沒有讀取雜訊之讀數)之分布。可能仍存在其他雜訊。對於(例如)用於實例第一儲存元件之狀態0而言，直方圖650展示落入V_TH 之不同範圍或桶形之讀數的數目。直方圖652係針對用於實例第二儲存元件之狀態1，且直方圖654係針對用於實例第三儲存元件之狀態15。未描繪用於中間狀態之直方圖。此等直方圖為指示M個儲存元件單元中之多少個具有在指定範圍內之V_TH 的條形圖。步驟512包括正規化及曲線擬合直方圖以獲得f1(u│X=狀態k)，其為指示在儲存元件經程式化至狀態k時儲存元件將具有V_TH =u之機率的機率密度函數(pdf)。舉例而言，在k=0的情況下，函數f1(u│X=0)為在吾人隨機地自記憶體晶片選擇儲存元件的情況下(其中儲存元件已被程式化(寫入)至狀態0)其無雜訊V_TH 將為u的機率。正規化直方圖(例如，直方圖650、650、…654中之一者)可包括以M除條形圖之高度，使得用於給定狀態之每一條形之高度的總和為一。Step 510 (Fig. 5a) includes constructing a histogram of the distribution of all memory elements programmed into the set of non-noise _VTHs across the set to state k using the noise-free _VTH from each of the storage elements. For example, Figure 6c depicts the distribution of no noise voltage threshold readings (eg, readings without reading noise). There may still be other noise. For, for example, state 0 for the example first storage element, histogram 650 shows the number of readings that fall into different ranges or buckets of the _VTH . The histogram 652 is for state 1 for the example second storage element, and the histogram 654 is for state 15 for the example third storage element. A histogram for the intermediate state is not depicted. These histogram storage elements M indicating the number of units within the specified range has a bar graph of V _TH. Step 512 includes normalizing and curve fitting the histogram to obtain f1 (u│X=state k), which is a probability density function indicating that the storage element will have a probability of _VTH =u when the storage element is programmed to state k. (pdf). For example, in the case of k=0, the function f1(u│X=0) is in the case where we randomly select a storage element from the memory chip (where the storage element has been programmed (written) to the state) 0) Its noise-free V _TH will be the probability of u. Normalizing the histogram (eg, one of the histograms 650, 650, ... 654) may include dividing the height of the bar graph by M such that the sum of the heights of each of the bars for a given state is one.

在步驟514處，儲存結果，例如，包括界定函數f1(u│X=狀態k)之資料。若將在決策步驟516處分析下一狀態，則在步驟504處遞增狀態索引，且處理再次在步驟506-514處 進行。針對所有記憶體狀態來重複此處理。該過程結束於步驟518處，此時，已獲得pdf f1(u│X=0)、f1(u│X=1)、f1(u│X=2)、f1(u∣X=3)、…f1(u│X=n)，其中n+1為狀態之數目。圖6d描繪用於非揮發性儲存元件集合之不同狀態之電壓臨限值的機率分布。此處，描繪針對f1(u│X=0)之實例分布660、針對f1(u│X=0)之實例分布662、…及針對f1(u│X=15)之實例分布664，其中存在16個狀態。未描繪用於中間狀態之分布。At step 514, the result is stored, for example, including data defining a function f1 (u│X = state k). If the next state is to be analyzed at decision step 516, the state index is incremented at step 504 and the process is again at steps 506-514. get on. This process is repeated for all memory states. The process ends at step 518, at which point pdf f1(u│X=0), f1(u│X=1), f1(u│X=2), f1(u∣X=3), ...f1(u│X=n), where n+1 is the number of states. Figure 6d depicts the probability distribution of voltage thresholds for different states of a non-volatile storage element set. Here, an instance distribution 660 for f1 (u│X=0), an instance distribution 662 for f1 (u│X=0), and an instance distribution 664 for f1(u│X=15) are depicted, where 16 states. The distribution for the intermediate state is not depicted.

圖5b為用於針對非揮發性儲存元件集合來獲得第二機率密度函數f2之過程的流程圖。步驟520、522及526對應於圖5a之步驟500、502及506。另外，可相對於圖5a之對應步驟而重複此等步驟，或來自圖5a之步驟500、502及506之結果可用於在圖5b之步驟528處開始。步驟528包括自每一量測中減去無雜訊V_TH 以獲得經移位量測。舉例而言，圖7a描繪自無雜訊V_TH 之此等經移位量測或偏差的直方圖。步驟530包括建構經移位量測跨越經程式化至狀態k之所有儲存元件之分布的直方圖。圖7b描繪此直方圖之實例。步驟532包括正規化及曲線擬合直方圖以獲得函數f2(v)，其為指示在儲存元件經程式化至狀態k時儲存元件將具有與無雜訊V_TH 偏差v之讀取V_TH 之機率的pdf。函數f2(v)為在吾人隨機地自記憶體晶片選擇儲存元件且進行單一量測的情況下所得V_TH 為與"真"或"無雜訊"V_TH 相距距離"v"的機率。圖7c至圖7e描繪用於不同狀態之f2(v)的實例。具體言之，圖7c描繪用於狀態0之電壓臨限值偏差之 機率分布，圖7d描繪用於狀態1之電壓臨限值偏差之機率分布，且圖7e描繪用於狀態15之電壓臨限值偏差之機率分布。注意，該等圖指示該等分布有可能稍微不同。f1之分布可類似地不同。Figure 5b is a flow diagram of a process for obtaining a second probability density function f2 for a non-volatile storage element set. Steps 520, 522, and 526 correspond to steps 500, 502, and 506 of Figure 5a. Alternatively, the steps may be repeated with respect to the corresponding steps of Figure 5a, or the results from steps 500, 502, and 506 of Figure 5a may be used to begin at step 528 of Figure 5b. Step 528 includes subtracting the noise-free _VTH from each measurement to obtain a shifted measurement. For example, Figure 7a depicts a histogram of such shifted measurements or deviations from a no-noise _VTH . Step 530 includes constructing a histogram that shifts the distribution across all of the storage elements programmed to state k. Figure 7b depicts an example of this histogram. Step 532 includes normalization and curve fitting function to obtain a histogram f2 (v), which is indicative of the time k to the state storage element having the read noiseless deviation v of V _TH V _TH of the storage element via stylized The probability of pdf. Function f2 (v) is obtained with the V _TH is "true" or "noiseless" V _TH at a distance "v" at the probability I randomly selected from the storage element of memory chips and for the case where a single measurement. Figures 7c to 7e depict examples of f2(v) for different states. In particular, Figure 7c depicts the probability distribution for the voltage threshold deviation for state 0, Figure 7d depicts the probability distribution for the voltage threshold deviation for state 1, and Figure 7e depicts the voltage threshold for state 15 The probability distribution of the value deviation. Note that these figures indicate that the distributions may be slightly different. The distribution of f1 can be similarly different.

在步驟534處，儲存結果，例如，包括界定函數f2(v)之資料。若將在決策步驟536處分析下一狀態，則在步驟524處遞增狀態索引，且處理再次在步驟526-534處進行。針對所有記憶體狀態來重複此處理。該過程結束於步驟538處，此時，已獲得用於所有狀態之pdf f2(v)。At step 534, the result is stored, for example, including information defining the function f2(v). If the next state is to be analyzed at decision step 536, the state index is incremented at step 524 and processing proceeds again at steps 526-534. This process is repeated for all memory states. The process ends at step 538, at which point pdf f2(v) for all states has been obtained.

注意，pdf可在無雜訊V_TH 分布可改變時隨著記憶體設備之壽命/循環而變化。可用於獲得pdf之V_TH 之量測可在不同設備壽命時執行及經平均化，(例如)以獲得pdf及所得LLR(其表示平均設備壽命)。Note that pdf can vary with the lifetime/cycle of the memory device when the noise-free _VTH distribution can be changed. Measurements of _{VTH that} can be used to obtain pdf can be performed and averaged over different device lifetimes, for example, to obtain pdf and resulting LLR (which represents average device life).

圖8為用於自非揮發性儲存元件獲得用於解碼讀取資料之對數概似比(LLR)之過程的流程圖。在步驟800處，以f1(u)及f2(v)為基礎，吾人計算條件機率P(Y₁ ,Y₂ │X)。此為以下情況的機率：在經寫入至儲存元件時給定彼狀態X的情況下，第一讀取得到Y₁ 、第二讀取得到Y₂ ，等等。該機率可在存在兩個讀取操作時以形式P(Y₁ ,Y₂ │X)來表達，或在存在N個讀取操作時通常以形式P(Y₁ ,Y₂ ,…, Y_N │X)來表達。可在測試環境中針對量測來判定機率。在步驟810處，以此等機率及貝斯(Bayes)規則為基礎，吾人在存在兩個讀取操作時計算P(X│Y1,Y2)，或在存在N個讀取操作時通常計算P(X│Y1,Y2,Y3,Y4…Y_N )。P(X│Y1,Y2)為以下情況 的機率：在給定第一讀取結果Y1及第二讀取結果Y2的情況下，經程式化狀態為X。步驟820包括在給定N個讀取之所有可能y值的情況下計算每一位元之LLR，且步驟830包括將結果儲存於(例如)一或多個表中。亦即，LLR經指派給用於表示經程式化狀態之每一碼字中的每一位元。在記憶體設備之操作期間，所提供之表可用於在一可能方法中在給定多重讀取操作之結果的情況下尋找用於解碼之初始LLR數。8 is a flow diagram of a process for obtaining a logarithmic power ratio (LLR) for decoding read data from a non-volatile storage element. At step 800, based on f1(u) and f2(v), we calculate the conditional probability P(Y ₁ , Y ₂ │X). This is the probability that in the case where a state X is given when writing to the storage element, the first reading yields Y ₁ , the second reading yields Y ₂ , and so on. This probability can be expressed in the form P(Y ₁ , Y ₂ │X) when there are two read operations, or in the form P (Y ₁ , Y ₂ ,..., Y _N when there are N read operations). │X) to express. The probability can be determined for measurement in the test environment. At step 810, based on such odds and Bayes rules, we calculate P(X│Y1, Y2) when there are two read operations, or generally P when there are N read operations ( X│Y1, Y2, Y3, Y4...Y _N ). P(X│Y1, Y2) is a probability that, given the first reading result Y1 and the second reading result Y2, the stylized state is X. Step 820 includes calculating the LLR for each bit given all of the possible y values for the N reads, and step 830 includes storing the results in, for example, one or more tables. That is, the LLR is assigned to each bit in each codeword used to represent the programmed state. During operation of the memory device, the provided table can be used to find the initial number of LLRs for decoding in the case of a given multiple read operation in a possible method.

注意，此處所概述之技術假設讀取雜訊與"無雜訊"V_TH 之間的獨立性。該技術可經擴展以涵蓋讀取雜訊值與"無雜訊"V_TH 不獨立的狀況。此本質上涉及自實驗資料建構接合pdf f(u,v₁ ,v₂ ,…v_n )。Note that the technique outlined here assumes the independence between reading noise and "no noise" _VTH . The technology can be extended to cover situations where the read noise value is not independent of the "no noise" _VTH . This essentially involves constructing the joint pdf f(u, v ₁ , v ₂ , ... v _n ) from the experimental data.

圖9a描繪為非揮發性儲存元件之不同經程式化狀態提供多位元碼字的表。如先前所提及，可藉由碼字來表示儲存元件之每一程式化狀態。舉例而言，在16個狀態的情況下，可利用四位元碼字。另外，將LLR或其他可靠度計量與指示位元未被弄錯之機率的每一位元相關聯(較高量值LLR指示位元未被弄錯之較高機率)。圖9a描繪在經程式化狀態0至15之下的行中之位元值或碼字。將位元位置描繪為頂部、較高、上部及下部。下部位元為最高有效位元且頂部位元為最低有效位元。因此，用於狀態0之碼字為1111，用於狀態1之碼字為1110，等等。如圖9b所指示，將LLR與每一位元相關聯。Figure 9a depicts a table providing multi-bit codewords for different programmed states of non-volatile storage elements. As mentioned previously, each stylized state of the storage element can be represented by a codeword. For example, in the case of 16 states, a four-bit codeword can be utilized. In addition, the LLR or other reliability measure is associated with each bit of the probability that the bit is not mistaken (the higher magnitude LLR indicates a higher probability that the bit was not mistaken). Figure 9a depicts the bit value or codeword in a row below the stylized states 0-15. The bit positions are depicted as top, upper, upper, and lower. The lower part element is the most significant bit and the top bit is the least significant bit. Therefore, the codeword for state 0 is 1111, the codeword for state 1 is 1110, and so on. As indicated in Figure 9b, the LLR is associated with each bit.

圖9b描繪以第一讀取結果為基礎而為碼字之每一位元提 供LLR之初始值的表。LLR由值M1、M2及M3表示，其中M1<M2<M3。如先前所提及，正LLR指示0位元，負LLR指示1位元，且較大量值指示較大可靠度或正確性機率。舉例而言，對於處於狀態0至5之下部位元而言，LLR=-M3，其指示此等位元具有為1之高機率。此可被直觀地看出，因為讀取狀態Y1遠離於經程式化狀態(例如，若干狀態遠)的機率較小。因此，用於狀態5之下部位元之LLR為-M3(較高正確性機率)，因為讀取狀態可能必須自經程式化狀態(例如，狀態8(其中下部位元為0，而非1))離開三個狀態。然而，用於狀態6之下部位元之LLR為-M2(中間正確性機率)，因為讀取狀態可能必須針對待弄錯之位元離開兩個狀態。類似地，用於狀態7之下部位元之LLR為-M1(較低正確性機率)，因為讀取狀態可能必須針對待弄錯之位元離開僅一個狀態。類似推理適用於其他位元位置。舉例而言，用於頂部位元之LLR指示相對較低之正確性機率，因為僅一個狀態之錯誤可能導致位元為不正確的。Figure 9b depicts each bit of the codeword based on the first read result A table for the initial values of LLRs. LLR is represented by values M1, M2, and M3, where M1 < M2 < M3. As mentioned previously, a positive LLR indicates 0 bits, a negative LLR indicates 1 bit, and a larger magnitude indicates a greater reliability or correctness probability. For example, for a location element below state 0 to 5, LLR = -M3, which indicates that these bits have a high probability of being one. This can be seen visually because the probability of reading state Y1 being far away from the stylized state (eg, several states are far) is small. Therefore, the LLR used for the location element below state 5 is -M3 (higher probability of correctness) because the read state may have to be self-programmed (eg, state 8 (where the lower part is 0 instead of 1) )) Leave three states. However, the LLR used for the location element below state 6 is -M2 (intermediate correctness probability) because the read state may have to leave both states for the bit to be missed. Similarly, the LLR for the location element below state 7 is -M1 (lower probability of correctness) because the read state may have to leave only one state for the bit to be misplaced. Similar reasoning applies to other bit positions. For example, the LLR for the top bit indicates a relatively low probability of correctness, since only one state error may result in the bit being incorrect.

圖9c描繪以第二讀取結果為基礎而為碼字之每一位元提供對由解碼器所利用之LLR之當前值之調整的表。當執行第二或其他額外讀取操作時，可調整LLR值。在一可能方法中，在已開始解碼第一讀取結果之後，對當前由解碼器所利用之LLR值進行調整。如結合(例如)圖12及圖13進一步所解釋，迭代機率性解碼涉及將錯誤校正碼之同位檢查施加至讀取碼字。若同位檢查失敗，則解碼器在朝向滿足同位檢查的方向上調整LLR值。可在連續迭代中重複此過 程。有時，調整結束於不正確位元被翻轉且同位檢查被滿足時。在此狀況下，在可應用的情況下執行下一同位檢查。因此，在進行解碼時，可對LLR之當前(最近利用之)值進行調整。Figure 9c depicts a table providing adjustments to the current value of the LLR utilized by the decoder for each bit of the codeword based on the second read result. The LLR value can be adjusted when performing a second or other additional read operation. In a possible method, after the first read result has been decoded, the LLR value currently utilized by the decoder is adjusted. As explained further in connection with, for example, Figures 12 and 13, the iterative probability decoding involves applying a parity check of the error correction code to the read codeword. If the parity check fails, the decoder adjusts the LLR value in the direction that satisfies the parity check. This can be repeated in successive iterations Cheng. Sometimes, the adjustment ends when the incorrect bit is flipped and the parity check is satisfied. In this case, the next parity check is performed if applicable. Therefore, the current (most recently utilized) value of the LLR can be adjusted while decoding is in progress.

通常，若第二讀取值與第一讀取值一致，則基於每一位元，可在量值方面增加當前LLR以指示位元具有較大可靠度。舉例而言，若第一讀取為Y1=狀態7(碼字1011)且第二讀取為Y2=狀態6(碼字1010)，則可針對頂部位元來調整LLR以指示位元為1之較大機率。注意，以第一讀取為基礎(圖9b)，用於位元之初始LLR為-M1，但解碼過程可能已將此值改變至另一負或甚至正值。在此實施例中，將調整施加至當前值。舉例而言，LLR當前可為-M2，在此狀況下，可能將其調整至在量值方面大於M2之負值。或，LLR當前可為+4，在此狀況下，可能將其調整至+1。Generally, if the second read value coincides with the first read value, based on each bit, the current LLR may be added in terms of magnitude to indicate that the bit has greater reliability. For example, if the first read is Y1=state 7 (codeword 1011) and the second read is Y2=state 6 (codeword 1010), the LLR can be adjusted for the top bit to indicate that the bit is 1 A greater chance. Note that based on the first read (Fig. 9b), the initial LLR for the bit is -M1, but the decoding process may have changed this value to another negative or even positive value. In this embodiment, the adjustment is applied to the current value. For example, the LLR can currently be -M2, in which case it may be adjusted to a negative value greater than M2 in magnitude. Or, the LLR can currently be +4, in which case it may be adjusted to +1.

注意，可以不同方式來表達調整，例如，藉由加上或減去常數，或藉由函數。不需要利用表。舉例而言，可以LLR之量值為基礎來進行調整。可能沒有必要利用較高量值來調整LLR，或可在此狀況下進行相對較小調整。相反地，可在LLR具有較小量值時進行相對較大調整。通常，調整可以諸如以下各項之因素為基礎：解碼過程有多麼接近於收斂(例如，以迭代之數目及/或所滿足之同位檢查之數目為基礎)、LLR之當前值及/或第二或其他額外讀取狀態。亦可執行不同調整之測試以判定令人滿意的調整。所利用之指定調整可適合於特定記憶體設備實施例。Note that the adjustment can be expressed in different ways, for example, by adding or subtracting a constant, or by a function. No need to use the table. For example, the adjustment can be made based on the magnitude of the LLR. It may not be necessary to use a higher magnitude to adjust the LLR, or a relatively small adjustment can be made under this condition. Conversely, a relatively large adjustment can be made when the LLR has a small magnitude. In general, the adjustment can be based on factors such as how close the decoding process is to convergence (eg, based on the number of iterations and/or the number of parity checks satisfied), the current value of the LLR, and/or the second Or other extra read status. Different adjustment tests can also be performed to determine a satisfactory adjustment. The specified adjustments utilized may be adapted to a particular memory device embodiment.

圖10a至圖10d描繪以第一讀取結果及第二讀取結果為基礎而為碼字之每一位元提供LLR之初始值的表。在一方法中，可以多重讀取操作之結果為基礎來設定用於解碼過程中之LLR之初始值。可針對碼字之每一位元位置來提供單獨的表。舉例而言，圖10a、圖10b、圖10c及圖10d分別為頂部位元、較高位元、上部位元及下部位元提供LLR值。舉例而言，可以兩個讀取結果Y1及Y2為基礎來讀取每一表。在讀取每一表之後，將用於每一位元之初始LLR提供至解碼過程。注意，表在利用三個或三個以上讀取操作的情況下可具有三個或三個以上維度。Figures 10a through 10d depict a table that provides an initial value of LLR for each bit of a codeword based on the first read result and the second read result. In one method, the initial value of the LLR used in the decoding process can be set based on the result of the multiple read operation. A separate table can be provided for each bit position of the codeword. For example, FIGS. 10a, 10b, 10c, and 10d provide LLR values for the top bit, the upper bit, the upper part, and the lower part, respectively. For example, each table can be read based on two read results Y1 and Y2. After reading each table, the initial LLR for each bit is provided to the decoding process. Note that the table can have three or more dimensions with three or more read operations.

圖11a為用於解碼表示非揮發性儲存元件之狀態之碼字之過程的流程圖，其中以第一讀取操作及第二讀取操作為基礎來獲得初始機率計量。步驟1100包括開始第一讀取操作。讀取操作可包括感測儲存元件之V_TH 是高於還是低於許多比較點(步驟1102)。比較點中之一些可導致硬位元(hard bit)，例如，用於分離程式化狀態之V_TH 範圍之比較點，且比較點中之一些可導致軟位元(soft bit)，例如，用於平分程式化狀態之V_TH 範圍之比較點。在一方法中，讀取操作可利用第一比較點集合，接著利用平分第一集合之第二比較點集合。Figure 11a is a flow diagram of a process for decoding a codeword representing the state of a non-volatile storage element, wherein an initial probability meter is obtained based on a first read operation and a second read operation. Step 1100 includes initiating a first read operation. The reading operation can include sensing whether the _VTH of the storage element is above or below a plurality of comparison points (step 1102). Some of the comparison points may result in a hard bit, for example, a comparison point for separating the _VTH range of the stylized state, and some of the comparison points may result in a soft bit, for example, The comparison point of the V _TH range of the stylized state. In one method, the read operation may utilize a first set of comparison points, followed by a second set of comparison points that bisect the first set.

每一比較點判定可被視為感測操作，此總體上可為讀取操作。實務上，可在讀取操作期間讀取許多儲存元件。舉例而言，可在許多儲存元件之上施加錯誤校正編碼，在此狀況下，自彼等儲存元件獲得讀取結果以用於解碼中。以 感測為基礎，判定儲存元件之程式化狀態(步驟1104)，且以程式化狀態為基礎來指派碼字(步驟1106)。舉例而言，可在存在16個狀態時利用圖9a之碼字或位元指派。在步驟1108處開始第二讀取操作，諸如，藉由再次感測儲存元件之V_TH 是高於還是低於比較點(步驟1110)。以感測為基礎，再次判定儲存元件之程式化狀態(步驟1112)。Each comparison point decision can be considered a sensing operation, which can be a read operation in general. In practice, many storage elements can be read during a read operation. For example, an error correction code can be applied over a number of storage elements, in which case the read results are obtained from the storage elements for use in decoding. Based on the sensing, the stylized state of the storage element is determined (step 1104) and the codeword is assigned based on the stylized state (step 1106). For example, the codeword or bit assignment of Figure 9a can be utilized in the presence of 16 states. A second read operation is initiated at step 1108, such as by again sensing whether the _VTH of the storage element is above or below the comparison point (step 1110). Based on the sensing, the stylized state of the storage element is again determined (step 1112).

步驟1114包括將初始機率計量指派給碼字中之每一位元，其中計量以第一讀取結果及第二讀取結果為基礎來指示位元之可靠度。舉例而言，此步驟可涉及讀取圖10a至圖10d之表以獲得LLR，但亦可利用其他機率性計量。步驟1116包括利用初始機率計量來執行迭代解碼，及在連續迭代中調整機率計量。在步驟1116之迭代之後，若在決策步驟1118處解碼收斂(例如，滿足錯誤校正碼之所有同位檢查)，則將經解碼碼字儲存為最終讀取結果(步驟1120)。Step 1114 includes assigning an initial probability measure to each bit in the codeword, wherein the metering indicates the reliability of the bit based on the first read result and the second read result. For example, this step may involve reading the tables of Figures 10a through 10d to obtain LLRs, but may also utilize other probabilistic measurements. Step 1116 includes performing iterative decoding using the initial probability metering and adjusting the probability metering in successive iterations. After the iteration of step 1116, if the decoding converges at decision step 1118 (eg, all co-located checks satisfying the error correction code), the decoded codeword is stored as the final read result (step 1120).

注意，可在同位檢查擴展於碼字之上的同時解碼與錯誤校正過程相關聯之碼字。或者，單一碼字有可能在一或多個同位檢查涉及僅彼碼字時由自身解碼。若解碼未收斂，則(例如)在步驟1122處宣告錯誤或可執行額外讀取操作。Note that the codeword associated with the error correction process can be decoded while the parity check extends over the codeword. Alternatively, it is possible for a single codeword to be decoded by itself when one or more parity checks involve only one codeword. If the decoding does not converge, then an error is declared, for example, at step 1122 or an additional read operation can be performed.

圖11b為用於解碼表示非揮發性儲存元件之狀態之碼字之過程的流程圖，其中以第一讀取操作為基礎來獲得初始機率計量，接著以第二讀取操作為基礎來進一步調整經調整機率計量。如所論述，在一實施例中，可臨時地暫停解碼過程，使得以一或多個額外讀取結果為基礎來進一步調整相對於初始LLR值而經調整之當前LLR值。步驟1130、 1132、1134及1136分別對應於圖11a之步驟1100、1102、1104及1106。步驟1138包括將初始機率計量指派給碼字中之每一位元，其中計量以第一讀取結果為基礎來指示位元之可靠度。舉例而言，此步驟可涉及讀取圖9b之表以獲得LLR，但亦可利用其他機率性計量。步驟1140包括利用初始機率計量來執行迭代解碼，及在連續迭代中調整機率計量。若在決策步驟1142處解碼在給定時間週期(例如，流逝時間)及/或給定數目之迭代內收斂，則將經解碼碼字儲存為最終讀取結果(步驟1144)。若解碼(諸如)藉由滿足指定數目之同位檢查而朝向收斂前進，則解碼繼續。適當軟體、硬體及/或韌體可提供於解碼器中以加強此供應。Figure 11b is a flow diagram of a process for decoding a codeword representing a state of a non-volatile storage element, wherein an initial probability meter is obtained based on a first read operation, and then further adjusted based on the second read operation It is measured by the probability of adjustment. As discussed, in an embodiment, the decoding process may be temporarily suspended such that the current LLR value adjusted relative to the initial LLR value is further adjusted based on one or more additional read results. Step 1130, 1132, 1134, and 1136 correspond to steps 1100, 1102, 1104, and 1106 of Figure 11a, respectively. Step 1138 includes assigning an initial probability measure to each bit in the codeword, wherein the metering indicates the reliability of the bit based on the first read result. For example, this step may involve reading the table of Figure 9b to obtain an LLR, but may also utilize other probabilistic measures. Step 1140 includes performing iterative decoding with initial probability metering and adjusting the probability metering in successive iterations. If the decoding converges at decision step 1142 for a given time period (e.g., elapsed time) and/or a given number of iterations, the decoded codeword is stored as the final read result (step 1144). If the decoding progresses toward convergence, such as by satisfying a specified number of parity checks, the decoding continues. Appropriate software, hardware and/or firmware may be provided in the decoder to enhance this supply.

若解碼不收斂或朝向收斂前進，則調整解碼。在步驟1146處儲存機率計量之當前值，且在步驟1148處開始第二讀取操作。步驟1150及1152分別對應於步驟1132及1134。步驟1154包括以第二讀取為基礎來調整機率計量之當前值。舉例而言，此可包括施加由圖9c之表所描繪之LLR調整。在步驟1156處，迭代解碼利用可在後續迭代中經進一步調整之機率計量之經調整值而繼續。解碼過程歸因於由第二讀取所提供之資訊而得以改良。舉例而言，解碼過程與僅利用來自單讀取之結果的情況相比可收斂得更快，或解碼過程可在單讀取狀況可能不會收斂的情況下收斂。在決策步驟1158處，再次檢查解碼狀態，類似於決策步驟1142之檢查。若在步驟1158處解碼在給定時間週期(例如，流逝時間)及/或給定數目之迭代內收斂，則將經解碼 碼字儲存為最終讀取結果(步驟1160)。注意，用於在步驟1158中朝向收斂之前進的計量可比步驟1142處更不嚴格。若解碼(諸如)藉由滿足指定數目之同位檢查而朝向收斂前進，則解碼繼續。若解碼不滿足第二條件，則可宣告錯誤或可執行額外讀取操作(步驟1162)，且彼讀取操作之結果用於再次調整解碼過程。If the decoding does not converge or the convergence progresses, the decoding is adjusted. The current value of the probability meter is stored at step 1146 and the second read operation begins at step 1148. Steps 1150 and 1152 correspond to steps 1132 and 1134, respectively. Step 1154 includes adjusting the current value of the probability meter based on the second reading. For example, this can include applying an LLR adjustment as depicted by the table of Figure 9c. At step 1156, the iterative decoding continues with the adjusted value of the probability measure that can be further adjusted in subsequent iterations. The decoding process is improved due to the information provided by the second reading. For example, the decoding process may converge faster than if only the result from a single read is used, or the decoding process may converge if the single read condition may not converge. At decision step 1158, the decoding status is checked again, similar to the check of decision step 1142. If the decoding converges within a given time period (eg, elapsed time) and/or a given number of iterations at step 1158, it will be decoded The codeword is stored as the final read result (step 1160). Note that the metering used to converge toward convergence in step 1158 may be less stringent than at step 1142. If the decoding progresses toward convergence, such as by satisfying a specified number of parity checks, the decoding continues. If the decoding does not satisfy the second condition, an error may be declared or an additional read operation may be performed (step 1162), and the result of the read operation is used to adjust the decoding process again.

注意，代替回應於解碼不滿足特定條件而開始額外讀取操作，有可能在解碼過程已以第一讀取操作為基礎而開始之後自動地執行額外讀取操作。在此狀況下，可在第二讀取操作已完成時暫停解碼過程以更新LLR，而不管解碼是否滿足特定條件，或在必要的情況下，可儲存第二操作之結果以供在解碼過程中後續利用。Note that instead of starting an additional read operation in response to the decoding not satisfying certain conditions, it is possible to automatically perform an additional read operation after the decoding process has started on the basis of the first read operation. In this case, the decoding process may be suspended to update the LLR when the second read operation has completed, regardless of whether the decoding satisfies certain conditions or, if necessary, the result of the second operation may be stored for use in the decoding process. Subsequent use.

圖11c為用於解碼表示非揮發性儲存元件之狀態之碼字之過程的流程圖，其中以第一讀取操作為基礎來獲得初始機率計量，接著以第一讀取操作及第二讀取操作為基礎來獲得新的初始機率計量。在此方法中，解碼本質上在其不滿足特定條件時以自第一讀取所獲得之初始LLR為基礎而自開始重新開始。然而，新的初始LLR係以第一讀取操作及第二讀取操作或其他額外讀取操作為基礎。步驟1170、1172、1174、1176、1178、1180、1182及1184分別對應於圖11b之步驟1130、1132、1134、1136、1138、1140、1142及1144。在步驟1186處，當在決策步驟1182處解碼不滿足第一條件時，可宣告錯誤或可執行額外讀取。若將利用第二讀取操作(步驟1188)，則在步驟1190處廢除由解碼 器所利用之機率計量(例如，LLR)之當前值。步驟1192及1194分別對應於圖11b之步驟1150及1152。在步驟1196處，將新的初始機率計量指派給碼字(例如，在步驟1176中所指派之碼字)中之每一位元。此等新的機率計量以第一及第二讀取操作為基礎來指示位元之可靠度。Figure 11c is a flow diagram of a process for decoding a codeword representing a state of a non-volatile storage element, wherein an initial probability meter is obtained based on a first read operation, followed by a first read operation and a second read Based on the operation to obtain a new initial probability measurement. In this method, decoding essentially restarts from the beginning based on the initial LLR obtained from the first read when it does not satisfy the particular condition. However, the new initial LLR is based on a first read operation and a second read operation or other additional read operation. Steps 1170, 1172, 1174, 1176, 1178, 1180, 1182, and 1184 correspond to steps 1130, 1132, 1134, 1136, 1138, 1140, 1142, and 1144 of FIG. 11b, respectively. At step 1186, when the decoding does not satisfy the first condition at decision step 1182, an error may be declared or an additional read may be performed. If the second read operation is to be utilized (step 1188), then at step 1190, the decoding is aborted. The current value of the probability measure (eg, LLR) utilized by the device. Steps 1192 and 1194 correspond to steps 1150 and 1152 of Figure 11b, respectively. At step 1196, a new initial probability meter is assigned to each of the codewords (eg, the codeword assigned in step 1176). These new probabilities are based on the first and second read operations to indicate the reliability of the bit.

圖12描繪稀疏同位檢查矩陣。如先前所提及，儲存元件儲存表示資訊位元及同位位元之資料，其中根據錯誤校正編碼過程來提供同位位元。此過程涉及將同位位元添加至資訊位元。在一可能方法中，利用低密度同位檢查(LDPC)碼。實務上，通常將此等碼施加至跨越許多儲存元件而被編碼之多個碼字。LDPC碼為所需的，因為其招致相對較低之附加項成本。此外，LDPC碼在迭代訊息傳遞解碼演算法下展現接近向農(Shannon)極限之效能。然而，此僅為實例實施例，因為可利用任何類型之錯誤校正碼。舉例而言，可利用其他線性塊碼。Figure 12 depicts a sparse parity check matrix. As mentioned previously, the storage element stores data representing the information bits and the parity bits, wherein the parity bits are provided in accordance with the error correction encoding process. This process involves adding a parity bit to the information bit. In one possible approach, a low density parity check (LDPC) code is utilized. In practice, these codes are typically applied to multiple codewords that are encoded across a number of storage elements. The LDPC code is required because it incurs a relatively low additional item cost. In addition, the LDPC code exhibits an approach to the Shannon limit under an iterative message passing decoding algorithm. However, this is merely an example embodiment as any type of error correction code can be utilized. For example, other linear block codes can be utilized.

LDPC碼為由稀疏同位檢查矩陣所特徵化之線性塊碼，例如，如由矩陣H 1200所描繪。矩陣包括K個資訊位元及M個同位位元，且碼長度為N=K+M。另外，同位位元經界定成使得滿足M個同位檢查方程式，其中矩陣之每一列表示同位檢查方程式。詳言之，矩陣之列係藉由檢查節點cn1至cn10來識別且行係藉由變數v1至v13來識別，其指示儲存於儲存元件中之資料(例如，碼字位元)。此資料包括資訊位元i及同位位元p，以如下方程式為基礎：， 其中H為稀疏同位檢查矩陣，為資料矩陣，為資訊位元矩陣，且p為同位位元矩陣。在一方法中，可自不同碼字之不同位元位置採取資訊位元。可藉由求解以上方程式來判定資料矩陣v。另外，若矩陣H為下三角形，則此可利用高斯(Gaussian)消除程序來有效地完成。The LDPC code is a linear block code characterized by a sparse parity check matrix, for example as depicted by matrix H 1200. The matrix includes K information bits and M co-located bits, and the code length is N=K+M. Additionally, the parity bits are defined such that M parity check equations are satisfied, where each column of the matrix represents a parity check equation. In particular, the matrix is identified by checking nodes cn1 through cn10 and the line is identified by variables v1 through v13, which indicate the data (eg, codeword bits) stored in the storage element. This information includes the information bit i and the parity bit p, based on the following equation: , where H is a sparse parity check matrix, For the data matrix, It is an information bit matrix, and p is a parity matrix. In one method, information bits can be taken from different bit positions of different codewords. The data matrix v can be determined by solving the above equation. In addition, if the matrix H is a lower triangle, this can be efficiently performed using a Gaussian elimination program.

圖13描繪對應於圖12之稀疏同位檢查矩陣的稀疏偶圖。圖1300更詳細地指示LDPC碼如何工作。可變節點v1至v13表示碼字位元，且檢查節點cn1至cn10表示對位元之同位檢查約束。Figure 13 depicts a sparse diffractogram corresponding to the sparse parity check matrix of Figure 12. Diagram 1300 indicates in more detail how the LDPC code works. The variable nodes v1 to v13 represent codeword bits, and the check nodes cn1 to cn10 represent co-located check constraints on the bit.

在解碼期間，解碼器試圖滿足同位檢查。在此實例中，存在如由檢查節點cn1至cn10所指示之十個同位檢查。cn1處之第一同位檢查判定是否v2v4v11v13=0，其中表示互斥或(XOR)邏輯運算。此檢查在v2、v4、v11及v13中存在偶數數目之"1"位元的情況下得以滿足。此檢查藉由圖1300中自節點v2、v4、v11及v13之箭頭指向節點cn1的事實來表示。cn2處之第二同位檢查判定是否v1v7v12=0，其在存在奇數數目之"1"位元的情況下得以滿足。cn3處之第三同位檢查判定是否v3v5v6v9v10=0，其在存在奇數數目之"1"位元的情況下得以滿足。類似地，cn4處之第四同位檢查判定是否v2v8v11=0，cn5處之第五同位檢查判定是否v4v7v12=0，cn6處之第六同位檢查判定是否 v1v5v6v9=0，cn7處之第七同位檢查判定是否v2v8v10v13=0，cn8處之第八同位檢查判定是否v4v7v11v12=0，cn9處之第九同位檢查判定是否v1v3v5v13=0，且cn10處之第十同位檢查判定是否v7v8v9v10=0。During decoding, the decoder attempts to satisfy the parity check. In this example, there are ten parity checks as indicated by check nodes cn1 through cn10. The first parity test at cn1 determines whether v2 V4 V11 V13=0, where Represents a mutually exclusive or (XOR) logical operation. This check is satisfied in the case where an even number of "1" bits exist in v2, v4, v11, and v13. This check is represented by the fact that the arrows from nodes v2, v4, v11, and v13 point to node cn1 in graph 1300. The second parity check at cn2 determines whether v1 V7 V12=0, which is satisfied if there is an odd number of "1" bits. The third parity check at cn3 determines whether v3 V5 V6 V9 V10=0, which is satisfied if there is an odd number of "1" bits. Similarly, the fourth parity check at cn4 determines whether v2 V8 V11=0, the fifth parity check at cn5 determines whether v4 V7 V12=0, the sixth parity check at cn6 determines whether v1 V5 V6 V9=0, the seventh parity check at cn7 determines whether v2 V8 V10 V13=0, the eighth parity check at cn8 determines whether v4 V7 V11 V12=0, the ninth parity check at cn9 determines whether v1 V3 V5 V13=0, and the tenth parity check at cn10 determines whether v7 V8 V9 V10=0.

用於LDPC之解碼過程為被稱為迭代訊息傳遞解碼之迭代機率性解碼過程。迭代涉及連續地橫過檢查節點及以每一同位檢查為基礎來更新所涉及之位元之LLR值。在一方法中，試圖滿足cn1之第一同位檢查。一旦滿足彼同位檢查，則試圖滿足cn2之第一同位檢查，等等。在必要的情況下，以熟習此項技術者已知之方式而針對每一迭代來調整LLR值。此迭代演算法為置信傳播(belief propagation)之形式。The decoding process for LDPC is an iterative probability decoding process called iterative message passing decoding. Iteration involves continuously traversing the check node and updating the LLR values of the bits involved based on each parity check. In one method, an attempt is made to satisfy the first parity check of cn1. Once the peer check is satisfied, an attempt is made to satisfy the first parity check of cn2, and so on. If necessary, the LLR values are adjusted for each iteration in a manner known to those skilled in the art. This iterative algorithm is in the form of belief propagation.

預調節波形之利用Use of pre-adjusted waveforms

儲存元件之經感測程式化狀態可以儲存元件之歷史為基礎而在不同讀取操作內變化。舉例而言，儲存元件之狀態將有時在兩個讀取操作之間改變，且改變狀態之儲存元件之數目可視控制閘極電壓之歷史而定。讀取狀態將改變之傾向係以多種因素為基礎，包括用於每一狀態之V_TH 寬度、狀態之間的間隔、截獲位點雜訊及其他因素。The sensed stylized state of the storage element can be varied within different read operations based on the history of the stored component. For example, the state of the storage element will sometimes change between two read operations, and the number of storage elements that change state can depend on the history of the control gate voltage. The tendency for the read state to change is based on a number of factors, including the _VTH width for each state, the spacing between states, the interception site noise, and other factors.

因此，可能有用的係在執行兩個或兩個以上感測操作時有意地產生不同短期歷史。在一方法中，在相同電壓位準下或在相鄰電壓位準下利用不同短期歷史。舉例而言，恰好在第一讀取操作之前，可使選定字線接地。為了使第二 讀取操作之短期歷史不同，吾人可恰好在第二讀取操作之開始之前將(例如)以讀取通過電壓(read pass voltage)(例如，V_READ =5.5 V)之形式的預調節波形施加至選定字線。V_READ 為在讀取選定字線上之儲存元件時通常施加至未選定字線的電壓。然而，此為許多可能實施例當中之一實例。舉例而言，除了預調節波形之結束與感測整合時間之開始之間的時間間隔以外，振幅、持續時間及形狀均為可(例如)利用字線及所注意之其他線之RC時間常數來最佳化的參數。Therefore, it may be useful to intentionally generate different short-term histories when performing two or more sensing operations. In one approach, different short-term histories are utilized at the same voltage level or at adjacent voltage levels. For example, the selected word line can be grounded just prior to the first read operation. In order to make the short-term history of the second read operation different, we can, for example, read the read pass voltage (eg, V _READ = 5.5 V) just before the start of the second read operation. The pre-regulated waveform is applied to the selected word line. V _READ is the voltage that is typically applied to an unselected word line when the storage element on the selected word line is read. However, this is one of many possible embodiments. For example, in addition to the time interval between the end of the pre-adjusted waveform and the beginning of the sensing integration time, the amplitude, duration, and shape are all operative, for example, using the RC time constant of the word line and other lines of interest. Optimized parameters.

就一些有雜訊儲存元件之V_TH 視施加至其各種端子(諸如，控制閘極及C-P井)之偏壓的短期歷史而定而言，不同短期歷史應增加有雜訊行為，且此增加將幫助吾人識別更多可疑位元。此額外資訊應藉由識別有雜訊儲存元件且確認關於特定位元之值的不定性來改良迭代解碼過程。此無知確認可用於幫助將解碼過程之注意力集中於需要更多注意力之更麻煩的位元。簡而言之，較好的係知道吾人不知道一些位元之值而非假裝吾人知道。Some noise on the storage element of V _TH is applied to depending on its various terminals (such as CP and the control gate well) and short-term history of bias voltage set, the short term history of different noise behavior there should be increased, and this increase Will help us identify more suspicious bits. This additional information should improve the iterative decoding process by identifying the noise storage element and confirming the uncertainty about the value of a particular bit. This ignorance confirmation can be used to help focus the decoding process on more troublesome bits that require more attention. In short, the better system knows that we don't know the value of some bits rather than pretending to be known.

預調節波形在感測操作之前的利用允許讀取操作之歷史更接近地類似於在程式化期間所執行之驗證操作，因為驗證操作之短期歷史包括程式(V_PGM )脈衝。圖24中描繪振幅在(例如)13-20 V之間變化之實例V_PGM 脈衝。預調節波形之振幅無需與程式脈衝之振幅一樣高，但其可仍重複儲存元件在驗證操作作為程式化操作之一部分而被執行時所經受之短期歷史。因此，程式脈衝在驗證操作之前對儲存元件 之效應由預調節脈衝在讀取操作之前對儲存元件之效應部分地複製。對於額外讀取操作僅在必要時(例如，當以一讀取操作為基礎之解碼過程未收斂時)被執行之實施例而言，在一可能方法中，第一讀取可在感測操作之前利用預調節波形。The utilization of the pre-conditioning waveform prior to the sensing operation allows the history of the read operation to be more closely similar to the verify operation performed during the stylization because the short-term history of the verify operation includes the program (V _PGM ) pulse. An example V _PGM pulse whose amplitude varies between, for example, 13-20 V is depicted in FIG. The amplitude of the pre-conditioned waveform need not be as high as the amplitude of the program pulse, but it can still repeat the short-term history that the storage element is subjected to when the verification operation is performed as part of the stylized operation. Thus, the effect of the program pulse on the storage element prior to the verify operation is partially replicated by the effect of the pre-conditioning pulse on the storage element prior to the read operation. For embodiments in which an additional read operation is only performed when necessary (eg, when the decoding process based on a read operation does not converge), in a possible approach, the first read may be in a sensing operation Previously used pre-adjusted waveforms.

另外，用於解碼過程中之機率計量(諸如，LLR)可說明預調節波形之效應。因此，指派給位元之初始LLR可以關聯儲存元件之歷史為基礎而變化。舉例而言，若碼字中之相同位元值係自具有及無預調節波形之讀取操作被獲得，則用於位元之LLR之量值與位元值係自均無預調節波形或甚至均具有預調節波形之讀取操作被獲得的情況相比應更高以指示位元之值的更確信量測。Additionally, probability measurements (such as LLR) used in the decoding process can account for the effects of the pre-conditioned waveform. Thus, the initial LLR assigned to a bit can vary based on the history of the associated storage element. For example, if the same bit value in the codeword is obtained from a read operation with and without a pre-adjusted waveform, the magnitude and bit value of the LLR for the bit are independent of the pre-adjusted waveform or Even the case where the read operation with the pre-adjusted waveform is obtained is higher to indicate a more confident measurement of the value of the bit.

詳言之，預調節波形可影響各種程式化狀態之機率分布函數(pdf)。此效應藉由比較具有及無預調節波形之儲存元件集合之V_TH 分布的pdf而可量測。通常，在利用預調節波形的情況下，可以用於特定技術之儲存元件之行為為基礎來提供用於自多重讀取聚集LLR結果的數學方法。舉例而言，若讀取中之每一者得到相同結果，則吾人可針對碼字之位元來指派表示狀態之高量值LLR。此峰值LLR(LLRpeak)可能高於用於僅單讀取(LLRsingle)之LLR。另一方面，若讀取系列得到不同結果，則可能產生較低最終LLR。聚集讀取系列之一方法係採取單讀取LLR之平均值，且接著使平均值乘以正規化因子(諸如，LLRpeak/LLRsingle)。In particular, the pre-conditioning waveform can affect the probability distribution function (pdf) of various stylized states. This effect is measurable by comparing the pdf of the _VTH distribution with and without the pre-adjusted waveform of the set of storage elements. In general, mathematical methods for multiplying aggregated LLR results are provided on the basis of the behavior of storage elements that can be used for a particular technique, using pre-conditioned waveforms. For example, if each of the reads yields the same result, then we can assign a high value LLR representing the state for the bits of the codeword. This peak LLR (LLRpeak) may be higher than the LLR for single read only (LLRsingle). On the other hand, if the reading series yields different results, a lower final LLR may result. One of the methods of the aggregated read series is to take the average of the single read LLR and then multiply the average by a normalization factor (such as LLRpeak/LLRsingle).

下文之實例描繪在讀取操作之感測操作之前發生的一或多個預調節脈衝，但一般而言，可利用任何預調節波形。另外，可將預調節波形施加至儲存元件之端子(例如，控制閘極、源極及/或汲極)，及/或至形成有儲存元件之基板。舉例而言，可將第一預調節波形經由形成有非揮發性儲存元件之基板之本體而施加至非揮發性儲存元件，且可將第二預調節波形施加至儲存元件之控制閘極、源極及汲極。或，可將第二預調節波形經由本體而施加至非揮發性儲存元件，且將第一預調節波形施加至儲存元件之控制閘極、源極及/或汲極。另外，可在一讀取操作期間或在不同讀取操作期間施加具有不同特徵之預調節波形。The examples below depict one or more pre-conditioning pulses that occur prior to the sensing operation of the read operation, but in general, any pre-conditioned waveform can be utilized. Additionally, a pre-conditioning waveform can be applied to the terminals of the storage element (eg, control gates, sources, and/or drains), and/or to the substrate on which the storage elements are formed. For example, the first pre-conditioning waveform can be applied to the non-volatile storage element via the body of the substrate on which the non-volatile storage element is formed, and the second pre-conditioning waveform can be applied to the control gate, source of the storage element. Extreme and bungee jumping. Alternatively, a second pre-conditioning waveform can be applied to the non-volatile storage element via the body and a first pre-conditioning waveform can be applied to the control gate, source and/or drain of the storage element. Additionally, pre-conditioned waveforms having different characteristics can be applied during a read operation or during different read operations.

此外，預調節波形可用於單讀取方法以及多重讀取方法中。另外，可在利用任何類型之錯誤校正解碼或無需錯誤校正解碼的情況下利用預調節波形。In addition, the pre-conditioning waveform can be used in single read methods as well as in multiple read methods. Additionally, the pre-conditioned waveform can be utilized with any type of error correction decoding or without error correction decoding.

圖14a為解釋讀取/驗證操作期間特定波形之行為的時序圖，其中在關聯讀取脈衝之前將預調節波形施加至選定字線。此及其他時序圖中之波形未必按比例。Figure 14a is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, where a pre-conditioned waveform is applied to a selected word line prior to correlating the read pulses. Waveforms in this and other timing diagrams are not necessarily to scale.

如所提及，可將預調節波形施加至儲存元件作為讀取操作之一部分。此可涉及(例如)在將感測電壓施加至字線以用於比較儲存元件之V_TH 與比較點之前經由關聯選定字線而將預調節波形(諸如，脈衝)施加至經讀取之儲存元件的控制閘極。此外，可恰好在任何讀取之前或恰好在讀取操作中之一些之前施加預調節波形。可將其與各種位準之軟讀取組合。亦可在相同電壓位準下將其與多重讀取組合。As mentioned, a pre-conditioning waveform can be applied to the storage element as part of a read operation. This may involve, for example, applying a pre-conditioned waveform (such as a pulse) to the read storage via the associated selected word line prior to applying the sense voltage to the word line for comparing the _{VTH of the} storage element with the comparison point. The control gate of the component. In addition, the pre-conditioned waveform can be applied just prior to any reading or just prior to some of the read operations. It can be combined with soft reading at various levels. It can also be combined with multiple reads at the same voltage level.

一般而言，在讀取及驗證操作期間，將選定字線或其他控制線連接至電壓，其位準經指定用於每一讀取及驗證操作，以便判定有關儲存元件之臨限電壓是否已達到此位準。在施加字線電壓之後，量測儲存元件之傳導電流以判定儲存元件是否開啟。若傳導電流經量測為大於特定值，則假設儲存元件開啟且施加至字線之電壓大於儲存元件之臨限電壓。若傳導電流未經量測為大於特定值，則假設儲存元件未開啟且施加至字線之電壓不大於儲存元件之臨限電壓。In general, during a read and verify operation, a selected word line or other control line is connected to a voltage whose level is specified for each read and verify operation to determine if the threshold voltage of the associated storage element has Reach this level. After the word line voltage is applied, the conduction current of the storage element is measured to determine if the storage element is on. If the conduction current is measured to be greater than a particular value, then the storage element is turned on and the voltage applied to the word line is greater than the threshold voltage of the storage element. If the conduction current is not measured to be greater than a particular value, then the storage element is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the storage element.

存在用以在讀取或驗證操作期間量測儲存元件之傳導電流的許多方式。在一實例中，儲存元件之傳導電流係藉由其允許(或未能允許)包括儲存元件之NAND串使位元線放電的速率來量測。在一時間週期之後量測位元線上之電荷以查看其是否已放電。在另一實施例中，選定儲存元件之傳導允許電流在位元線上流動或不流動，此係藉由感測放大器中之電容器是否歸因於電流流動而充電來量測。論述兩個實例。There are many ways to measure the conduction current of a storage element during a read or verify operation. In one example, the conduction current of the storage element is measured by the rate at which it allows (or fails to allow) the NAND string including the storage element to discharge the bit line. The charge on the bit line is measured after a period of time to see if it has been discharged. In another embodiment, conduction of the selected storage element allows current to flow or not flow on the bit line, which is measured by whether the capacitor in the sense amplifier is charged due to current flow. Discuss two examples.

詳言之，波形1400描繪汲極側選擇閘極電壓(SGD)，波形1402描繪未選定字線電壓，波形1404描繪(為讀取/驗證所選定之字線之)選定字線電壓，波形1410描繪源極側選擇閘極(SGS)電壓(選項1)，波形1412描繪SGS電壓(選項2)，波形1414描繪(為讀取/驗證所選定之位元線之)選定位元線(BL)電壓(選項1)，波形1418描繪選定BL電壓(選項2)，且波形1419描繪源極電壓。另外，時間點t0-t4在水平 方向上擴展。In particular, waveform 1400 depicts the drain side select gate voltage (SGD), waveform 1402 depicts the unselected word line voltage, and waveform 1404 depicts (to read/verify the selected word line) the selected word line voltage, waveform 1410 Depicting the source side select gate (SGS) voltage (option 1), waveform 1412 depicting the SGS voltage (option 2), and waveform 1414 depicting (for reading/verifying the selected bit line) the selected bit line (BL) Voltage (option 1), waveform 1418 depicts the selected BL voltage (option 2), and waveform 1419 depicts the source voltage. In addition, the time point t0-t4 is at the level Expand in the direction.

注意，存在所描繪之SGS及選定BL的兩個版本。選項1描繪用於藉由判定位元線是否已放電來量測儲存元件之傳導電流之儲存元件陣列的讀取/驗證操作。選項2描繪用於藉由儲存元件使感測放大器中之專用電容器放電之速率來量測儲存元件之傳導電流之儲存元件陣列的讀取/驗證操作。Note that there are two versions of the depicted SGS and the selected BL. Option 1 depicts a read/verify operation for a storage element array for measuring the conduction current of the storage element by determining whether the bit line has been discharged. Option 2 depicts a read/verify operation of the array of storage elements for measuring the conduction current of the storage element by the rate at which the storage element discharges the dedicated capacitor in the sense amplifier.

首先，將關於選項1來論述藉由判定位元線是否已放電來量測儲存元件之傳導電流時所涉及之感測電路及儲存元件陣列的行為。First, the behavior of the sensing circuit and the array of storage elements involved in measuring the conduction current of the storage element by determining whether the bit line has been discharged will be discussed with respect to Option 1.

在t0之前，電壓在近似0 V之穩定狀態電壓Vss下開始。Prior to t0, the voltage begins at a steady state voltage Vss of approximately 0 V.

在t0與t1之間，在讀取脈衝1408之前將預調節波形1406施加至選定字線。注意，在另一方法中，預調節波形可與感測操作(讀取脈衝1408)重疊。在t2，SGD及SGS(選項2)分別上升至V_SGD 及V_SGS (例如，3.5 V)。未選定字線上升至V_READ (例如，6 V)，其因為使未選定儲存元件開啟且充當通過閘極(pass gate)而充當過激勵電壓。預調節波形1406可具有與(例如)大於V_CGR 之V_READ 相當之振幅。V_READ 通常為可被施加而不引起干擾之最高電壓。選定字線對於讀取操作而言上升至V_CGR (控制閘極讀取電壓)或對於驗證操作而言上升至驗證位準。將t2與t4之間的選定字線上之波形視為在感測操作期間所利用之讀取脈衝1408。在一方法中，將選定BL(選項1)預充電至近似0.7V。Between t0 and t1, a pre-conditioning waveform 1406 is applied to the selected word line prior to reading pulse 1408. Note that in another method, the pre-conditioning waveform may overlap with the sensing operation (read pulse 1408). At t2, SGD and SGS (option 2) rise to V _SGD and V _SGS (for example, 3.5 V), respectively. The unselected word line rises to V _READ (eg, 6 V), which acts as an overdrive voltage because the unselected storage element is turned on and acts as a pass gate. The pre-conditioning waveform 1406 can have an amplitude that is comparable to, for example, V _{READ that} is greater than V _CGR . V _READ is typically the highest voltage that can be applied without causing interference. The selected word line rises to V _CGR (control gate read voltage) for a read operation or rises to a verify level for a verify operation. The waveform on the selected word line between t2 and t4 is taken as the read pulse 1408 utilized during the sensing operation. In one method, the selected BL (option 1) is precharged to approximately 0.7V.

可接著在下一讀取或驗證位準下重複圖14a中所描繪之 過程，其中施加不同V_CGR 以感測與選定字線相關聯之儲存元件之V_TH 是高於還是低於對應比較點。在一方法中，在每一感測操作之前提供預調節脈衝。The process depicted in Figure 14a can then be repeated at the next read or verify level, where a different V _CGR is applied to sense whether the _VTH of the storage element associated with the selected word line is above or below the corresponding comparison point. In one method, a pre-conditioning pulse is provided prior to each sensing operation.

在t3，NAND串可控制位元線。亦在t3，藉由使SGS(選項1)上升至V_SGS 來開啟源極側選擇閘極。此提供用以耗散位元線上之電荷的路徑。若為讀取所選定之儲存元件之V_TH 大於V_CGR 或施加至選定字線之驗證位準，則選定儲存元件將不開啟且位元線將不放電，如由線1415所描繪。若為讀取所選定之儲存元件之臨限電壓低於V_CGR 或低於施加至選定字線之驗證位準，則為讀取所選定之儲存元件將開啟(傳導)且位元線電壓將耗散，如由曲線1416所描繪。在時間t3之後且在時間t4之前的某一點(如由特定實施例所判定)，感測放大器將判定位元線是否已耗散足夠量。在t3與t4之間，感測放大器量測經評估之BL電壓。在時間t4，所描繪之波形將降低至Vss(或用於待用或恢復之另一值)。At t3, the NAND string can control the bit line. Also at t3, the source side select gate is turned on by raising SGS (option 1) to V _SGS . This provides a path to dissipate the charge on the bit line. If the _VTH for reading the selected storage element is greater than V _CGR or the verify level applied to the selected word line, the selected storage element will not turn on and the bit line will not discharge, as depicted by line 1415. If the threshold voltage for reading the selected storage element is below V _CGR or below the verify level applied to the selected word line, then the selected storage element will be turned on (conducted) and the bit line voltage will be read. Dissipation, as depicted by curve 1416. At some point after time t3 and before time t4 (as determined by the particular embodiment), the sense amplifier will determine if the bit line has been dissipated a sufficient amount. Between t3 and t4, the sense amplifier measures the evaluated BL voltage. At time t4, the depicted waveform will be reduced to Vss (or another value for inactivity or recovery).

緊接著關於選項2所論述的係感測電路及儲存元件陣列之行為，其藉由儲存元件使感測放大器中之專用電容器放電之速率來量測儲存元件之傳導電流。如前所述，在t0與t1之間施加預調節波形1406。在時間t2，SGD上升至V_SGD ，未選定字線上升至V_READ ，且選定字線對於讀取操作而言上升至V_CGR 或對於驗證操作而言上升至驗證位準。Following the behavior of the sensing circuit and the array of storage elements discussed with respect to option 2, the conduction current of the storage element is measured by the rate at which the storage element discharges the dedicated capacitor in the sense amplifier. As previously mentioned, a pre-conditioning waveform 1406 is applied between t0 and t1. At time t2, SGD rises to V _SGD , the unselected word line rises to V _READ , and the selected word line rises to V _CGR for a read operation or rises to a verify level for a verify operation.

在此狀況下，感測放大器使位元線電壓保持恆定而不管NAND串正在進行什麼活動，因此，感測放大器利用"箝位"至彼電壓之位元線來量測電流流動。在t2之後且在t4之前 的某一點(如由特定實施例所判定)，感測放大器將判定感測放大器中之電容器是否已耗散足夠量。在t4，所描繪之波形將降低至Vss(或用於待用或恢復之另一值)。注意，在其他實施例中，可改變波形中之一些之時序。In this case, the sense amplifier keeps the bit line voltage constant regardless of what activity the NAND string is performing, so the sense amplifier uses the "clamp" to the bit line of the voltage to measure the current flow. After t2 and before t4 At some point (as determined by the particular embodiment), the sense amplifier will determine if the capacitor in the sense amplifier has dissipated a sufficient amount. At t4, the depicted waveform will be reduced to Vss (or another value for inactivity or recovery). Note that in other embodiments, the timing of some of the waveforms can be changed.

圖14b為解釋讀取/驗證操作期間特定波形之行為的時序圖，其中在關聯讀取脈衝之前將一或多個預調節波形施加至選定字線。此處，描繪組成讀取操作之一部分的三個感測操作。舉例而言，在16個狀態的情況下，可能存在15個感測操作。波形1420、1422、1424、1435、1436、1437、1438及1439分別表示在三個感測操作內圖14a之波形1400、1402、1104、1410、1412、1414、1418及1419。波形1432類似於波形1424，但僅在組成讀取操作之讀取脈衝系列中之第一讀取脈衝1427之前包括預調節波形1426。在波形1424中，分別在與不同V_TH 比較點相關聯之讀取脈衝1427、1429及1431之前將預調節波形1426、1428及1430施加至選定字線。讀取脈衝振幅在每一感測操作中增加，例如，自V_CGR-1 至V_CGR-2 至V_CGR-3 ，等等。預調節波形之振幅對於每一感測操作可相同或可(例如)隨著關聯讀取脈衝之振幅而變化。關於波形1432，注意，通常，可在讀取操作中之一或多個選定讀取脈衝之前提供預調節波形。此外，可隨機地選擇具有關聯預調節波形之讀取脈衝。Figure 14b is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein one or more pre-conditioned waveforms are applied to the selected word line prior to correlating the read pulses. Here, three sensing operations that form part of a read operation are depicted. For example, in the case of 16 states, there may be 15 sensing operations. Waveforms 1420, 1422, 1424, 1435, 1436, 1437, 1438, and 1439 represent waveforms 1400, 1402, 1104, 1410, 1412, 1414, 1418, and 1419 of Figure 14a, respectively, within three sensing operations. Waveform 1432 is similar to waveform 1424, but includes pre-conditioned waveform 1426 only prior to the first read pulse 1427 in the series of read pulses that make up the read operation. In waveform 1424, pre-conditioning waveforms 1426, 1428, and 1430 are applied to the selected word line prior to read pulses 1427, 1429, and 1431 associated with different _VTH comparison points, respectively. The read pulse amplitude is increased in each sensing operation, for example, from V _CGR-1 to V _CGR-2 to V _CGR-3 , and so on. The amplitude of the pre-adjusted waveform may be the same for each sensing operation or may vary, for example, with the amplitude of the associated read pulse. Regarding waveform 1432, it is noted that in general, the pre-conditioned waveform can be provided prior to one or more selected read pulses in the read operation. Additionally, read pulses with associated pre-conditioned waveforms can be randomly selected.

圖14c為描繪不同預調節波形之時序圖。如所提及，預調節波形可具有多種特徵。波形1404(亦在圖14a中論述)包括基線預調節波形1406作為在讀取脈衝1408之前所提供的 脈衝。注意，波形1406及脈衝1408展示對於不同記憶體設備將變化之上升時間及衰變時間。在一選項中，波形1440包括預調節波形1441作為與脈衝1406相比具有較長持續時間之脈衝。波形1442包括與脈衝1406相比更接近於讀取脈衝1408之預調節波形1443。爭論中之時間週期自預調節波形之結束擴展至讀取脈衝之開始。波形1444包括預調節波形1445作為與脈衝1406相比具有較低振幅之脈衝。波形1446包括與脈衝1406相比具有不同形狀之預調節波形1447。此處，利用振盪波形。雖然此波形不複製程式化脈衝，且甚至包括負電壓，但其仍可有用於(例如)導致截獲位點活動。亦可利用包括斜坡、台階等等之其他波形。亦有可能在讀取脈衝之前提供多個預調節波形。Figure 14c is a timing diagram depicting different pre-conditioning waveforms. As mentioned, the pre-conditioned waveform can have a variety of features. Waveform 1404 (also discussed in Figure 14a) includes a baseline pre-conditioning waveform 1406 as provided prior to reading pulse 1408 pulse. Note that waveform 1406 and pulse 1408 show the rise time and decay time that will vary for different memory devices. In an option, waveform 1440 includes pre-adjusted waveform 1441 as a pulse having a longer duration than pulse 1406. Waveform 1442 includes a pre-conditioned waveform 1443 that is closer to read pulse 1408 than pulse 1406. The time period in the debate extends from the end of the pre-conditioned waveform to the beginning of the read pulse. Waveform 1444 includes pre-conditioned waveform 1445 as a pulse having a lower amplitude than pulse 1406. Waveform 1446 includes a pre-conditioned waveform 1447 having a different shape than pulse 1406. Here, an oscillating waveform is utilized. Although this waveform does not replicate stylized pulses and even includes negative voltages, it can still be used, for example, to cause interception site activity. Other waveforms including ramps, steps, and the like can also be utilized. It is also possible to provide multiple pre-conditioned waveforms before reading the pulses.

圖14d為解釋讀取/驗證操作期間特定波形之行為的時序圖，其中在關聯讀取脈衝之前將預調節波形經由選定位元線而施加至選定儲存元件之汲極。通常，代替經由選定字線而將電壓波形施加至儲存元件之控制閘極，可將電壓波形施加至或經由本體偏壓(body bias)而將電壓波形施加至任何其他端子(諸如，源極或汲極)。在此方法中，經由與NAND鏈相關聯之位元線而存取汲極端子。如由波形1450所描繪，藉由在t0與t1之間上升V_SGD 來打開汲極側選擇閘極，此時，將預調節波形1456或1460施加(分別為波形1454及1458)至位元線。可恰好在t0之前直至恰好在t1之後打開汲極側選擇閘極以包絡預調節波形1460。讀取脈衝1408出現在t2與t4之間，如先前所論述。亦在讀取脈衝期 間在t2與t4之間打開汲極側選擇閘極。注意，亦可在t0與t4之間連續地使汲極側選擇閘極保持打開。Figure 14d is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein the pre-conditioned waveform is applied to the drain of the selected storage element via the selected positioning element prior to correlating the read pulse. Typically, instead of applying a voltage waveform to the control gate of the storage element via the selected word line, a voltage waveform can be applied to or applied to any other terminal (such as a source or via a body bias). Bungee jumping). In this method, the 汲 terminal is accessed via a bit line associated with the NAND chain. As depicted by waveform 1450, the drain side select gate is turned on by raising V _SGD between t0 and t1, at which point preconditioning waveforms 1456 or 1460 are applied (waveforms 1454 and 1458, respectively) to the bit line. . The drain side selection gate can be turned on just before t0 until just after t1 to envelope the preconditioning waveform 1460. Read pulse 1408 occurs between t2 and t4 as previously discussed. The drain side selection gate is also opened between t2 and t4 during the read pulse. Note that the drain side selection gate can also be kept open continuously between t0 and t4.

圖14e為解釋讀取/驗證操作期間特定波形之行為的時序圖，其中在關聯讀取脈衝之前將預調節波形經由源極線而施加至選定儲存元件之源極。在此方法中，經由與NAND鏈相關聯之源極線而存取源極端子。如由波形1462或1464所描繪，藉由在t0與t1之間上升V_SGS 來打開源極側選擇閘極，此時，將波形1466中之預調節波形1468施加至源極線。可恰好在t0之前直至恰好在t1之後打開源極側選擇閘極以包絡預調節波形1468。讀取脈衝1408出現在t2與t4之間，如先前所論述。亦在讀取脈衝期間在t2與t4之間打開源極側選擇閘極。注意，亦可在t0與t4之間連續地使源極側選擇閘極保持打開。Figure 14e is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein a pre-conditioned waveform is applied to the source of the selected storage element via the source line prior to correlating the read pulse. In this method, the source terminal is accessed via a source line associated with the NAND chain. As depicted by waveform 1462 or 1464, the source side select gate is turned on by raising V _SGS between t0 and t1, at which point the preconditioned waveform 1468 in waveform 1466 is applied to the source line. The source side select gate can be turned on just before t0 until just after t1 to envelope the pre-conditioned waveform 1468. Read pulse 1408 occurs between t2 and t4 as previously discussed. The source side select gate is also turned on between t2 and t4 during the read pulse. Note that the source side selection gate can also be kept open continuously between t0 and t4.

圖14f為解釋讀取/驗證操作期間特定波形之行為的時序圖，其中在關聯讀取脈衝之前將預調節波形經由本體偏壓而施加至選定儲存元件。在此方法中，利用本體偏壓電壓V_B 來偏壓形成有儲存元件之基板。舉例而言，可利用V_B <0來偏壓基板之p井以使控制閘極增加至本體電壓。如由波形1470所描繪，可在t0與t1之間將預調節波形1472施加至本體。讀取脈衝1408出現在t2與t4之間，如先前所論述。Figure 14f is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein the pre-conditioned waveform is applied to the selected storage element via a body bias prior to correlating the read pulses. In this method, the substrate bias voltage V _{B is} used to bias the substrate on which the storage element is formed. For example, V _B <0 can be used to bias the p-well of the substrate to increase the control gate to the body voltage. As depicted by waveform 1470, pre-conditioned waveform 1472 can be applied to the body between t0 and t1. Read pulse 1408 occurs between t2 and t4 as previously discussed.

圖14g為用於對儲存元件執行讀取操作之過程之流程圖，其中在關聯讀取脈衝之前將預調節波形施加至儲存元件。讀取操作始於步驟1474。在步驟1475處將表示經程式 化狀態之索引k初始化為零。在步驟1476處施加預調節波形且在步驟1477處施加讀取脈衝。步驟1478包括感測V_TH 是高於還是低於讀取比較點。若在決策步驟1479處存在下一比較點，則在步驟1480處遞增索引，且重複步驟1476-1478。若不存在其他比較點，則讀取操作已完成且在步驟1481處儲存結果。Figure 14g is a flow diagram of a process for performing a read operation on a storage element, wherein a pre-conditioning waveform is applied to the storage element prior to correlating the read pulses. The read operation begins at step 1474. The index k representing the stylized state is initialized to zero at step 1475. A pre-conditioning waveform is applied at step 1476 and a read pulse is applied at step 1477. Step 1478 includes sensing whether the _VTH is above or below the read comparison point. If there is a next comparison point at decision step 1479, then the index is incremented at step 1480 and steps 1476-1478 are repeated. If there are no other comparison points, the read operation is complete and the result is stored at step 1481.

圖14h為用於對儲存元件執行讀取操作之過程之流程圖，其中在讀取脈衝系列之前將預調節波形施加至儲存元件。讀取操作始於步驟1482。在步驟1483處將表示經程式化狀態之索引k初始化為零。在步驟1484處施加預調節波形且在步驟1485處施加讀取脈衝。步驟1486包括感測V_TH 是高於還是低於讀取比較點。若在決策步驟1487處存在下一比較點，則在步驟1488處遞增索引，且重複步驟1485及1486。若不存在其他比較點，則讀取操作已完成且在步驟1489處儲存結果。在此狀況下，預調節脈衝未再次用於讀取操作。Figure 14h is a flow diagram of a process for performing a read operation on a storage element, wherein a pre-conditioning waveform is applied to the storage element prior to reading the series of pulses. The read operation begins at step 1482. At step 1485, the index k representing the stylized state is initialized to zero. A pre-conditioning waveform is applied at step 1484 and a read pulse is applied at step 1485. Step 1486 includes sensing whether the _VTH is above or below the read comparison point. If there is a next comparison point at decision step 1487, the index is incremented at step 1488 and steps 1485 and 1486 are repeated. If no other comparison points exist, the read operation is complete and the result is stored at step 1489. In this case, the pre-conditioning pulse is not used again for the read operation.

圖14i為用於利用預調節波形來獲得可靠度計量以供在解碼中後續利用之過程的流程圖。亦見圖5a、圖5b及圖8。步驟1490包括將隨機資料程式化至儲存元件，且步驟1491將索引k初始化至狀態0。步驟1492包括針對寫入至狀態k之每一儲存元件來執行V_TH 之量測，有時利用預調節波形且有時無需預調節波形，及/或利用不同波形特徵(例如，振幅、持續時間及時序)。以此方式，儲存元件中之電子經影響以進入及退出截獲位點，(例如)以提供更精確 的V_TH 分布。步驟1493包括以量測為基礎而針對狀態k來獲得可靠度計量(例如，LLR)，且步驟1494包括儲存結果。若在決策步驟1495處存在下一狀態，則在步驟1496處遞增k，且重複步驟1492及1493。若不存在下一狀態，則過程在步驟1497處結束。Figure 14i is a flow diagram of a process for utilizing a pre-conditioned waveform to obtain reliability measurements for subsequent utilization in decoding. See also Figure 5a, Figure 5b and Figure 8. Step 1490 includes staging the random data to the storage element, and step 1491 initializes index k to state 0. Step 1492 includes performing a _VTH measurement for each storage element written to state k, sometimes using a pre-conditioned waveform and sometimes without pre-conditioning the waveform, and/or utilizing different waveform characteristics (eg, amplitude, duration) And timing). In this manner, electrons in the storage element are affected to enter and exit the interception site, for example, to provide a more accurate _VTH distribution. Step 1493 includes obtaining a reliability measure (eg, LLR) for state k based on the measurement, and step 1494 includes storing the result. If there is a next state at decision step 1495, then k is incremented at step 1496 and steps 1492 and 1493 are repeated. If there is no next state, the process ends at step 1497.

因此，預調節波形可在針對非揮發性儲存器來開發可靠度計量時用於測試環境中及/或在讀取非揮發性儲存器時用於生產環境中。在一方法中，類似於結合圖9b至圖10d所論述之表的表可在利用及不利用預調節脈衝的情況下及/或在利用不同預調節脈衝的情況下得以開發。如先前所論述，接著在讀取非揮發性儲存器時在生產環境期間存取此等表。Thus, the pre-conditioning waveform can be used in a test environment when developing reliability meters for non-volatile storage and/or in a production environment when reading non-volatile storage. In one approach, a table similar to that discussed in connection with Figures 9b through 10d can be developed with and without pre-conditioning pulses and/or with different pre-conditioning pulses. As discussed previously, these tables are then accessed during the production environment while the non-volatile storage is being read.

圖15說明NAND儲存元件(諸如，圖1及圖2所示之儲存元件)陣列1500的實例。沿每一行，位元線1506耦合至NAND串1550之汲極選擇閘極之汲極端子1526。沿NAND串之每一列，源極線1504可連接NAND串之源極選擇閘極之所有源極端子1528。NAND串及儲存元件形成於p井1505上，其在一些實施例中可接收本體偏壓V_B 。作為記憶體系統之一部分之NAND架構陣列及其操作之實例在美國專利第5,570,315號、第5,774,397號及第6,046,935號中被找到。FIG. 15 illustrates an example of an array 1500 of NAND storage elements, such as the storage elements shown in FIGS. 1 and 2. Along each row, bit line 1506 is coupled to the drain terminal 1526 of the drain select gate of NAND string 1550. Along the NAND string, source line 1504 can be connected to all source terminals 1528 of the source select gate of the NAND string. The NAND string and storage elements are formed on p-well 1505, which in some embodiments can receive body bias _VB . Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Patent Nos. 5,570,315, 5,774,397, and 6,046,935.

將儲存元件陣列劃分為大量儲存元件區塊。如對於快閃EEPROM系統而言為共同的，區塊為抹除單位。亦即，每一區塊含有經一起抹除的最小數目之儲存元件。通常將每一區塊劃分為許多頁。頁為程式化單位。在一實施例中， 可將個別頁劃分為若干片段，且該等片段可含有作為基本程式化操作而經一次寫入的最少數目之儲存元件。通常將一或多個資料頁儲存於一儲存元件列中。一頁可儲存一或多個區段。區段包括使用者資料及附加項資料。附加項資料通常包括已自區段之使用者資料所計算的錯誤校正碼(ECC)。控制器(下文所描述)之一部分在資料經程式化至陣列中時計算ECC，且在自陣列讀取資料時亦對其進行檢查。或者，將ECC及/或其他附加項資料儲存於不同於與其有關之使用者資料的頁或甚至區塊中。The storage element array is divided into a plurality of storage element blocks. As common to flash EEPROM systems, the block is the erase unit. That is, each block contains a minimum number of storage elements that are erased together. Each block is usually divided into a number of pages. The page is a stylized unit. In an embodiment, Individual pages can be divided into segments, and the segments can contain a minimum number of storage elements that are written once as a basic stylized operation. One or more data pages are typically stored in a storage element column. One page can store one or more sections. The section includes user data and additional item information. The additional item data typically includes an error correction code (ECC) that has been calculated from the user data for the segment. One portion of the controller (described below) calculates the ECC when the data is programmed into the array and also checks the data as it is read from the array. Alternatively, the ECC and/or other additional item data may be stored in a page or even a block other than the user profile associated with it.

使用者資料之區段通常為512個位元組，此對應於磁碟驅動器中之區段的大小。附加項資料通常為額外的16至20個位元組。大量頁形成一區塊，自8個頁(例如)至32、64、128或更多頁的任何數量。在一些實施例中，一NAND串列包含一區塊。The section of user data is typically 512 bytes, which corresponds to the size of the section in the disk drive. The additional item data is usually an additional 16 to 20 bytes. A large number of pages form a block, from 8 pages (for example) to any number of 32, 64, 128 or more pages. In some embodiments, a NAND string comprises a block.

在一實施例中，藉由將形成有NAND串及儲存元件之p井1505上升至抹除電壓(例如，20 V)持續足夠的時間週期且在源極線及位元線浮動時使選定區塊之字線接地來抹除記憶體儲存元件。歸因於電容耦合，未選定字線、位元線、選擇線及共同源極(c-source)亦上升至抹除電壓之顯著部分。因此，當浮動閘極之電子通常藉由Fowler-Nordheim穿隧機制而發射至基板側時，將強電場施加至選定儲存元件之隧道氧化物層，且將選定儲存元件之資料抹除。當電子自浮動閘極轉移至p井區域時，選定儲存元件之臨限電壓降低。可對整個記憶體陣列、單獨區塊或另一儲存元件 單位執行抹除。In one embodiment, the selected well is made by raising the p-well 1505 formed with the NAND string and the storage element to an erase voltage (eg, 20 V) for a sufficient period of time and while the source line and the bit line are floating. The word line of the block is grounded to erase the memory storage element. Due to capacitive coupling, the unselected word lines, bit lines, select lines, and common source (c-source) also rise to a significant portion of the erase voltage. Thus, when the electrons of the floating gate are typically emitted to the substrate side by the Fowler-Nordheim tunneling mechanism, a strong electric field is applied to the tunnel oxide layer of the selected storage element and the data of the selected storage element is erased. When the electrons are transferred from the floating gate to the p-well region, the threshold voltage of the selected storage element is reduced. Can be used for the entire memory array, individual blocks or another storage component The unit performs the erase.

圖16為利用單列/行解碼器及讀取/寫入電路之非揮發性記憶體系統的方塊圖。該圖說明根據本發明之一實施例之記憶體設備1696，其具有用於並行地讀取及程式化儲存元件頁之讀取/寫入電路。記憶體設備1696可包括一或多個記憶體晶粒1698。記憶體晶粒1698包括儲存元件二維陣列1500、控制電路1610，及讀取/寫入電路1665。在一些實施例中，儲存元件陣列可為三維的。記憶體陣列1500可由字線經由列解碼器1630而存取且可由位元線經由行解碼器1660而存取。讀取/寫入電路1665包括多個感測區塊1600且允許並行地讀取或程式化儲存元件頁。通常，控制器1650包括於與一或多個記憶體晶粒1698相同的記憶體設備1696(例如，抽取式儲存卡)中。控制器1650可包括本文所論述之ECC解碼能力。命令及資料經由線1620而在主機與控制器1650之間轉移，且經由線1618而在控制器與一或多個記憶體晶粒1698之間轉移。Figure 16 is a block diagram of a non-volatile memory system utilizing a single column/row decoder and a read/write circuit. The figure illustrates a memory device 1696 having read/write circuits for reading and programming memory element pages in parallel, in accordance with an embodiment of the present invention. Memory device 1696 can include one or more memory dies 1698. The memory die 1698 includes a two-dimensional array of storage elements 1500, a control circuit 1610, and a read/write circuit 1665. In some embodiments, the array of storage elements can be three dimensional. Memory array 1500 is accessible by word lines via column decoder 1630 and can be accessed by bit lines via row decoder 1660. The read/write circuit 1665 includes a plurality of sensing blocks 1600 and allows the storage of component pages in parallel. Typically, controller 1650 is included in a memory device 1696 (e.g., a removable memory card) that is identical to one or more memory dies 1698. Controller 1650 can include the ECC decoding capabilities discussed herein. Commands and data are transferred between the host and controller 1650 via line 1620 and transferred between the controller and one or more memory dies 1698 via line 1618.

控制電路1610與讀取/寫入電路1665協作以對記憶體陣列1500執行記憶體操作。控制電路1610包括狀態機1612、晶片上位址解碼器1614、增壓控制器(boost control)1615及功率控制模組1616。狀態機1612提供記憶體操作之晶片級控制。晶片上位址解碼器1614將由主機或記憶體控制器所利用之位址之間的位址介面提供至由解碼器1630及1660所利用之硬體位址。增壓控制器1615可用於設定增壓模式，包括判定用於起始源極側及汲極側增壓之時序，如本 文所論述。功率控制模組1616控制在記憶體操作期間供應至字線及位元線之功率及電壓。Control circuit 1610 cooperates with read/write circuit 1665 to perform a memory operation on memory array 1500. Control circuit 1610 includes state machine 1612, on-chip address decoder 1614, boost control 1615, and power control module 1616. State machine 1612 provides wafer level control of memory operations. The on-wafer address decoder 1614 provides the address interface between the addresses utilized by the host or memory controller to the hardware addresses utilized by the decoders 1630 and 1660. The boost controller 1615 can be used to set a boost mode, including determining a timing for initializing the source side and the drain side, such as The article discusses. Power control module 1616 controls the power and voltage supplied to the word lines and bit lines during memory operation.

在一些實施例中，可組合圖16之一些組件。在各種設計中，可將組件中除了儲存元件陣列1500以外之一或多個組件(單獨或組合)視為管理電路。舉例而言，一或多個管理電路可包括控制電路1610、狀態機1612、解碼器1614/1660、功率控制器1616、感測區塊1600、讀取/寫入電路1665、控制器1650等等中之任一者或組合。In some embodiments, some of the components of FIG. 16 may be combined. In various designs, one or more components (alone or in combination) in the assembly other than the storage element array 1500 can be considered a management circuit. For example, one or more management circuits may include control circuit 1610, state machine 1612, decoder 1614/1660, power controller 1616, sensing block 1600, read/write circuit 1665, controller 1650, and the like. Any one or combination.

圖17為利用雙列/行解碼器及讀取/寫入電路之非揮發性記憶體系統的方塊圖。此處，提供圖16所示之記憶體設備1696之另一配置。在陣列之相反側上以對稱方式來實施由各種周邊電路對記憶體陣列1500之存取，使得每一側上之存取線及電路的密度減小一半。因此，將列解碼器分為列解碼器1630A及1630B，且將行解碼器分為行解碼器1660A及1660B。類似地，將讀取/寫入電路分為自陣列1500之底部連接至位元線的讀取/寫入電路1665A及自陣列1500之頂部連接至位元線的讀取/寫入電路1665B。以此方式，讀取/寫入模組之密度本質上減小一半。如上文針對圖16之設備所描述，圖17之設備亦可包括控制器。17 is a block diagram of a non-volatile memory system utilizing a dual column/row decoder and a read/write circuit. Here, another configuration of the memory device 1696 shown in FIG. 16 is provided. Access to the memory array 1500 by various peripheral circuits is performed symmetrically on opposite sides of the array such that the density of access lines and circuitry on each side is reduced by half. Therefore, the column decoder is divided into column decoders 1630A and 1630B, and the row decoder is divided into row decoders 1660A and 1660B. Similarly, the read/write circuit is divided into a read/write circuit 1665A connected from the bottom of the array 1500 to the bit line and a read/write circuit 1665B connected from the top of the array 1500 to the bit line. In this way, the density of the read/write modules is essentially reduced by half. As described above with respect to the device of Figure 16, the device of Figure 17 may also include a controller.

圖18為描繪感測區塊之一實施例的方塊圖。個別感測區塊1600經分割成核心部分(被稱為感測模組1680)，及共同部分1690。在一實施例中，將存在用於每一位元線之單獨感測模組1680及用於多個感測模組1680之集合的一共同部分1690。在一實例中，一感測區塊將包括一個共同部分 1690及八個感測模組1680。群中之感測模組中之每一者將經由資料匯流排1672而與關聯共同部分通信。關於其他細節，參考2006年6月29日公開的名為"Non-Volatile Memory and Method with Shared Processing for an Aggregateof Sense Amplifiers"之美國專利申請案公開案第2006/0140007號，且其全文以引用的方式併入本文中。18 is a block diagram depicting one embodiment of a sensing block. The individual sensing blocks 1600 are segmented into a core portion (referred to as sensing module 1680), and a common portion 1690. In one embodiment, there will be a separate sensing module 1680 for each bit line and a common portion 1690 for the collection of multiple sensing modules 1680. In an example, a sensing block will include a common portion 1690 and eight sensing modules 1680. Each of the sensing modules in the group will communicate with the associated common portion via data bus 1672. For further details, reference is made to U.S. Patent Application Publication No. 2006/014, the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire The manner is incorporated herein.

感測模組1680包含感測電路1670，感測電路1670判定所連接之位元線中之傳導電流是高於還是低於預定臨限位準。感測模組1680亦包括位元線鎖存器1682，位元線鎖存器1682用於設定所連接之位元線上之電壓條件。舉例而言，鎖存於位元線鎖存器1682中之預定狀態將導致所連接之位元線被拉至指定程式禁止之狀態(例如，V_dd )。The sensing module 1680 includes a sensing circuit 1670 that determines whether the conduction current in the connected bit line is above or below a predetermined threshold level. The sensing module 1680 also includes a bit line latch 1682 for setting a voltage condition on the connected bit line. For example, a predetermined state latched in the bit line latch 1682 will cause the connected bit line to be pulled to a state (eg, V _dd ) that the specified program is disabled.

共同部分1690包含處理器1692、資料鎖存器集合1694及耦合於資料鎖存器集合1694與資料匯流排1620之間的I/O介面1696。處理器1692執行計算。舉例而言，其功能中之一者係判定儲存於經感測儲存元件中之資料，且將經判定資料儲存於資料鎖存器集合中。資料鎖存器集合1694用於在讀取操作期間儲存由處理器1692所判定之資料位元。其亦用於在程式操作期間儲存自資料匯流排1620所輸入之資料位元。所輸入之資料位元表示意欲經程式化至記憶體中之寫入資料。I/O介面1696提供資料鎖存器1694與資料匯流排1620之間的介面。The common portion 1690 includes a processor 1692, a data latch set 1694, and an I/O interface 1696 coupled between the data latch set 1694 and the data bus 1620. The processor 1692 performs the calculation. For example, one of its functions determines the data stored in the sensed storage element and stores the determined data in a set of data latches. The data latch set 1694 is used to store the data bits determined by the processor 1692 during the read operation. It is also used to store data bits entered from the data bus 1620 during program operation. The entered data bit represents the written data intended to be programmed into the memory. I/O interface 1696 provides an interface between data latch 1694 and data bus 1620.

在讀取或感測期間，系統之操作處於狀態機1612之控制下，狀態機1612控制不同控制閘極電壓至經定址儲存元件 之供應。由於其經由對應於由記憶體所支援之各種記憶體狀態的各種預定控制閘極電壓而步進，所以感測模組1680可在此等電壓中之一者下跳脫且輸出將經由匯流排1672而自感測模組1680提供至處理器1692。此時，處理器1692藉由考慮感測模組之跳脫事件及關於經由輸入線1693而自狀態機所施加之控制閘極電壓的資訊來判定所得記憶體狀態。其接著計算用於記憶體狀態之二元編碼(碼字)且將所得資料位元儲存至資料鎖存器1694中。在核心部分之另一實施例中，位元線鎖存器1682提供雙重用途，均作為用於鎖存感測模組1680之輸出的鎖存器且亦作為如上文所描述之位元線鎖存器。During reading or sensing, the operation of the system is under the control of state machine 1612, which controls different control gate voltages to the addressed storage elements. Supply. Since it is stepped through various predetermined control gate voltages corresponding to various memory states supported by the memory, the sensing module 1680 can trip under one of the voltages and the output will be via the busbar The self-sense module 1680 is provided to the processor 1692. At this time, the processor 1692 determines the obtained memory state by considering the tripping event of the sensing module and the information about the control gate voltage applied from the state machine via the input line 1693. It then computes the binary code (codeword) for the memory state and stores the resulting data bit into data latch 1694. In another embodiment of the core portion, bit line latch 1682 provides dual use, both as latches for latching the output of sensing module 1680 and also as a bit line lock as described above. Save.

據預期，一些實施例將包括多個處理器1692。在一實施例中，每一處理器1692將包括輸出線(未描繪)，使得輸出線中之每一者經線或(wired-OR)在一起。在一些實施例中，輸出線在連接至線或線之前被反轉。此組態使得能夠在程式驗證過程期間快速判定程式化過程何時已完成，因為接收線或之狀態機可判定經程式化之所有位元何時已達到所要位準。舉例而言，當每一位元已達到其所要位準時，用於彼位元之邏輯0將被發送至線或線(或資料1被反轉)。當所有位元輸出資料0(經反轉之資料1)時，則狀態機知道終止程式化過程。因為每一處理器與八個感測模組通信，所以狀態機需要讀取線或線八次，或將邏輯添加至處理器1692以累積關聯位元線之結果，使得狀態機僅需要讀取線或線一次。類似地，藉由正確地選擇邏輯位準，全域 狀態機可偵測第一位元何時改變其狀態其相應地改變演算法。It is contemplated that some embodiments will include multiple processors 1692. In an embodiment, each processor 1692 will include an output line (not depicted) such that each of the output lines is wired-OR together. In some embodiments, the output line is inverted before being connected to a line or line. This configuration enables a quick determination of when the stylization process has completed during the program verification process because the receive line or state machine can determine when all of the stylized bits have reached the desired level. For example, when each bit has reached its desired level, a logic 0 for that bit will be sent to the line or line (or data 1 is inverted). When all bits output data 0 (inverted data 1), the state machine knows to terminate the stylization process. Because each processor communicates with eight sensing modules, the state machine needs to read the lines or lines eight times, or add logic to the processor 1692 to accumulate the result of the associated bit lines, so that the state machine only needs to read Line or line once. Similarly, by properly selecting the logical level, the whole domain The state machine can detect when the first bit changes its state and change the algorithm accordingly.

在程式化或驗證期間，將待程式化之資料自資料匯流排1620儲存於資料鎖存器集合1694中。在狀態機之控制下的程式操作包含施加至經定址儲存元件之控制閘極的程式化電壓脈衝系列。每一程式化脈衝之後為讀回(驗證)以判定儲存元件是否已被程式化至所要記憶體狀態。處理器1692相對於所要記憶體狀態而監視所讀回之記憶體狀態。當兩者達成一致時，處理器1692設定位元線鎖存器1682，以便使位元線被拉至指定程式禁止之狀態。此禁止耦合至位元線之儲存元件進一步程式化，即使程式化脈衝出現在其控制閘極上時亦係如此。在其他實施例中，在驗證過程期間，處理器最初載入位元線鎖存器1682，且感測電路將其設定為禁止值。The data to be programmed is stored in the data latch set 1694 from the data bus 1620 during stylization or verification. Program operations under the control of the state machine include a series of stylized voltage pulses applied to the control gates of the addressed storage elements. Each stylized pulse is then read back (verified) to determine if the storage element has been programmed to the desired memory state. The processor 1692 monitors the read back memory state with respect to the desired memory state. When the two agree, the processor 1692 sets the bit line latch 1682 to cause the bit line to be pulled to a state where the specified program is disabled. This storage element, which is prohibited from coupling to the bit line, is further programmed, even if a stylized pulse appears on its control gate. In other embodiments, during the verification process, the processor initially loads the bit line latch 1682 and the sensing circuit sets it to a disable value.

資料鎖存器堆疊1694含有對應於感測模組之資料鎖存器堆疊。在一實施例中，每一感測模組1680存在三個資料鎖存器。在一些實施例(但並非所需要的)中，將資料鎖存器實施為移位暫存器，使得儲存於其中之並行資料轉換成用於資料匯流排1620之串行資料，且反之亦然。在較佳實施例中，對應於具有m個儲存元件之讀取/寫入區塊的所有資料鎖存器可聯接於一起以形成區塊移位暫存器，使得可藉由串行轉移來輸入或輸出資料區塊。詳言之，具有r個讀取/寫入模組之組經調適成使得其資料鎖存器集合中之每一者依次將資料移入或移出資料匯流排，如同其為用於整 個讀取/寫入區塊之移位暫存器之一部分一般。The data latch stack 1694 contains a data latch stack corresponding to the sense module. In one embodiment, there are three data latches per sensing module 1680. In some embodiments, but not required, the data latch is implemented as a shift register such that parallel data stored therein is converted to serial data for data bus 1620, and vice versa . In a preferred embodiment, all of the data latches corresponding to the read/write blocks having m storage elements can be coupled together to form a block shift register so that it can be transferred by serial transfer. Enter or output data blocks. In particular, a group having r read/write modules is adapted such that each of its data latch sets sequentially shifts data into or out of the data bus as if it were used for One of the shift registers of the read/write block is generally.

關於非揮發性儲存設備之各種實施例之結構及/或操作的額外資訊可在以下各案中被找到：(1)2004年3月25日公開之美國專利申請案公開案第2004/0057287號，"Non-Volatile Memory And Method With Reduced Source Line Bias Errors";(2)2004年6月10日公開之美國專利申請案公開案第2004/0109357號，"Non-Volatile Memory And Method with Improved Sensing";(3)2004年12月16日提出申請之名為"Improved Memory Sensing Circuit And Method For Low Voltage Operation"之美國專利申請案第11/015,199號；(4)2005年4月5日提出申請之名為"Compensating for Coupling During Read Operations of Non-Volatile Memory"之美國專利申請案11/099,133；及(5)2005年13月28日提出申請之名為"Reference Sense Amplifier For Non-Volatile Memory"之美國專利申請案第11/321,953號。所有五個緊接上文所列出之專利文獻的全部內容均以引用的方式併入本文中。Additional information regarding the structure and/or operation of various embodiments of non-volatile storage devices can be found in the following: (1) U.S. Patent Application Publication No. 2004/0057287, issued March 25, 2004 "Non-Volatile Memory And Method With Reduced Source Line Bias Errors"; (2) US Patent Application Publication No. 2004/0109357, published on Jun. 10, 2004, "Non-Volatile Memory And Method with Improved Sensing" (3) US Patent Application No. 11/015,199, entitled "Improved Memory Sensing Circuit And Method For Low Voltage Operation", filed on December 16, 2004; (4) Application filed on April 5, 2005 U.S. Patent Application Serial No. 11/099,133, entitled "Compensating for Coupling During Read Operations of Non-Volatile Memory"; and (5) "Reference Sense Amplifier For Non-Volatile Memory", filed on March 28, 2005 U.S. Patent Application Serial No. 11/321,953. All of the five patent documents listed immediately above are hereby incorporated by reference.

圖19說明記憶體陣列至用於全位元線記憶體架構或用於奇偶記憶體架構之區塊之組織的實例。描述記憶體陣列1500之例示性結構。作為一實例，描述經分割成1,024個區塊之NAND快閃EEPROM。儲存於每一區塊中之資料可經同時抹除。在一實施例中，區塊為經同時抹除之最小儲存元件單位。在此實例中，在每一區塊中存在對應於位元線BL0、BL1、…BL8511之8,512個行。在被稱為全位元線 (ABL)架構(架構1910)之一實施例中，可在讀取及程式操作期間同時選擇區塊之所有位元線。可同時程式化沿共同字線且連接至任一位元線之儲存元件。Figure 19 illustrates an example of a memory array to organization for a full bit line memory architecture or a block for a parity memory architecture. An illustrative structure of memory array 1500 is depicted. As an example, a NAND flash EEPROM that is partitioned into 1,024 blocks is described. The data stored in each block can be erased at the same time. In one embodiment, the block is the smallest storage element unit that is simultaneously erased. In this example, there are 8,512 rows corresponding to bit lines BL0, BL1, ... BL8511 in each block. Full bit line In one embodiment of the (ABL) architecture (architecture 1910), all of the bit lines of the block can be selected simultaneously during read and program operations. Storage elements along a common word line and connected to any bit line can be programmed simultaneously.

在所提供之實例中，64個儲存元件及兩個虛設儲存元件串聯連接以形成NAND串。存在64個資料字線及2個虛設字線WL-d0及WL-d1，其中每一NAND串包括64個資料儲存元件及2個虛設儲存元件。在其他實施例中，NAND串可具有多於或少於64個資料儲存元件及2個虛設儲存元件。資料記憶體單元可儲存使用者或系統資料。虛設記憶體單元通常不用於儲存使用者或系統資料。In the example provided, 64 storage elements and two dummy storage elements are connected in series to form a NAND string. There are 64 data word lines and 2 dummy word lines WL-d0 and WL-d1, wherein each NAND string includes 64 data storage elements and 2 dummy storage elements. In other embodiments, the NAND string can have more or less than 64 data storage elements and 2 dummy storage elements. The data memory unit stores user or system data. Dummy memory cells are typically not used to store user or system data.

NAND串之一端子經由汲極選擇閘極(連接至選擇閘極汲極線SGD)而連接至對應位元線，且另一端子經由源極選擇閘極(連接至選擇閘極源極線SGS)而連接至共同源極。One terminal of the NAND string is connected to the corresponding bit line via the drain select gate (connected to the select gate drain line SGD), and the other terminal is connected to the select gate source line SGS via the source select gate ) and connected to a common source.

在被稱為奇偶架構(架構1900)之一實施例中，將位元線劃分為偶數位元線(BLe)及奇數位元線(BLo)。在此狀況下，沿共同字線且連接至奇數位元線之儲存元件在一時間經程式化，而沿共同字線且連接至偶數位元線之儲存元件在另一時間經程式化。可將資料程式化至不同區塊中，且同時自不同區塊讀取資料。在此實例中，在每一區塊中存在經劃分為偶數行及奇數行的8,512個行。In one embodiment, referred to as an odd-even architecture (architecture 1900), the bit lines are divided into even bit lines (BLe) and odd bit lines (BLo). In this case, the storage elements along the common word line and connected to the odd bit lines are programmed at one time, while the storage elements along the common word line and connected to the even bit lines are programmed at another time. The data can be programmed into different blocks and data can be read from different blocks at the same time. In this example, there are 8,512 rows divided into even rows and odd rows in each block.

在讀取及程式化操作之一組態期間，同時選擇4,256個儲存元件。所選定之儲存元件具有同一字線及同一種位元線(例如，偶數或奇數)。因此，可同時讀取或程式化形成邏輯頁之532個資料位元組，且記憶體之一個區塊可儲存 至少八個邏輯頁(四個字線，每一者具有奇數頁及偶數頁)。對於多狀態儲存元件而言，當每一儲存元件儲存兩個資料位元(其中此等兩個位元中之每一者儲存於不同頁中)時，一個區塊儲存十六個邏輯頁。亦可利用其他大小的區塊及頁。During the configuration of one of the read and program operations, 4,256 storage elements are selected simultaneously. The selected storage elements have the same word line and the same bit line (eg, even or odd). Therefore, 532 data bytes of the logical page can be simultaneously read or programmed, and one block of the memory can be stored. At least eight logical pages (four word lines, each with odd and even pages). For multi-state storage elements, one block stores sixteen logical pages when each storage element stores two data bits (where each of the two bits is stored in a different page). Other sizes of blocks and pages can also be utilized.

對於ABL或奇偶架構而言，可藉由將p井上升至抹除電壓(例如，20 V)且使選定區塊之字線接地來抹除儲存元件。源極及位元線係浮動的。可對整個記憶體陣列、單獨區塊或作為記憶體設備之一部分的另一儲存元件單位執行抹除。電子自儲存元件之浮動閘極轉移至p井區域，使得儲存元件之V_TH 變為負。For an ABL or parity architecture, the storage element can be erased by raising the p-well to an erase voltage (eg, 20 V) and grounding the word line of the selected block. The source and bit lines are floating. Erasing can be performed on the entire memory array, in a separate block, or as another storage element unit that is part of a memory device. The floating gate of the electron self-storage element is transferred to the p-well region such that the _{VTH of the} storage element becomes negative.

在讀取及驗證操作中，選擇閘極(SGD及SGS)連接至在2.5至4.5 V之範圍內的電壓，且未選定字線(例如，在WL2為選定字線時的WL0、WL1及WL3)上升至讀取通過電壓V_READ (通常為在4.5至6V之範圍內的電壓)以使電晶體作為通過閘極而操作。選定字線WL2連接至電壓，其位準經指定用於每一讀取及驗證操作，以便判定有關儲存元件之V_TH 是高於還是低於此位準。舉例而言，在用於二級儲存元件之讀取操作中，可使選定字線WL2接地，使得偵測V_TH 是否高於0 V。在用於二級儲存元件之驗證操作中，將選定字線WL2連接至(例如)0.8 V，使得驗證V_TH 是否已達到至少0.8 V。源極及p井處於0 V。選定位元線(假設為偶數位元線(BLe))被預充電至(例如)0.7 V之位準。若V_TH 高於字線上之讀取或驗證位準，則與所關注儲存元件相關聯 之位元線(BLe)的電位位準由於非導電儲存元件而維持高位準。另一方面，若V_TH 低於讀取或驗證位準，則因為導電儲存元件使位元線放電，所以有關位元線(BLe)之電位位準降低至低位準(例如，小於0.5 V)。儲存元件之狀態可藉此由連接至位元線之電壓比較器感測放大器偵測。In the read and verify operations, the select gates (SGD and SGS) are connected to voltages in the range of 2.5 to 4.5 V, and the word lines are not selected (eg, WL0, WL1, and WL3 when WL2 is the selected word line) Rising to the read pass voltage V _READ (typically a voltage in the range of 4.5 to 6V) to operate the transistor as a pass gate. The selected word line WL2 is coupled to a voltage whose level is designated for each read and verify operation to determine if the _VTH of the associated storage element is above or below this level. For example, in a read operation for a secondary storage element, the selected word line WL2 can be grounded such that the _VTH is detected to be above 0V. In the verify operation for the secondary storage element, the selected word line WL2 is connected to, for example, 0.8 V, such that it is verified whether the _VTH has reached at least 0.8 V. The source and p wells are at 0 V. The selected positioning element line (assumed to be an even bit line (BLe)) is precharged to a level of, for example, 0.7 V. If the _{VTH is} above the read or verify level on the word line, the potential level of the bit line (BLe) associated with the storage element of interest maintains a high level due to the non-conductive storage element. On the other hand, if the _{VTH is} lower than the read or verify level, since the conductive storage element discharges the bit line, the potential level of the relevant bit line (BLe) is lowered to a low level (for example, less than 0.5 V). . The state of the storage element can thereby be detected by a voltage comparator sense amplifier connected to the bit line.

上文所描述之抹除、讀取及驗證操作係根據此項技術中已知之技術來執行。因此，所解釋之細節中的許多細節可由熟習此項技術者改變。亦可利用此項技術中已知之其他抹除、讀取及驗證技術。The erase, read and verify operations described above are performed in accordance with techniques known in the art. Thus, many of the details of the details explained can be changed by those skilled in the art. Other erase, read, and verify techniques known in the art can also be utilized.

圖20描繪實例臨限電壓分布集合。為每一儲存元件儲存兩個資料位元之狀況提供用於儲存元件陣列之實例V_TH 分布。提供用於經抹除儲存元件之第一臨限電壓分布E。亦描繪用於經程式化儲存元件之三種臨限電壓分布A、B及C。在一實施例中，E分布中之臨限電壓為負，且A、B及C分布中之臨限電壓為正。注意，此簡化實例指代四個狀態。然而，可利用額外狀態(例如，16、32、64或更多)。Figure 20 depicts an example set of threshold voltage distributions. The condition of storing two data bits for each storage element provides an example _VTH distribution for storing the array of elements. A first threshold voltage distribution E is provided for erasing the storage element. Three threshold voltage distributions A, B, and C for the stylized storage elements are also depicted. In one embodiment, the threshold voltage in the E distribution is negative and the threshold voltage in the A, B, and C distributions is positive. Note that this simplified example refers to four states. However, additional states (eg, 16, 32, 64 or more) may be utilized.

每一相異臨限電壓範圍對應於資料位元集合之預定值。經程式化至儲存元件中之資料與儲存元件之臨限電壓位準之間的特定關係視用於儲存元件之資料編碼機制而定。舉例而言，美國專利第6,222,762號及2004年12月16日公開之美國專利申請案公開案第2004/0255090號(其全部內容均以引用的方式併入本文中)描述用於多狀態快閃儲存元件之各種資料編碼機制。在一實施例中，利用格雷(Gray)碼指派而將資料值指派給臨限電壓範圍，使得若浮動閘極之臨 限電壓錯誤地移至其相鄰實體狀態，則僅一個位元將受到影響。一實例將"11"指派給臨限電壓範圍E(狀態E)，將"10"指派給臨限電壓範圍A(狀態A)，將"00"指派給臨限電壓範圍B(狀態B)，且將"01"指派給臨限電壓範圍C(狀態C)。然而，在其他實施例中，不利用格雷碼。儘管展示四個狀態，但本發明亦可與包括彼等包括多於或少於四個狀態之結構的其他多狀態結構一起利用。Each distinct threshold voltage range corresponds to a predetermined value of the set of data bits. The particular relationship between the data programmed into the storage element and the threshold voltage level of the storage element depends on the data encoding mechanism used to store the component. For example, U.S. Patent No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090, the entire contents of each of Various data encoding mechanisms for storage components. In one embodiment, the data value is assigned to the threshold voltage range using a Gray code assignment such that if the floating gate is present If the voltage limit is incorrectly moved to its neighboring entity state, only one bit will be affected. An example assigns "11" to the threshold voltage range E (state E), "10" to the threshold voltage range A (state A), and "00" to the threshold voltage range B (state B), And assign "01" to the threshold voltage range C (state C). However, in other embodiments, the Gray code is not utilized. Although four states are shown, the invention may also be utilized with other multi-state structures including structures that include more or less than four states.

亦提供三個讀取參考電壓Vra、Vrb及Vrc以用於自儲存元件讀取資料。藉由測試給定儲存元件之臨限電壓是高於還是低於Vra、Vrb及Vrc，系統可判定儲存元件所處之狀態(例如，程式化條件)。在四個狀態的情況下，利用三個讀取參考電壓或比較點。在16個狀態的情況下，利用15個比較點，等等。此等為在先前所論述之步驟1102、1110、1132、1150、1172、1192、1478及1486處所參考之類型的比較點。Three read reference voltages Vra, Vrb, and Vrc are also provided for reading data from the storage element. By testing whether the threshold voltage of a given storage element is above or below Vra, Vrb, and Vrc, the system can determine the state in which the storage element is located (eg, stylized conditions). In the case of four states, three read reference voltages or comparison points are utilized. In the case of 16 states, 15 comparison points are utilized, and so on. These are the comparison points of the types referenced at steps 1102, 1110, 1132, 1150, 1172, 1192, 1478, and 1486 previously discussed.

另外，提供三個驗證參考電壓Vva、Vvb及Vvc。額外驗證點可用於儲存指示額外程式化狀態之資料的儲存元件。In addition, three verification reference voltages Vva, Vvb, and Vvc are provided. Additional verification points can be used to store storage elements that indicate additional stylized status.

當將儲存元件程式化至狀態A時，系統將測試彼等儲存元件是否具有大於或等於Vva之臨限電壓。當將儲存元件程式化至狀態B時，系統將測試儲存元件是否具有大於或等於Vvb之臨限電壓。當將儲存元件程式化至狀態C時，系統將判定儲存元件是否具有其大於或等於Vvc之臨限電壓。When the storage elements are programmed to state A, the system will test whether their storage elements have a threshold voltage greater than or equal to Vva. When the storage element is programmed to state B, the system will test whether the storage element has a threshold voltage greater than or equal to Vvb. When the storage element is programmed to state C, the system will determine if the storage element has its threshold voltage greater than or equal to Vvc.

在被稱為全序列程式化之一實施例中，可將儲存元件直 接自抹除狀態E程式化至經程式化狀態A、B或C中之任一者。舉例而言，可首先抹除待程式化之儲存元件群體，使得群體中之所有儲存元件均處於經抹除狀態E。諸如由圖24之控制閘極電壓序列所描繪之程式化脈衝系列將接著用於將儲存元件直接程式化至狀態A、B或C中。在將一些儲存元件自狀態E程式化至狀態A時，將其他儲存元件自狀態E程式化至狀態B及/或自狀態E程式化至狀態C。當在WLn上自狀態E程式化至狀態C時，使在WLn-1下至鄰近浮動閘極之寄生耦合量最大化，因為與在自狀態E程式化至狀態A或自狀態E程式化至狀態B時的電壓改變相比，在WLn下浮動閘極上之電荷量改變最大。當自狀態E程式化至狀態B時，至鄰近浮動閘極之耦合量減小，但仍顯著。In one embodiment referred to as full sequence stylization, the storage component can be straight The erase state E is stylized to any of the stylized states A, B, or C. For example, the population of storage elements to be programmed may be erased first such that all storage elements in the population are in erased state E. A series of stylized pulses, such as depicted by the control gate voltage sequence of Figure 24, will then be used to program the storage elements directly into state A, B or C. When staging some of the storage elements from state E to state A, the other storage elements are programmed from state E to state B and/or from state E to state C. When staging from state E to state C on WLn, the parasitic coupling amount from WLn-1 to the adjacent floating gate is maximized because it is stylized from state E to state A or from state E to The amount of charge on the floating gate at WLn changes the most compared to the voltage change in state B. When staging from state E to state B, the amount of coupling to the adjacent floating gate is reduced, but still significant.

當自狀態E程式化至狀態A時，耦合量甚至進一步減小。When staging from state E to state A, the amount of coupling is even further reduced.

因此，為隨後讀取WLn-1之每一狀態所需要的校正量將視WLn上之鄰近儲存元件之狀態而變化。亦可將所展示之過程擴展至額外狀態。Therefore, the amount of correction required to subsequently read each state of WLn-1 will vary depending on the state of the adjacent storage elements on WLn. The process shown can also be extended to an extra state.

圖21說明程式化多狀態儲存元件之雙進程(two-pass)技術的實例，多狀態儲存元件儲存用於兩個不同頁之資料：下部頁及上部頁。描繪四個狀態：狀態E(11)、狀態A(10)、狀態B(00)及狀態C(01)。亦可將所展示之過程擴展至額外狀態。對於狀態E而言，兩個頁均儲存"1"。對於狀態A而言，下部頁儲存"0"且上部頁儲存"1"。對於狀態B而言，兩個頁均儲存"0"。對於狀態C而言，下部頁儲存"1"且上部頁儲存"0"。注意，儘管已將特定位元型樣指派給 狀態中之每一者，但亦可指派不同位元型樣。Figure 21 illustrates an example of a two-pass technique for a stylized multi-state storage element that stores data for two different pages: a lower page and an upper page. Four states are depicted: state E (11), state A (10), state B (00), and state C (01). The process shown can also be extended to an extra state. For state E, both pages store "1". For state A, the lower page stores "0" and the upper page stores "1". For state B, both pages store "0". For state C, the lower page stores "1" and the upper page stores "0". Note that although a specific bit pattern has been assigned to Each of the states, but different bit patterns can also be assigned.

在第一程式化進程中，儲存元件之臨限電壓位準係根據待程式化至下部邏輯頁中之位元來設定。若彼位元為邏輯"1"，則臨限電壓不改變，因為其由於早先已得以抹除而處於適當狀態。然而，若待程式化之位元為邏輯"0"，則如箭頭2100所示，儲存元件之臨限位準增加至處於狀態A。彼結束第一程式化進程。In the first stylization process, the threshold voltage level of the storage element is set according to the bit to be programmed into the lower logical page. If the bit is a logical "1", the threshold voltage does not change because it is in an appropriate state because it has been erased earlier. However, if the bit to be programmed is a logic "0", then as indicated by arrow 2100, the threshold level of the storage element is increased to state A. He ended the first stylization process.

在第二程式化進程中，儲存元件之臨限電壓位準係根據經程式化至上部邏輯頁中之位元來設定。若上部邏輯頁位元將儲存邏輯"1"，則不發生程式化，因為視下部頁位元之程式化而定，儲存元件處於狀態E或A中之一者，其均載運上部頁位元"1"。若上部頁位元將為邏輯"0"，則臨限電壓移位。若第一進程導致儲存元件保持於經抹除狀態E，則在第二階段中，如由箭頭2120所描繪，儲存元件經程式化，使得臨限電壓增加至處於狀態C內。若儲存元件已由於第一程式化進程而經程式化至狀態A中，則儲存元件在第二進程中經進一步程式化，使得，如由箭頭2110所描繪，臨限電壓增加至處於狀態B內。第二進程之結果係將儲存元件程式化至所指定之狀態中以儲存用於上部頁之邏輯"0"，而無需改變用於下部頁之資料。在圖20及圖21中，至鄰近字線上之浮動閘極的耦合量視最終狀態而定。In the second stylization process, the threshold voltage level of the storage element is set according to the bits that are programmed into the upper logical page. If the upper logical page bit will store a logic "1", no stylization will occur, because depending on the stylization of the lower page bit, the storage element is in one of the states E or A, which carry the upper page bit. "1". If the upper page bit will be a logic "0", the threshold voltage is shifted. If the first process causes the storage element to remain in the erased state E, then in the second phase, as depicted by arrow 2120, the storage element is programmed such that the threshold voltage is increased to be in state C. If the storage element has been programmed into state A due to the first stylization process, the storage element is further stylized in the second process such that, as depicted by arrow 2110, the threshold voltage is increased to be in state B. . The result of the second process is to program the storage element into the specified state to store the logic "0" for the upper page without changing the data for the lower page. In Figures 20 and 21, the amount of coupling to the floating gates on adjacent word lines depends on the final state.

在一實施例中，若足夠資料經寫入以填滿整頁，則可設置系統以執行全序列寫入。若對於全頁而言未寫入足夠資料，則程式化過程可程式化利用所接收之資料而程式化的 下部頁。當接收到後續資料時，系統將接著程式化上部頁。在又一實施例中，系統可在程式化下部頁之模式中開始寫入，且若隨後接收到足夠資料以填滿整個字線(或字線之大部分)之儲存元件，則系統可轉換至全序列程式化模式。2006年6月15日公開的名為"Pipelined Programming of Non-Volatile Memories Using Early Data"之美國專利申請案公開案第2006/0126390號中揭示此實施例之更多細節，該案之全部內容以引用的方式併入本文中。In one embodiment, if enough data is written to fill the entire page, the system can be set up to perform a full sequence of writes. If sufficient data is not written for the full page, the stylization process can be stylized using the received data to be stylized. Lower page. When subsequent data is received, the system will then program the upper page. In yet another embodiment, the system can begin writing in the mode of the programmed lower page, and the system can convert if sufficient data is subsequently received to fill the storage elements of the entire word line (or a majority of the word lines). To full sequence stylized mode. Further details of this embodiment are disclosed in U.S. Patent Application Publication No. 2006/0126390, the entire disclosure of which is incorporated herein to The manner of reference is incorporated herein.

圖22a至圖22c揭示用於程式化非揮發性記憶體之另一過程，其藉由對於任一特定儲存元件而在針對先前頁來寫入至鄰近儲存元件之後相對於特定頁而寫入至彼特定儲存元件來減少浮動閘極至浮動閘極耦合效應。在一實例實施例中，非揮發性儲存元件利用四個資料狀態而在每一儲存元件上儲存兩個資料位元。亦可將所展示之過程擴展至額外狀態。舉例而言，假設狀態E為經抹除狀態且狀態A、B及C為經程式化狀態。狀態E儲存資料11。狀態A儲存資料01。狀態B儲存資料10。狀態C儲存資料00。因為兩個位元均在鄰近狀態A與B之間改變，所以此為非格雷編碼之實例。亦可利用資料至實體資料狀態之其他編碼。每一儲存元件儲存兩個資料頁。出於參考之目的，此等資料頁將被稱為上部頁及下部頁；然而，其可被給定其他標記。參考狀態A，上部頁儲存位元0且下部頁儲存位元1。參考狀態B，上部頁儲存位元1且下部頁儲存位元0。參考狀態C，兩個頁均儲存位元資料0。22a-22c disclose another process for programming non-volatile memory that is written to a particular page after being written to a neighboring storage element for a previous page for any particular storage element The specific storage element reduces the floating gate to floating gate coupling effect. In an example embodiment, the non-volatile storage element stores two data bits on each storage element using four data states. The process shown can also be extended to an extra state. For example, assume that state E is the erased state and states A, B, and C are stylized. State E stores data 11. State A stores data 01. State B stores data 10. State C stores data 00. This is an example of non-Gray coding because both bits change between adjacent states A and B. Other codes for the status of the data can also be used. Each storage element stores two data pages. For the purposes of this reference, such material pages will be referred to as upper and lower pages; however, they may be given other indicia. Referring to state A, the upper page stores bit 0 and the lower page stores bit 1. Referring to state B, the upper page stores bit 1 and the lower page stores bit 0. Referring to state C, both pages store bit data 0.

程式化過程為二步驟過程。在第一步驟中，程式化下部頁。若下部頁將保持資料1，則儲存元件狀態保持於狀態E。若資料將經程式化至0，則儲存元件之電壓臨限值上升，使得儲存元件經程式化至狀態B'。圖22a因此展示儲存元件自狀態E至狀態B'之程式化。狀態B'為中間狀態B；因此，驗證點被描繪為Vvb'，其低於Vvb。The stylization process is a two-step process. In the first step, the lower page is programmed. If the lower page will hold data 1, the storage element state remains in state E. If the data is programmed to zero, the voltage threshold of the storage element rises, causing the storage element to be programmed to state B'. Figure 22a thus shows the stylization of the storage element from state E to state B'. State B' is intermediate state B; therefore, the verification point is depicted as Vvb', which is lower than Vvb.

在一實施例中，在將儲存元件自狀態E程式化至狀態B'之後，其在NAND串中之相鄰儲存元件(WLn+1)接著將相對於其下部頁而經程式化。舉例而言，參看圖2，在程式化儲存元件106之下部頁之後，可能程式化儲存元件104之下部頁。在程式化儲存元件104之後，浮動閘極至浮動閘極耦合效應將在儲存元件104使臨限電壓自狀態E上升至狀態B'的情況下上升儲存元件106之視臨限電壓(apparent threshold voltage)。此將具有使針對狀態B'之臨限電壓分布加寬至經描繪為圖22b之臨限電壓分布2250之臨限電壓分布的效應。臨限電壓分布之此視加寬(apparent widening)將在程式化上部頁時得以矯正。In one embodiment, after the storage element is programmed from state E to state B', its adjacent storage element (WLn+1) in the NAND string will then be programmed relative to its lower page. For example, referring to FIG. 2, after staging the lower page of storage element 106, it is possible to program the lower page of storage element 104. After staging the storage element 104, the floating gate to floating gate coupling effect will raise the apparent threshold voltage of the storage element 106 when the storage element 104 causes the threshold voltage to rise from state E to state B'. ). This will have the effect of widening the threshold voltage distribution for state B' to the threshold voltage distribution depicted as threshold voltage distribution 2250 of Figure 22b. The apparent widening of the threshold voltage distribution will be corrected when the upper page is programmed.

圖22c描繪程式化上部頁之過程。若儲存元件處於經抹除狀態E且上部頁將保持於1，則儲存元件將保持於狀態E中。若儲存元件處於狀態E且其上部頁資料將經程式化為0，則儲存元件之臨限電壓將上升，使得儲存元件處於狀態A。若儲存元件在中間臨限電壓分布2250中且上部頁資料將保持於1，則儲存元件將經程式化至最終狀態B。若儲存元件在中間臨限電壓分布2250中且上部頁資料將變成資 料0，則儲存元件之臨限電壓將上升，使得儲存元件處於狀態C。由圖22a至圖22c所描繪之過程減小了浮動閘極至浮動閘極耦合效應，因為僅相鄰儲存元件之上部頁程式化將對給定儲存元件之視臨限電壓有影響。替代狀態編碼之實例係在上部頁資料為1時自分布2250移動至狀態C，且在上部頁資料為0時移動至狀態B。Figure 22c depicts the process of stylizing the upper page. If the storage element is in the erased state E and the upper page will remain at 1, the storage element will remain in state E. If the storage element is in state E and its upper page data is programmed to zero, then the threshold voltage of the storage element will rise, causing the storage element to be in state A. If the storage element is in the intermediate threshold voltage distribution 2250 and the upper page data will remain at 1, the storage element will be programmed to final state B. If the storage element is in the middle threshold voltage distribution 2250 and the upper page data will become Feed 0, the threshold voltage of the storage element will rise, causing the storage element to be in state C. The process depicted by Figures 22a through 22c reduces the floating gate to floating gate coupling effect because only the top page stylization of adjacent storage elements will have an effect on the apparent threshold voltage of a given storage element. An example of an alternate status code is to move from state 2250 to state C when the upper page data is 1, and to state B when the upper page data is zero.

儘管圖22a至圖22c提供關於四個資料狀態及兩個資料頁之實例，但所教示之概念可應用於具有多於或少於四個狀態及不同於兩頁之其他實施例。Although Figures 22a through 22c provide examples of four data states and two data pages, the concepts taught can be applied to other embodiments having more or less than four states and different from two pages.

圖23為描述用於程式化非揮發性記憶體之方法之一實施例的流程圖。在一實施例中，在程式化之前抹除(以區塊或其他單位)儲存元件。在步驟2300中，由控制器發布"資料載入"命令且由控制電路1610接收輸入。在步驟2305中，將指定頁位址之位址資料自控制器或主機輸入至解碼器1614。在步驟2310中，將用於經定址頁之程式資料頁輸入至資料緩衝器以供程式化。將彼資料鎖存於適當鎖存器集合中。在步驟2315中，由控制器將"程式"命令發布至狀態機1612。23 is a flow chart depicting one embodiment of a method for staging non-volatile memory. In one embodiment, the storage element is erased (in blocks or other units) prior to stylization. In step 2300, a "data load" command is issued by the controller and input is received by control circuit 1610. In step 2305, the address data specifying the page address is input from the controller or host to the decoder 1614. In step 2310, the program data page for the addressed page is entered into the data buffer for stylization. The data is latched into the appropriate set of latches. In step 2315, the "program" command is issued by the controller to state machine 1612.

由"程式"命令觸發，將利用圖24中施加至適當選定字線之脈衝串2400之台階狀程式脈衝來將在步驟2310中所鎖存之資料程式化至由狀態機1612所控制之選定儲存元件中。在步驟2320中，將程式電壓V_PGM 初始化至開始脈衝(例如，12 V或其他值)，且將由狀態機1612所維持之程式計數器(PC)初始化為0。在步驟2330中，將第一V_PGM 脈衝施 加至選定字線以開始程式化與選定字線相關聯之儲存元件。若邏輯"0"儲存於特定資料鎖存器中而指示應程式化對應儲存元件，則使對應位元線接地。另一方面，若邏輯"1"儲存於特定鎖存器中而指示對應儲存元件應保持於其當前資料狀態中，則將對應位元線連接至V_dd 以禁止程式化。Triggered by a "program" command, the data latched in step 2310 will be programmed to the selected memory controlled by state machine 1612 using the stepped program pulse of pulse train 2400 applied to the appropriately selected word line in FIG. In the component. In step 2320, the program voltage V _{PGM is} initialized to a start pulse (eg, 12 V or other value) and the program counter (PC) maintained by state machine 1612 is initialized to zero. In step 2330, a first V _PGM pulse is applied to the selected word line to begin programming the storage elements associated with the selected word line. If a logic "0" is stored in a particular data latch indicating that the corresponding storage element should be programmed, the corresponding bit line is grounded. On the other hand, if a logic "1" is stored in a particular latch indicating that the corresponding storage element should remain in its current data state, the corresponding bit line is connected to V _dd to disable stylization.

在步驟2335中，驗證選定儲存元件之狀態。若偵測到選定儲存元件之目標臨限電壓已達到適當位準，則將儲存於對應資料鎖存器中之資料改變至邏輯"1"。若偵測到臨限電壓尚未達到適當位準，則不改變儲存於對應資料鎖存器中之資料。以此方式，在對應資料鎖存器中儲存有邏輯"1"之位元線無需經程式化。當所有資料鎖存器均儲存邏輯"1"時，狀態機(經由上文所描述之線或型機制)知道所有選定儲存元件已被程式化。在決策步驟2340中，進行關於是否所有資料鎖存器均儲存邏輯"1"的檢查。若所有資料鎖存器均儲存邏輯"1"，則程式化過程完成且成功，因為所有選定儲存元件均經程式化及驗證。在步驟2345中報告"PASS"(通過)狀態。In step 2335, the status of the selected storage element is verified. If it is detected that the target threshold voltage of the selected storage element has reached the appropriate level, the data stored in the corresponding data latch is changed to logic "1". If it is detected that the threshold voltage has not reached the appropriate level, the data stored in the corresponding data latch is not changed. In this way, the bit line storing the logic "1" in the corresponding data latch does not need to be programmed. When all data latches store a logic "1", the state machine (via the line or type mechanism described above) knows that all selected storage elements have been programmed. In decision step 2340, a check is made as to whether all of the data latches store a logical "1". If all data latches store a logic "1", the stylization process is complete and successful because all selected storage elements are programmed and verified. The "PASS" status is reported in step 2345.

若在步驟2340中判定並非所有資料鎖存器均儲存邏輯"1"，則程式化過程繼續。在決策步驟2350中，對照程式極限值PCmax而檢查程式計數器PC。程式極限值之一實例為20；然而，亦可利用其他數目。若程式計數器PC不小於PCmax，則程式過程已失敗，且在步驟2355中報告"FAIL"(失敗)狀態。若程式計數器PC小於PCmax，則將 V_PGM 增加步長，且在步驟2360中遞增程式計數器PC。過程接著返回至步驟2330以施加下一V_PGM 脈衝。If it is determined in step 2340 that not all of the data latches store a logic "1", the stylization process continues. In decision step 2350, the program counter PC is checked against the program limit value PCmax. An example of one of the program limits is 20; however, other numbers may be utilized. If the program counter PC is not less than PCmax, the program process has failed and the "FAIL" status is reported in step 2355. If the program counter PC is less than PCmax, V _{PGM is} incremented by the step size and the program counter PC is incremented in step 2360. The process then returns to step 2330 to apply the next V _PGM pulse.

圖24描繪在程式化期間施加至非揮發性儲存元件之控制閘極之實例脈衝串2400。脈衝串2400包括施加至經選定用於程式化之字線的程式脈衝系列2405、2410、2415、2420、2425、2430、2435、2440、2445、2450、…。在一實施例中，程式化脈衝具有電壓V_PGM ，其以12 V開始且增加增量(例如，0.5 V)，以用於每一連續程式化脈衝，直至達到20 V之最大值。在程式脈衝之間的係驗證脈衝。舉例而言，驗證脈衝集合2406包括三個驗證脈衝。在一些實施例中，可存在用於資料經程式化至之每一狀態(例如，狀態A、B及C)之驗證脈衝。在其他實施例中，可存在更多或更少驗證脈衝。每一集合中之驗證脈衝可具有為(例如)Vva、Vvb及Vvc(圖21)或Vvb'(圖22a)之振幅。Figure 24 depicts an example pulse train 2400 applied to a control gate of a non-volatile storage element during stylization. Pulse train 2400 includes program pulse trains 2405, 2410, 2415, 2420, 2425, 2430, 2435, 2440, 2445, 2450, ... applied to selected word lines. In one embodiment, the stylized pulses have a voltage V _PGM that begins at 12 V and increases in increments (eg, 0.5 V) for each successive stylized pulse until a maximum of 20 V is reached. A system verification pulse between program pulses. For example, the set of verification pulses 2406 includes three verify pulses. In some embodiments, there may be a verify pulse for each state (eg, states A, B, and C) that the data is programmed to. In other embodiments, there may be more or fewer verification pulses. The verify pulses in each set may have amplitudes of, for example, Vva, Vvb, and Vvc (Fig. 21) or Vvb' (Fig. 22a).

如所提及，施加至字線以實施增壓模式之電壓在程式化發生時(例如，在程式脈衝之前及期間)被施加。實務上，可將增壓模式之增壓電壓稍微在每一程式脈衝之前起始且在每一程式脈衝之後移除。另一方面，在(例如)出現在程式脈衝之間的驗證過程期間，不施加增壓電壓。實情為，將通常小於增壓電壓之讀取電壓施加至未選定字線。讀取電壓具有足以在將當前經程式化之儲存元件之臨限電壓與驗證位準比較時使NAND串中先前經程式化之儲存元件維持開啟的振幅。As mentioned, the voltage applied to the word line to implement the boost mode is applied when stylization occurs (eg, before and during the program pulse). In practice, the boost voltage of the boost mode can be initiated slightly before each program pulse and removed after each program pulse. On the other hand, no boost voltage is applied during the verification process, for example, occurring between program pulses. The reality is that a read voltage, typically less than the boost voltage, is applied to the unselected word lines. The read voltage has an amplitude sufficient to maintain the previously programmed storage element in the NAND string open when comparing the threshold voltage of the currently programmed storage element to the verify level.

已為了說明及描述之目的而呈現本發明之前述詳細描 述。其不意欲為詳盡的或將本發明限於所揭示之精確形式。按照上述教示，許多修改及變化為可能的。選擇所描述實施例，以便最好地解釋本發明之原理及其實際應用，以藉此使得熟習此項技術者能夠最好地將本發明用於各種實施例中且在適合於所預期之特定用途之各種修改的情況下最好地利用本發明。意欲藉由此處附加之申請專利範圍來界定本發明之範疇。The foregoing detailed description of the present invention has been presented for purposes of illustration and description. Said. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments described are chosen to best explain the principles of the invention and the application of the invention in the The invention is best utilized in the context of various modifications of the use. The scope of the invention is intended to be defined by the scope of the appended claims.

100‧‧‧電晶體100‧‧‧Optoelectronics

100CG‧‧‧控制閘極100CG‧‧‧Control gate

100FG‧‧‧浮動閘極100FG‧‧‧ floating gate

102‧‧‧電晶體102‧‧‧Optoelectronics

102CG‧‧‧控制閘極102CG‧‧‧Control gate

102FG‧‧‧浮動閘極102FG‧‧‧ Floating Gate

104‧‧‧電晶體104‧‧‧Optoelectronics

104CG‧‧‧控制閘極104CG‧‧‧Control gate

104FG‧‧‧浮動閘極104FG‧‧‧Floating gate

106‧‧‧電晶體106‧‧‧Optoelectronics

106CG‧‧‧控制閘極106CG‧‧‧Control gate

106FG‧‧‧浮動閘極106FG‧‧‧ Floating Gate

120‧‧‧第一選擇閘極120‧‧‧First choice gate

120CG‧‧‧控制閘極120CG‧‧‧Control gate

122‧‧‧第二選擇閘極122‧‧‧Second selection gate

122CG‧‧‧控制閘極122CG‧‧‧Control gate

126‧‧‧位元線126‧‧‧ bit line

128‧‧‧源極線128‧‧‧ source line

320‧‧‧NAND串320‧‧‧NAND strings

321‧‧‧位元線321‧‧‧ bit line

322‧‧‧選擇閘極322‧‧‧Select gate

323‧‧‧儲存元件323‧‧‧Storage components

324‧‧‧儲存元件324‧‧‧Storage components

325‧‧‧儲存元件325‧‧‧Storage components

326‧‧‧儲存元件326‧‧‧Storage components

327‧‧‧選擇閘極327‧‧‧Selected gate

340‧‧‧NAND串340‧‧‧NAND string

341‧‧‧位元線341‧‧‧ bit line

342‧‧‧選擇閘極342‧‧‧Select gate

343‧‧‧儲存元件343‧‧‧Storage components

344‧‧‧儲存元件344‧‧‧Storage components

345‧‧‧儲存元件345‧‧‧Storage components

346‧‧‧儲存元件346‧‧‧Storage components

347‧‧‧選擇閘極347‧‧‧Selecting the gate

360‧‧‧NAND串360‧‧‧NAND string

361‧‧‧位元線361‧‧‧ bit line

362‧‧‧選擇閘極362‧‧‧Select gate

363‧‧‧儲存元件363‧‧‧Storage components

364‧‧‧儲存元件364‧‧‧Storage components

365‧‧‧儲存元件365‧‧‧Storage components

366‧‧‧儲存元件366‧‧‧Storage components

367‧‧‧選擇閘極367‧‧‧Select gate

402‧‧‧編碼器402‧‧‧Encoder

404‧‧‧非揮發性儲存器404‧‧‧Non-volatile storage

406‧‧‧LLR(對數概似比)表406‧‧‧LLR (logarithmic approximate ratio) table

408‧‧‧解碼器408‧‧‧Decoder

600‧‧‧直方圖600‧‧‧Histogram

602‧‧‧直方圖602‧‧‧Histogram

604‧‧‧直方圖604‧‧‧Histogram

650‧‧‧直方圖650‧‧‧Histogram

652‧‧‧直方圖652‧‧‧Histogram

654‧‧‧直方圖654‧‧‧Histogram

660‧‧‧實例分布660‧‧‧Instance distribution

662‧‧‧實例分布662‧‧‧Instance distribution

664‧‧‧實例分布664‧‧‧Instance distribution

1200‧‧‧矩陣1200‧‧‧Matrix

1300‧‧‧稀疏偶圖1300‧‧‧Sparse

1400‧‧‧波形1400‧‧‧ waveform

1402‧‧‧波形1402‧‧‧ waveform

1404‧‧‧波形1404‧‧‧ Waveform

1406‧‧‧預調節波形1406‧‧‧Pre-adjusted waveform

1408‧‧‧讀取脈衝1408‧‧‧Read pulse

1410‧‧‧波形1410‧‧‧ waveform

1412‧‧‧波形1412‧‧‧ waveform

1414‧‧‧波形1414‧‧‧ waveform

1415‧‧‧線Line 1415‧‧

1416‧‧‧曲線1416‧‧‧ Curve

1418‧‧‧波形1418‧‧‧ waveform

1419‧‧‧波形1419‧‧‧ waveform

1420‧‧‧波形1420‧‧‧ waveform

1422‧‧‧波形1422‧‧‧ waveform

1424‧‧‧波形1424‧‧‧ Waveform

1426‧‧‧預調節波形1426‧‧‧Pre-adjusted waveform

1427‧‧‧讀取脈衝1427‧‧‧Read pulse

1428‧‧‧預調節波形1428‧‧‧Pre-adjusted waveform

1429‧‧‧讀取脈衝1429‧‧‧Read pulse

1430‧‧‧預調節波形1430‧‧‧Pre-adjusted waveform

1431‧‧‧讀取脈衝1431‧‧‧Read pulse

1432‧‧‧波形1432‧‧‧ Waveform

1435‧‧‧波形1435‧‧‧ waveform

1436‧‧‧波形1436‧‧‧ waveform

1437‧‧‧波形1437‧‧‧ waveform

1438‧‧‧波形1438‧‧‧ waveform

1439‧‧‧波形1439‧‧‧ waveform

1440‧‧‧波形1440‧‧‧ waveform

1441‧‧‧預調節波形1441‧‧‧Pre-adjusted waveform

1442‧‧‧波形1442‧‧‧ waveform

1443‧‧‧預調節波形1443‧‧‧Pre-adjusted waveform

1444‧‧‧波形1444‧‧‧ waveform

1445‧‧‧預調節波形1445‧‧‧Pre-adjusted waveform

1446‧‧‧波形1446‧‧‧ Waveform

1447‧‧‧預調節波形1447‧‧‧Pre-adjusted waveform

1450‧‧‧波形1450‧‧‧ waveform

1454‧‧‧波形1454‧‧‧ waveform

1456‧‧‧預調節波形1456‧‧‧Pre-adjusted waveform

1458‧‧‧波形1458‧‧‧ Waveform

1460‧‧‧預調節波形1460‧‧‧Pre-adjusted waveform

1462‧‧‧波形1462‧‧‧ waveform

1464‧‧‧波形1464‧‧‧ Waveform

1466‧‧‧波形1466‧‧‧ waveform

1468‧‧‧預調節波形1468‧‧‧Pre-adjusted waveform

1470‧‧‧波形1470‧‧‧ waveform

1472‧‧‧預調節波形1472‧‧‧Pre-adjusted waveform

1500‧‧‧陣列1500‧‧‧Array

1504‧‧‧源極線1504‧‧‧Source line

1505‧‧‧p井1505‧‧‧p well

1506‧‧‧位元線1506‧‧‧ bit line

1526‧‧‧汲極端子1526‧‧‧汲 extremes

1528‧‧‧源極端子1528‧‧‧ source terminal

1550‧‧‧NAND串1550‧‧‧NAND string

1600‧‧‧感測區塊1600‧‧‧Sensing block

1610‧‧‧控制電路1610‧‧‧Control circuit

1612‧‧‧狀態機1612‧‧‧ state machine

1614‧‧‧晶片上位址解碼器1614‧‧‧ on-chip address decoder

1615‧‧‧增壓控制器1615‧‧‧Supercharger controller

1616‧‧‧功率控制模組1616‧‧‧Power Control Module

1618‧‧‧線1618‧‧‧ line

1620‧‧‧線1620‧‧‧ line

1630‧‧‧列解碼器1630‧‧‧ column decoder

1630A‧‧‧列解碼器1630A‧‧‧ column decoder

1630B‧‧‧列解碼器1630B‧‧‧ column decoder

1650‧‧‧控制器1650‧‧‧ Controller

1660‧‧‧行解碼器1660‧‧‧ row decoder

1660A‧‧‧行解碼器1660A‧‧ ‧ row decoder

1660B‧‧‧行解碼器1660B‧‧ ‧ row decoder

1665‧‧‧讀取/寫入電路1665‧‧‧Read/Write Circuit

1665A‧‧‧讀取/寫入電路1665A‧‧‧Read/Write Circuit

1665B‧‧‧讀取/寫入電路1665B‧‧‧Read/Write Circuit

1670‧‧‧感測電路1670‧‧‧Sensor circuit

1672‧‧‧匯流排1672‧‧ ‧ busbar

1680‧‧‧感測模組1680‧‧‧Sensor module

1682‧‧‧位元線鎖存器1682‧‧‧ bit line latch

1690‧‧‧共同部分1690‧‧‧Common part

1692‧‧‧處理器1692‧‧‧ processor

1693‧‧‧輸入線1693‧‧‧Input line

1694‧‧‧資料鎖存器1694‧‧‧ Data Latches

1696‧‧‧記憶體設備/I/O介面1696‧‧‧Memory device/I/O interface

1698‧‧‧記憶體晶粒1698‧‧‧ memory grain

1900‧‧‧架構1900‧‧‧ architecture

1910‧‧‧架構1910‧‧‧ Architecture

2100‧‧‧箭頭2100‧‧‧ arrow

2110‧‧‧箭頭2110‧‧‧ arrow

2120‧‧‧箭頭2120‧‧‧ arrow

2400‧‧‧脈衝串2400‧‧‧pulse

SGD‧‧‧選擇線SGD‧‧‧ selection line

SGS‧‧‧選擇線SGS‧‧‧Selection line

WL0‧‧‧字線WL0‧‧‧ word line

WL1‧‧‧字線WL1‧‧‧ word line

WL2‧‧‧字線WL2‧‧‧ word line

WL3‧‧‧字線WL3‧‧‧ word line

圖1為NANE串之俯視圖。Figure 1 is a top view of the NANE string.

圖2為圖1之NAND串之等效電路圖。2 is an equivalent circuit diagram of the NAND string of FIG. 1.

圖3為NAND快閃儲存元件陣列的方塊圖。3 is a block diagram of an NAND flash storage element array.

圖4描繪用於非揮發性儲存器之資料編碼及解碼的系統。Figure 4 depicts a system for data encoding and decoding of non-volatile storage.

圖5a為用於針對非揮發性儲存元件集合來獲得第一機率密度函數f1之過程的流程圖。Figure 5a is a flow diagram of a process for obtaining a first probability density function f1 for a non-volatile storage element set.

圖5b為用於針對非揮發性儲存元件集合來獲得第二機率密度函數f2之過程的流程圖。Figure 5b is a flow diagram of a process for obtaining a second probability density function f2 for a non-volatile storage element set.

圖6a描繪電壓臨限值讀數之分布。Figure 6a depicts the distribution of voltage threshold readings.

圖6b描繪無雜訊電壓臨限值讀數。Figure 6b depicts the noise-free threshold reading.

圖6c描繪無雜訊電壓臨限值讀數之分布。Figure 6c depicts the distribution of noise-free threshold readings.

圖6d描繪非揮發性儲存元件集合之不同狀態之電壓臨限值的機率分布。Figure 6d depicts the probability distribution of voltage thresholds for different states of the non-volatile storage element set.

圖7a描繪非揮發性儲存元件之實例狀態之電壓臨限值偏差的分布。Figure 7a depicts the distribution of voltage threshold deviations for example states of non-volatile storage elements.

圖7b描繪非揮發性儲存元件集合之實例狀態之電壓臨限值偏差的分布。Figure 7b depicts the distribution of voltage threshold deviations for example states of a non-volatile storage element set.

圖7c描繪非揮發性儲存元件集合之狀態0之電壓臨限值偏差的機率分布。Figure 7c depicts the probability distribution of the voltage threshold deviation of state 0 of the non-volatile storage element set.

圖7d描繪非揮發性儲存元件集合之狀態1之電壓臨限值偏差的機率分布。Figure 7d depicts the probability distribution of the voltage threshold deviation for state 1 of the non-volatile storage element set.

圖7e描繪非揮發性儲存元件集合之狀態15之電壓臨限值偏差的機率分布。Figure 7e depicts the probability distribution of the voltage threshold deviation for state 15 of the non-volatile storage element set.

圖8為用於自非揮發性儲存元件獲得用於解碼讀取資料之對數概似比(LLR)之過程的流程圖。8 is a flow diagram of a process for obtaining a logarithmic power ratio (LLR) for decoding read data from a non-volatile storage element.

圖9a描繪為非揮發性儲存元件之不同經程式化狀態提供多位元碼字的表。Figure 9a depicts a table providing multi-bit codewords for different programmed states of non-volatile storage elements.

圖9b描繪以第一讀取結果為基礎而為碼字之每一位元提供LLR之初始值的表。Figure 9b depicts a table that provides an initial value of LLR for each bit of a codeword based on the first read result.

圖9c描繪以第二讀取結果為基礎而為碼字之每一位元提供對由解碼器所利用之LLR之當前值之調整的表。Figure 9c depicts a table providing adjustments to the current value of the LLR utilized by the decoder for each bit of the codeword based on the second read result.

圖10a至圖10d描繪以第一讀取結果及第二讀取結果為基礎而為碼字之每一位元提供LLR之初始值的表。Figures 10a through 10d depict a table that provides an initial value of LLR for each bit of a codeword based on the first read result and the second read result.

圖11a為用於解碼表示非揮發性儲存元件之狀態之碼字之過程的流程圖，其中以第一讀取操作及第二讀取操作為基礎來獲得初始機率計量。Figure 11a is a flow diagram of a process for decoding a codeword representing the state of a non-volatile storage element, wherein an initial probability meter is obtained based on a first read operation and a second read operation.

圖11b為用於解碼表示非揮發性儲存元件之狀態之碼字之過程的流程圖，其中以第一讀取操作為基礎來獲得初始機率計量，接著以第二讀取操作為基礎來進一步調整經調 整機率計量。Figure 11b is a flow diagram of a process for decoding a codeword representing a state of a non-volatile storage element, wherein an initial probability meter is obtained based on a first read operation, and then further adjusted based on the second read operation Adjusted The whole rate is measured.

圖11c為用於解碼表示非揮發性儲存元件之狀態之碼字之過程的流程圖，其中以第一讀取操作為基礎來獲得初始機率計量，接著以第一讀取操作及第二讀取操作為基礎來獲得新的初始機率計量。Figure 11c is a flow diagram of a process for decoding a codeword representing a state of a non-volatile storage element, wherein an initial probability meter is obtained based on a first read operation, followed by a first read operation and a second read Based on the operation to obtain a new initial probability measurement.

圖12描繪稀疏同位檢查矩陣。Figure 12 depicts a sparse parity check matrix.

圖13描繪對應於圖12之稀疏同位檢查矩陣的稀疏偶圖。Figure 13 depicts a sparse diffractogram corresponding to the sparse parity check matrix of Figure 12.

圖14a為解釋讀取/驗證操作期間特定波形之行為的時序圖，其中在關聯讀取脈衝之前將預調節波形施加至選定字線。Figure 14a is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, where a pre-conditioned waveform is applied to a selected word line prior to correlating the read pulses.

圖14b為解釋讀取/驗證操作期間特定波形之行為的時序圖，其中在關聯讀取脈衝之前將一或多個預調節波形施加至選定字線。Figure 14b is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein one or more pre-conditioned waveforms are applied to the selected word line prior to correlating the read pulses.

圖14c為描繪不同預調節波形之時序圖。Figure 14c is a timing diagram depicting different pre-conditioning waveforms.

圖14d為解釋讀取/驗證操作期間特定波形之行為的時序圖，其中在關聯讀取脈衝之前將預調節波形經由選定位元線而施加至選定儲存元件之汲極。Figure 14d is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein the pre-conditioned waveform is applied to the drain of the selected storage element via the selected positioning element prior to correlating the read pulse.

圖14e為解釋讀取/驗證操作期間特定波形之行為的時序圖，其中在關聯讀取脈衝之前將預調節波形經由源極線而施加至選定儲存元件之源極。Figure 14e is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein a pre-conditioned waveform is applied to the source of the selected storage element via the source line prior to correlating the read pulse.

圖14f為解釋讀取/驗證操作期間特定波形之行為的時序圖，其中在關聯讀取脈衝之前將預調節波形經由本體偏壓而施加至選定儲存元件。Figure 14f is a timing diagram illustrating the behavior of a particular waveform during a read/verify operation, wherein the pre-conditioned waveform is applied to the selected storage element via a body bias prior to correlating the read pulses.

圖14g為用於對儲存元件執行讀取操作之過程之流程 圖，其中在關聯讀取脈衝之前將預調節波形施加至儲存元件。Figure 14g is a flow chart of a process for performing a read operation on a storage element A diagram in which a pre-conditioning waveform is applied to a storage element prior to associating a read pulse.

圖14h為用於對儲存元件執行讀取操作之過程之流程圖，其中在讀取脈衝系列之前將預調節波形施加至儲存元件。Figure 14h is a flow diagram of a process for performing a read operation on a storage element, wherein a pre-conditioning waveform is applied to the storage element prior to reading the series of pulses.

圖14i為用於利用預調節波形來獲得可靠度計量以供在解碼中後續利用之過程的流程圖。Figure 14i is a flow diagram of a process for utilizing a pre-conditioned waveform to obtain reliability measurements for subsequent utilization in decoding.

圖15為NAND快閃儲存元件陣列的方塊圖。Figure 15 is a block diagram of an array of NAND flash memory elements.

圖16為利用單列/行解碼器及讀取/寫入電路之非揮發性記憶體系統的方塊圖。Figure 16 is a block diagram of a non-volatile memory system utilizing a single column/row decoder and a read/write circuit.

圖17為利用雙列/行解碼器及讀取/寫入電路之非揮發性記憶體系統的方塊圖。17 is a block diagram of a non-volatile memory system utilizing a dual column/row decoder and a read/write circuit.

圖18為描繪感測區塊之一實施例的方塊圖。18 is a block diagram depicting one embodiment of a sensing block.

圖19說明記憶體陣列至用於全位元線記憶體架構或用於奇偶記憶體架構之區塊之組織的實例。Figure 19 illustrates an example of a memory array to organization for a full bit line memory architecture or a block for a parity memory architecture.

圖20描繪實例臨限電壓分布集合。Figure 20 depicts an example set of threshold voltage distributions.

圖21描繪實例臨限電壓分布集合。Figure 21 depicts an example threshold voltage distribution set.

圖22a至圖22c展示各種臨限電壓分布且描述用於程式化非揮發性記憶體之過程。Figures 22a through 22c show various threshold voltage distributions and describe the process for programming non-volatile memory.

圖23為描述用於程式化非揮發性記憶體之過程之一實施例的流程圖。23 is a flow chart depicting one embodiment of a process for programming non-volatile memory.

圖24描繪在程式化期間施加至非揮發性儲存元件之控制閘極之實例脈衝串。Figure 24 depicts an example pulse train applied to a control gate of a non-volatile storage element during stylization.

(無元件符號說明)(no component symbol description)

Claims (16)

一種用於解碼非揮發性儲存器中之資料的方法，其包含：對至少一非揮發性儲存元件執行多重感測操作，該等多重感測操作包括一第一感測操作及至少一後續感測操作；利用迭代機率性解碼來判定該至少一非揮發性儲存元件之一程式化狀態，該迭代機率性解碼利用以該等多重感測操作為基礎之可靠度計量，其中該迭代機率性解碼最初利用以該第一感測操作而非該至少一後續感測操作為基礎之第一可靠度計量來迭代；調整該等第一可靠度計量以在該迭代機率性解碼迭代時獲得經調整可靠度計量；及以該至少一後續感測操作為基礎，在該迭代機率性解碼進一步迭代時，調整該等經調整可靠度計量。A method for decoding data in a non-volatile memory, comprising: performing a multiple sensing operation on at least one non-volatile storage element, the multiple sensing operations including a first sensing operation and at least a subsequent sense Using a iterative probability decoding to determine a stylized state of the at least one non-volatile storage element, the iterative probability decoding utilizing a reliability measure based on the multiple sensing operations, wherein the iterative probability decoding Iterating initially using a first reliability measure based on the first sensing operation rather than the at least one subsequent sensing operation; adjusting the first reliability meters to obtain an adjusted reliability at the iterative probability decoding iteration And metering; and based on the at least one subsequent sensing operation, adjusting the adjusted reliability metering when the iterative probability decoding further iterates. 如請求項1之方法，其中該等可靠度計量包含對數概似比。The method of claim 1, wherein the reliability measures comprise a logarithmic approximation ratio. 如請求項1之方法，其中該等感測操作包含讀取操作。The method of claim 1, wherein the sensing operations comprise a read operation. 如請求項1之方法，其進一步包含：對於該等多重感測操作中之每一者而言，提供表示該至少一非揮發性儲存元件之一經感測程式化狀態的位元，該等可靠度計量經提供用於該等位元中之每一者。The method of claim 1, further comprising: providing, for each of the multiple sensing operations, a bit representing a sensed stylized state of one of the at least one non-volatile storage element, the reliable A measure is provided for each of the bits. 如請求項4之方法，其進一步包含：讀取一交叉參考經感測程式化狀態及位元與可靠度計 量之表。The method of claim 4, further comprising: reading a cross-reference sensed stylized state and a bit and reliability meter The table of quantities. 如請求項1之方法，其中該迭代機率性解碼試圖滿足一錯誤校正碼之同位檢查。The method of claim 1, wherein the iterative probability decoding attempts to satisfy a parity check of an error correction code. 如請求項6之方法，其中該錯誤校正碼包含一低密度同位檢查碼，該低密度同位檢查碼被施加於包括該至少一非揮發性儲存元件之一非揮發性儲存元件集合之上。The method of claim 6, wherein the error correction code comprises a low density parity check code applied to the set of non-volatile storage elements comprising the at least one non-volatile storage element. 如請求項1之方法，其進一步包含：以該等多重感測操作為基礎來判定用以在該迭代機率性解碼中利用之一初始可靠度計量集合。The method of claim 1, further comprising: determining, based on the multiple sensing operations, an initial set of reliability measurements to utilize in the iterative probability decoding. 如請求項1之方法，其中當該至少一後續感測操作之一經感測程式化狀態與該第一感測操作之一經感測程式化狀態一致時，該等經調整可靠度計量經調整以指示一較高可靠度。The method of claim 1, wherein the adjusted reliability measure is adjusted when one of the at least one subsequent sensing operations is consistent with the sensed stylized state by one of the first sensing operations Indicates a higher reliability. 如請求項1之方法，其中當該至少一後續感測操作之一經感測程式化狀態與該第一感測操作之一經感測程式化狀態不一致時，該等經調整可靠度計量經調整以指示一較低可靠度。The method of claim 1, wherein the adjusted reliability measure is adjusted when one of the at least one subsequent sensing operations is inconsistent with the sensed stylized state by one of the first sensing operations Indicates a lower reliability. 如請求項1之方法，其進一步包含：利用以該第一感測操作及該至少一後續感測操作為基礎之機率計量來重新開始該迭代機率性解碼過程。The method of claim 1, further comprising: restarting the iterative probability decoding process with probability metering based on the first sensing operation and the at least one subsequent sensing operation. 如請求項1之方法，其進一步包含：以對一非揮發性儲存元件集合所執行之複數個感測操作為基礎而針對複數個程式化狀態中之每一者來獲得該至少一非揮發性儲存元件之電壓臨限值概況； 以該等電壓臨限值概況為基礎來提供一可靠度計量集合；及自該可靠度計量集合存取用於該迭代機率性解碼中之該等可靠度計量。The method of claim 1, further comprising: obtaining the at least one non-volatile for each of the plurality of stylized states based on a plurality of sensing operations performed on a set of non-volatile storage elements An overview of the voltage threshold of the storage element; Providing a set of reliability measures based on the voltage threshold profiles; and accessing the reliability measures used in the iterative probability decoding from the set of reliability meters. 如請求項12之方法，其中該提供該可靠度計量集合包含：以該複數個感測操作為基礎來判定一條件機率函數f1(u|X)，其中u指示一經感測臨限電壓，且X表示該複數個程式化狀態中之一經程式化狀態；及以該複數個感測操作為基礎而針對每一程式化狀態來判定一機率函數f2(v)，其中v指示一經感測臨限電壓自無讀取雜訊之一臨限電壓的一偏差。The method of claim 12, wherein the providing the reliability measurement set comprises: determining a conditional probability function f1(u|X) based on the plurality of sensing operations, wherein u indicates a sense threshold voltage, and X represents a programmed state of the plurality of stylized states; and a probability function f2(v) is determined for each stylized state based on the plurality of sensing operations, wherein v indicates a sensing threshold The voltage is one deviation from the threshold voltage of one of the read noises. 一種非揮發性儲存系統，其包含：一非揮發性儲存元件集合；及與該非揮發性儲存元件集合通信之一或多個控制電路，該一或多個控制電路：對至少一非揮發性儲存元件執行多重感測操作，該等多重感測操作包括一第一感測操作及至少一後續感測操作；利用迭代機率性解碼來判定該至少一非揮發性儲存元件之一程式化狀態，該迭代機率性解碼利用以該等多重感測操作為基礎之可靠度計量，其中該迭代機率性解碼最初利用以該第一感測操作而非該至少一後續感測操作為基礎之第一可靠度計量來迭代；調整該等第一可靠度計量以在該迭代機率性解碼迭代時獲得經調整可靠度計量；及以該至少一後續感測 操作為基礎，在該迭代機率性解碼進一步迭代時，調整該等經調整可靠度計量。A non-volatile storage system comprising: a set of non-volatile storage elements; and one or more control circuits in communication with the non-volatile storage element set, the one or more control circuits: for at least one non-volatile storage The component performs a multiple sensing operation, the multiple sensing operations including a first sensing operation and at least one subsequent sensing operation; determining, by using iterative probability decoding, a stylized state of the at least one non-volatile storage element, Iterative probability decoding utilizes reliability metering based on the multiple sensing operations, wherein the iterative probability decoding initially utilizes first reliability based on the first sensing operation rather than the at least one subsequent sensing operation Metering to iterate; adjusting the first reliability measure to obtain an adjusted reliability measure at the iterative probability decoding iteration; and using the at least one subsequent sense Based on the operation, the adjusted reliability measures are adjusted as the iterative probability decoding is further iterated. 如請求項14之非揮發性儲存系統，其中：該迭代機率性解碼試圖滿足一錯誤校正碼之同位檢查；且該錯誤校正碼包含一低密度同位檢查碼，該低密度同位檢查碼被施加於包括該至少一非揮發性儲存元件之該非揮發性儲存元件集合之上。The non-volatile storage system of claim 14, wherein: the iterative probability decoding attempts to satisfy a parity check of an error correction code; and the error correction code includes a low density parity check code, the low density parity check code being applied to The non-volatile storage element set of the at least one non-volatile storage element is included. 如請求項14之非揮發性儲存系統，其中：當該至少一後續感測操作之一經感測程式化狀態與該第一感測操作之一經感測程式化狀態一致時，該等經調整可靠度計量被調整以指示一較高可靠度；且當該至少一後續感測操作之一經感測程式化狀態與該第一感測操作之一經感測程式化狀態不一致時，該等經調整可靠度計量被調整以指示一較低可靠度。The non-volatile storage system of claim 14, wherein: when one of the at least one subsequent sensing operations is consistent with the sensed stylized state by one of the first sensing operations, the adjusted The metering is adjusted to indicate a higher reliability; and when one of the at least one subsequent sensing operations is inconsistent with the sensed stylized state by one of the first sensing operations, the adjusted The metering is adjusted to indicate a lower reliability.