TWI715211B - 半導體元件及其形成方法 - Google Patents

半導體元件及其形成方法 Download PDF

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TWI715211B
TWI715211B TW108134709A TW108134709A TWI715211B TW I715211 B TWI715211 B TW I715211B TW 108134709 A TW108134709 A TW 108134709A TW 108134709 A TW108134709 A TW 108134709A TW I715211 B TWI715211 B TW I715211B
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Taiwan
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dielectric layer
conductive
layer
opening
forming
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TW108134709A
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TW202029444A (zh
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何嘉瑋
徐俊偉
沈稘翔
劉啟人
林易生
鄭仰鈞
洪偉倫
陳亮光
陳科維
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台灣積體電路製造股份有限公司
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Abstract

一種半導體元件包括：第一介電層，該第一介電層在基板上，該第一介電層包含第一介電材料，該第一介電材料從第一介電層遠離基板的第一側延伸到第一介電層與該第一側相對的第二側；第二介電層，該第二介電層在該第一介電層上；導電線，該導電線在該第一介電層中，該導電線包含第一傳導性材料，該導電線的上表面比該第一介電層的上表面更靠近該基板；金屬蓋，該金屬蓋在該第一介電層中，該金屬蓋在該導電線上方並與該導電線實體連接，該金屬蓋包括與該第一傳導性材料不同的第二傳導性材料；以及導通孔，該導通孔在該第二介電層中並與該金屬蓋實體連接，該導通孔包含該第二傳導性材料。

Description

半導體元件及其形成方法
本揭露的實施例係有關於一種半導體元件及其形成方法。
由於各種電子部件(例如，電晶體、二極體、電阻器、電容器等)的整合密度的不斷提高，半導體工業經歷了快速增長。在大多數情況下，整合密度的此種改進來源於最小特徵大小的重複減少，此允許將更多部件整合到給定區域中。隨著特徵大小在先進處理技術中繼續縮小，可以使用新的處理步驟來實現所形成的半導體元件的效能目標。新的處理步驟亦可能為半導體製造帶來新的挑戰。
依據本揭露的實施例，一種半導體元件包括：第一介電層，該第一介電層在基板上，該第一介電層包含第一介電材料，該第一介電材料從第一介電層遠離基板的第一側延伸到第一介電層與該第一側相對的第二側；第二介電層，該第二介電層在該第一介電層上；導電線，該導電線在 該第一介電層中，該導電線包含第一傳導性材料，該導電線的上表面比該第一介電層的上表面更靠近該基板；金屬蓋，該金屬蓋在該第一介電層中，該金屬蓋在該導電線上方並與該導電線實體連接，該金屬蓋包括與該第一傳導性材料不同的第二傳導性材料；以及導通孔，該導通孔在該第二介電層中並與該金屬蓋實體連接，該導通孔包含該第二傳導性材料。
依據本揭露的實施例，一種半導體元件包括：基板；第一介電層，該第一介電層在該基板上，該第一介電層是單層；導電特徵，該導電特徵在第一介電層中，該導電特徵包含第一傳導性材料，該導電特徵遠離該基板的第一表面比該第一介電層遠離該基板的第一表面更靠近該基板；第二介電層，該第二介電層在該第一介電層和該導電特徵上；以及導電插塞，該導電插塞具有上部和下部，該上部和該下部包含與該第一傳導性材料不同的第二傳導性材料，該導電插塞的上部設置在該第二介電層中，該導電插塞的下部延伸到該第一介電層中並且與該導電特徵實體連接。
依據本揭露的實施例，一種半導體元件形成方法包括在基板上形成第一介電層；使用第一材料在該第一介電層中形成導電線，其中在形成該導電線之後，在該第一介電層中存在靠近遠離基板的第一介電層上表面的凹槽，其中該凹槽的底部暴露該導電線的上表面；使用不同於該第一材料的第二材料填充該第一介電層中的凹槽以形成金屬蓋，其中該金屬蓋比該導電線更寬；在該第一介電層上形成第二介 電層；在該第二介電層中形成開口以暴露該金屬蓋；以及使用該第二材料填充該開口以形成導通孔。
20:半導體基板
22:積體電路元件
24:層間介電質(ILD)
28:接觸插塞
30:金屬間介電(IMD)層
30A:側壁
30B:側壁
30C:側壁
31:阻障層
32:開口
32B:底部
33:開口
34:導電線
34T:上表面
34T':上表面
36:傳導性材料
36L:下部
36U:上部
37:界面
38:蓋
38:A
42:蝕刻終止層
43:導通孔開口
44:IMD層
45:開口
46:導通孔
46A:第一子層
46B:第二子層
47:界面
48:導通孔
53:IMD層
54:導電特徵
56:鈍化層
62:球下冶金層(UBM)結構
64:外部連接器
100:半導體元件
200:半導體元件
300:半導體元件
1010:方塊
1020:方塊
1030:方塊
1040:方塊
1050:方塊
1060:方塊
T1、T2、T3:厚度
W1、W2、W9:寬度
W3、W4、W5、W6、W7、W8:距離
當結合附圖閱讀時，從以下詳細描述可以最好地理解本揭露的實施例的各態樣。應注意，根據行業中的標準實踐，各種特徵未按比例繪製。實際上，為了論述的清楚性，可以任意地增大或縮小各種特徵的尺寸。
第1圖至第7圖、第8A圖、第8B圖和第9圖圖示了根據一個實施例的處於各個製造階段的半導體元件的剖視圖。
第10圖至第12圖圖示了根據一個實施例的處於各個製造階段的半導體元件的剖視圖。
第13圖至第19圖、第20A圖、第20B圖和第21圖圖示了根據一個實施例的處於各個製造階段的半導體元件的剖視圖。
第22圖圖示了在一些實施例中用於形成半導體元件的方法的流程圖。
以下揭露內容提供了用於實施本揭露的不同特徵的許多不同實施例或實例。以下描述了部件和佈置的特定實例以簡化本揭露的實施例內容。當然，該等僅僅是實例，而並且意欲為限制性的。例如，在以下描述中在第二特徵上方或之上形成第一特徵可以包括第一特徵和第二特徵形成 為直接接觸的實施例，並且亦可以包括可以在第一特徵與第二特徵之間形成額外特徵，使得第一特徵和第二特徵可以不直接接觸的實施例。
此外，在此可以使用空間相對術語，諸如「下方」、「以下」、「下部」、「上方」、「上部」等來簡化描述，以描述如圖中所示的一個元件或特徵與另一元件或特徵的關係。除了圖中所示的取向之外，空間相對術語意欲包括使用或操作中的裝置/元件的不同取向。設備可以以其他方式取向(旋轉90度或在其他方向上)，並且可以類似地相應解釋在此使用的空間相對描述詞。
在半導體元件製造的背景下，特別是在形成半導體元件的導通孔的背景下，論述了本揭露的實施例。
在一些實施例中，半導體元件包括形成在第一介電層中的金屬線。金屬線由第一傳導性材料形成，並且金屬線的上表面從第一介電層的上表面凹進。半導體元件進一步包括在金屬線上方並連接到金屬線的金屬蓋。金屬蓋由不同於第一傳導性材料的第二傳導性材料形成。金屬蓋比金屬線更寬，並且金屬蓋的上表面與第一介電層的上表面齊平。半導體元件進一步包括在第一介電層上的第二介電層，以及在第二介電層中的導通孔。導通孔在金屬蓋上方並連接到金屬蓋。該導通孔由第二傳導性材料形成。
第1圖至第7圖、第8A圖、第8B圖和第9圖圖示了根據一個實施例的處於各個製造階段的半導體元件100的剖視圖。半導體元件100可以是包括有源元件(例如，電 晶體、二極體等)及/或無源元件(例如，電容器、電感器、電阻器等)的元件晶圓。在一些實施例中，半導體元件100是中介晶圓，其可以包括或可以不包括有源元件及/或無源元件。根據本揭露的又一實施例，半導體元件100是封裝基板條帶，該封裝基板條帶可以是其中具有芯的封裝基板，或者可以是無芯封裝基板。在隨後的論述中，元件晶圓用作示例性半導體元件100。本揭露的實施例的教示亦可以應用於中介晶圓、封裝基板、或其他半導體結構。
如第1圖所示，半導體元件100包括半導體基板20和形成在半導體基板20上或半導體基板20中的積體電路元件22(例如，有源元件、無源元件、導電墊)。半導體基板20可以包含摻雜或未摻雜的半導體材料(諸如矽)，或者絕緣體上半導體(SOI)基板的有源層。半導體基板20可以包含其他半導體材料，諸如鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、氮化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可以使用其他基板，諸如多層或梯度基板。
在第1圖的實例中，積體電路元件22形成在半導體基板20上或半導體基板20中。示例性積體電路元件22包括電晶體(例如，互補金氧半導體(CMOS)電晶體)、電阻器、電容器、二極體等。可以使用任何合適的方法形成積體電路元件22，在此不論述細節。
在形成積體電路元件22之後，在半導體基板20上和積體電路元件22上形成層間介電質(ILD)24。ILD 24可以填充積體電路元件22中的電晶體(未單獨圖示)的閘極堆疊之間的空間。根據一些實施例，ILD 24包括磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜的磷矽酸鹽玻璃(BPSG)、氟摻雜的矽酸鹽玻璃(FSG)、原矽酸四乙酯(TEOS)等。可以使用旋塗、可流動化學氣相沉積(FCVD)等形成ILD 24。在一些實施例中，使用合適的沉積方法形成ILD 24，該等合適的沉積方法為例如電漿增強化學氣相沉積(PECVD)、低壓化學氣相沉積(LPCVD)等。
參照第1圖，在ILD 24中形成接觸插塞28，並將積體電路元件22電耦合到上覆導電特徵，諸如金屬線、導通孔和導電柱。根據本揭露的一些實施例，接觸插塞28由傳導性材料形成，該傳導性材料為諸如鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金及/或多層上述物質。接觸插塞28的形成可以包括在ILD 24中形成接觸開口，將(多種)傳導性材料填充到該接觸開口中，以及執行平坦化製程，諸如化學機械拋光(CMP)，以使接觸插塞28的頂表面與ILD 24的頂表面齊平。
接下來，在第2圖中，在ILD 24上形成金屬間介電(IMD)層30，並且在IMD層30中形成開口32以暴露接觸插塞28。IMD層30可以由介電材料形成，該介電材料為諸如氧化矽、氮化矽、碳化矽、氧氮化矽等。根據一些實施例，IMD層30由低介電常數介電材料形成，該低介電常數 介電材料的介電常數(k值)低於3.0，諸如約2.5、約2.0，或甚至更低。IMD層30可以包含Black Diamond(Applied Materials的註冊商標)、含碳的低介電常數介電材料、氫矽酸鹽類(Hydrogen SilsesQuioxane,HSQ)、矽氧烷(MethylSilsesQuioxane,MSQ)等。作為實例，IMD層30的形成可以包括在ILD 24上沉積含致孔劑的介電質材料，隨後執行固化製程以驅除致孔劑，從而形成多孔的IMD層30。其他合適的方法亦可用於形成IMD層30。
使用諸如光微影和蝕刻技術等合適方法形成開口32。在第2圖所示的實例中，開口32具有寬度W1的上部和寬度W2的下部，其中寬度W1大於寬度W2。在所示實例中，開口32具有直的側壁(例如，垂直於ILD 24的上表面)。在其他實施例中，開口可以具有傾斜的側壁(參見例如第14圖中的開口33)，或者由於用於形成開口的處理而具有其他形狀。可以藉由使用例如兩個單獨的光微影和蝕刻製程來形成開口32。例如，可以執行使用第一掩模層的第一光微影和蝕刻製程來形成寬度W2的第一開口，其中該第一開口延伸穿過IMD層30並暴露接觸插塞28。接下來，在移除第一掩模層之後，可以執行使用第二掩模層的第二光微影和蝕刻製程以形成開口32的上部，該上部具有寬度W1。用於形成開口32的其他方法亦是可能的，並且完全意欲包括在本揭露的實施例的範疇內。
接下來，如第3圖所示，形成傳導性材料36以填充開口32(參見第2圖中的元件符號)。傳導性材料36可 以是用於形成例如導電線的任何合適的傳導性材料。在一個實施例中，傳導性材料36是鈷(Co)。用於傳導性材料36的材料的其他實例包括W、Cu和Ru。如第3圖所示，傳導性材料36的下部36L填充開口32的下部，並且傳導性材料36的上部36U填充開口32的上部。傳導性材料36可以藉由化學氣相沉積(CVD)、物理氣相沉積(PVD)、鍍敷(例如，電鍍或無電鍍敷)或其他合適的方法形成。在一些實施例中，傳導性材料36溢出開口32並覆蓋IMD層30的上表面，因此，執行諸如CMP等平坦化製程以從IMD層30的上表面移除傳導性材料36的多餘部分。
在一些實施例中，在形成傳導性材料36之前，在開口32中形成阻障層31(亦稱為擴散阻障層)，該阻障層31襯於開口32的側壁和底部。阻障層31可以包含鈦、氮化鈦、鉭、氮化鉭等，並且可以藉由CVD、PVD、原子層沉積(ALD)等形成。在其他實施例中，省略了阻障層31。為簡單起見，本揭露的實施例中的後續附圖可能未圖示IMD層30與傳導性材料36之間的阻障層31，應理解阻障層31可形成在IMD層30與傳導性材料36之間。
接下來參考第4圖，執行減薄製程以減小IMD層30的厚度並減小傳導性材料36的上部36U的厚度。諸如CMP等平坦化製程可以用作減薄製程。減薄製程在到達傳導性材料36的下部36L之前停止，如第4圖所示。在所示實施例中，在減薄製程之後，上部36U的剩餘部分的厚度T1在約5nm與約10nm之間，IMD層30的厚度在約0nm與約 30nm之間，並且在上部36U的剩餘部分的側壁與下部36L的相應側壁之間的距離W3在約2nm與約3nm之間。上面論述的尺寸是非限制性實例。其他尺寸亦是可能的，並且完全意欲包括在本揭露的實施例的範疇內。例如，在不同的處理節點中距離W3和厚度T1的值可以改變(例如，縮放)。
接下來，在第5圖中，移除上部36U的剩餘部分(參見第4圖)。在一些實施例中，執行蝕刻製程，諸如濕法蝕刻製程，以移除上部36U的剩餘部分。濕法蝕刻製程可以使用對傳導性材料36具有選擇性(例如，具有更高蝕刻速率)的蝕刻劑(例如，HF、HCl、H2O2或KOH)，使得在基本上不攻擊IMD層30的情況下移除傳導性材料36。在蝕刻製程之後，開口32的下部中的傳導性材料36的剩餘部分形成導電線34。導電線34的上表面34T可以與開口32的上部的底部32B齊平。沿著上部36U的側壁的阻障層31(參見第3圖)(若形成)亦藉由濕法蝕刻製程移除。
在一些實施例中，代替執行單獨的濕法蝕刻製程，藉由CMP製程移除上部36U的剩餘部分(參見第4圖)。例如，CMP製程中使用的漿料可以經調諧(例如，選擇)為對傳導性材料36具有選擇性，使得傳導性材料36被以比IMD層30更快的速率移除。在CMP製程之後，傳導性材料36的剩餘部分形成導電線34。如第5圖所示，由於CMP製程的凹槽效應，藉由CMP製程形成的導電線34的上表面34T'(以虛線圖示)可以是凹形的。為簡單起見，本揭露的實施例中的後續附圖可能未圖示導電線34的凹形上表面 34T'，應理解，取決於用於移除傳導性材料36的製程，導電線34的上表面可以是平坦的(參見例如34T)或凹形的(參見例如34T')。
接下來參照第6圖，蓋38(亦可以稱為金屬蓋)在導電線34上形成並填充IMD層30中的凹槽，該凹槽是藉由移除傳導性材料36而形成的(參見第5圖)。在所示實施例中，蓋38和導電線34由不同材料形成。例如，蓋38由傳導性材料(例如，導電材料)形成，該傳導性材料不同於導電線34的傳導性材料36。在一個示例性實施例中，導電線34由鈷形成，並且蓋38由鎢(W)形成。蓋38的材料的其他實例包括Co和Ru。在所示實施例中，蓋38與IMD層30直接接觸(例如，實體接觸)。
蓋38可以使用例如CVD、PVD、電鍍或其他合適的方法形成。蓋38的材料可能溢出IMD層30中的凹槽，在該情況下，可以執行諸如CMP等平坦化製程以移除蓋38的材料的多餘部分。在其他實施例中，蓋38的材料形成在凹槽中並填充該凹槽而不會溢出，因此省略了平坦化製程。
在一些實施例中，在形成之後，蓋38的厚度T2在約5nm與約10nm之間，並且蓋38的側壁與導電線34的對應側壁之間的距離W4在約2nm與約3nm之間，但是其他尺寸亦是可能的。換言之，蓋38的寬度(沿距離W4方向量測)大於導電線34的寬度。在一些實施例中，蓋38的厚度T2和導電線34的厚度之和等於IMD層30的厚度，該厚度在5nm與約30nm之間。如下文更詳細論述的，由於蓋38比 導電線34寬，並且由於蓋38由與導電線34不同的材料形成，所以蓋38能夠保護導電線34不被在後續CMP製程中使用的用以成導通孔46的漿料蝕刻(參見第8A圖)，從而減少或防止在導電線34上形成空腔，該等空腔可能導致不良的電連接或元件故障。
接下來，在第7圖中，在IMD層30和蓋38上形成蝕刻終止層42和IMD層44。蝕刻終止層42由相對於上覆介電層(例如，44)具有高蝕刻選擇性的材料形成，並且可以用於控制(例如，終止)上覆介電層的蝕刻製程。蝕刻終止層42可以由碳化矽、氮化矽、氧氮化矽、碳氮化矽等形成，並且可以使用合適的沉積製程(諸如PVD、CVD、其組合等)形成。IMD層44可以由與IMD層30相同或相似的介電材料(例如，低介電常數介電材料)形成，並且可以使用與IMD層30相同或類似的方法形成，因此細節不再重複。
接下來，使用諸如光微影和蝕刻等合適方法在IMD層44中形成導通孔開口43。導通孔開口43延伸穿過IMD層44和蝕刻終止層42，並暴露蓋38。在第7圖的實例中，導通孔開口43的寬度小於蓋38的寬度，因此暴露蓋38的上表面的一部分。
接下來，在第8A圖中，使用蓋38的傳導性材料(例如，鎢)在導通孔開口43(參見第7圖)中形成導通孔46。換言之，導通孔46和蓋38由相同的傳導性材料形成。導通孔46直接形成在蓋38上(例如，與蓋38直接接觸)。取決於傳導性材料和用於形成導通孔46的製程，在導通孔46與蓋 38之間可以存在或不存在界面37。導通孔46和蓋38可以統稱為導通孔48，導通孔48亦可以稱為插塞或導電插塞。導通孔46可以被稱為導電插塞48的上部，並且蓋38可以被稱為導電插塞48的下部。
可以使用合適的形成方法(諸如CVD、PVD、鍍敷、ALD等或其組合)在導通孔開口43中形成導通孔46。可以執行諸如CMP等平坦化製程以從IMD層44的上表面上移除導通孔46的材料的多餘部分。
在所示實施例中，導通孔46形成在導通孔開口43中並且與IMD層44、蝕刻終止層42和蓋38直接接觸。換言之，在導通孔46與IMD層44/蝕刻終止層42/蓋38之間沒有形成阻障層。在高級處理節點中，隨著元件大小繼續縮小，與待形成的特徵(例如，導通孔46)的尺寸相比，阻障層的厚度不再可忽略不計。因此，在所示實施例中，藉由不具有阻障層，導通孔46具有更大的容積，並且因此具有更小的電阻，從而減小了所形成的元件的電阻-電容延遲(RC延遲)。因此，可為有利的是形成沒有阻障層的導通孔46以減少RC延遲。
然而，在沒有可以用作導通孔46與IMD層44之間的膠層的阻障層的情況下，導通孔46與IMD層44之間的黏附力可能縮小，因此在導通孔46與IMD層44之間可能存在微小裂縫。在CMP製程期間，為了移除導通孔46的材料的多餘部分，CMP製程中使用的漿料可以滲透穿過導通孔46與IMD層44之間的微小裂縫並到達導電線34。若導電 線34被漿料蝕刻(亦稱為腐蝕或金屬腐蝕)，則可在導電線34的上表面處形成空腔(例如，凹槽)，此可能導致導通孔46與下面的導電線34之間的不可靠的電連接，並且甚至可能導致元件故障。
本揭露的實施例藉由形成蓋38來防止或減少對導電線34的腐蝕，蓋38比下面的導電線34更寬並且用作導電線34的遮罩。因此，蓋38保護(例如，遮罩)導電線34免受穿過導通孔46與IMD層44之間的微小裂縫向下滲透的漿料。
另外，由於導通孔46使用與導電線34的傳導性材料(例如，鈷)不同的傳導性材料(例如，鎢)形成，所以在CMP製程中使用的漿料(例如，用於移除導通孔46的材料的過量部分)可選擇為對導通孔46的材料具有選擇性(例如，對導通孔46的材料具有更高的蝕刻速率)。因此，用於移除導通孔46的材料的漿料基本上不會侵蝕導電線34。換言之，在用於形成導通孔46的CMP製程期間，可以利用導通孔46和導電線34的兩種不同傳導性材料之間的蝕刻選擇性來減少或防止對導電線34的腐蝕。此可以藉由選擇與導通孔46的材料反應但不易與導電線34的材料反應的酸性漿料(例如，PH值小於7)或鹼性漿料(例如，PH值大於7)來實現。例如，鈷容易與酸性漿料反應，但不易與鹼性漿料反應；鎢容易與鹼性漿液反應，但不易與酸性漿液反應。
在示例性實施例中，導電線34由鈷形成，導通孔46/蓋38由鎢形成，並且用以移除導通孔46的材料的多餘 部分的CMP製程使用鹼性漿料，該鹼性漿料容易與鎢反應，但不易與鈷反應，由此在CMP製程期間減少或防止對導電線34的腐蝕。鹼性漿料可以是含有來自供體的鐵(Fe)離子或鈷(Co)離子的漿料，該等供體為諸如Fe(NO3)3、Fe(CN)6 3-、CO(NO3)3、Co(CN)6 3-等。在一些實施例中，漿料與蓋38反應並在蓋38與蝕刻終止層42之間的界面處形成副產物，例如蓋38的材料的氧化物38A(參見第8B圖)。為簡單起見，本揭露的實施例中的後續附圖可能未圖示氧化物38A，但是應理解氧化物38A可以形成在蓋38與蝕刻終止層42之間的界面處。
第8B圖圖示了第8A圖中的導通孔48的放大視圖。在一些實施例中，當在蓋38上形成導通孔46時，使用兩種不同的形成方法來形成導通孔46。特別地，執行ALD沉積製程以形成導通孔46的第一子層46A(例如，保形層)，並且使用不同的沉積製程(諸如CVD、PVD或鍍敷)來填充導通孔開口43的剩餘部分(參見第7圖)並形成導通孔46的第二子層46B。換言之，第一子層46A和第二子層46B由相同的材料(例如，鎢)，但是使用不同的沉積方法形成。在第一子層46A與第二子層46B之間可以存在界面47。第一子層46A的厚度可介於約0nm與約3nm之間。由於第一子層46A由ALD形成，因此其密度高於第二子層46B。在一些實施例中，使第一子層46A具有更高質量(例如，更高密度)降低了所形成的導通孔46的電阻。由於ALD沉積製程的沉積速率可低於例如PVD、CVD或鍍敷的沉積速率，因此藉 由PVD、CVD或鍍敷形成第二子層46B可有利地縮短製造時間。因此，導通孔46的兩個雙子層結構允許在減小導通孔46的電阻(例如，RC延遲)與縮短製造時間之間實現平衡。
在一些實施例中，導通孔46的總密度(例如，平均密度)高於蓋38的總密度，此係因為導通孔46具有由ALD(例如，較高密度的材料)形成的第一子層46A，並且蓋38藉由CVD、PVD或鍍敷(例如，較低密度的材料)形成。在其他實施例中，導通孔46不具有複數個子層，而是替代地，導通孔46使用諸如CVD、PVD、鍍敷等單一沉積製程形成，在該種情況下，導通孔46和蓋38可具有相同的密度。
接下來，在第9圖中，使用與上述用於形成IMD層(例如，30或44)和導電特徵(例如，34、38、46)的方法相同或類似的方法，在IMD層44上形成包括導電特徵(例如，導電線和導通孔)的一個或多個IMD層53。接下來，在IMD層53上形成鈍化層56，諸如聚合物層。在形成鈍化層56之後，在鈍化層56上形成球下冶金層(under bump metallurgy,UBM)結構62，並將其電耦合到IMD層53的導電特徵54(例如，導電線)。
在一個實施例中，UBM結構62包括三層傳導性材料，諸如鈦層、銅層和鎳層。然而，有許多適用於形成UBM結構62的合適材料和層佈置，諸如鉻/鉻銅合金/銅/金的佈置，鈦/鈦鎢/銅的佈置、或銅/鎳/金的佈置。可以用於UBM結構62的任何合適的材料或材料層完全意欲包括在本揭露的實施例的範疇內。
UBM結構62可以藉由以下步驟形成：在鈍化層56中形成開口以暴露IMD層53中的導電特徵54；在該鈍化層56上並沿著該鈍化層中的開口內部形成種晶層；在該種晶層上形成圖案化掩模層(例如，光阻劑)；在圖案化掩模層的開口中和該種晶層上方形成(例如，藉由鍍敷)(多種)傳導性材料；移除該掩模層並移除該種晶層的上面未形成傳導性材料的部分。用於形成UBM結構62的其他方法是可能的，並且完全意欲包括在本揭露的實施例的範疇內。
仍然參考第9圖，接下來，在UBM結構62上形成外部連接器64。在一個實施例中，外部連接器64是接觸凸塊，諸如受控塌陷晶片連接(C4)凸塊，並且包含諸如錫等材料或諸如銀或銅等其他合適的材料。在外部連接器64是錫焊料凸塊的實施例中，外部連接器64可以藉由最初經由任何合適的方法(諸如蒸發、電鍍、印刷、焊料轉移、球放置等)形成錫層而形成。一旦已經在該結構上形成錫層，就執行回流以將材料成形為直徑為例如約80μm的凸塊形狀。
然而，儘管上面已經將外部連接器64描述為C4凸塊，但是該等僅僅是說明性的而不是用於限制實施例。相反，可以替代地利用任何合適類型的外部觸點，諸如球柵陣列(BGA)、微凸塊、銅柱、銅層、鎳層、無鉛(LF)層、化學鍍鎳化學鍍鈀浸金(ENEPIG)層、Cu/LF層、Sn/Ag層、Sn/Pb、該等的組合等。任何合適的外部連接器和用於形成 外部連接器的任何合適的製程可以用於外部連接器64，並且所有此類外部連接器完全意欲包括在實施例的範疇內。
第10圖至第12圖圖示了在一個實施例中處於各個製造階段的半導體元件200的剖視圖。除非另有說明，否則第10圖至第12圖中相同的數字符號表示與第1圖至第9圖中由相同或相似的形成方法形成的相同或相似的元件，因此不再重複細節。第10圖中的處理遵循第6圖中所示的處理，因此，第1圖至第6圖和第10圖至第12圖圖示了本揭露的另一個實施例。
參照第10圖，在第6圖所示的處理步驟之後，在IMD層30和蓋38上形成蝕刻終止層42和IMD層44。接下來，使用諸如光微影和蝕刻等合適方法在IMD層44中形成導通孔開口45。導通孔開口45延伸穿過IMD層44和蝕刻終止層42，並暴露蓋38。在第10圖的實例中，導通孔開口45的寬度W9大於蓋38的寬度，因此，暴露蓋38的上表面和IMD層30的上表面的一部分。在一些實施例中，寬度W9介於約15nm與約40nm之間。
接下來，在第11圖中，使用蓋38的傳導性材料(例如，鎢)在導通孔開口45(參見第10圖)中形成導通孔46。換言之，導通孔46和蓋38由相同的傳導性材料形成。導通孔46直接形成在蓋38上(例如，與蓋38直接接觸)。取決於傳導性材料和用於形成導通孔46的製程，在導通孔46與蓋38之間可以存在或不存在界面37。導通孔46和蓋38可以統稱為導通孔48，導通孔48亦可以稱為插塞或導電插 塞。導通孔46可以被稱為導電插塞48的上部，並且蓋38可以被稱為導電插塞48的下部。
可以使用合適的形成方法(諸如CVD、PVD、鍍敷、ALD等或其組合)在導通孔開口43中形成導通孔46。可以執行諸如CMP等平坦化製程以從IMD層44的上表面上移除導通孔46的材料的多餘部分。
在所示實施例中，導通孔46形成在導通孔開口45中並且與IMD層44、蝕刻終止層42、IMD層30和蓋38直接接觸。換言之，在導通孔46和IMD層44/IMD層30/蝕刻終止層42之間沒有形成阻障層，此可以有利地減小所形成的半導體元件200的RC延遲。在一些實施例中，當在蓋38上形成導通孔46時，使用兩種不同的形成方法來形成導通孔46。特別地，執行ALD沉積製程以形成導通孔46的第一子層46A，並且使用不同的沉積製程(諸如CVD、PVD或鍍敷)來填充導通孔開口45的剩餘部分(參見第10圖)並形成導通孔46的第二子層46B。換言之，第一子層46A和第二子層46B由相同的材料(例如，鎢)，但是使用不同的沉積方法形成。在第一子層46A與第二子層46B之間可以存在界面47。第一子層46A的厚度可介於約0nm與約3nm之間。由於第一子層46A由ALD形成，因此其密度高於第二子層46B。在一些實施例中，使第一子層46A具有更高質量(例如，更高密度)降低了所形成的導通孔46的電阻。由於ALD沉積製程的沉積速率可低於例如PVD、CVD或鍍敷的沉積速率，因此藉由PVD、CVD或鍍敷形成第二子層46B可有 利地縮短製造時間，從而允許在減小導通孔46的電阻(例如，RC延遲)與縮短製造時間之間實現平衡。
在一些實施例中，導通孔46的總密度(例如，平均密度)高於蓋38的總密度，此係因為導通孔46具有由ALD(例如，較高密度的材料)形成的第一子層46A，並且蓋38藉由CVD、PVD或鍍敷(例如，較低密度的材料)形成。在其他實施例中，導通孔46不具有複數個子層，而是替代地，導通孔46使用諸如CVD、PVD、鍍敷等單一沉積製程形成，在該種情況下，導通孔46和蓋38可具有相同的密度。
接下來，在第12圖中，使用與上述用於形成IMD層(例如，30或44)和導電特徵(例如，34、38、46)的方法相同或類似的方法，在IMD層44上形成包括導電特徵(例如，導電線和導通孔)的一個或多個IMD層53。接下來，在IMD層53上形成鈍化層56，諸如聚合物層。在形成鈍化層56之後，在鈍化層56上形成球下冶金層(under bump metallurgy,UBM)結構62，並將其電耦合到IMD層53的導電特徵54(例如，導電線)。接下來，在UBM結構62上形成外部連接器64。UBM結構62和外部連接器64的形成可以與上面參考第9圖描述的彼等相同或相似，因此不再重複細節。
第13圖至第21圖圖示了在一個實施例中處於各個製造階段的半導體元件300的剖視圖。除非另有說明，否則第13圖至第21圖中相同的數字符號表示與第1圖至第9圖中由相同或相似的形成方法形成的相同或相似的元件，因 此不再重複細節。第13圖中的處理遵循第1圖中所示的處理，因此，第1圖和第13圖至第21圖圖示了本揭露的另一個實施例。
參考第13圖，在ILD 24上和接觸插塞28上形成IMD層30。在IMD層30中形成開口33，以使用諸如光微影和蝕刻等合適方法暴露下面的接觸插塞28。蝕刻可以是各向異性的，使得開口33的側壁垂直於ILD 24的上表面。
接下來，在第14圖中，藉由諸如乾法蝕刻製程等蝕刻製程來改變開口33的輪廓(例如，側壁的形狀)。在一些實施例中，藉由另一光微影和蝕刻製程擴展開口33的上部的寬度，隨後在開口33的底部處形成掩模層，諸如光阻劑。隨後執行乾法蝕刻製程以改變開口33的上部的輪廓。在一些實施例中，使用電漿製程改變開口33的上部的輪廓。電漿製程可以使用包含氬的氣體源。包含氬的氣體源被激活成電漿，並且氬的電漿轟擊IMD層30並改變開口33的輪廓。在一些實施例中，在介於約200瓦特與約600瓦特之間的RF功率，介於約25℃與約80℃之間的溫度和介於約0.002托與約0.05托之間的壓力下執行電漿處理。氬氣的流速介於約2標準立方公分/分鐘(sccm)與約20sccm之間。在一些實施例中，調諧電漿製程的RF功率以改變電漿製程的橫向蝕刻速率，使得橫向蝕刻速率沿著從IMD層30的上表面朝向IMD層30的下表面的方向減小，從而形成開口33的上部的傾斜側壁。在完成電漿處理之後，從開口33的底部移除掩模層，使得開口33的底部仍具有豎直側壁。
在完成蝕刻製程之後，開口33的上部具有傾斜側壁30A，並且開口33的下部具有直的(例如，垂直於ILD 24的上表面)側壁30C。如第14圖所示，相對側壁30A之間的距離隨著開口33延伸到IMD層30中而減小。另外，與ILD 24的上表面平行的側壁30B在傾斜側壁30A與直的側壁30C之間提供過渡。因此，開口33的側壁的形狀包括台階形狀(亦稱為階梯形狀)。在第14圖中，在傾斜側壁30A的底部處量測的傾斜側壁30A之間的距離W5大於直側壁30C之間的距離W6。距離W5可以介於約20nm與約40nm之間，並且距離W6可以在約15nm與約35nm之間。
接下來，在第15圖中，在開口33中形成諸如鈷等傳導性材料36。如第15圖所示，傳導性材料36的下部36L填充開口33的下部，並且傳導性材料36的上部36U填充開口33的上部。在一些實施例中，傳導性材料36溢出開口33並覆蓋IMD層30的上表面。隨後執行諸如CMP等平坦化製程以從IMD層30的上表面上移除傳導性材料36的多餘部分。
在一些實施例中，在形成傳導性材料36之前，在開口33中形成阻障層，該阻障層襯於開口33的側壁和底部。阻障層的一個實例如第3圖所示。為簡單起見，此處未圖示阻障層。在其他實施例中，省略了阻障層。
接下來，在第16圖中，執行減薄製程以減小IMD層30的厚度並減小傳導性材料36的上部36U的厚度。諸如CMP等平坦化製程可以用作減薄製程。減薄製程在到 達傳導性材料36的下部36L之前停止，如第16圖所示。在所示實施例中，在減薄製程之後，上部36U的剩餘部分的厚度T3在約5nm與約10nm之間，並且在上部36U的剩餘部分的側壁與下部36L的相應側壁之間的距離W7在約2nm與約3nm之間。IMD層30的厚度可以在約0nm與約30nm之間。上面論述的尺寸是非限制性實例。其他尺寸亦是可能的，並且完全意欲包括在本揭露的實施例的範疇內。
接下來，在第17圖中，移除上部36U的剩餘部分(參見第16圖)。在一些實施例中，執行蝕刻製程，諸如濕法蝕刻製程，以移除上部36U的剩餘部分。濕法蝕刻製程可以使用對傳導性材料36具有選擇性(例如，具有更高蝕刻速率)的蝕刻劑(例如，HF、HCl、H2O2或KOH)，使得在基本上不攻擊IMD層30的情況下移除傳導性材料36。在蝕刻製程之後，開口33的下部中的傳導性材料36的剩餘部分形成導電線34。導電線34的上表面34T可以與側壁30B齊平。
在一些實施例中，代替執行單獨的濕法蝕刻製程，藉由CMP製程移除上部36U的剩餘部分(參見第16圖)。例如，CMP製程中使用的漿料可以對傳導性材料36具有選擇性，使得傳導性材料36被以比IMD層30更快的速率移除。在CMP製程之後，傳導性材料36的剩餘部分形成導電線34。如第17圖所示，由於CMP製程的凹槽效應，藉由CMP製程形成的導電線34的上表面34T'(以虛線圖示)可以是凹形的。為簡單起見，本揭露的實施例中的後續附圖可能未圖示導電線34的凹形上表面34T'，應理解，取決於用 於移除傳導性材料36的製程，導電線34的上表面可以是平坦的(參見例如34T)或凹形的(參見例如34T')。
接下來參照第18圖，蓋38在導電線34上形成並填充IMD層30中的凹槽，該凹槽是藉由移除傳導性材料36而形成的(參見第17圖)。在所示實施例中，蓋38和導電線34由不同材料形成。例如，蓋38由傳導性材料(例如，導電材料)形成，該傳導性材料不同於導電線34的傳導性材料36。在一個示例性實施例中，導電線34由鈷形成，並且蓋38由鎢(W)形成。蓋38的材料的其他實例包括Ru、Al和Cu。在第18圖的實例中，由於凹槽的傾斜側壁，蓋38亦具有傾斜側壁。
蓋38可以使用例如CVD、PVD、電鍍或其他合適的方法形成。蓋38的材料可能溢出IMD層30中的凹槽，在該情況下，可以執行諸如CMP等平坦化製程以移除蓋38的材料的多餘部分。在其他實施例中，蓋38的材料形成在凹槽中並填充該凹槽而不會溢出，因此省略了平坦化製程。
在一些實施例中，在形成之後，蓋38的厚度T4在約5nm與約10nm之間，並且蓋38的側壁與導電線34的對應側壁之間的距離W8在約2nm與約3nm之間，但是其他尺寸亦是可能的。如第18圖所示，蓋38的寬度(沿距離W8方向量測)大於導電線34的寬度。在一些實施例中，距離W8介於約1nm與約5nm之間。
接下來，在第19圖中，在IMD層30和蓋38上形成蝕刻終止層42和IMD層44。接下來，使用諸如光微影和 蝕刻等合適方法在IMD層40中形成導通孔開口43。導通孔開口43延伸穿過IMD層40和蝕刻終止層42，並暴露蓋38。在第19圖的實例中，導通孔開口43的寬度小於蓋38的寬度，因此暴露蓋38的上表面的一部分。在其他實施例中，導通孔開口43的寬度大於蓋38的寬度，類似於第10圖中的開口45。
接下來，在第20A圖中，使用蓋38的傳導性材料(例如，鎢)在導通孔開口43(參見第19圖)中形成導通孔46。換言之，導通孔46和蓋38由相同的傳導性材料形成。導通孔46直接形成在蓋38上(例如，與蓋38直接接觸)。取決於傳導性材料和用於形成導通孔46的製程，在導通孔46與蓋38之間可以存在或不存在界面37。導通孔46和蓋38可以統稱為導通孔48。
可以使用合適的形成方法(諸如CVD、PVD、鍍敷、ALD等或其組合)在導通孔開口43中形成導通孔46。可以執行諸如CMP等平坦化製程以從IMD層44的上表面上移除導通孔46的材料的多餘部分。在所示實施例中，導通孔46形成在導通孔開口43中並且與IMD層44和蝕刻終止層42直接接觸。換言之，在導通孔46和IMD層44/蝕刻終止層42之間沒有形成阻障層，此可以有利地減少半導體元件300的RC延遲。
第20B圖圖示了第20A圖中的導通孔48的放大視圖。在一些實施例中，當在蓋38上形成導通孔46時，使用兩種不同的形成方法來形成導通孔46。特別地，執行ALD 沉積製程以形成導通孔46的第一子層46A，並且使用不同的沉積製程(諸如CVD、PVD或鍍敷)來填充導通孔開口43的剩餘部分(參見第19圖)並形成導通孔46的第二子層46B。換言之，第一子層46A和第二子層46B由相同的材料(例如，鎢)，但是使用不同的沉積方法形成。在第一子層46A與第二子層46B之間可以存在界面47。由於第一子層46A由ALD形成，因此其密度高於第二子層46B。在一些實施例中，使第一子層46A具有更高質量(例如，更高密度)降低了所形成的導通孔46的電阻。由於ALD沉積製程的沉積速率可低於例如PVD、CVD或鍍敷的沉積速率，因此藉由PVD、CVD或鍍敷形成第二子層46B可有利地縮短製造時間，從而允許在減小導通孔46的電阻(例如，RC延遲)與縮短製造時間之間實現平衡。
仍然參考第20B圖，在一些實施例中，導通孔46的總密度(例如，平均密度)高於蓋38的總密度，此係因為導通孔46具有由ALD(例如，較高密度的材料)形成的第一子層46A，並且蓋38藉由CVD、PVD或鍍敷(例如，較低密度的材料)形成。在其他實施例中，導通孔46不具有複數個子層，而是替代地，導通孔46使用諸如CVD、PVD、鍍敷等單一沉積製程形成，在該種情況下，導通孔46和蓋38可具有相同的密度。
接下來，在第21圖中，使用與上述用於形成IMD層(例如，30或44)和導電特徵(例如，34、38、46)的方法相同或類似的方法，在IMD層44上形成包括導電特徵 (例如，導電線和導通孔)的一個或多個IMD層53。接下來，在IMD層53上形成鈍化層56，諸如聚合物層。在形成鈍化層56之後，在鈍化層56上形成球下冶金層(under bump metallurgy,UBM)結構62，並將其電耦合到IMD層53的導電特徵54(例如，導電線)。接下來，在UBM結構62上形成外部連接器64。UBM結構62和外部連接器64的形成可以與上面參考第9圖描述的彼等相同或相似，因此不再重複細節。
所揭示的實施例的變型是可能的，並且完全意欲包括在本揭露的實施例中。例如，儘管蓋38被圖示為形成在導通孔46下方和IMD層(例如，44、45)中，但是蓋38亦可以形成在接觸插塞28下方和ILD 24中。由於接觸插塞28連接到下面的導電特徵(例如，電晶體的閘電極或電晶體的源極/汲極區域)，所以本揭露的實施例的原理亦可以應用於在接觸插塞28與積體電路元件22的導電特徵之間形成蓋38。換言之，藉由使用與積體電路元件22的導電特徵的材料不同的材料形成蓋38，可以防止或減少對積體電路元件22的導電特徵的侵蝕。作為另一個實例，例如當蓋38比下面的導電線(例如，34)更寬時，蓋38的輪廓，例如蓋38的側壁的形狀，可以被修改為具有其他形狀，並且蓋38的益處仍然保持。該等和其他修改完全意欲包括在本揭露的實施例的範疇內。
實施例可以實現優點。蓋38遮罩導電線34以免受後續CMP製程中使用的漿料影響，由此防止或減少了對 導電線34的侵蝕，此提高了所形成的元件的效能並提高了產量。藉由使用兩種不同的材料用於蓋38和導電線34，可以利用該兩種不同材料之間的蝕刻選擇性來減少或防止對導電線34的侵蝕。本揭露的實施例允許在沒有阻障層的情況下形成導通孔46，此有利地減少了所形成的元件的RC延遲。
第22圖圖示了根據一些實施例的用於形成半導體元件的方法的流程圖。應該理解，第22圖中所示的實施例方法僅僅是許多可能的實施例方法的實例。本領域一般技藝人士將認識到許多變化、替代和修改。例如，可以添加、移除、替換、重新排列和重複如第22圖所示的各種步驟。
參考第22圖，在方塊1010中，在基板上形成第一介電層。在方塊1020中，使用第一材料在第一介電層中形成導電線，其中在形成導電線之後，在第一介電層中存在靠近遠離基板的第一介電層的上表面的凹槽，其中該凹槽的底部暴露導電線的上表面。在方塊1030中，使用不同於第一材料的第二材料填充第一介電層中的凹槽以形成金屬蓋，其中金屬蓋比導電線更寬。在方塊1040中，在第一介電層上形成第二介電層。在方塊1050中，在第二介電層中形成開口以暴露金屬蓋。在方塊1060中，使用第二材料填充開口以形成導通孔。
在一個實施例中，半導體元件包括：第一介電層，該第一介電層在基板上，該第一介電層包含第一介電材料，該第一介電材料從第一介電層遠離基板的第一側延伸到 第一介電層與該第一側相對的第二側；第二介電層，該第二介電層在該第一介電層上；導電線，該導電線在該第一介電層中，該導電線包含第一傳導性材料，該導電線的上表面比該第一介電層的上表面更靠近該基板；金屬蓋，該金屬蓋在該第一介電層中，該金屬蓋在該導電線上方並與該導電線實體連接，該金屬蓋包括與該第一傳導性材料不同的第二傳導性材料；以及導通孔，該導通孔在該第二介電層中並與該金屬蓋實體連接，該導通孔包含該第二傳導性材料。在一個實施例中，金屬蓋的上表面與第一介電層的上表面齊平。在一個實施例中，金屬蓋比導電線更寬。在一個實施例中，金屬蓋具有垂直於導電線的上表面的側壁。在一個實施例中，金屬蓋具有相對於導電線的上表面傾斜的側壁。在一個實施例中，第一傳導性材料是鈷，並且第二傳導性材料是鎢。在一個實施例中，導通孔比金屬蓋更寬。在一個實施例中，半導體元件進一步包括在第一介電層與第二介電層之間的蝕刻終止層，其中該導通孔延伸穿過該蝕刻終止層。在一個實施例中，導通孔實體地接觸第二介電層。在一個實施例中，半導體元件進一步包括在導電線與第一介電層之間的阻障層。
在一個實施例中，半導體元件包括：基板；第一介電層，該第一介電層在該基板上，該第一介電層是單層；導電特徵，該導電特徵在第一介電層中，該導電特徵包含第一傳導性材料，該導電特徵遠離該基板的第一表面比該第一介電層遠離該基板的第一表面更靠近該基板；第二介電層，該第二介電層在該第一介電層和該導電特徵上；以及導 電插塞，該導電插塞具有上部和下部，該上部和該下部包含與該第一傳導性材料不同的第二傳導性材料，該導電插塞的上部設置在該第二介電層中，該導電插塞的下部延伸到該第一介電層中並且與該導電特徵實體連接。在一個實施例中，導電插塞的下部的寬度大於導電特徵的寬度。在一個實施例中，導電插塞與第二介電層實體接觸。在一個實施例中，半導體元件進一步包括在導電特徵與第一介電層之間的阻障層。在一個實施例中，導電插塞的上部的第一密度高於導電插塞的下部的第二密度。
在一個實施例中，一種半導體元件形成方法包括在基板上形成第一介電層；使用第一材料在該第一介電層中形成導電線，其中在形成該導電線之後，在該第一介電層中存在靠近遠離基板的第一介電層上表面的凹槽，其中該凹槽的底部暴露該導電線的上表面；使用不同於該第一材料的第二材料填充該第一介電層中的凹槽以形成金屬蓋，其中該金屬蓋比該導電線更寬；在該第一介電層上形成第二介電層；在該第二介電層中形成開口以暴露該金屬蓋；以及使用該第二材料填充該開口以形成導通孔。在一個實施例中，形成該導電線包括在該第一介電層中形成通孔，該通孔具有靠近該第一介電層的上表面的上部和位於該上部下面的下部，該通孔的上部比該通孔的下部更寬；用該第一材料填充該通孔，該第一材料的第一部分填充該通孔的上部，並且該第一材料的第二部分填充該通孔的下部；減小該第一材料的第一部分的高度和該第一介電層的高度；以及在該減小之 後，移除該第一材料的第一部分的剩餘部分以在該第一介電層中形成凹槽，其中該第一材料的第二部分在該移除之後形成導電線。在一個實施例中，填充開口包括使用原子層沉積(ALD)在開口中沉積包含第二材料的第一子層；以及使用除ALD之外的沉積方法在開口中的第一子層上沉積包含該第二材料的第二子層。在一個實施例中，開口形成為比金屬蓋更寬。在一個實施例中，第一材料是鈷，並且第二材料是鎢。
先前概述了若干實施例的特徵，使得本領域技藝人士可以更好地理解本揭露的實施例的各態樣。本領域技藝人士應當理解，他們可以容易地使用本揭露的實施例作為設計或修改其他製程和結構的基礎，以實現與本揭露介紹的實施例相同的目的及/或實現與本揭露介紹的實施例相同的優點。本領域技藝人士亦應當認識到，此類等同構造不脫離本揭露的實施例的精神和範圍，並且在不脫離本揭露的實施例的精神和範圍的情況下，他們可以在本揭露的實施例中進行各種改變、替換和變更。
20:半導體基板
22:積體電路元件
24:層間介電質(ILD)
28:接觸插塞
30:金屬間介電(IMD)層
34:導電線
38:蓋
42:蝕刻終止層
44:IMD層
46:導通孔
53:IMD層
54:導電特徵
56:鈍化層
62:球下冶金層(UBM)結構
64:外部連接器
200:半導體元件

Claims (10)

  1. 一種半導體元件，包括：一第一介電層，該第一介電層在一基板上，該第一介電層包含一第一介電材料，該第一介電材料從該第一介電層遠離該基板的一第一側延伸到該第一介電層與該第一側相對的一第二側；一第二介電層，該第二介電層在該第一介電層上；一導電線，該導電線在該第一介電層中，該導電線包括一第一傳導性材料，該導電線的一上表面比該第一介電層的一上表面更靠近該基板；一金屬蓋，該金屬蓋在該第一介電層中，該金屬蓋在該導電線上並與該導電線實體連接，該金屬蓋包含不同於該第一傳導性材料的一第二傳導性材料；以及一導通孔，該導通孔在該第二介電層中並且實體連接到該金屬蓋，該導通孔包含該第二傳導性材料，其中該金屬蓋與該導通孔之間不具有阻障層。
  2. 如請求項1所述之半導體元件，其中該金屬蓋的一上表面與該第一介電層的該上表面齊平。
  3. 如請求項2所述之半導體元件，其中該金屬蓋比該導電線更寬。
  4. 一種半導體元件，包括：一基板； 一第一介電層，該第一介電層在該基板上，該第一介電層是一單層；一導電特徵，該導電特徵在該第一介電層中，該導電特徵包含一第一傳導性材料，該導電特徵遠離該基板的一第一表面比該第一介電層遠離該基板的一第一表面更靠近該基板；一第二介電層，該第二介電層在該第一介電層和該導電特徵上；以及一導電插塞，該導電插塞具有一上部和一下部，該上部和該下部包含與該第一傳導性材料不同的一第二傳導性材料，該導電插塞的該上部設置在該第二介電層中，該導電插塞的該下部延伸到該第一介電層中並與該導電特徵實體連接，其中該上部與該下部之間不具有阻障層。
  5. 如請求項4所述之半導體元件，其中該導電插塞的該下部的一寬度大於該導電特徵的一寬度。
  6. 一種半導體元件形成方法，包括：在一基板上形成一第一介電層；使用一第一材料在該第一介電層中形成一導電線，其中在形成該導電線之後，在該第一介電層中存在靠近該第一介電層的遠離該基板的上表面的一凹槽，其中該凹槽的一底部暴露該導電線的一上表面； 使用不同於該第一材料的一第二材料填充該第一介電層中的該凹槽以形成一金屬蓋，其中該金屬蓋比該導電線更寬；在該第一介電層上形成一第二介電層；在該第二介電層中形成一開口以暴露該金屬蓋；以及使用該第二材料填充該開口以形成一導通孔，其中形成該導電線包括：在該第一介電層中形成一通孔，該通孔具有靠近該第一介電層的該上表面的一上部和位於該上部下面的一下部，該導通孔的該上部比該通孔的該下部更寬；用該第一材料填充該通孔，該第一材料的一第一部分填充該通孔的該上部，並且該第一材料的一第二部分填充該通孔的該下部；減小該第一材料的該第一部分的一高度和該第一介電層的一高度；以及在該減小之後，移除該第一材料的該第一部分的剩餘部分以在該第一介電層中形成該凹槽，其中該第一材料的該第二部分在該移除之後形成該導電線。
  7. 如請求項6所述之半導體元件形成方法，其中填充該開口包括：在該開口中沉積一第一子層；以及在該開口中的該第一子層上沉積一第二子層，其中該第一子層的密度高於該第二子層的密度。
  8. 如請求項6所述之半導體元件形成方法，其中填充該開口包括：使用原子層沉積(ALD)在該開口中沉積包含該第二材料的一第一子層；以及使用除ALD之外的一沉積方法在該開口中的該第一子層上沉積包含該第二材料的一第二子層。
  9. 如請求項6所述之半導體元件形成方法，其中該開口形成為比該金屬蓋更寬。
  10. 如請求項6所述之半導體元件形成方法，其中該第一材料是鈷，並且該第二材料是鎢。
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