TWI713858B - 積體電路封裝及其形成方法 - Google Patents

積體電路封裝及其形成方法 Download PDF

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TWI713858B
TWI713858B TW107122287A TW107122287A TWI713858B TW I713858 B TWI713858 B TW I713858B TW 107122287 A TW107122287 A TW 107122287A TW 107122287 A TW107122287 A TW 107122287A TW I713858 B TWI713858 B TW I713858B
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Taiwan
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integrated circuit
opening
circuit die
sealing body
layer
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TW107122287A
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TW201906109A (zh
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吳逸文
郭宏瑞
何明哲
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供一種積體電路封裝及其形成方法。積體電路的形成方法包含將積體電路晶粒之第一側附接至載體；於積體電路晶粒上方及周圍形成密封體；圖案化密封體以形成與積體電路晶粒橫向間隔開的第一開口以及積體電路晶粒上方的第二開口，其中第一開口延伸穿過密封體，第二開口暴露積體電路晶粒之第二側，積體電路晶粒之第一側與積體電路晶粒之第二側相對；以及同時於第一開口及第二開口中沈積導電材料。

Description

積體電路封裝及其形成方法
本發明實施例是有關於一種積體電路封裝及其形成方法。
半導體元件用於多種電子應用中，諸如個人電腦、行動電話、數位攝影機以及其他電子設備。一般而言，藉由在半導體基底上方依序沈積絕緣層或介電層、導電層以及半導電材料層，且使用微影製程以圖案化各種材料層來製造半導體元件。如此一來，可在半導體基底上形成電路組件以及元件。在單一半導體晶圓上通常可製造數十或數百個積體電路。藉由沿著切割道(scribe line)鋸切積體電路而將個別晶粒單體化。接著以單獨封裝、多晶片模組形式或以其他類型的封裝形式封裝個別晶粒。
由於各種電子組件(例如電晶體、二極體、電阻器、電容器等)的積集度(integration density)的持續提高，半導體產業經歷了快速的成長。主要地，積集度的提高來自於最小特徵尺寸之持續減小(例如，半導體製程節點朝向次20奈米節點演進)，其使得在給定區域中整合更多組件。隨著近年來對小型化、較高速度及 較大頻寬以及較低功耗及延遲時間(latency)之需求的增長，已出現對於半導體晶粒而言更小且更具創造性封裝技術的需求。
隨著半導體技術進一步發展，已發展出堆疊半導體元件，例如三維積體電路(three dimensional integrated circuit；3DIC)，以作為有效的方案而進一步減小半導體元件之實體尺寸。在堆疊半導體元件中，諸如邏輯、記憶體、處理器電路及類似者之主動電路製造於不同的半導體晶圓上。兩個或更多半導體晶圓可安裝或彼此堆疊以進一步減小半導體元件之形狀因素(form factor)。疊層封裝(Package-on-package；POP)元件是3DIC的一種類型，其中晶粒經封裝且接著再與另一封裝晶粒或多個封裝晶粒一起被封裝。晶片封裝(chip-on-package；COP)元件是另一種類型之3DIC，其中晶粒經封裝且隨後與另一晶粒或多個晶粒一起被封裝。
根據一實施例，一種積體電路的形成方法包含：將積體電路晶粒之第一側附接至載體；於積體電路晶粒上方及周圍形成密封體；圖案化密封體以形成與積體電路晶粒橫向間隔開的第一開口以及積體電路晶粒上方的第二開口，第一開口延伸穿過密封體，第二開口暴露積體電路晶粒之第二側，積體電路晶粒之第一側與積體電路晶粒之第二側相對；以及同時於第一開口及第二開口中沈積導電材料。
根據另一實施例，一種積體電路的形成方法包含：將積體電路晶粒之第一側附接至載體，積體電路晶粒之第二側具有接觸墊，積體電路晶粒之第一側與積體電路晶粒之第二側相對；於積 體電路晶粒上方及周圍形成密封體；以及同時於密封體中形成導通孔及第一重佈線層，導通孔與積體電路晶粒之側壁橫向間隔開，導通孔之頂部表面在密封體之最頂部表面下方，第一重佈線層在積體電路晶粒之第二側上方，第一重佈線層與接觸墊電接觸。
根據又一實施例，一種積體電路包含：積體電路晶粒；密封體，沿積體電路晶粒之側壁及最頂部表面延伸；導通孔，在密封體中，所述導通孔與積體電路晶粒之側壁間隔開；以及導通孔上方的絕緣層。在一實施例中，導通孔包含：沿絕緣層之底部表面延伸的第一部分；以及沿絕緣層之側壁延伸的第二部分，第一部分之高度大於第二部分之寬度。
100、1601:工件
101:晶粒區域
103:切割道
105:基底
107:主動元件及/或被動元件
109:金屬化層
111:接觸墊
113:鈍化層
115、203、403、1003、1005:開口
201:緩衝層
301、1101:晶種層
401、1201:圖案化罩幕
501:導電柱
503:焊料層
701:保護層
703、1501:膠帶
801、1411:積體電路晶粒
803、1503:框架
805:黏著劑
901:載體
903:離形層
905、14031、14032、14033、17031、17032、19031、19032:絕緣層
907:黏著層
1001:密封體
1203:導電材料
1301:導通孔
1303、14051、14052、17051、17052、19051、19052:重佈線層(RDL)
1401、1701、1901:重佈線結構
1407:凸塊下金屬化物
1409、1413、1603:連接件
1500、1700、1900:積體電路封裝
1600、1800、2000:堆疊半導體元件
1605:底填充料
2000:方法
2101、2103、2105、2107、2109、2111、2113:步驟
T1、T2:厚度
結合附圖閱讀以下詳細描述會最佳地理解本發明之態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。實際上，為論述清楚起見，可任意增大或減小各種特徵之尺寸。
圖1至圖8是根據一些實施例在製造積體電路晶粒期間的各種處理步驟之截面圖。
圖9至圖16是根據一些實施例在製造積體電路封裝期間的各種處理步驟之截面圖。
圖17及圖18是根據一些實施例在製造積體電路封裝期間的各種處理步驟之截面圖。
圖19及圖20是根據一些實施例在製造積體電路封裝期間的各種處理步驟之截面圖。
圖21根據一些實施例示出形成積體電路封裝的方法的流程 圖。
以下揭露內容提供用於實施本發明之不同構件的許多不同實施例或實例。下文描述組件以及配置的特定實例以簡化本發明。當然，這些組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含第一特徵以及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外，本發明可在各種實例中重複參考數字及/或字母。此重複是出於簡單性及清晰性之目的，且本身並不指示所論述之各種實施例及/或組態之間的關係。
另外，諸如「在……下面(beneath)」、「在……下方(below)」、「下部的(lower)」、「在……上方(above)」、「上部的(upper)」及類似術語等空間相對術語可在本文中出於簡單描述而使用以描述如圖中所示的一個元件或構件與另一元件或構件的關係。除了圖式中所描繪的定向以外，空間相對術語亦意欲涵蓋元件在使用或操作中之不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
將相對於特定情形中之實施例來描述實施例，特定情形中的實施例亦即諸如積體扇出型(integrated fan-out；InFO)封裝件及包括InFO封裝件之PoP封裝的積體電路封裝。然而，其他實施例亦可應用於其他電連接組件，包含但不限於在組合封裝中，在 處理基底、***件、基底或其類似物、或安裝輸入組件、板、晶粒或其他組件中，或用於連接任何類型的積體電路或電組件之封裝或安裝組合的疊層封裝總成、晶粒對晶粒總成、晶圓對晶圓總成、晶粒對基底總成。本文所描述之各種實施例使得經由相同製程步驟中形成積體電路封裝的穿過密封體的通孔以及重佈線，故可減少用於形成積體電路封裝之製程步驟數並降低製造成本。
圖1至圖8是根據一些實施例在製造積體電路晶粒期間的各種處理步驟的截面圖。參看圖1，示出具有由切割道103(亦稱為分割線(dicing line)或分割道(dicing street))分離的晶粒區域101的工件100之一部分。如下文更詳細地描述，將沿著切割道103分割工件100以形成個別積體電路晶粒(諸如圖8中所示出的積體電路晶粒801)。在一些實施例中，工件100包括基底105、基底105上的一或多個主動元件及/或被動元件107、以及基底105及一或多個主動元件及/或被動元件107上方的一或多個金屬化層109。在一些實施例中，基底105可由矽形成，但其亦可由其他第III族、第IV族及/或第V族元素(諸如矽、鍺、鎵、砷以及其組合)形成。基底105亦可呈絕緣體上覆矽(silicon-on-insulator；SOI)的形式。SOI基底可包括形成於絕緣層(例如內埋氧化物及/或其類似者)上方的半導體材料(例如矽、鍺及/或其類似者)層，所述絕緣層形成於矽基底上。另外，可使用的其他基底包含多層基底(multi-layered substrate)、梯度基底(gradient substrate)、混合定向基底(hybrid orientation substrate)、其任何組合及/或其類似者。
在一些實施例中，一或多個主動元件及/或被動元件107 可包含各種n型金屬氧化物半導體(n-type metal-oxide semiconductor；NMOS)元件及/或p型金屬氧化物半導體(p-type metal-oxide semiconductor；PMOS)元件，諸如電晶體、電容器、電阻器、二極體、光電二極體、保險絲及/或其類似者。
一或多個金屬化層109可包含形成於基底105及一或多個主動元件及/或被動元件107上方的層間介電(inter-layer dielectric；ILD)層/金屬間介電(inter-metal dielectric；IMD)層。ILD/IMD可藉由本領域中已知的任何適合的方法(諸如旋塗式塗覆(spin-on coating)方法、化學氣相沈積(chemical vapor deposition；CVD)、電漿增強CVD(plasma enhanced CVD；PECVD)、其類似方法或其組合)由例如低介電常數介電材料(諸如磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼磷矽玻璃(borophosphosilicate glass；BPSG)、FSG、SiOxCy、旋塗式玻璃(Spin-On-Glass)、旋塗式聚合物(Spin-On-Polymer)、矽碳材料(silicon carbon material)、其化合物、其複合材料、其組合或其類似者)形成。在一些實施例中，可使用例如金屬鑲嵌製程(damascene process)、雙金屬鑲嵌製程(dual damascene process)、其組合或其類似者來使互連結構形成於ILD/IMD中。在一些實施例中，互連結構可包括銅、銅合金、銀、金、鎢、鉭、鋁或其類似者。在一些實施例中，互連結構可提供形成於基底105上的一或多個主動元件及/或被動元件107之間的電連接。
在一些實施例中，於一或多個金屬化層109上方形成接觸墊111。接觸墊111可經由一或多個金屬化層109電耦合至一或多個主動元件及/或被動元件107。在一些實施例中，接觸墊111可 包括導電材料，諸如鋁、銅、鎢、銀、金、其類似者或其組合。在一些實施例中，可使用例如物理氣相沈積(physical vapor deposition；PVD)、原子層沈積(atomic layer deposition；ALD)、電化學鍍覆(electro-chemical plating)、無電式鍍覆(electroless plating)、其類似者或其組合來使導電材料形成於一或多個金屬化層109上方。隨後，圖案化導電材料以形成接觸墊111。在一些實施例中，可使用微影技術來圖案化導電材料。一般而言，微影技術涉及沈積光阻材料(未圖示)，所述光阻材料隨後經輻照(曝光)及顯影以移除光阻材料的一部分。剩餘光阻材料可在接下來的處理步驟(諸如蝕刻)中保護下伏材料，諸如接觸墊111之導電材料。適合的蝕刻製程(諸如反應性離子蝕刻(reactive ion etch；RIE)或其他乾式蝕刻、等向性或非等向性濕式蝕刻，或任何其他適合的蝕刻或圖案化製程)可應用於導電材料以移除導電材料之暴露部分並形成接觸墊111。在導電材料為鋁的一些實施例中，可使用例如80%磷酸、5%硝酸、5%乙酸與10%去離子(de-ionized；DI)水之混合物來蝕刻導電材料。隨後，可使用例如灰化製程(ashing process)與後續的濕式清潔製程(wet clean process)來移除光阻材料。
進一步參看圖1，於基底105及接觸墊111上方形成鈍化層113。在一些實施例中，鈍化層113可包括諸如氮化矽(silicon nitride)、氧化矽(silicon oxide)、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(borosilicate glass；BSG)、硼摻磷矽酸鹽玻璃(boron-doped phosphosilicate glass；BPSG)、其組合或其類似者的一或多個非光可圖案化(non-photo-patternable)介電材料層，且可使用化學氣相 沈積(CVD)、PVD、ALD、旋塗式塗覆製程、其組合或其類似方法形成。在其他實施例中，鈍化層113可包括諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺(polyimide；PI)、苯并環丁烯(benzocyclobutene；BCB)、其組合或其類似者的一或多個光可圖案化(photo-patternable)絕緣材料層，且可使用旋塗式塗覆製程或其類似方法形成。可使用類似於光阻材料之微影方法來圖案化此類光可圖案化介電材料。
於鈍化層113中形成開口115以暴露接觸墊111的一部分。在鈍化層113包括非光可圖案化介電材料的一些實施例中，可使用適合的微影方法及蝕刻方法來圖案化鈍化層113。在一些實施例中，光阻材料(未圖示)形成於鈍化層113上方。光阻材料隨後經輻照(曝光)及顯影以移除光阻材料的一部分。隨後，使用例如適合的蝕刻製程來移除鈍化層113的暴露部分以形成開口115。在一些實施例中，可使用例如緩衝氫氟酸(hydrofluoric acid；HF)來蝕刻由氧化矽形成的鈍化層113。在其他實施例中，可使用例如熱磷酸(H3PO4)來蝕刻由氮化矽形成的鈍化層113。
參看圖2，於鈍化層113及接觸墊111上方形成緩衝層201。在一些實施例中，緩衝層201可包括諸如聚苯并噁唑(PBO)、聚醯亞胺(PI)、苯并環丁烯(BCB)、其組合或其類似者的一或多個光可圖案化絕緣材料層，且可使用旋塗式塗覆製程或其類似方法形成。在一些實施例中，圖案化緩衝層201以形成開口203且暴露接觸墊111。在一些實施例中，可使用適合的微影技術以使緩衝層201暴露於光線，以形成開口203。在曝光之後，顯影及/或固化緩衝層201。
參看圖3，於緩衝層201上方及開口203中毯覆式沈積晶種層301。晶種層301可包括一或多個銅層、鈦層、鎳層、金層、錳層、其組合或其類似物的層，且可藉由ALD、PVD、濺鍍、其組合或其類似方法形成。在一些實施例中，晶種層301包括鈦層以及形成於鈦層上方的銅層。
參看圖4，於晶種層301上方形成圖案化罩幕401。在一些實施例中，圖案化罩幕401可包括光阻材料或任何光可圖案化材料。在一些實施例中，圖案化罩幕401之材料經沈積、輻照(曝光)以及顯影以移除材料之部分且形成開口403，藉此形成圖案化罩幕401。在所示出的實施例中，開口403暴露形成於開口203中之接觸墊111上方的晶種層301之一部分。如下文更詳細地論述，將於開口403中形成導電柱(諸如圖5中所示出的導電柱501)以提供與接觸墊111之間的電連接。
參看圖5，在由開口403及開口203(參看圖4)形成的組合開口之中形成導電柱501。在一些實施例中，使用電化學鍍覆製程、無電式鍍覆製程、ALD、PVD、其組合或其類似方法用諸如銅、鎢、鋁、銀、金、其組合或其類似物之導電材料填充組合開口，以形成導電柱501。在一些實施例中，導電柱501部分地填充組合開口，且用焊接材料填充組合開口之未被填充的剩餘部分，以在相應導電柱501上方形成焊料層503。在一些實施例中，適合的焊接材料可為諸如PbSn組合物的鉛類焊料；包含InSb的無鉛焊料；錫-銀-銅組合物(Sn-Ag-Cu，SAC)；以及具有共同熔點且在電應用中形成導電焊料連接的其他共晶材料。對於無鉛焊料，作為實例，可使用各種組成比例的SAC焊料，諸如SAC 105(Sn 98.5%、 Ag 1.0%、Cu 0.5%)、SAC 305以及SAC 405。無鉛焊料亦包含SnCu化合物而無需使用銀(Ag)，以及SnAg化合物而無需使用銅(Cu)。在一些實施例中，焊料層503可使用蒸鍍、電化學鍍覆製程、無電式鍍覆製程、列印、焊料轉移、其組合或其類似方法形成。
參看圖6，在形成導電柱501及焊料層503之後，移除圖案化罩幕401(參看圖5)。在一些實施例中，可使用例如灰化製程以及後續的濕式清潔製程移除包括光阻材料的圖案化罩幕401。隨後，使用例如適合的蝕刻製程來移除晶種層301之暴露部分。在晶種層301包括鈦層與形成於鈦層上方的銅層的實施例中，可使用例如FeCl3、HCl與H2O的混合物(用於蝕刻銅)以及H2O2、HF與H2O的混合物(用於蝕刻鈦)來蝕刻晶種層301。
參看圖7，於導電柱501及對應的焊料層503上方及周圍形成保護層701。在一些實施例中，保護層701可包括諸如聚苯并噁唑(PBO)、聚醯亞胺(PI)、苯并環丁烯(BCB)、其組合或其類似者的一或多個光可圖案化絕緣材料層，且可使用旋塗式塗覆製程或其類似方法形成。在一些實施例中，在形成保護層701之前，可測試晶粒區域101中之各者以識別已知良好晶粒(known good die；KGD)，以供進一步處理。
進一步參看圖7，在一些實施例中，需要背面研磨基底105，以例如是減小工件100之厚度以及隨後形成的積體電路晶粒之厚度。在此類實施例中，執行薄化製程，其中將諸如背面研磨(back grinding；BG)膠帶之膠帶703應用於保護層701之頂部表面，且藉由研磨、蝕刻、CMP製程、其組合或其類似者薄化基底105之背側。在一些實施例中，膠帶703保護工件100免受由研磨 流體及/或殘渣導致的污染。
參看圖8，在一些實施例中，在完成上文所描述的薄化製程之後，使用CMP製程、研磨製程、蝕刻製程、其組合或其類似者移除膠帶703並平坦化保護層701。在一些實施例中，執行平坦化製程直至暴露導電柱501為止。在一些實施例中，平坦化製程亦可移除導電柱501上方的焊料層503(參見圖7)。在一些實施例中，導電柱501之頂部表面與保護層701之頂部表面實質上共面。
進一步參看圖8，在一些實施例中，在完成上文所描述的平坦化製程之後，單體化工件100以形成個別晶粒801。在一些實施例中，可使用黏著劑805將工件100附接至框架803以使工件100準備用於後續分割製程。在一些實施例中，框架803可為膜框架或任何適合的載體以為後續操作(諸如分割)提供機械支撐。黏合劑805可為晶粒附接膜、分割膜或任何適合的黏著劑、環氧樹脂、紫外(ultraviolet；UV)膠(在曝光於UV輻射時失去其黏著特性)或其類似者，且可使用沈積製程、旋塗、列印製程、層壓製程或其類似製程形成黏合劑805。在一些實施例中，黏著劑805可具有多層結構且可包括離形層(未圖示)。離形層可有助於在完成分割製程之後自框架803安全地移除個別晶粒801。在一些實施例中，離形層可為UV類型，其中在將離形層曝光於UV輻射之後離形層之黏著強度實質上降低。在其他實施例中，離形層可為熱離形之態樣，其中在將離形層暴露於適合的熱源之後離形層之黏著強度實質上降低。在一些實施例中，可例如藉由鋸切、雷射切除、其組合或其類似者而將工件100單體化成個別晶粒801。
如圖8中所示，各積體電路晶粒801包括單個鈍化層(諸如鈍化層113)、單個緩衝層(諸如緩衝層201)、兩個接觸墊(諸如接觸墊111)、兩個導電柱(諸如導電柱501)以及單個保護層(諸如保護層701)。所屬領域中具通常知識者將認識到，鈍化層、緩衝層、接觸墊、導電柱以及保護層之數目僅出於示出目的而提供且並不用於限制本發明之範疇。在其他實施例中，各積體電路晶粒801可包括視積體電路晶粒801的設計要求而定的適當數目的鈍化層、緩衝層、接觸墊、導電柱以及保護層。
圖9至圖16是根據一些實施例在使用圖1至圖8中所製造的積體電路晶粒801來製造積體電路封裝期間的各種處理步驟之截面圖。首先參看圖9，在一些實施例中，於載體901上方形成離形層903，且於離形層903上方形成絕緣層905，以開始形成積體電路封裝。在一些實施例中，載體901可由石英、玻璃或其類似者形成，並為後續操作提供機械支撐。在一些實施例中，離形層903可包括光熱轉化(light to heat conversion；LTHC)材料、UV黏著劑、聚合物層或其類似者，且可使用旋塗式塗覆製程、列印製程、層壓製程或其類似製程形成離形層903。在離形層903由LTHC材料形成的一些實施例中，在暴露於光時離形層903部分地或完全地失去其黏著強度，且載體901可容易地自隨後形成的結構之背側移除。在一些實施例中，絕緣層905可使用類似於上文參看圖2所描述的緩衝層201的材料及方法形成，且出於簡潔起見在本文中不重複描述。
進一步參看圖9，使用黏著層907將積體電路晶粒801附接至絕緣層905。在一些實施例中，使用例如取放型設備將積體 電路晶粒801置放於絕緣層905上。在其他實施例中，可手動地或使用任何其他適合的方法將積體電路晶粒801置放於絕緣層905上。在一些實施例中，黏著層907可包括LTHC材料、UV黏著劑、晶粒附接膜或其類似者，且可使用旋塗式塗覆製程、列印製程、層壓製程或其類似製程形成黏著層907。
參看圖10，於絕緣層905上方以及積體電路晶粒801上方及周圍形成密封體1001。在一些實施例中，密封體1001可包括諸如聚苯并噁唑(PBO)、聚醯亞胺(PI)、苯并環丁烯(BCB)、其組合或其類似者的一或多個光可圖案化絕緣材料層，且可使用旋塗式塗覆製程或其類似方法形成密封體1001。在一些實施例中，圖案化密封體1001以在密封體1001中形成開口1003及開口1005。在一些實施例中，可使用適合的微影技術以使密封體1001暴露於光線而形成開口1003及開口1005。在曝光之後，顯影及/或固化密封體1001。在一些實施例中，開口1003延伸穿過密封體1001並暴露絕緣層905。在一些實施例中，開口1005暴露積體電路晶粒801之導電柱501。如下文更詳細地所描述，密封體穿孔形成於開口1003中，且重佈線層通孔形成於開口1005中(參見圖13)。
參看圖11，於密封體1001上方以及開口1003及開口1005中形成晶種層1101。在一些實施例中，可使用類似於上文參看圖3所描述的晶種層301的材料及方法形成晶種層1101，且出於簡潔起見在本文中不重複描述。在一些實施例中，晶種層1101的厚度可在約500埃與約1微米之間。在一些實施例中，晶種層1101可包括鈦層與形成於鈦層上方的銅層。在一些實施例中，鈦 層的厚度可在約100埃與約1000埃之間。在一些實施例中，銅層的厚度可在約300埃與約9000埃之間。
參看圖12，於密封體1001上方形成其中具有開口的圖案化罩幕1201。在一些實施例中，可使用類似於上文參看圖4所描述的圖案化罩幕401的材料及方法形成圖案化罩幕1201，且出於簡潔起見在本文中不重複描述。隨後，經由開口而將導電材料1203沈積於圖案化罩幕1201中。在一些實施例中，導電材料1203可包括銅、鎢、鋁、銀、金、其組合或其類似者，且可使用電化學鍍覆製程、無電式鍍覆製程、ALD、PVD、其組合或其類似製程形成。在一些實施例中，導電材料1203可完全填滿開口1005(參見圖11)。在一些實施例中，導電材料1203可部分地填充開口1003。在一些實施例中，導電材料1203以非保形(non-conformal)方式形成於開口1003中，使得安置於開口1003之底部上的導電材料1203之厚度T1大於安置於開口1003之側壁上的導電材料1203之厚度T2。在一些實施例中，厚度T2在約2微米與約10微米之間。在一些實施例中，厚度T1在約12微米與約60微米之間。在一些實施例中，開口1003之未填充部分的底部可在積體電路晶粒801之最頂部表面下方。在一些實施例中，開口1003之未填充部分的底部可在積體電路晶粒801之最頂部表面上方。在一些實施例中，開口1003之未填充部分的底部可與積體電路晶粒801之最頂部表面實質上齊平。
參看圖13，在形成導電材料1203之後，移除圖案化罩幕1201(參看圖12)。在一些實施例中，圖案化罩幕1201可使用類似於上文參看圖6所描述的圖案化罩幕401的方法移除，且出 於簡潔起見在本文中不重複描述。隨後，移除晶種層1101之暴露部分。在一些實施例中，晶種層1101之暴露部分可使用類似於上文參看圖6所描述的晶種層301之暴露部分的方法移除，且出於簡潔起見在本文中不重複描述。在一些實施例中，安置於開口1003中之晶種層1101及導電材料1203在積體電路晶粒801之最頂部表面下方的部分可稱為導通孔1301或密封體導通孔1301。在一些實施例中，晶種層1101及導電材料1203在積體電路晶粒801之最頂部表面上方的部分可稱為重佈線層(redistribution layer；RDL)1303。藉由在相同製程步驟中形成導通孔1301及RDL 1303，減少用於形成所得封裝之製程步驟數以及製造成本。如下文更詳細地所描述，連接件(諸如圖16中所示出的連接件1603)與導通孔1301之底部表面接觸形成。在導電材料1203保形地形成於開口1003中的一些實施例中，導電材料1203在開口1003之底部處的厚度可小於所要厚度，使得安置於開口1003之底部上的全部導電材料1203可被位於導通孔1301與連接件之間的界面處形成的金屬間化合物(intermetallic compound；IMC)耗盡，這可能會增加在導通孔1301與連接件之間的界面處形成裂痕的可能性。另一方面，藉由用導電材料1203完全填滿開口1003以在開口1003之底部處獲得所要厚度，導電材料1203的沈積時間(諸如鍍覆時間)可大於所要沈積時間，可增加生產成本並降低晶圓/小時(wafer-per-hour；WPH)產率。藉由非保形地形成具有如上文所描述的在開口1003之底部處之厚度T1的導通孔1301，導電材料1203可不被位於導通孔1301與連接件之間的界面處形成的IMC耗盡，且可減少導電材料1203的沈積時間。因此，可減小或排除在導通孔 1301與連接件之間的界面處形成裂痕的可能性，可減低生產成本，且可提高WPH產率。
參看圖14，於積體電路晶粒801及密封體1001上方形成重佈線結構1401。在一些實施例中，RDL 1303可為重佈線結構1401之第一RDL層。在一些實施例中，重佈線結構1401可更包括絕緣層14031至絕緣層14033，以及安置於絕緣層14031至絕緣層14033內的RDL 14051及RDL 14052(包括導電線以及通孔)。在一些實施例中，絕緣層14031至絕緣層14033可使用類似於上文參看圖2所描述的緩衝層201的材料及方法形成，且出於簡潔起見在本文中不重複描述。在一些實施例中，RDL 14051及RDL 14052可使用類似於上文參看圖13所描述的RDL 1303的材料及方法形成，且出於簡潔起見在本文中不重複描述。
進一步參看圖14，在一些實施例中，用於形成重佈線結構1401之製程步驟可包含圖案化絕緣層14031以使用類似於例如上文參看圖2所描述的緩衝層201的方法於其中形成開口，且出於簡潔起見在本文中不重複描述。RDL 14051形成於絕緣層14031上方及絕緣層14031中之開口中以接觸RDL 1303。RDL 14051可包括各種線/跡線(跨絕緣層14031之頂部表面「水平地」延行)及/或通孔(「豎直地」延伸至絕緣層14031中)。在一些實施例中，於絕緣層14031上方及絕緣層14031上方內的開口中沈積晶種層(未圖示)。可使用類似於上文參看圖3所描述的晶種層301的材料及方法形成晶種層，且出於簡潔起見在本文中不重複描述。隨後，於晶種層上方沈積圖案化罩幕(未圖示)，以定義RDL 14051的所要圖案。在一些實施例中，可使用類似於上文參看圖4所描述的圖 案化罩幕401的材料及方法形成其中具有開口的圖案化罩幕，且出於簡潔起見在本文中不重複描述。在一些實施例中，藉由電化學鍍覆製程、無電式鍍覆製程、ALD、PVD、其組合或其類似製程於晶種層上形成導電材料。隨後，移除圖案化罩幕，且亦移除在移除圖案化罩幕之後晶種層的暴露部分。在一些實施例中，可使用類似於上文參看圖6所描述的圖案化罩幕401的方法移除圖案化罩幕，且出於簡潔起見在本文中不重複描述。在一些實施例中，可使用類似於上文參看圖6所描述的晶種層301之暴露部分的方法移除晶種層之暴露部分，且出於簡潔起見在本文中不重複描述。
進一步參看圖14，於絕緣層14031及RDL 14051上方形成絕緣層14032、RDL 14052以及絕緣層14033，以完成重佈線結構1401之形成。在一些實施例中，可使用類似於RDL 14051的方法於絕緣層14032上方形成RDL 14052，且出於簡潔起見在本文中不重複描述。在一些實施例中，RDL 14052延伸穿過絕緣層14032並與RDL 14051的一部分接觸。
如圖14中所示，重佈線結構1401包括三個RDL(諸如RDL 1303、RDL 14051以及RDL 14052)。所屬領域中具通常知識者將認識到，RDL之數目僅出於示出目的而提供且並不用於限制本發明之範疇。在其他實施例中，重佈線結構1401可包括視所得封裝元件的設計要求而定的適當數目的RDL。
進一步參看圖14，於重佈線結構1401上方形成凸塊下金屬化物(underbump metallization；UBM)1407，且將UBM 1407電耦合至重佈線結構1401。在一些實施例中，一組開口可形成穿過絕緣層14033以暴露RDL 14052之一部分。在一些實施例中， UBM 1407可包含多個導電材料層，諸如鈦層、銅層以及鎳層。然而，於本領域具有通常知識者將認識到，存在有適合於形成UBM 1407的許多適合的材料及層的配置，諸如鉻/鉻銅合金/銅/金之配置、鈦/鈦鎢/銅之配置、或銅/鎳/金之配置。可用於UBM 1407之任何適合的材料或材料層全部意欲包含於當前申請案的範疇內。在一些實施例中，於UBM 1407中之一些上方形成連接件1409，且將連接件1409電耦合至對應的UBM 1407。在一些實施例中，連接件1409可為焊料球、受控塌陷晶粒連接(C4)凸塊、球柵陣列封裝(ball grid array；BGA)球、微型凸塊、化學鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)形成之凸塊，或其類似者。在連接件1409由焊料材料形成的一些實施例中，可執行回焊製程以便使焊料材料成形為所要凸塊形狀。在其他實施例中，連接件1409可為導電柱，所述導電柱可使用類似於上文參看圖5所描述的導電柱501的材料及方法形成，且出於簡潔起見在本文中不重複描述。在連接件1409包括導電柱的一些實施例中，連接件1409可更包括可形成於導電柱之頂部上的頂蓋層。在一些實施例中，頂蓋層可包括焊料、鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似者、其組合或其類似者，且可使用電化學鍍覆製程、無電式鍍覆製程或其類似製程形成。
進一步參看圖14，將積體電路晶粒1411安裝於重佈線結構1401上方且電耦合至重佈線結構1401。在一些實施例中，使用連接件1413將積體電路晶粒1411附接至UBM 1407。在一些實施例中，可使用類似於連接件1409的材料及方法形成連接件 1413，且出於簡潔起見在本文中不重複描述。在一些實施例中，積體電路晶粒1411可為分離的(discrete)半導體元件晶片，諸如表面安裝元件(surface mount device；SMD)、積體被動元件(integrated passive device；IPD)或其類似者。
參看圖15，於重佈線結構1401上方形成連接件1409以及將積體電路晶粒1411附接至重佈線結構1401之後，所得結構藉由框架1503附接至膠帶1501，使得連接件1409接觸膠帶1501。在一些實施例中，膠帶1501可包括晶粒附接膜、分割膠帶或其類似者。隨後，脫離載體901(參看圖14)與所得結構，以暴露絕緣層905。隨後，可分割所得結構以形成個別積體電路封裝1500。在一些實施例中，所得結構可藉由鋸切、雷射切除方法、其組合或其類似者而分割。隨後，可測試積體電路封裝1500中之各者以識別已知良好封裝件(known good package；KGP)以供進一步處理。
參看圖16，在一些實施例中，藉由延伸穿過絕緣層905中之開口的一組連接件1603而將工件1601結合至積體電路封裝1500，以形成堆疊半導體元件1600。在一些實施例中，可使用例如雷射切除方法形成絕緣層905中之開口。在絕緣層905由光可圖案化材料形成的一些實施例中，可使用微影方法形成開口。在一些實施例中，工件1601可為封裝件、一或多個晶粒、印刷電路板(printed circuit board；PCB)、封裝基底、***件或其類似者。在工件1601為封裝件的一些實施例中，堆疊半導體元件1600為疊層封裝(PoP)元件。在工件1601為晶粒的其他實施例中，堆疊半導體元件1600為晶片封裝(CoP)元件。在一些實施例中，可使用類似於上文參看圖14所描述的連接件1409的材料及方法形 成連接件1603，且出於簡潔起見在本文中不重複描述。在其他實施例中，工件1601可在上文參看圖15所描述的分割製程之前結合至積體電路封裝1500。
進一步參看圖16，可在工件1601與積體電路封裝1500之間的空間中注入底填充料1605，或者可將底填充料1605形成於所述空間中且包圍連接件1603。底填充料1605可例如為在結構之間分配且隨後經固化而硬化的流體環氧樹脂、可變形凝膠、矽橡膠或其類似者。底填充料1605可尤其用於降低對連接件1603之損害，且保護連接件1603。在一些實施例中，底填充料1605及密封體1001可包括相同材料。在其他實施例中，底填充料1605及密封體1001可包括不同材料。
參看圖17，在一些實施例中，在使載體901脫離之後以及在如上文參看圖15所描述的分割製程之前，於絕緣層905上方形成重佈線結構1701。在一些實施例中，絕緣層905可為重佈線結構1701之第一絕緣層。在所示出的實施例中，重佈線結構1701更包括絕緣層17031及絕緣層17032以及RDL 17051及RDL 17052。在一些實施例中，可使用類似於上文參看圖2所描述的緩衝層201的材料及方法形成絕緣層17031及絕緣層17033，且出於簡潔起見在本文中不重複描述。在一些實施例中，可使用類似於上文參看圖13所描述的RDL 1303的材料及方法形成RDL 17051及RDL 17052，且出於簡潔起見在本文中不重複描述。在一些實施例中，可使用類似於上文參看圖14所描述的重佈線結構1401的方法形成重佈線結構1701，且出於簡潔起見在本文中不重複描述。所屬領域中具通常知識者將認識到，RDL及絕緣層之數目僅出於說明目的而提 供且並不用以限制本發明之範疇。在其他實施例中，重佈線結構1701可包括視所得封裝元件的設計要求而定的適當數目的RDL及絕緣層。
進一步參看圖17，在一些實施例中，在形成重佈線結構1701之後，將所得結構附接至由框架1503支撐的膠帶1501，使得連接件與1409膠帶1501接觸。隨後，可分割所得結構以形成個別積體電路封裝1700。在一些實施例中，所得結構可藉由鋸切、雷射切除方法、其組合或其類似者而分割。隨後，可測試積體電路封裝1700中之各者以識別已知良好封裝件(KGP)以供進一步處理。
參看圖18，在一些實施例中，藉由延伸穿過絕緣層17032中之開口的一組連接件1603而將工件1601結合至積體電路封裝1700，以形成堆疊半導體元件1800。在一些實施例中，堆疊半導體元件1800類似於堆疊半導體元件1600，其中相同元件使用相同數字參考標註。在一些實施例中，可使用類似於上文參看圖16所描述的堆疊半導體元件1600的方法形成堆疊半導體元件1800，且出於簡潔起見在本文中不重複描述。
參看圖19，在一些實施例中，於載體901上方形成絕緣層905之後以及在附接如上文參看圖9所描述的積體電路晶粒801之前，於載體901上方形成重佈線結構1901。在一些實施例中，在形成重佈線結構1901之後，可執行上文參看圖9至圖14所描述的製程步驟以形成圖19中所示出的結構。在一些實施例中，絕緣層905可為重佈線結構1901之第一絕緣層。在所示出的實施例中，重佈線結構1901更包括絕緣層19031及絕緣層19032以及RDL 19051及RDL 19052。在一些實施例中，可使用類似於上文參看圖2所描述的緩衝層201的材料及方法形成絕緣層19031及絕緣層19033，且出於簡潔起見在本文中不重複描述。在一些實施例中，可使用類似於上文參看圖13所描述的RDL 1303的材料及方法形成RDL 19051及RDL 19052，且出於簡潔起見在本文中不重複描述。在一些實施例中，可使用類似於上文參看圖14所描述的重佈線結構1401的方法形成重佈線結構1901，且出於簡潔起見在本文中不重複描述。所屬領域中具通常知識者將認識到，RDL及絕緣層之數目僅出於說明目的而提供且並不限制本發明之範疇。在其他實施例中，重佈線結構1901可包括視所得封裝元件的設計要求而定的適當數目的RDL及絕緣層。隨後，可分割所得結構以形成個別積體電路封裝1900。在一些實施例中，所得結構可藉由鋸切、雷射切除方法、其組合或其類似者而分割。隨後，可測試積體電路封裝1900中之各者以識別已知良好封裝體(KGP)以供進一步處理。
參看圖20，在一些實施例中，藉由延伸穿過絕緣層905中之開口的一組連接件1603而將工件1601結合至積體電路封裝1900，以形成堆疊半導體元件2000。在一些實施例中，堆疊半導體元件2000類似於堆疊半導體元件1600，其中相同元件使用相同數字參考標註。在一些實施例中，可使用類似於上文參看圖16所描述的堆疊半導體元件1600的方法形成堆疊半導體元件2000，且出於簡潔起見在本文中不重複描述。
圖21根據一些實施例示出形成積體電路封裝的方法2100的流程圖。在一些實施例中，方法2100開始於步驟2103， 其中積體電路晶粒(諸如圖9中所示出的積體電路晶粒801)附接於載體(諸如圖9中所示出的載體901)上方，如上文參看圖9所描述。在步驟2105中，於積體電路晶粒上方及周圍形成密封體(諸如圖10中所示出的密封體1001)，如上文參看圖10所描述。在步驟2107中，圖案化密封體以形成延伸穿過密封體的第一開口(諸如圖10中所示出的開口1003)以及暴露積體電路晶粒的一部分之第二開口(諸如圖10中所示出的開口1005)，如上文參看圖10所描述。在步驟2109中，同時於第一開口及第二開口中沈積導電材料(諸如圖12中所示出的導電材料1203)，如上文參看圖12所描述。在步驟2111中，移除載體，如上文參看圖15所描述。在替代實施例中，在執行步驟2103之前，執行步驟2101，其中於載體上方形成重佈線結構(諸如圖19中所示出的重佈線結構1901)，如上文參看圖19所描述。在另一些其他替代實施例中，在執行步驟2111之後，執行步驟2113，其中形成重佈線結構(諸如圖17中所示出的重佈線結構1701)，如上文參看圖17所描述。
根據一實施例，一種積體電路的形成方法包含：將積體電路晶粒之第一側附接至載體；於積體電路晶粒上方及周圍形成密封體；圖案化密封體以形成與積體電路晶粒橫向間隔開的第一開口以及積體電路晶粒上方的第二開口，第一開口延伸穿過密封體，第二開口暴露積體電路晶粒之第二側，積體電路晶粒之第一側與積體電路晶粒之第二側相對；以及同時於第一開口及第二開口中沈積導電材料。在一實施例中，積體電路的形成方法更包含：在將積體電路晶粒附接至載體之前，在載體上方形成重佈線結構。在一實施例中，所述積體電路的形成方法更包含：自積體電路晶粒之 第一側移除載體；以及在積體電路晶粒之第一側上方形成重佈線結構。在一實施例中，導電材料部分地填充第一開口。在一實施例中，導電材料在第一開口之底部上方的厚度大於導電材料沿第一開口之側壁的厚度。在一實施例中，導電材料填滿(overfill)第二開口。在一實施例中，所述積體電路的形成方法更包含：同時於第一開口及第二開口中沈積導電材料之後，於第一開口中沈積絕緣材料，絕緣材料填滿第一開口。
根據另一實施例，一種積體電路的形成方法包含：將積體電路晶粒之第一側附接至載體，積體電路晶粒之第二側具有接觸墊，積體電路晶粒之第一側與積體電路晶粒之第二側相對；於積體電路晶粒上方及周圍形成密封體；以及同時於密封體中形成導通孔及第一重佈線層，導通孔與積體電路晶粒之側壁橫向間隔開，導通孔之頂部表面在密封體之最頂部表面下方，第一重佈線層在積體電路晶粒之第二側上方，第一重佈線層與接觸墊電接觸。在一實施例中，所述積體電路的形成方法更包含：在將積體電路晶粒附接至載體之前，在載體上方形成第二佈線層。在一實施例中，所述積體電路的形成方法更包含：使載體自積體電路晶粒之第一側脫離；以及在積體電路晶粒之第一側上方形成第二重佈線層。在一實施例中，同時於密封體中形成導通孔及第一重佈線層包含：圖案化密封體以在密封體中形成第一開口及第二開口，第一開口延伸穿過密封體，第二開口暴露積體電路晶粒之第二側；以及同時於第一開口及第二開口中非保形地沈積導電材料。在一實施例中，導電材料在第一開口之底部上方的厚度大於導電材料沿第一開口之側壁的厚度。在一實施例中，導電材料在第一開口之底部上方的厚度小 於積體電路晶粒之高度。在一實施例中，密封體包括光可圖案化絕緣材料。
根據又一實施例，一種積體電路包含：積體電路晶粒；密封體，沿積體電路晶粒之側壁及最頂部表面延伸；導通孔，在密封體中，所述導通孔與積體電路晶粒之側壁間隔開；以及導通孔上方的絕緣層。在一實施例中，導通孔包含：沿絕緣層之底部表面延伸的第一部分；以及沿絕緣層之側壁延伸的第二部分，第一部分之高度大於第二部分之寬度。在一實施例中，所述結構更包含位於密封體之最頂部表面上方的重佈線層，重佈線層的至少一部分延伸至密封體中並與導通孔接觸。在一實施例中，導通孔之最底部表面與密封體之最底部表面實質上齊平。在一實施例中，絕緣層的至少一部分在密封體的最頂部表面下方。在一實施例中，導通孔與絕緣層之間的界面在積體電路晶粒的最頂部表面下方。在一實施例中，密封體包括光可圖案化絕緣材料。
亦可包含其他特徵及製程。舉例而言，可包含測試結構以幫助對3D封裝或3DIC元件之驗證測試。測試結構可包含例如形成於重佈線層中或基底上的測試墊，從而允許測試3D封裝或3DIC、使用探測器及/或探測卡及其類似者。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合併有對已知良好晶粒的中間驗證的測試方法使用，以提高產率及降低成本。
前文概述若干實施例的特徵，使得所屬領域中具通常知識者可更好地理解本發明的態樣。所屬領域中具通常知識者應理解，其可易於使用本發明作為設計或修改用於實現本文中所引入 之實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本發明的精神及範疇，且其可在不脫離本發明的精神及範疇的情況下在本文中進行各種改變、替代以及更改。
501‧‧‧導電柱
801‧‧‧積體電路晶粒
901‧‧‧載體
903‧‧‧離形層
905‧‧‧絕緣層
907‧‧‧黏著層
1001‧‧‧密封體
1003‧‧‧開口
1101‧‧‧晶種層
1201‧‧‧圖案化罩幕
1203‧‧‧導電材料
T1、T2‧‧‧厚度

Claims (14)

  1. 一種積體電路的形成方法，包括：將積體電路晶粒之第一側附接至載體；於所述積體電路晶粒上方及周圍形成密封體；圖案化所述密封體以形成與所述積體電路晶粒橫向間隔開的第一開口以及所述積體電路晶粒上方的第二開口，所述第一開口延伸穿過所述密封體，所述第二開口暴露所述積體電路晶粒之第二側，所述積體電路晶粒之所述第一側與所述積體電路晶粒之所述第二側相對；同時於所述第一開口及所述第二開口中沈積導電材料；以及自所述積體電路晶粒之所述第一側移除所述載體。
  2. 如申請專利範圍第1項所述的積體電路的形成方法，更包括：在將所述積體電路晶粒附接至所述載體之前，在所述載體上方形成重佈線結構。
  3. 如申請專利範圍第1項所述的積體電路的形成方法，在將所述載體自所述積體電路晶粒之所述第一側移除之後，更包括：在所述積體電路晶粒之所述第一側上方形成重佈線結構。
  4. 如申請專利範圍第1項所述的積體電路的形成方法，其中所述導電材料部分地填充所述第一開口；或其中所述導電材料填滿所述第二開口。
  5. 如申請專利範圍第4項所述的積體電路的形成方法，其中所述導電材料在所述第一開口之底部上方的厚度大於所述導電材料沿所述第一開口之側壁的厚度。
  6. 如申請專利範圍第1項所述的積體電路的形成方法，更 包括：同時於所述第一開口及所述第二開口中沈積所述導電材料之後，於所述第一開口中沈積絕緣材料，所述絕緣材料填滿所述第一開口。
  7. 一種積體電路的形成方法，包括：將積體電路晶粒之第一側附接至載體，所述積體電路晶粒之第二側具有接觸墊，所述積體電路晶粒之所述第一側與所述積體電路晶粒之所述第二側相對；於所述積體電路晶粒上方及周圍形成密封體；同時於所述密封體中形成導通孔及第一重佈線層，所述導通孔與所述積體電路晶粒之側壁橫向間隔開，所述導通孔之頂部表面在所述密封體之最頂部表面下方，所述第一重佈線層在所述積體電路晶粒之所述第二側上方，所述第一重佈線層與所述接觸墊電接觸；以及自所述積體電路晶粒之所述第一側移除所述載體。
  8. 如申請專利範圍第7項所述的積體電路的形成方法，其中同時於所述密封體中形成所述導通孔及所述第一重佈線層包括：圖案化所述密封體以在所述密封體中形成第一開口及第二開口，所述第一開口延伸穿過所述密封體，所述第二開口暴露所述積體電路晶粒之所述第二側；以及同時於所述第一開口及所述第二開口中非保形地沈積導電材料。
  9. 如申請專利範圍第8項所述的積體電路的形成方法，其中所述導電材料在所述第一開口之底部上方的厚度小於所述積體 電路晶粒之高度。
  10. 一種積體電路，包括：積體電路晶粒，附接於背側絕緣層上，其中所述積體電路晶粒具有導電柱以及側向環繞所述導電柱的保護層，其中所述導電柱與所述保護層的頂部表面構成所述積體電路晶粒的最頂部表面，且其中所述保護層包括光可圖案化絕緣材料；密封體，設置於所述背側絕緣層上，且沿所述積體電路晶粒之側壁及所述最頂部表面延伸，其中所述密封體包括光可圖案化絕緣材料，且所述密封體實體接觸所述積體電路晶粒的所述最頂部表面；導通孔，在所述密封體中，所述導通孔與所述積體電路晶粒之側壁間隔開；以及絕緣層，在所述導通孔上方，其中所述導通孔包括：第一部分，沿所述絕緣層之底部表面延伸，且實體接觸於所述背側絕緣層與所述絕緣層之間；以及第二部分，沿所述絕緣層之側壁延伸，所述第一部分之高度大於所述第二部分之寬度。
  11. 如申請專利範圍第10項所述的積體電路，更包括重佈線層，位於所述密封體之最頂部表面上方，所述重佈線層之至少一部分延伸至所述密封體中並接觸所述導通孔。
  12. 如申請專利範圍第10項所述的積體電路，其中所述導通孔之最底部表面與所述密封體之最底部表面實質上齊平。
  13. 如申請專利範圍第10項所述的積體電路，其中所述絕緣層之至少一部分在所述密封體之最頂部表面下方。
  14. 如申請專利範圍第10項所述的積體電路，其中所述導通孔與所述絕緣層之間的界面在所述積體電路晶粒之所述最頂部表面下方。
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