TWI713092B

TWI713092B - Semiconductor structure and method for fabricating the same

Info

Publication number: TWI713092B
Application number: TW107137350A
Authority: TW
Inventors: 李芳名; 傅勝威; 李宗曄
Original assignee: 世界先進積體電路股份有限公司
Priority date: 2018-10-23
Filing date: 2018-10-23
Publication date: 2020-12-11
Also published as: TW202016997A

Abstract

In some embodiments, a semiconductor structure includes a substrate, an epitaxial layer disposed on the substrate, a conductive feature disposed in the epitaxial layer, and a diffusion barrier layer disposed on sidewalls of the conductive feature. The conductive feature has a protruding portion higher than the epitaxial layer.

Description

半導體結構及其製造方法 Semiconductor structure and manufacturing method thereof

本發明是關於半導體技術，特別是有關於具有導電部件的半導體裝置。 The present invention relates to semiconductor technology, in particular to semiconductor devices having conductive components.

由於橫向擴散金屬氧化物半導體(Laterally Diffused Metal Oxide Semiconductor，LDMOS)具有高操作效率及良好的增益特性及易於與其它電路整合的優點，故橫向擴散金屬氧化物半導體已成為各種電子產品經常選用的半導體元件。 Since Laterally Diffused Metal Oxide Semiconductor (LDMOS) has the advantages of high operating efficiency, good gain characteristics and easy integration with other circuits, laterally diffused metal oxide semiconductors have become the most commonly used semiconductor for various electronic products. element.

然而，由於橫向擴散金屬氧化物半導體具有連接源極與基底導電端之導電部件，當進行後續製程(例如高溫熱製程)時，經常造成導電部件中的摻質擴散至周遭元件，使橫向擴散金屬氧化物半導體的電性變差。此外，當橫向擴散金屬氧化物半導體的尺寸縮小時，導電部件的摻質之擴散造成的影響更顯著，如此便限制橫向擴散金屬氧化物半導體的尺寸縮之極限，造成無法降低源極-汲極電阻值(R_DSON)，導致不能進一步改善橫向擴散金屬氧化物半導體的性能。 However, because laterally diffused metal oxide semiconductors have conductive components connecting the source and the conductive ends of the substrate, when subsequent processes (such as high-temperature thermal processes) are performed, the dopants in the conductive components often diffuse to surrounding components, causing the lateral diffusion The electrical properties of the metal oxide semiconductor deteriorate. In addition, when the size of the laterally diffused metal oxide semiconductor is reduced, the influence caused by the diffusion of the conductive components is more significant, which limits the size of the laterally diffused metal oxide semiconductor to the limit, resulting in the inability to reduce the source-drain The resistance value (R _DSON ) results in the inability to further improve the performance of the laterally diffused metal oxide semiconductor.

因此，雖然現有的橫向擴散金屬氧化物半導體(LDMOS)已大致符合需求，但仍然存在許多問題，因此如何改善現有的橫向擴散金屬氧化物半導體已成為目前業界相當重視的課題之一。 Therefore, although the existing laterally diffused metal oxide semiconductor (LDMOS) has roughly met the demand, there are still many problems, so how Improving the existing laterally diffused metal oxide semiconductor has become one of the issues that the industry attaches great importance to.

本發明的一些實施例提供半導體結構，此結構可包括：基底；設置於基底上的磊晶層；設置於磊晶層中的導電部件，且導電部件具有高於磊晶層的突出部；以及設置於導電部件的複數個側壁上的擴散阻障層。在一實施例中，突出部的寬度大於在磊晶層中之導電部件的寬度。在一實施例中，突出部覆蓋擴散阻障層之頂表面。在一實施例中，擴散阻障層包括一或多個介電阻障層。在一實施例中，擴散阻障層包括一阻障氧化層及在阻障氧化層上之阻障氮化層。 Some embodiments of the present invention provide a semiconductor structure, the structure may include: a substrate; an epitaxial layer disposed on the substrate; a conductive component disposed in the epitaxial layer, and the conductive component has a protrusion higher than the epitaxial layer; and Diffusion barrier layers arranged on a plurality of sidewalls of the conductive component. In one embodiment, the width of the protrusion is greater than the width of the conductive component in the epitaxial layer. In one embodiment, the protrusion covers the top surface of the diffusion barrier layer. In one embodiment, the diffusion barrier layer includes one or more dielectric resistance barrier layers. In one embodiment, the diffusion barrier layer includes a barrier oxide layer and a barrier nitride layer on the barrier oxide layer.

在一實施例中，半導體結構可更包括：設置於磊晶層中的源極區，其中擴散阻障層接觸源極區且分隔源極區及導電部件。在一實施例中，導電部件設置於兩個橫向擴散金屬氧化物半導體(LDMOS)之間，且導電部件穿過橫向擴散金屬氧化物半導體之一共同源極。 In one embodiment, the semiconductor structure may further include a source region disposed in the epitaxial layer, wherein the diffusion barrier layer contacts the source region and separates the source region and the conductive component. In one embodiment, the conductive member is disposed between two laterally diffused metal oxide semiconductors (LDMOS), and the conductive member passes through a common source electrode of the laterally diffused metal oxide semiconductor.

本發明的一些實施例提供半導體結構的製造方法，此方法可包括：提供基底；於基底上形成磊晶層；於磊晶層上形成遮罩結構，遮罩結構具有開口，其露出部分磊晶層；使用遮罩結構作為蝕刻遮罩，以移除露出之磊晶層而形成溝槽；於溝槽的複數個側壁上形成擴散阻障層；於溝槽中形成導電部件，導電部件具有高於磊晶層的突出部；以及移除遮罩結構。 Some embodiments of the present invention provide a method for manufacturing a semiconductor structure. The method may include: providing a substrate; forming an epitaxial layer on the substrate; forming a mask structure on the epitaxial layer, the mask structure having an opening that exposes part of the epitaxial layer Layer; use the mask structure as an etching mask to remove the exposed epitaxial layer to form a trench; form a diffusion barrier layer on a plurality of sidewalls of the trench; form a conductive component in the trench, the conductive component has a high On the protrusion of the epitaxial layer; and removing the mask structure.

在一實施例中，突出部的寬度大於在溝槽中之導電部件的寬度。在一實施例中，突出部覆蓋擴散阻障層之頂表面。在一實施例中，遮罩結構包括一或多個介電層。在一實施例中，遮罩結構包括第一氧化層及形成於第一氧化層上的氮化層。在一實施例中，遮罩結構更包括形成於氮化層上的第二氧化層。在一實施例中，遮罩結構為多個介電層，且遮罩結構的移除包括：先移除部份遮罩結構並保留最接近磊晶層的一層介電層；以及在移除部分遮罩結構之後，移除剩餘的遮罩結構。 In one embodiment, the width of the protrusion is greater than the guide in the groove The width of the electrical component. In one embodiment, the protrusion covers the top surface of the diffusion barrier layer. In one embodiment, the mask structure includes one or more dielectric layers. In one embodiment, the mask structure includes a first oxide layer and a nitride layer formed on the first oxide layer. In one embodiment, the mask structure further includes a second oxide layer formed on the nitride layer. In one embodiment, the mask structure is a plurality of dielectric layers, and the removal of the mask structure includes: first removing part of the mask structure and leaving the dielectric layer closest to the epitaxial layer; and removing After the partial mask structure, remove the remaining mask structure.

在一實施例中，擴散阻障層包括一或多個介電阻障層。在一實施例中，擴散阻障層包括阻障氧化層及形成於阻障氧化層上之阻障氮化層。在一實施例中，半導體結構的製造方法，更包括：於磊晶層中形成源極區，擴散阻障層接觸源極區且分隔源極區及導電部件。在一實施例中，導電部件形成於兩個橫向擴散金屬氧化物半導體(LDMOS)之間，且導電部件穿過橫向擴散金屬氧化物半導體之共同源極。 In one embodiment, the diffusion barrier layer includes one or more dielectric resistance barrier layers. In one embodiment, the diffusion barrier layer includes a barrier oxide layer and a barrier nitride layer formed on the barrier oxide layer. In one embodiment, the manufacturing method of the semiconductor structure further includes: forming a source region in the epitaxial layer, and the diffusion barrier layer contacts the source region and separates the source region and the conductive component. In one embodiment, the conductive member is formed between two laterally diffused metal oxide semiconductors (LDMOS), and the conductive member passes through the common source of the laterally diffused metal oxide semiconductor.

100‧‧‧半導體結構 100‧‧‧Semiconductor structure

10‧‧‧基底 10‧‧‧Base

12‧‧‧磊晶層 12‧‧‧Epitaxial layer

14‧‧‧遮罩結構 14‧‧‧Mask structure

15‧‧‧開口 15‧‧‧Open

16a、16b‧‧‧第一氧化層 16a、16b‧‧‧First oxide layer

18‧‧‧溝槽 18‧‧‧Groove

20‧‧‧擴散阻障層 20‧‧‧Diffusion barrier

22‧‧‧阻障氧化層 22‧‧‧Barrier oxide layer

24‧‧‧阻障氮化層 24‧‧‧Barrier nitride layer

26‧‧‧導電材料 26‧‧‧Conductive material

28‧‧‧導電部件 28‧‧‧Conductive parts

30‧‧‧突出部 30‧‧‧Protrusion

32a、32b‧‧‧氮化層 32a, 32b‧‧‧Nitriding layer

34‧‧‧第二氧化層 34‧‧‧Second oxide layer

36‧‧‧接觸摻雜區 36‧‧‧Contact doped area

38‧‧‧第一井區 38‧‧‧The first well area

40‧‧‧源極區 40‧‧‧Source area

42‧‧‧第二井區 42‧‧‧Second Well Area

44‧‧‧汲極區 44‧‧‧Dip pole area

46‧‧‧閘極結構 46‧‧‧Gate structure

48‧‧‧閘極介電層 48‧‧‧Gate Dielectric Layer

50‧‧‧閘極電極 50‧‧‧Gate electrode

52‧‧‧閘極矽化層 52‧‧‧Gate Silica Layer

54‧‧‧間隔物 54‧‧‧Spacer

55‧‧‧絕緣層 55‧‧‧Insulation layer

56‧‧‧導電層 56‧‧‧Conductive layer

58‧‧‧層間介電層 58‧‧‧Interlayer dielectric layer

60‧‧‧接觸插塞 60‧‧‧Contact plug

62‧‧‧導電部件 62‧‧‧Conductive parts

S1、S2‧‧‧側壁 S1, S2‧‧‧ side wall

藉由以下的詳細描述配合所附圖式，可以更加理解本發明實施例的內容。需強調的是，根據產業上的標準慣例，許多部件(feature)並未按照比例繪製。事實上，為了能清楚地討論，各種部件的尺寸可能被任意地增加或減少。 The content of the embodiments of the present invention can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be emphasized that according to industry standard practices, many features are not drawn to scale. In fact, in order to be able to discuss clearly, the size of various components may be arbitrarily increased or decreased.

第1-15圖是根據本發明的一些實施例之形成半導體結構之不同階段的剖面圖，其中第8-10圖是一些實施例之移除遮罩結構之不同階段的剖面圖，第11-13圖是另一些實施例之移除遮罩結構之不同階段的剖面圖。 Figures 1-15 are cross-sectional views at different stages of forming a semiconductor structure according to some embodiments of the present invention. Figures 8-10 are cross-sectional views at different stages of removing the mask structure of some embodiments, and Figures 11- FIG. 13 is a cross-sectional view of other embodiments at different stages of removing the mask structure.

以下內容提供了很多不同的實施例或範例，用於實施本發明實施例的不同部件。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例來說，敘述中若提及第一部件形成於第二部件之上，可能包含第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。另外，本發明實施例可能在許多範例中重複元件符號及/或字母。這些重複是為了簡化和清楚的目的，其本身並非代表所討論各種實施例及/或配置之間有特定的關係。 The following content provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first part is formed on the second part, it may include an embodiment where the first and second parts are in direct contact, or may include additional parts formed between the first and second parts. , So that the first and second components do not directly contact an embodiment. In addition, the embodiment of the present invention may repeat component symbols and/or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed.

再者，此處可能使用空間上的相對用語，例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」和其他類似的用語可用於此，以便描述如圖所示之一元件或部件與其他元件或部件之間的關係。此空間上的相關用語除了包含圖式繪示的方位外，也包含使用或操作中的裝置的不同方位。當裝置被轉至其他方位時(旋轉90度或其他方位)，則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。 Furthermore, relative terms in space may be used here, such as "below", "below", "below", "above", "above" and other similar terms It can be used here to describe the relationship between one element or component and other elements or components as shown in the figure. The related terms in this space include not only the orientation shown in the diagram, but also the different orientations of the device in use or operation. When the device is turned to another orientation (rotated by 90 degrees or other orientations), the relative description of the space used here can also be interpreted according to the rotated orientation.

第1-7圖及第14-15圖是根據本發明的一些實施例之形成第15圖所示之半導體結構100之不同階段的圖式。請先參照第1圖，在本實施例中，提供基底10。基底10可包括矽或其他半導體材料，或者，基底10可包含其他元素半導體材料，例如鍺(Ge)。在一些實施例中，基底10可包括化合物半導體製成，例如碳化矽、氮化鎵、砷化鎵、砷化銦或磷化銦。在一些實施例中，基底10由合金半導體製成，例如矽鍺、碳化矽鍺、磷化砷鎵或磷化銦鎵。在本實施例中，基底10可為P型基底。在一些實施例中，基底10摻雜有摻質，摻質可以是或包括硼、鎵、銦、鋁或其組合。 FIGS. 1-7 and 14-15 are diagrams of different stages of forming the semiconductor structure 100 shown in FIG. 15 according to some embodiments of the present invention. Please refer to FIG. 1 first. In this embodiment, a substrate 10 is provided. The substrate 10 may include silicon or other semiconductor materials, or the substrate 10 may include other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the substrate 10 may include a compound half The conductor is made of, for example, silicon carbide, gallium nitride, gallium arsenide, indium arsenide or indium phosphide. In some embodiments, the substrate 10 is made of alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. In this embodiment, the substrate 10 may be a P-type substrate. In some embodiments, the substrate 10 is doped with dopants, and the dopants may be or include boron, gallium, indium, aluminum, or a combination thereof.

隨後，於基底10上形成磊晶層12。在一些實施例中，磊晶層12的形成包括使用磊晶成長(epitaxial growth)製程在基底10上形成磊晶層12。在本實施例中，磊晶層12可為P型。在一些實施例中，磊晶成長製程可例如為金屬有機物化學氣相沉積法(metal organic chemical vapor deposition，MOCVD)、電漿增強化學氣相沉積法(plasma-enhanced CVD，PECVD)、分子束磊晶法(molecular beam epitaxy，MBE)、氫化物氣相磊晶法(hydride vapour phase epitaxy，HVPE)、液相磊晶法(liquid phase epitaxy，LPE)、氯化物氣相磊晶法(Cl-VPE)、其他相似的製程方法或前述之組合。 Subsequently, an epitaxial layer 12 is formed on the substrate 10. In some embodiments, the formation of the epitaxial layer 12 includes using an epitaxial growth process to form the epitaxial layer 12 on the substrate 10. In this embodiment, the epitaxial layer 12 may be P-type. In some embodiments, the epitaxial growth process may be, for example, metal organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (plasma-enhanced CVD, PECVD), molecular beam epitaxy Crystallization method (molecular beam epitaxy, MBE), hydride vapour phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE) ), other similar manufacturing methods or a combination of the foregoing.

接著，於磊晶層12上形成遮罩結構14，遮罩結構14具有開口15，其露出部分磊晶層12。在一些實施例中，遮罩結構14包括一或多個介電層。在本實施例中，遮罩結構14為第一氧化層。第一氧化層的厚度例如是約2000埃至約5000埃。第一氧化層之材料可以是或包括二氧化矽或其他適合的氧化物。可利用例如熱氧化法(thermal oxidation)、化學氣相沉積法(chemical vapor deposition，CVD)、原子層化學氣相沉積法(atomic layer deposition，ALD)或相似製程形成第一氧化層。在一些實施例中，遮罩結構14的形成包括於磊晶層12上形成遮罩材料，然後圖案化遮罩材料以形成遮罩結構14。 Next, a mask structure 14 is formed on the epitaxial layer 12. The mask structure 14 has an opening 15 that exposes a part of the epitaxial layer 12. In some embodiments, the mask structure 14 includes one or more dielectric layers. In this embodiment, the mask structure 14 is a first oxide layer. The thickness of the first oxide layer is, for example, about 2000 angstroms to about 5000 angstroms. The material of the first oxide layer can be or include silicon dioxide or other suitable oxides. The first oxide layer may be formed by, for example, thermal oxidation, chemical vapor deposition (CVD), atomic layer chemical vapor deposition (ALD) or similar processes. In some embodiments, the formation of the mask structure 14 includes on the epitaxial layer 12 The mask material is formed, and then the mask material is patterned to form the mask structure 14.

請參照第2圖，使用遮罩結構14作為蝕刻遮罩，以通過開口15移除露出之磊晶層12而形成溝槽18。溝槽18的深度例如是約1.5μm至約1.9μm。移除露出之磊晶層12的步驟可包括使用乾式蝕刻、濕式蝕刻或上述之組合進行蝕刻製程。濕式蝕刻可包括浸洗蝕刻、噴洗蝕刻、上述之組合或其他合適之製程。乾式蝕刻可包括電容耦合電漿蝕刻(capacitively couple plasma etching)、感應耦合型電漿蝕刻(inductively coupled plasma etching)、電子迴旋共振電漿蝕刻(electron cyclotron resonance plasma etching)、上述之組合或其他合適之製程。上述蝕刻製程可在進行一段時間之後停止蝕刻而未貫穿磊晶層12。因此，溝槽18露出磊晶層12但未露出基底10。 Please refer to FIG. 2, the mask structure 14 is used as an etching mask to remove the exposed epitaxial layer 12 through the opening 15 to form a trench 18. The depth of the trench 18 is, for example, about 1.5 μm to about 1.9 μm. The step of removing the exposed epitaxial layer 12 may include performing an etching process using dry etching, wet etching or a combination of the above. Wet etching may include dip etching, spray etching, a combination of the above, or other suitable processes. Dry etching can include capacitively coupled plasma etching, inductively coupled plasma etching, electron cyclotron resonance plasma etching, a combination of the above, or other suitable ones. Process. The above-mentioned etching process can stop etching after a period of time without penetrating the epitaxial layer 12. Therefore, the trench 18 exposes the epitaxial layer 12 but does not expose the substrate 10.

此外，在上述移除磊晶層12而形成溝槽18時，作為蝕刻遮罩的第一氧化層亦會被部分地消耗而變薄。在一些實施例中，在移除部分磊晶層12以形成溝槽18之前，第一氧化層(如第1圖所示之第一氧化層)的厚度例如是約2000埃至約5000埃。在上述第一氧化層之厚度範圍內進行蝕刻部分磊晶層12以形成溝槽18之步驟時，第一氧化層的厚度將足以保護第一氧化層下方的元件而不受傷害，且在形成溝槽18之後仍保留部分的第一氧化層。形成溝槽18後剩餘的第一氧化層之厚度例如是約1500埃至約2500埃。 In addition, when the epitaxial layer 12 is removed to form the trench 18, the first oxide layer serving as the etching mask is also partially consumed and thinned. In some embodiments, before removing part of the epitaxial layer 12 to form the trench 18, the thickness of the first oxide layer (the first oxide layer shown in FIG. 1) is, for example, about 2000 angstroms to about 5000 angstroms. When the step of etching part of the epitaxial layer 12 to form the trench 18 is performed within the thickness range of the first oxide layer, the thickness of the first oxide layer will be sufficient to protect the components under the first oxide layer from damage, and the formation Part of the first oxide layer remains after the trench 18. The thickness of the first oxide layer remaining after forming the trench 18 is, for example, about 1500 angstroms to about 2500 angstroms.

請參照第3圖，於溝槽18的複數個側壁S1、S2上形成擴散阻障層20。在一些實施例中，擴散阻障層20包括一或多個介電阻障層。在本實施例中，擴散阻障層20包括直接形成於側壁S1、S2上的阻障氧化層22及形成於阻障氧化層上之阻障氮化層24。藉由於阻障氮化層24與磊晶層12之間設置阻障氧化層22，可以解決阻障氮化層24與磊晶層12直接接觸產生應力過大的問題。在一些實施例中，阻障氧化層22可以是或包括二氧化矽或其他適合的氧化物。阻障氮化層24可以是或包括氮化矽或其他適合的氮化物。 Referring to FIG. 3, a diffusion barrier layer 20 is formed on the plurality of sidewalls S1, S2 of the trench 18. In some embodiments, the diffusion barrier layer 20 includes a Or multiple dielectric barrier layers. In this embodiment, the diffusion barrier layer 20 includes a barrier oxide layer 22 formed directly on the sidewalls S1 and S2 and a barrier nitride layer 24 formed on the barrier oxide layer. By providing the barrier oxide layer 22 between the barrier nitride layer 24 and the epitaxial layer 12, the problem of excessive stress caused by the direct contact between the barrier nitride layer 24 and the epitaxial layer 12 can be solved. In some embodiments, the barrier oxide layer 22 may be or include silicon dioxide or other suitable oxides. The barrier nitride layer 24 may be or include silicon nitride or other suitable nitrides.

在第3圖所示之一些實施例中，阻障氧化層22的厚度例如是約70埃至約120埃，阻障氮化層24的厚度例如是約140埃至約190埃。在另一些實施例中，擴散阻障層20可僅為單層之阻障氧化層22。單層之阻障氧化層22的厚度例如是約200埃至約300埃。 In some embodiments shown in FIG. 3, the thickness of the barrier oxide layer 22 is, for example, about 70 angstroms to about 120 angstroms, and the thickness of the barrier nitride layer 24 is, for example, about 140 angstroms to about 190 angstroms. In other embodiments, the diffusion barrier layer 20 may only be a single layer of barrier oxide layer 22. The thickness of the single-layer barrier oxide layer 22 is, for example, about 200 angstroms to about 300 angstroms.

請參照第4圖，在形成擴散阻障層20之後，於磊晶層12上形成覆蓋溝槽18及遮罩結構14的表面之導電材料26。請參照第5圖，接著對導電材料26施加平坦化製程，以暴露出遮罩結構14的上表面。平坦化製程例如是化學機械研磨(chemical mechanical polish，CMP)。 Referring to FIG. 4, after the diffusion barrier layer 20 is formed, a conductive material 26 covering the surface of the trench 18 and the mask structure 14 is formed on the epitaxial layer 12. Referring to FIG. 5, a planarization process is then applied to the conductive material 26 to expose the upper surface of the mask structure 14. The planarization process is, for example, chemical mechanical polish (CMP).

請參照第6圖，之後對導電材料26施加蝕刻製程，將導電材料26的上表面蝕刻至低於遮罩結構14之上表面但高於磊晶層12的上表面，以於溝槽18中形成導電部件28，導電部件28具有高於磊晶層12的突出部30。在一些實施例中，突出部30的寬度大於在溝槽18中之導電部件28的寬度。在一些實施例中，突出部30覆蓋擴散阻障層20之頂表面，如第6圖所示。 Please refer to FIG. 6, and then an etching process is applied to the conductive material 26 to etch the upper surface of the conductive material 26 to be lower than the upper surface of the mask structure 14 but higher than the upper surface of the epitaxial layer 12, so as to be in the trench 18 A conductive member 28 is formed, and the conductive member 28 has a protrusion 30 higher than the epitaxial layer 12. In some embodiments, the width of the protrusion 30 is greater than the width of the conductive member 28 in the trench 18. In some embodiments, the protrusion 30 covers the top surface of the diffusion barrier layer 20, as shown in FIG. 6.

值得注意的是，由於溝槽18中的導電部件28容易形成接縫(seam)，當導電部件28之頂面的高度低於或等於磊晶層12之頂表面的高度時，此接縫會貫穿導電部件28的頂面，造成後續進行清洗步驟時易遭受到侵蝕，並導致後續形成之線路短路等問題。因此本發明之具有高於磊晶層12的突出部30之導電部件28，能避免導電部件28中的接縫貫穿導電部件28的頂面，進而防止後續製程可能造成的問題。在一實施例中，突出部30之高度為200埃至800埃。 It is worth noting that since the conductive component 28 in the trench 18 is easy to form a seam, when the height of the top surface of the conductive component 28 is lower than or equal to the height of the top surface of the epitaxial layer 12, the seam will be The penetration through the top surface of the conductive component 28 causes the subsequent cleaning steps to be easily eroded, and causes problems such as short circuits in subsequent lines. Therefore, the conductive member 28 having the protrusion 30 higher than the epitaxial layer 12 of the present invention can prevent the seam in the conductive member 28 from penetrating the top surface of the conductive member 28, thereby preventing possible problems caused by subsequent manufacturing processes. In one embodiment, the height of the protrusion 30 is 200 to 800 angstroms.

此外，導電部件28可為P型導電部件。在一些實施例中，導電部件28摻雜有摻質。摻質可以是或包括硼、鎵、銦、鋁或其組合。值得注意的是，由於本發明具有設置於導電部件28與磊晶層12之間擴散阻障層20，因此在進行後續製程(例如高溫熱製程)時，擴散阻障層20可以阻礙導電部件28的摻質擴散至周遭，進而避免影響周遭元件的電性。 In addition, the conductive member 28 may be a P-type conductive member. In some embodiments, the conductive features 28 are doped with dopants. The dopant can be or include boron, gallium, indium, aluminum, or a combination thereof. It is worth noting that, because the present invention has a diffusion barrier layer 20 disposed between the conductive component 28 and the epitaxial layer 12, the diffusion barrier layer 20 can hinder the conductive component during subsequent processes (such as high-temperature thermal processes). The dopant of 28 diffuses to the surroundings to avoid affecting the electrical properties of surrounding devices.

此外，一般而言，當後續製成如第15圖之半導體結構100的尺寸縮小時，導電部件28的摻質之擴散對周遭元件造成的影響會更顯著，然而，由於本發明具有設置於導電部件28與磊晶層12之間擴散阻障層20，因此即使半導體結構100的尺寸縮小，導電部件28的摻質也不會影響周遭元件。如此，半導體結構100的尺寸能不受限制而能繼續縮小，進而降低源極-汲極電阻值(R_DSON)，以改善半導體結構100的效能。 In addition, generally speaking, when the size of the semiconductor structure 100 as shown in FIG. 15 is reduced subsequently, the diffusion of the dopant of the conductive component 28 will have a more significant impact on the surrounding components. However, since the present invention has the configuration in the conductive The barrier layer 20 is diffused between the component 28 and the epitaxial layer 12, so even if the size of the semiconductor structure 100 is reduced, the dopant of the conductive component 28 will not affect the surrounding components. In this way, the size of the semiconductor structure 100 can be continuously reduced without being limited, thereby reducing the source-drain resistance (R _DSON ) to improve the performance of the semiconductor structure 100.

在一些實施例中，溝槽18的底表面可為平坦底表面或U型底表面。當溝槽18的底表面為U型底表面時，可增加導電部件28與磊晶層12直接接觸之面積，以增加操作電流的流量，可提升後續製成之半導體結構100之效能。 In some embodiments, the bottom surface of the trench 18 may be a flat bottom surface or a U-shaped bottom surface. When the bottom surface of the trench 18 is a U-shaped bottom surface, the area where the conductive component 28 directly contacts the epitaxial layer 12 can be increased to increase the operating current The flow rate can improve the performance of the semiconductor structure 100 subsequently manufactured.

請參照第7圖，移除遮罩結構14。遮罩結構14的移除包括使用熱磷酸、氫氟酸或其組合來移除遮罩結構14。在本實施例中，遮罩結構14為單層之第一氧化層。第一氧化層的移除步驟例如是使用氫氟酸來移除第一氧化層。 Please refer to Figure 7 to remove the mask structure 14. The removal of the mask structure 14 includes using hot phosphoric acid, hydrofluoric acid, or a combination thereof to remove the mask structure 14. In this embodiment, the mask structure 14 is a single-layer first oxide layer. The step of removing the first oxide layer is, for example, using hydrofluoric acid to remove the first oxide layer.

第8-10圖是根據本發明的另一些實施例之移除遮罩結構14之步驟之不同階段的圖式。第8-10圖所示之實施例相似於第1-7圖之實施例，主要差異在於遮罩結構14之組成及移除步驟，因此僅繪示出第8-10圖以進行說明。 FIGS. 8-10 are diagrams of different stages of the step of removing the mask structure 14 according to other embodiments of the present invention. The embodiment shown in Figs. 8-10 is similar to the embodiment shown in Figs. 1-7. The main difference lies in the composition and removal steps of the mask structure 14, so only Figs. 8-10 are drawn for description.

在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參照前述實施例，下述實施例不再重複贅述。 It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, refer to the foregoing embodiments, and the following embodiments will not be repeated.

請先參照第8圖，在此實施例中，遮罩結構14為多個介電層。遮罩結構14包括第一氧化層16a及形成於第一氧化層16a上的氮化層32a。第一氧化層16a的厚度例如是約300埃至700埃。氮化層32a例如是約400埃至約900埃。第一氧化層16a之材料可以是或包括二氧化矽或其他適合的氧化物。氮化層32a可以是或包括氮化矽或其他合適的氮化物。在一些實施例中，可利用例如化學氣相沉積法(chemical vapor deposition，CVD)、原子層化學氣相沉積法(atomic layer deposition，ALD)或相似製程形成氮化層32a。在本實施例中，可藉由將第一氧化層16a設置於氮化層32a與磊晶層12之間，以解決氮化層32a與磊晶層12直接接觸產生應力過大的問題。 Please refer to FIG. 8 first. In this embodiment, the mask structure 14 is a plurality of dielectric layers. The mask structure 14 includes a first oxide layer 16a and a nitride layer 32a formed on the first oxide layer 16a. The thickness of the first oxide layer 16a is, for example, about 300 angstroms to 700 angstroms. The nitride layer 32a is, for example, about 400 angstroms to about 900 angstroms. The material of the first oxide layer 16a may be or include silicon dioxide or other suitable oxides. The nitride layer 32a may be or include silicon nitride or other suitable nitrides. In some embodiments, the nitride layer 32a can be formed by, for example, chemical vapor deposition (CVD), atomic layer chemical vapor deposition (ALD) or similar processes. In this embodiment, the first oxide layer 16a can be disposed between the nitride layer 32a and the epitaxial layer 12 In order to solve the problem of excessive stress caused by direct contact between the nitride layer 32a and the epitaxial layer 12.

需說明的是，在第8-10圖所示之實施例中，在形成溝槽18的步驟之前(未繪示)，氮化層32a的厚度例如是約2500埃至約3500埃。在上述氮化層32a的厚度範圍內，將氮化層32a作為蝕刻遮罩進行蝕刻製程形成溝槽18後，可以保留部分的氮化層32a及全部的第一氧化層16a。也就是說，氮化層32a的厚度在上述範圍內，足夠使氮化層32a下方的元件不受傷害。在一些實施例中，形成溝槽18之後剩餘的氮化層32a例如是約400埃至約900埃(如第8圖所示之氮化層32a)。 It should be noted that, in the embodiment shown in FIGS. 8-10, before the step of forming the trench 18 (not shown), the thickness of the nitride layer 32a is, for example, about 2500 angstroms to about 3500 angstroms. Within the thickness range of the above-mentioned nitride layer 32a, after the nitride layer 32a is used as an etching mask to form the trench 18, part of the nitride layer 32a and all the first oxide layer 16a can be left. In other words, the thickness of the nitride layer 32a is within the above range, which is sufficient to prevent damage to the devices under the nitride layer 32a. In some embodiments, the remaining nitride layer 32a after forming the trench 18 is, for example, about 400 angstroms to about 900 angstroms (such as the nitride layer 32a shown in FIG. 8).

請繼續參照第8-10圖，在形成上述溝槽18及導電部件28之後，接著移除遮罩結構14。遮罩結構14的移除包括先移除部份遮罩結構14並保留最接近磊晶層12的一層介電層，且在移除部分遮罩結構14之後，移除剩餘的遮罩結構14。具體而言，遮罩結構14的移除包括先移除氮化層32a並保留第一氧化層16a，之後再移除第一氧化層16a。 Please continue to refer to FIGS. 8-10. After the trench 18 and the conductive member 28 are formed, the mask structure 14 is removed. The removal of the mask structure 14 includes first removing part of the mask structure 14 and leaving a dielectric layer closest to the epitaxial layer 12, and after removing part of the mask structure 14, removing the remaining mask structure 14 . Specifically, the removal of the mask structure 14 includes first removing the nitride layer 32a and leaving the first oxide layer 16a, and then removing the first oxide layer 16a.

在一些實施例中，由於氮化層32a的蝕刻選擇比大於第一氧化層16a的蝕刻選擇比，因此可以在移除氮化層32a後，保留全部的第一氧化層16a。然後，在移除氮化層32a之後，接著移除第一氧化層16a。 In some embodiments, since the etching selection ratio of the nitride layer 32a is greater than the etching selection ratio of the first oxide layer 16a, all the first oxide layer 16a can be left after the nitride layer 32a is removed. Then, after removing the nitride layer 32a, the first oxide layer 16a is then removed.

值得注意的是，在第一氧化層16a的厚度例如是約300埃至700埃的實施例中，可以使用短時間(例如約10秒至約30秒)之蝕刻製程來完全移除第一氧化層16a，藉此能較精準地達到完全移除第一氧化層16a而不傷害第一氧化層16a周遭的元件，更具體地說，使用約10秒至約30秒之短時間的蝕刻製程來完全移除第一氧化層16a，能避免過度蝕刻傷害到擴散阻障層20，進而確保擴散阻障層20能夠保持完整以有效阻礙導電部件28的摻質擴散至周遭，進而防止影響周遭元件的電性。 It is worth noting that in an embodiment where the thickness of the first oxide layer 16a is, for example, about 300 angstroms to 700 angstroms, a short time (for example, about 10 seconds to about 30 seconds) etching process can be used to completely remove the first oxide layer. Layer 16a, so that the first oxide layer 16a can be completely removed without damaging the circumference of the first oxide layer 16a. In particular, the first oxide layer 16a is completely removed using a short etching process of about 10 seconds to about 30 seconds, which can prevent excessive etching from damaging the diffusion barrier layer 20, thereby ensuring the diffusion barrier The layer 20 can remain intact to effectively prevent the dopants of the conductive component 28 from diffusing to the surroundings, thereby preventing the electrical properties of the surrounding components from being affected.

在一具體實施例中，可先使用熱磷酸對氮化層32a進行約50秒至約100秒之蝕刻製程以移除全部的氮化層32a，接著使用氫氟酸對第一氧化層16a進行約50秒至約100秒之蝕刻製程，以移除全部的第一氧化層16a。 In a specific embodiment, hot phosphoric acid may be used to perform an etching process on the nitride layer 32a for about 50 seconds to about 100 seconds to remove all of the nitride layer 32a, and then hydrofluoric acid may be used for the first oxide layer 16a. The etching process takes about 50 seconds to about 100 seconds to remove all the first oxide layer 16a.

第11-13圖是根據本發明的又一些實施例之移除遮罩結構14之步驟之不同階段的圖式。第11-13圖所示之實施例相似於第1-7圖之實施例，主要差異在於遮罩結構14之組成及移除步驟，因此僅繪示出第11-13圖以進行說明。 FIGS. 11-13 are diagrams of different stages of the step of removing the mask structure 14 according to still other embodiments of the present invention. The embodiment shown in Figs. 11-13 is similar to the embodiment shown in Figs. 1-7. The main difference lies in the composition and removal steps of the mask structure 14, so only Figs. 11-13 are drawn for explanation.

請先參照第11圖，在又另一些實施例中，遮罩結構14包括第一氧化層16b、形成於第一氧化層16b上的氮化層32b及形成於氮化層32b上的第二氧化層34。第一氧化層16b的厚度例如是約300埃至700埃。氮化層32b的厚度例如是約900埃至約1300埃。第二氧化層34的厚度例如是約2000埃至約4000埃。第一氧化層16b之材料可以是或包括二氧化矽或其他適合的氧化物。氮化層32b可以是或包括氮化矽或其他合適的氮化物。第二氧化層34可以是或包括二氧化矽或其他適合的氧化物。在本實施例中，可藉由將第一氧化層16b設置於氮化層32b與磊晶層12之間，以解決氮化層32b與磊晶層12直接接觸產生應力過大的問題。 Please refer to FIG. 11 first. In still other embodiments, the mask structure 14 includes a first oxide layer 16b, a nitride layer 32b formed on the first oxide layer 16b, and a second nitride layer 32b formed on the nitride layer 32b. Oxidized layer 34. The thickness of the first oxide layer 16b is, for example, about 300 angstroms to 700 angstroms. The thickness of the nitride layer 32b is, for example, about 900 angstroms to about 1300 angstroms. The thickness of the second oxide layer 34 is, for example, about 2000 angstroms to about 4000 angstroms. The material of the first oxide layer 16b may be or include silicon dioxide or other suitable oxides. The nitride layer 32b may be or include silicon nitride or other suitable nitrides. The second oxide layer 34 may be or include silicon dioxide or other suitable oxides. In this embodiment, the first oxide layer 16b can be disposed between the nitride layer 32b and the epitaxial layer 12 to solve the problem of excessive stress in direct contact between the nitride layer 32b and the epitaxial layer 12.

需說明的是，在第11-13圖所示之實施例中，在形成溝槽18的步驟前(未繪示)，第二氧化層34的厚度例如是約2500埃至約3300埃。在上述第二氧化層34的厚度範圍內，將第二氧化層34作為蝕刻遮罩進行蝕刻製程形成溝槽18後，可以保留部分的第二氧化層34、全部的氮化層32b及全部的第一氧化層16b。也就是說，第二氧化層34的厚度在上述範圍內，足夠使第二氧化層34下方的元件不受傷害。在一些實施例中，形成溝槽18後留下的第二氧化層34之厚度例如是約400埃至約900埃(如第11圖所示之第二氧化層34)。 It should be noted that, in the embodiment shown in FIGS. 11-13, before the step of forming the trench 18 (not shown), the thickness of the second oxide layer 34 is, for example, about 2500 angstroms to about 3300 angstroms. Within the above-mentioned thickness range of the second oxide layer 34, after the second oxide layer 34 is used as an etching mask to form the trench 18, part of the second oxide layer 34, all the nitride layer 32b and all of the The first oxide layer 16b. In other words, the thickness of the second oxide layer 34 is within the above range, which is sufficient to protect the components under the second oxide layer 34 from damage. In some embodiments, the thickness of the second oxide layer 34 left after the trench 18 is formed is, for example, about 400 angstroms to about 900 angstroms (such as the second oxide layer 34 shown in FIG. 11).

請繼續參照第11-13圖，在形成上述溝槽18及導電部件28之後，移除遮罩結構14。遮罩結構14的移除包括先移除部份遮罩結構14並保留最接近磊晶層12的一層介電層，且在移除部分遮罩結構14之後，移除剩餘的遮罩結構14。具體而言，遮罩結構14的移除可包括先移除氮化層32b及第二氧化層34並保留第一氧化層16b，接著移除第一氧化層16b。 Please continue to refer to FIGS. 11-13. After the trench 18 and the conductive member 28 are formed, the mask structure 14 is removed. The removal of the mask structure 14 includes first removing part of the mask structure 14 and leaving a dielectric layer closest to the epitaxial layer 12, and after removing part of the mask structure 14, removing the remaining mask structure 14 . Specifically, the removal of the mask structure 14 may include first removing the nitride layer 32b and the second oxide layer 34 and leaving the first oxide layer 16b, and then removing the first oxide layer 16b.

在一些實施例中，突出部30的頂面之高度介於氮化層32b的頂面及底面之間，因此在使用濕式蝕刻移除氮化層32b時會一併移除氮化層32b上的第二氧化層34。此外，在一些實施例中，氮化層32b的蝕刻選擇比大於第一氧化層16b的蝕刻選擇比，如此可以在移除氮化層32b後，保留全部的第一氧化層16b。 In some embodiments, the height of the top surface of the protrusion 30 is between the top surface and the bottom surface of the nitride layer 32b. Therefore, the nitride layer 32b is also removed when the nitride layer 32b is removed by wet etching.上的second oxide layer 34. In addition, in some embodiments, the etching selection ratio of the nitride layer 32b is greater than the etching selection ratio of the first oxide layer 16b, so that all the first oxide layer 16b can be retained after the nitride layer 32b is removed.

然後，在移除第二氧化層34及氮化層32b之後，接著移除第一氧化層16b。值得注意的是，在第一氧化層16b的厚度例如是約300埃至700埃的實施例中，可以使用短時間 (例如約10秒至約30秒)之蝕刻製程來完全移除第一氧化層16b，藉此較精準地達到完全移除第一氧化層16b而不傷害第一氧化層16b周遭的元件，更具體地說，使用約10秒至約30秒之短時間的蝕刻製程來完全移除第一氧化層16b，能避免過度蝕刻傷害到擴散阻障層20，進而確保擴散阻障層20能夠保持完整以有效阻礙導電部件28的摻質擴散至周遭，進而防止影響周遭元件的電性。 Then, after removing the second oxide layer 34 and the nitride layer 32b, the first oxide layer 16b is then removed. It is worth noting that in an embodiment where the thickness of the first oxide layer 16b is, for example, about 300 angstroms to 700 angstroms, a short time can be used (For example, about 10 seconds to about 30 seconds) etching process to completely remove the first oxide layer 16b, thereby achieving a more precise complete removal of the first oxide layer 16b without damaging the components around the first oxide layer 16b, and more Specifically, a short etching process of about 10 seconds to about 30 seconds is used to completely remove the first oxide layer 16b, which can prevent excessive etching from damaging the diffusion barrier layer 20, thereby ensuring that the diffusion barrier layer 20 can remain intact This effectively prevents the dopants of the conductive component 28 from diffusing to the surroundings, thereby preventing the electrical properties of surrounding components from being affected.

在一具體實施例中，可先使用熱磷酸對氮化層32b及第二氧化層34進行約50秒至約100秒之蝕刻製程以移除全部的氮化層32b及第二氧化層34，接著使用氫氟酸對第一氧化層16b進行約50秒至約100秒之蝕刻製程以移除全部的第一氧化層16b。 In a specific embodiment, the nitride layer 32b and the second oxide layer 34 may be etched for about 50 seconds to about 100 seconds using hot phosphoric acid to remove all the nitride layer 32b and the second oxide layer 34. Then, the first oxide layer 16b is etched for about 50 seconds to about 100 seconds using hydrofluoric acid to remove all of the first oxide layer 16b.

在另一些實施例，可依序移除第二氧化層34及氮化層32b，接著移除第一氧化層16b。舉例而言，先使用氫氟酸移除第二氧化層34，再使用熱磷酸移除氮化層32b，然後使用氫氟酸移除第一氧化層16b。 In other embodiments, the second oxide layer 34 and the nitride layer 32b may be sequentially removed, and then the first oxide layer 16b may be removed. For example, hydrofluoric acid is used to remove the second oxide layer 34 first, then hot phosphoric acid is used to remove the nitride layer 32b, and then hydrofluoric acid is used to remove the first oxide layer 16b.

請參照第14圖，可於磊晶層12中形成接觸摻雜區36，其相鄰於基底10且與導電部件28接觸，使電流能在導電部件28與接觸摻雜區36之間傳遞。接觸摻雜區36可為P型。在一實施例中，可於磊晶層12中形成第一井區38，其圍繞導電部件28之靠近磊晶層12的上表面的部分。第一井區38可為P型。在一些實施例中，可於第一井區38的兩側的磊晶層12中分別形成第二井區42。第二井區42可為N型。 Referring to FIG. 14, a contact doped region 36 may be formed in the epitaxial layer 12, which is adjacent to the substrate 10 and is in contact with the conductive component 28, so that current can pass between the conductive component 28 and the contact doped region 36. The contact doped region 36 may be P-type. In one embodiment, a first well region 38 may be formed in the epitaxial layer 12 to surround a portion of the conductive member 28 close to the upper surface of the epitaxial layer 12. The first well region 38 may be P-type. In some embodiments, second well regions 42 may be formed in the epitaxial layer 12 on both sides of the first well region 38 respectively. The second well region 42 may be N-type.

請參照第15圖，可於磊晶層12上形成兩個閘極結構46，且閘極結構46位在第一井區38及相鄰的第二井區42之間。在一些實施例中，閘極結構46可包括閘極介電層48、配置於閘極介電層48上之閘極電極50及配置於閘極電極50上之閘極矽化層52。閘極介電層48可為氧化矽、氮化矽、氮氧化矽、高介電常數(high-k)介電材料、其它任何適合之介電材料或上述之組合。此高介電常數介電材料之材料可為金屬氧化物、金屬氮化物、金屬矽化物、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽化物、金屬的氮氧化物、金屬鋁酸鹽、鋯矽酸鹽、鋯鋁酸鹽。閘極電極50可為金屬、金屬氮化物、導電金屬氧化物或上述之組合。上述金屬可包括但不限於鉬、鎢、鈦、鉭、鉑或鉿。閘極矽化層52可以是或包括矽化鎳、矽化鈷、矽化鈦或其組合。在一實施例中，閘極結構46可僅包括閘極介電層48及閘極電極50。 Referring to FIG. 15, two gate junctions can be formed on the epitaxial layer 12 The structure 46, and the gate structure 46 is located between the first well region 38 and the adjacent second well region 42. In some embodiments, the gate structure 46 may include a gate dielectric layer 48, a gate electrode 50 disposed on the gate dielectric layer 48, and a gate silicide layer 52 disposed on the gate electrode 50. The gate dielectric layer 48 can be silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, any other suitable dielectric material, or a combination of the foregoing. The material of this high-k dielectric material can be metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, metal aluminate, Zirconium silicate, zirconium aluminate. The gate electrode 50 can be a metal, a metal nitride, a conductive metal oxide, or a combination thereof. The aforementioned metals may include, but are not limited to, molybdenum, tungsten, titanium, tantalum, platinum, or hafnium. The gate silicide layer 52 may be or include nickel silicide, cobalt silicide, titanium silicide, or a combination thereof. In an embodiment, the gate structure 46 may only include the gate dielectric layer 48 and the gate electrode 50.

此外，可於第一井區38內形成源極區40，源極區40圍繞導電部件28的靠近磊晶層12的上表面的部分。在本實施例中，擴散阻障層20接觸源極區40且分隔源極區40及導電部件28，使擴散阻障層20可以阻礙導電部件28的摻質擴散至源極區40，進而避免干擾源極區40的電性。源極區40可為N型。在一些實施例中，可於第二井區42內形成汲極區44。汲極區44可為重摻雜N型。 In addition, a source region 40 may be formed in the first well region 38, and the source region 40 surrounds a portion of the conductive member 28 close to the upper surface of the epitaxial layer 12. In this embodiment, the diffusion barrier layer 20 contacts the source region 40 and separates the source region 40 and the conductive member 28, so that the diffusion barrier layer 20 can prevent the dopants of the conductive member 28 from diffusing to the source region 40, thereby preventing The electrical properties of the source region 40 are disturbed. The source region 40 may be N-type. In some embodiments, the drain region 44 may be formed in the second well region 42. The drain region 44 may be heavily doped N-type.

在一些實施例中，可於閘極結構46的側壁上形成間隔物54，且可於閘極結構46的上表面上、間隔物54的表面上及磊晶層12的上表面上形成絕緣層55，且絕緣層55暴露出導電部件28、源極區40及汲極區44。 In some embodiments, spacers 54 may be formed on the sidewalls of the gate structure 46, and an insulating layer may be formed on the upper surface of the gate structure 46, the surface of the spacer 54 and the upper surface of the epitaxial layer 12 55, and the insulating layer 55 exposes the conductive component 28, the source region 40 and the drain region 44.

在一些實施例中，可於磊晶層12上形成導電層56。導電層56覆蓋導電部件28、源極區40、閘極結構46及部分第二井區42並且暴露出汲極區44。在一些實施例中，可於磊晶層12上形成層間介電層58及貫穿層間介電層58且連接至汲極區44之接觸插塞60。接觸插塞60包括多晶矽、鋁、金、鈷、銅、類似之材料或其組合。之後，可於層間介電層58上形成導電部件62，其電性連接於接觸插塞60。導電部件62包括銅、金、錫、類似之材料或其組合。 In some embodiments, a conductive layer 56 may be formed on the epitaxial layer 12. The conductive layer 56 covers the conductive component 28, the source region 40, the gate structure 46 and a part of the second well region 42 and exposes the drain region 44. In some embodiments, an interlayer dielectric layer 58 and a contact plug 60 penetrating the interlayer dielectric layer 58 and connected to the drain region 44 may be formed on the epitaxial layer 12. The contact plug 60 includes polysilicon, aluminum, gold, cobalt, copper, similar materials, or a combination thereof. After that, a conductive component 62 may be formed on the interlayer dielectric layer 58 and electrically connected to the contact plug 60. The conductive component 62 includes copper, gold, tin, similar materials, or a combination thereof.

藉由上述一個或多個實施例之步驟，便可以得到如第15圖所示之半導體結構100。值得注意的是，在第15圖所示之實施例中，在半導體結構100中以源極區40為基準線之右側部分(包括源極區40)及左側部分(包括源極區40)各自為一個橫向擴散金屬氧化物半導體(LDMOS)。在本實施例中，源極區40可作為兩個橫向擴散金屬氧化物半導體之共同源極，且導電部件28形成於兩個橫向擴散金屬氧化物半導體之間，其穿過橫向擴散金屬氧化物半導體之共同源極，並且導電部件28藉由導電層56與源極區40電性連接。因此，兩個橫向擴散金屬氧化物半導體能藉由同一個源極區40及同一個導電部件28來傳遞電流，如此便可以達到節省空間及製造成本之功效。 Through the steps of one or more of the above embodiments, the semiconductor structure 100 as shown in FIG. 15 can be obtained. It is worth noting that in the embodiment shown in FIG. 15, the right part (including the source region 40) and the left part (including the source region 40) of the semiconductor structure 100 with the source region 40 as the reference line are respectively It is a laterally diffused metal oxide semiconductor (LDMOS). In this embodiment, the source region 40 can be used as a common source of two laterally diffused metal oxide semiconductors, and the conductive member 28 is formed between the two laterally diffused metal oxide semiconductors, which passes through the laterally diffused metal oxide semiconductors. The common source of the semiconductor, and the conductive component 28 is electrically connected to the source region 40 through the conductive layer 56. Therefore, two laterally diffused metal oxide semiconductors can transfer current through the same source region 40 and the same conductive member 28, so that space saving and manufacturing cost can be achieved.

綜上所述，本發明實施例之半導體結構具有設置於導電部件及磊晶層之間的擴散阻障層，因此在進行後續製程(例如高溫熱製程)時，擴散阻障層可以阻礙導電部件的摻質擴散至周遭，以避免影響周遭元件的電性，且能使擴散金屬氧化物半導體的尺寸不受限制而能繼續變小，進而繼續降低源極-汲極電阻值(R_DSON)，以改善橫向擴散金屬氧化(LDMOS)物半導體的性能。 In summary, the semiconductor structure of the embodiment of the present invention has a diffusion barrier layer disposed between the conductive component and the epitaxial layer. Therefore, the diffusion barrier layer can hinder conduction during subsequent processes (such as high-temperature thermal processes). The dopants of the component diffuse to the surroundings to avoid affecting the electrical properties of the surrounding components, and the size of the diffused metal oxide semiconductor is not limited and can continue to decrease, thereby continuing to reduce the source-drain resistance (R _DSON ) To improve the performance of laterally diffused metal oxide (LDMOS) semiconductors.

此外，當導電部件之頂面的高度低於或等於磊晶層之頂表面的高度時，導電部件中的接縫會貫穿導電部件的頂面，造成後續進行清洗步驟時易遭受到侵蝕，並導致後續形成之線路短路等問題。因此，本發明實施例之半導體結構之導電部件具有高於磊晶層的突出部，避免導電部件中的接縫貫穿導電部件的頂面，以預防後續製程可能造成的問題。 In addition, when the height of the top surface of the conductive component is lower than or equal to the height of the top surface of the epitaxial layer, the seam in the conductive component will penetrate the top surface of the conductive component, causing the subsequent cleaning steps to be easily eroded, and Causes problems such as short circuits in subsequent formations. Therefore, the conductive component of the semiconductor structure of the embodiment of the present invention has a protrusion higher than the epitaxial layer to prevent the seam in the conductive component from penetrating the top surface of the conductive component to prevent possible problems caused by subsequent manufacturing processes.

以上概述數個實施例之部件，以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能輕易地以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍下，做各式各樣的改變、取代和替換。因此，本發明之保護範圍當視後附之申請專利範圍所界定為準。 The components of several embodiments are summarized above so that those with ordinary knowledge in the technical field of the present invention can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. . Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and they can do various things without departing from the spirit and scope of the present invention. Such changes, substitutions and replacements. Therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.

100‧‧‧半導體結構 100‧‧‧Semiconductor structure

10‧‧‧基底 10‧‧‧Base

12‧‧‧磊晶層 12‧‧‧Epitaxial layer

18‧‧‧溝槽 18‧‧‧Groove

20‧‧‧擴散阻障層 20‧‧‧Diffusion barrier

22‧‧‧阻障氧化層 22‧‧‧Barrier oxide layer

24‧‧‧阻障氮化層 24‧‧‧Barrier nitride layer

28‧‧‧導電部件 28‧‧‧Conductive parts

30‧‧‧突出部 30‧‧‧Protrusion

36‧‧‧接觸摻雜區 36‧‧‧Contact doped area

38‧‧‧第一井區 38‧‧‧The first well area

40‧‧‧源極區 40‧‧‧Source area

42‧‧‧第二井區 42‧‧‧Second Well Area

44‧‧‧汲極區 44‧‧‧Dip pole area

46‧‧‧閘極結構 46‧‧‧Gate structure

48‧‧‧閘極介電層 48‧‧‧Gate Dielectric Layer

50‧‧‧閘極電極 50‧‧‧Gate electrode

52‧‧‧閘極矽化層 52‧‧‧Gate Silica Layer

54‧‧‧間隔物 54‧‧‧Spacer

55‧‧‧絕緣層 55‧‧‧Insulation layer

56‧‧‧導電層 56‧‧‧Conductive layer

58‧‧‧層間介電層 58‧‧‧Interlayer dielectric layer

60‧‧‧接觸插塞 60‧‧‧Contact plug

62‧‧‧導電部件 62‧‧‧Conductive parts

Claims

一種半導體結構，包括：一基底；一磊晶層，設置於該基底上；一導電部件，設置於該磊晶層中並接觸該磊晶層，且具有高於該磊晶層的一突出部，其中該導電部件與該突出部係為電性連接；以及一擴散阻障層，設置於該導電部件的複數個側壁上，其中該擴散阻障層的頂表面實質上未超出該磊晶層的頂表面。 A semiconductor structure includes: a substrate; an epitaxial layer disposed on the substrate; a conductive member disposed in the epitaxial layer and contacting the epitaxial layer, and having a protrusion higher than the epitaxial layer , Wherein the conductive component and the protrusion are electrically connected; and a diffusion barrier layer is disposed on the plurality of sidewalls of the conductive component, wherein the top surface of the diffusion barrier layer does not substantially exceed the epitaxial layer The top surface.

如申請專利範圍第1項所述之半導體結構，其中該突出部的寬度大於在該磊晶層中之該導電部件的寬度。 The semiconductor structure described in claim 1, wherein the width of the protrusion is greater than the width of the conductive member in the epitaxial layer.

如申請專利範圍第1項所述之半導體結構，其中該突出部覆蓋該擴散阻障層之頂表面。 The semiconductor structure described in claim 1, wherein the protrusion covers the top surface of the diffusion barrier layer.

如申請專利範圍第1項所述之半導體結構，其中該擴散阻障層包括一或多個介電阻障層。 According to the semiconductor structure described in claim 1, wherein the diffusion barrier layer includes one or more dielectric resistance barrier layers.

如申請專利範圍第4項所述之半導體結構，其中該擴散阻障層包括一阻障氧化層及在該阻障氧化層上之一阻障氮化層。 According to the semiconductor structure described in claim 4, the diffusion barrier layer includes a barrier oxide layer and a barrier nitride layer on the barrier oxide layer.

如申請專利範圍第1~5項中任一項所述之半導體結構，更包括：一源極區，設置於該磊晶層中，該擴散阻障層接觸該源極區且分隔該源極區及該導電部件。 The semiconductor structure described in any one of items 1 to 5 of the scope of the patent application further includes: a source region disposed in the epitaxial layer, the diffusion barrier layer contacts the source region and separates the source electrode Zone and the conductive part.

如申請專利範圍第1~5項中任一項所述之半導體結構，其中該導電部件設置於兩個橫向擴散金屬氧化物半導體 (LDMOS)之間，且該導電部件穿過該些橫向擴散金屬氧化物半導體之一共同源極。 The semiconductor structure described in any one of items 1 to 5 in the scope of the patent application, wherein the conductive component is arranged on two laterally diffused metal oxide semiconductors (LDMOS), and the conductive component passes through a common source of the laterally diffused metal oxide semiconductors.

如申請專利範圍第1~5項中任一項所述之半導體結構，其中該突出部接觸部分該磊晶層。 According to the semiconductor structure described in any one of items 1 to 5 in the scope of patent application, the protrusion contacts a part of the epitaxial layer.

如申請專利範圍第1~5項中任一項所述之半導體結構，更包括：至少一閘極結構，設置於該磊晶層上；一間隔物，設置於該至少一閘極結構的側壁上；一源極區，設置於該磊晶層中，該擴散阻障層接觸該源極區且分隔該源極區及該導電部件；一汲極區，設置於該磊晶層中以及該源極區的兩側；以及一絕緣層，設置於該閘極結構與該磊晶層的上表面上以及該間隔物的表面上，其中該絕緣層暴露出該導電部件、該源極區以及該汲極區。 The semiconductor structure described in any one of items 1 to 5 of the scope of the patent application further includes: at least one gate structure disposed on the epitaxial layer; a spacer disposed on the sidewall of the at least one gate structure On; a source region is provided in the epitaxial layer, the diffusion barrier layer contacts the source region and separates the source region and the conductive member; a drain region is provided in the epitaxial layer and the On both sides of the source region; and an insulating layer disposed on the upper surface of the gate structure and the epitaxial layer and on the surface of the spacer, wherein the insulating layer exposes the conductive component, the source region, and The drain area.

一種半導體結構的製造方法，包括：提供一基底；於該基底上形成一磊晶層；於該磊晶層上形成一遮罩結構，該遮罩結構具有一開口，其露出部分該磊晶層；使用該遮罩結構作為一蝕刻遮罩，以移除露出之該磊晶層而形成一溝槽；於該溝槽的複數個側壁上形成一擴散阻障層，該擴散阻障層的頂表面實質上未超出該磊晶層的頂表面；於該溝槽中形成接觸該磊晶層的一導電部件，該導電部件具有高於該磊晶層的一突出部，其中該導電部件與該突出部係為電性連接；以及移除該遮罩結構。 A method of manufacturing a semiconductor structure includes: providing a substrate; forming an epitaxial layer on the substrate; forming a mask structure on the epitaxial layer, the mask structure having an opening that exposes a part of the epitaxial layer ; Use the mask structure as an etching mask to remove the exposed epitaxial layer to form a trench; a diffusion barrier layer is formed on a plurality of sidewalls of the trench, the top of the diffusion barrier layer The surface does not substantially exceed the top surface of the epitaxial layer; a conductive component contacting the epitaxial layer is formed in the trench, the conductive component Having a protrusion higher than the epitaxial layer, wherein the conductive component and the protrusion are electrically connected; and removing the mask structure.

如申請專利範圍第10項所述之半導體結構的製造方法，其中該突出部的寬度大於在該溝槽中之該導電部件的寬度。 According to the method for manufacturing a semiconductor structure as described in claim 10, the width of the protrusion is greater than the width of the conductive member in the trench.

如申請專利範圍第10項所述之半導體結構的製造方法，其中該突出部覆蓋該擴散阻障層之頂表面。 According to the manufacturing method of the semiconductor structure described in claim 10, the protrusion covers the top surface of the diffusion barrier layer.

如申請專利範圍第10項所述之半導體結構的製造方法，其中該遮罩結構包括一或多個介電層。 According to the method for manufacturing a semiconductor structure as described in claim 10, the mask structure includes one or more dielectric layers.

如申請專利範圍第13項所述之半導體結構的製造方法，其中該遮罩結構包括一第一氧化層及形成於該第一氧化層上的一氮化層。 According to the manufacturing method of the semiconductor structure described in claim 13, wherein the mask structure includes a first oxide layer and a nitride layer formed on the first oxide layer.

如申請專利範圍第14項所述之半導體結構的製造方法，其中該遮罩結構更包括形成於該氮化層上的一第二氧化層。 According to the method for manufacturing a semiconductor structure described in claim 14, wherein the mask structure further includes a second oxide layer formed on the nitride layer.

如申請專利範圍第13項所述之半導體結構的製造方法，其中該遮罩結構為多個介電層，且該遮罩結構的移除包括：先移除部份該遮罩結構並保留最接近該磊晶層的一層該介電層；以及在移除部分該遮罩結構之後，移除剩餘的該遮罩結構。 According to the manufacturing method of the semiconductor structure described in claim 13, wherein the mask structure is a plurality of dielectric layers, and the removal of the mask structure includes: first removing part of the mask structure and retaining the most A layer of the dielectric layer close to the epitaxial layer; and after removing part of the mask structure, removing the remaining mask structure.

如申請專利範圍第10項所述之半導體結構的製造方法，其中該擴散阻障層包括一或多個介電阻障層。 According to the method of manufacturing a semiconductor structure described in claim 10, the diffusion barrier layer includes one or more dielectric resistance barrier layers.

如申請專利範圍第17項所述之半導體結構的製造方法，其中該擴散阻障層包括一阻障氧化層及形成於該阻障氧化層上之一阻障氮化層。 According to the method for manufacturing a semiconductor structure described in the scope of the patent application, the diffusion barrier layer includes a barrier oxide layer and a barrier nitride layer formed on the barrier oxide layer.

如申請專利範圍第10~18項中任一項所述之半導體結構的製造方法，更包括：於該磊晶層中形成一源極區，該擴散阻障層接觸該源極區且分隔該源極區及該導電部件。 The manufacturing method of the semiconductor structure as described in any one of the 10 to 18 patents, further comprising: forming a source region in the epitaxial layer, and the diffusion barrier layer contacts the source region and separates the The source region and the conductive component.

如申請專利範圍第10~18項中任一項所述之半導體結構的製造方法，其中該導電部件形成於兩個橫向擴散金屬氧化物半導體(LDMOS)之間，且該導電部件穿過該些橫向擴散金屬氧化物半導體之一共同源極。 According to the method for manufacturing a semiconductor structure according to any one of claims 10 to 18, the conductive component is formed between two laterally diffused metal oxide semiconductors (LDMOS), and the conductive component passes through the A common source of laterally diffused metal oxide semiconductors.