TWI706857B - Ceramic substrate assembly and element with metal thermal conductive bump pads and manufacturing method thereof - Google Patents

Ceramic substrate assembly and element with metal thermal conductive bump pads and manufacturing method thereof Download PDF

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TWI706857B
TWI706857B TW108103286A TW108103286A TWI706857B TW I706857 B TWI706857 B TW I706857B TW 108103286 A TW108103286 A TW 108103286A TW 108103286 A TW108103286 A TW 108103286A TW I706857 B TWI706857 B TW I706857B
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bonding layer
ceramic substrate
layer
metal
die
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TW202027988A (en
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余河潔
廖陳正龍
林俊佑
張孝民
張景堯
張道智
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璦司柏電子股份有限公司
財團法人工業技術研究院
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Priority to US16/737,288 priority patent/US10743411B1/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4076—Through-connections; Vertical interconnect access [VIA] connections by thin-film techniques

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

一種具有金屬導熱凸塊接墊的陶瓷基板元件，供設置至少一高發熱的晶粒，該陶瓷基板元件包括：一陶瓷基板本體，具有一上表面和相反於前述上表面的一下表面；及至少一金屬凸塊接墊，包括一結合於上述上表面、且厚度介於10至300微米的薄型接合層，該薄型接合層具有一個第一熱膨脹係數，該第一熱膨脹係數大於上述陶瓷基板本體的熱膨脹係數；及一結合於該薄型接合層、供上述晶粒焊接結合的固晶層，該固晶層具有一個第二熱膨脹係數，該第二熱膨脹係數大於上述陶瓷基板本體的熱膨脹係數，藉此減緩上述薄型接合層與該陶瓷基板界面受熱應力破裂。 A ceramic substrate element with metal thermal conductive bump pads for setting at least one high heat-generating crystal grain. The ceramic substrate element includes: a ceramic substrate body having an upper surface and a lower surface opposite to the foregoing upper surface; and at least A metal bump pad includes a thin bonding layer bonded to the upper surface and having a thickness of 10 to 300 microns. The thin bonding layer has a first thermal expansion coefficient greater than that of the ceramic substrate body. Thermal expansion coefficient; and a die bonding layer bonded to the thin bonding layer for bonding of the above-mentioned die welding, the die bonding layer has a second thermal expansion coefficient, the second thermal expansion coefficient is greater than the thermal expansion coefficient of the ceramic substrate body, thereby Alleviate thermal stress cracking at the interface between the thin bonding layer and the ceramic substrate.

Description

具有金屬導熱凸塊接墊的陶瓷基板組件、元件及其製法 Ceramic substrate assembly and element with metal thermal conductive bump pads and manufacturing method thereof

本發明是有關於一種陶瓷基板，尤其是一種具有金屬導熱凸塊接墊的陶瓷基板組件、元件及其製法。 The present invention relates to a ceramic substrate, in particular to a ceramic substrate assembly with metal thermal conductive bump pads, components and manufacturing methods thereof.

相較於傳統印刷電路板，陶瓷基板更具有散熱性佳、厚度薄、尺寸小、耐高溫及可靠度佳等優點，常使用於高功率晶粒或晶片等電子元件。最常見陶瓷基板材料有氧化鋁(Aluminum Oxide，Al2O3)製成的直接覆銅(Direct Bonded Copper，DBC)基板或直接覆鋁(Direct Bonded Aluminum，DBA)基板，而覆銅或鋁的厚度多在200至300微米之間，當銅或鋁的厚度大於300微米時，則會發生接合界面破裂問題。 Compared with traditional printed circuit boards, ceramic substrates have the advantages of good heat dissipation, thin thickness, small size, high temperature resistance and good reliability, and are often used in electronic components such as high-power dies or chips. The most common ceramic substrate materials are Direct Bonded Copper (DBC) substrates or Direct Bonded Aluminum (DBA) substrates made of alumina (Aluminum Oxide, Al 2 O 3 ). The thickness is usually between 200 and 300 microns. When the thickness of copper or aluminum is greater than 300 microns, cracking of the joint interface may occur.

隨著晶粒及晶片的功率日益提高，陶瓷基板上的金屬接墊、線路或導電層需要更厚的厚度，才能符合高功率元件的需求。然而，陶瓷基板與金屬層彼此的熱膨脹係數(coefficient of thermal expansion)及線膨脹係數(coefficient of linear expansion)差異極大，在溫度20度時，金屬銅與鋁的熱膨脹係數為16.5與23ppm/K，而陶瓷材料氧化鋁、氮化鋁與氮化矽大約分別是7、4.5與3.5ppm/K，當陶瓷基板與結合的金屬層熱膨脹係數差異過大時，金屬及陶瓷基板之間的界面容易產生破裂、翹曲或變形的問題，也勢必會造成因熱應力而讓接點產生受損的風險。 With the increasing power of dies and chips, metal pads, circuits, or conductive layers on ceramic substrates need to be thicker to meet the requirements of high-power devices. However, the coefficient of thermal expansion and coefficient of linear expansion between the ceramic substrate and the metal layer are very different. At a temperature of 20 degrees, the thermal expansion coefficients of copper and aluminum are 16.5 and 23ppm/K. The ceramic materials of alumina, aluminum nitride and silicon nitride are about 7, 4.5 and 3.5 ppm/K, respectively. When the thermal expansion coefficient of the ceramic substrate and the bonded metal layer is too different, the interface between the metal and the ceramic substrate is likely to crack , Warpage or deformation, it is bound to cause the risk of damage to the contact due to thermal stress.

因此，如何一方面使金屬電路層能增加厚度，使得溫差能分布在更厚的金屬層，減少單位高度中的溫度落差，讓陶瓷基板能適用於高功率晶粒及晶片；並且減緩金屬層與陶瓷基板界面受熱應力破裂，讓高功率電子元件的應用成為可行，還同時能依照不同的客戶需求，提供各式厚度的金屬接墊，提供製造彈性，就是本案所要達到的目的。 Therefore, how to increase the thickness of the metal circuit layer on the one hand, so that the temperature difference can be distributed in the thicker metal layer, reduce the temperature drop per unit height, so that the ceramic substrate can be suitable for high-power dies and wafers; and slow down the metal layer and The ceramic substrate interface is cracked by thermal stress, making the application of high-power electronic components feasible. At the same time, it can provide metal pads of various thicknesses to provide manufacturing flexibility according to different customer needs. This is the goal of this case.

鑑於上述問題，本發明的主要目的，在於提供一種具有金屬導熱凸塊接墊的陶瓷基板元件，透過上窄下寬的雙層金屬結構並且降低其中薄型接合層厚度，大幅降低金屬電路層與陶瓷基板結合界面破裂的風險。 In view of the above problems, the main purpose of the present invention is to provide a ceramic substrate element with metal thermally conductive bump pads, which can reduce the thickness of the thin bonding layer through the double-layer metal structure with a narrow upper and a wide bottom, thereby greatly reducing the metal circuit layer and ceramic Risk of cracking of the substrate bonding interface.

本發明的另一目的，在於提供一種具有金屬導熱凸塊接墊的陶瓷基板元件，使陶瓷基板能適用於高功率晶粒或晶片等電子元件。 Another object of the present invention is to provide a ceramic substrate component with metal thermal conductive bump pads, so that the ceramic substrate can be applied to electronic components such as high-power dies or chips.

本發明的再一目的，在提供一種具有金屬導熱凸塊的陶瓷基板組件，讓高功率晶粒或晶片可被設置於陶瓷基板上，且順利將發熱導出。 Another object of the present invention is to provide a ceramic substrate assembly with metal thermally conductive bumps, so that high-power dies or wafers can be placed on the ceramic substrate and heat generation can be smoothly discharged.

本發明的又一目的，在提供一種製造具有金屬導熱凸塊的陶瓷基板組件的製法，使高功率晶粒可被順利封裝於陶瓷基板上，並在操作過程不易造成陶瓷基板和金屬導熱凸塊接墊間的界面損壞，提升產出良率。 Another object of the present invention is to provide a method for manufacturing a ceramic substrate assembly with metal thermally conductive bumps, so that high-power die can be smoothly packaged on the ceramic substrate, and it is not easy to cause ceramic substrates and metal thermally conductive bumps during operation. The interface between the pads is damaged, which improves the yield rate.

為達上述目的，本發明提供一種具有金屬導熱凸塊接墊的陶瓷基板元件，供設置至少一高發熱的晶粒，該陶瓷基板元件包括：一陶瓷基板本體，具有一上表面和相反於前述上表面的一下表面；及至少一金屬凸塊接墊，包括一結合於上述上表面、且厚度介於10至300微米的薄型接合層，該薄型接合層具有一個第一熱膨脹係數，該第一熱膨脹係數大於上述 陶瓷基板本體的熱膨脹係數；及一結合於該薄型接合層、供上述晶粒焊接結合的固晶層，該固晶層具有一個第二熱膨脹係數，該第二熱膨脹係數大於上述陶瓷基板本體的熱膨脹係數，該固晶層之橫截面之面積不小於對應設置於該固晶層的上述晶粒，且該固晶層的上述橫截面之面積小於上述薄型接合層，藉此減緩上述薄型接合層與該陶瓷基板本體界面受熱應力破裂。 In order to achieve the above objective, the present invention provides a ceramic substrate element with metal thermal conductive bump pads for arranging at least one high heat-generating die. The ceramic substrate element includes: a ceramic substrate body with an upper surface and opposite to the foregoing The lower surface of the upper surface; and at least one metal bump pad, including a thin bonding layer bonded to the upper surface and having a thickness of 10 to 300 microns, the thin bonding layer having a first thermal expansion coefficient, the first The coefficient of thermal expansion is greater than the above The thermal expansion coefficient of the ceramic substrate body; and a die bonding layer combined with the thin bonding layer for bonding of the above-mentioned die welding, the die bonding layer having a second thermal expansion coefficient, the second thermal expansion coefficient being greater than the thermal expansion of the ceramic substrate body Coefficient, the cross-sectional area of the die-bonding layer is not less than the above-mentioned crystal grains corresponding to the die-bonding layer, and the cross-sectional area of the die-bonding layer is smaller than the thin bonding layer, thereby slowing down the thin bonding layer and The interface of the ceramic substrate body is cracked by thermal stress.

當把高發熱晶粒安裝於上述具有金屬導熱凸塊接墊的陶瓷基板元件，就可以構成本發明的一種陶瓷基板組件，包括：至少一高發熱的晶粒；一陶瓷基板本體，具有一上表面和相反於前述上表面的一下表面；至少一金屬凸塊接墊，包括一結合於上述上表面、且厚度介於10至300微米的薄型接合層，該薄型接合層具有一個第一熱膨脹係數，該第一熱膨脹係數大於上述陶瓷基板本體的熱膨脹係數；及一結合於該薄型接合層、供上述晶粒焊接結合的固晶層，該固晶層具有一個第二熱膨脹係數，該第二熱膨脹係數大於上述陶瓷基板本體的熱膨脹係數，該固晶層之橫截面之面積不小於對應設置於該固晶層的上述晶粒，且該固晶層的上述橫截面之面積小於上述薄型接合層，藉此降低上述薄型接合層與該陶瓷基板本體界面受熱應力破裂風險。 When the high heat-generating die is mounted on the above-mentioned ceramic substrate element with metal thermal conductive bump pads, a ceramic substrate assembly of the present invention can be constructed, including: at least one high-heating die; a ceramic substrate body with an upper The surface and the lower surface opposite to the aforementioned upper surface; at least one metal bump pad, including a thin bonding layer bonded to the upper surface and having a thickness of 10 to 300 microns, the thin bonding layer having a first thermal expansion coefficient , The first thermal expansion coefficient is greater than the thermal expansion coefficient of the ceramic substrate body; and a die bonding layer combined with the thin bonding layer for the die welding bonding, the die bonding layer has a second thermal expansion coefficient, and the second thermal expansion The coefficient is greater than the thermal expansion coefficient of the ceramic substrate body, the cross-sectional area of the die bond layer is not less than the above-mentioned crystal grains corresponding to the die bond layer, and the cross-sectional area of the die bond layer is smaller than the thin bonding layer, This reduces the risk of thermal stress cracking at the interface between the thin bonding layer and the ceramic substrate body.

本發明提供一種具有金屬導熱凸塊接墊的陶瓷基板製法，使至少一金屬凸塊接墊接合於一陶瓷基板本體，並供設置至少一高功率晶粒，該陶瓷基板本體具有一上表面和相反於前述上表面的一下表面，

Figure 108103286-A0305-02-0005-1
供上述晶粒焊接結合的固晶層，該固晶層具有一個第二熱膨脹係數，該製法包括下列步驟：a)在前述上表面上濺鍍一層厚度小於1微米的金屬的種子 層；b)在上述種子層上成型一層金屬的增厚層，使得該增厚層與上述種子層共同構成一厚度介於10至300微米的薄型接合層，該薄型接合層具有一個預訂橫截面之面積，以及該薄型接合層具有一個大於上述陶瓷基板本體熱膨脹係數的第一熱膨脹係數，藉此減緩上述薄型接合層與該陶瓷基板本體界面受熱應力破裂；c)在上述薄型接合層上形成一層面積不小於上述高功率晶粒的金屬的固晶層，且該固晶層的前述面積小於上述薄型接合層預訂橫截面之面積，使得該固晶層和上述薄型接合層共同構成一金屬導熱凸塊接墊，該固晶層具有一個大於上述陶瓷基板本體熱膨脹係數的第二熱膨脹係數。 The present invention provides a method for manufacturing a ceramic substrate with metal thermally conductive bump pads. At least one metal bump pad is joined to a ceramic substrate body, and at least one high-power die is provided. The ceramic substrate body has an upper surface and Contrary to the lower surface of the aforementioned upper surface,
Figure 108103286-A0305-02-0005-1
The bonding layer for the above-mentioned die welding and bonding, the bonding layer has a second thermal expansion coefficient, and the manufacturing method includes the following steps: a) sputtering a seed layer of metal with a thickness of less than 1 micron on the upper surface; b) Forming a thickened layer of metal on the seed layer, so that the thickened layer and the seed layer together form a thin bonding layer with a thickness of 10 to 300 microns, the thin bonding layer having a predetermined cross-sectional area, and The thin bonding layer has a first thermal expansion coefficient greater than the thermal expansion coefficient of the ceramic substrate body, thereby reducing thermal stress cracking of the interface between the thin bonding layer and the ceramic substrate body; c) forming a layer on the thin bonding layer with an area not less than the above A high-power die metal bonding layer, and the aforementioned area of the bonding layer is smaller than the predetermined cross-sectional area of the thin bonding layer, so that the bonding layer and the thin bonding layer together form a metal thermally conductive bump pad, The solid crystal layer has a second thermal expansion coefficient greater than the thermal expansion coefficient of the ceramic substrate body.

相較於習知技術，本發明揭露的具有金屬導熱凸塊接墊的陶瓷基板組件、元件及其製法，藉由多層結構的金屬凸塊接墊，使得與陶瓷基板連結的薄型接合層界面厚度在一定範圍內，降低介面受熱應力破裂的機率，藉此提升產出良率，同時延長使用壽命，並且利用多層金屬結構，讓陶瓷基板上結合有厚度較厚的金屬凸塊接墊，讓單位厚度內的溫差減小，藉此保護金屬和陶瓷的介面，延長使用壽命，且使得設置發熱度較高的晶粒、晶片等元件成為可行。 Compared with the prior art, the ceramic substrate assembly and device with metal thermally conductive bump pads and the manufacturing method thereof disclosed in the present invention, through the multi-layer structure of the metal bump pads, the thickness of the thin bonding layer interface with the ceramic substrate Within a certain range, the probability of interface cracking due to thermal stress is reduced, thereby increasing the yield rate and prolonging the service life. The multilayer metal structure is used to combine thick metal bump pads on the ceramic substrate, allowing the unit The temperature difference within the thickness is reduced, thereby protecting the metal and ceramic interface, prolonging the service life, and making it feasible to install components such as dies and chips with higher heat generation.

10、40:陶瓷基板元件 10.40: Ceramic substrate components

11、21、30:陶瓷基板本體 11, 21, 30: ceramic substrate body

12、22、41:金屬凸塊接墊 12, 22, 41: Metal bump pad

13、23:薄型接合層 13, 23: Thin bonding layer

14、24、36:固晶層 14, 24, 36: die bonding layer

111:上表面 111: upper surface

112:下表面 112: lower surface

20:陶瓷基板組件 20: Ceramic substrate assembly

25、37:晶粒 25, 37: Die

26、38:金屬引線 26, 38: Metal leads

27、39:金屬接墊 27, 39: Metal pads

231、34:上薄型接合層 231, 34: Upper thin bonding layer

232、32:下薄型接合層 232, 32: Lower thin bonding layer

31:通孔 31: Through hole

33、35:光阻層 33, 35: photoresist layer

42:保護層 42: protective layer

圖1為本案具有金屬導熱凸塊接墊的陶瓷基板元件的第一較佳實施例的側視示意圖。 FIG. 1 is a schematic side view of a first preferred embodiment of a ceramic substrate component with metal thermal conductive bump pads.

圖2為本案具有金屬導熱凸塊接墊的陶瓷基板組件的第一較佳實施例的側 視示意圖。 Figure 2 is a side view of the first preferred embodiment of the ceramic substrate assembly with metal thermally conductive bump pads See schematic diagram.

圖3A至圖3K為具有金屬導熱凸塊接墊的陶瓷基板製法過程的側面剖視結構示意圖。 3A to 3K are schematic side sectional views of the manufacturing process of the ceramic substrate with metal thermal conductive bump pads.

圖4為本案具有金屬導熱凸塊接墊的陶瓷基板元件的第二較佳實施例的側視示意圖。 4 is a schematic side view of the second preferred embodiment of the ceramic substrate component with metal thermal conductive bump pads.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之優點與功效。 The following specific examples illustrate the implementation of the present invention. Those familiar with the art can easily understand the advantages and effects of the present invention from the content disclosed in this specification.

本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書之揭示內容，以供熟悉此技藝之人士瞭解與閱讀，並非用以限定本發明可實施之限定條件，任何結構之修飾、大小之調整或比例關係之改變，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 The structure, ratio, size, etc. shown in the drawings in this specification are only used to match the disclosure content of the specification for the understanding and reading of those familiar with the art, and are not used to limit the implementation of the present invention. Any structural modification, size adjustment, or change in the proportional relationship, without substantial changes to the technical content, shall be regarded as the scope of the present invention.

本發明一種具有金屬導熱凸塊接墊的陶瓷基板元件的第一較佳實施例如圖1所示，陶瓷基板元件10包括陶瓷基板本體11和金屬凸塊接墊12，陶瓷基板本體11具有上表面111和相反於上表面111的下表面112，金屬凸塊接墊12包括薄型接合層13和固晶層14。本例中是以濺鍍的方式將銅結合於上表面111，再鍍厚形成厚度介於10至300微米的薄型接合層13，其中銅的熱膨脹係數約為17ppm/K，而一般陶瓷基板材料(例如氧化鋁、氮化鋁與氮化矽)的熱膨脹係數約為4~7ppm/K，藉由設置厚度較薄的薄型接合層13，使其發揮較佳的延展性；接著利用光阻進行顯影而第二次電鍍銅，在薄型接合層13上進一步形成可供晶粒焊接結合的固晶層14，固晶層14的 橫截面之面積小於薄型接合層13。當固晶層14受熱膨脹時，一方面溫度差會分布在較厚的金屬層級中，使得單位厚度的溫差降低；另方面藉由薄型接合層13的延展性，保持金屬凸塊接墊12與陶瓷基板接合界面不易因熱應力破裂。 The first preferred embodiment of a ceramic substrate component with metal thermally conductive bump pads of the present invention is shown in FIG. 1. The ceramic substrate component 10 includes a ceramic substrate body 11 and a metal bump pad 12. The ceramic substrate body 11 has an upper surface 111 and the lower surface 112 opposite to the upper surface 111, the metal bump pad 12 includes a thin bonding layer 13 and a bonding layer 14. In this example, copper is bonded to the upper surface 111 by sputtering, and then plated to form a thin bonding layer 13 with a thickness of 10 to 300 microns. The thermal expansion coefficient of copper is about 17 ppm/K, while the general ceramic substrate material (Such as aluminum oxide, aluminum nitride, and silicon nitride) have a thermal expansion coefficient of about 4~7ppm/K. The thin bonding layer 13 is provided with a thinner thickness to make it exhibit better ductility; then use photoresist After developing and the second copper electroplating, on the thin bonding layer 13, a solid crystal layer 14 which can be used for die welding and bonding is further formed. The cross-sectional area is smaller than the thin bonding layer 13. When the die bond layer 14 is heated and expands, on the one hand, the temperature difference will be distributed in the thicker metal layer, which reduces the temperature difference per unit thickness; on the other hand, the ductility of the thin bonding layer 13 keeps the metal bump pad 12 and The ceramic substrate bonding interface is not easy to crack due to thermal stress.

本案中所述薄型接合層和固晶層經過佈局(Pattern)等一系列後續常規加工程序即為金屬電路層，金屬凸塊接墊為金屬電路層中供焊接晶粒的焊墊或接墊(Pad)。當然，熟知此技術者可以採用電鍍、濺鍍、蒸鍍或化學鍍或其他可行的方式，並且採用合適的金屬用以形成薄型接合層和固晶層的金屬電路層。 In this case, the thin bonding layer and die bonding layer are the metal circuit layer after a series of subsequent conventional processing procedures such as layout (Pattern), and the metal bump pads are the pads or pads in the metal circuit layer for soldering the die. Pad). Of course, those skilled in this technology can use electroplating, sputtering, vapor deposition or chemical plating or other feasible methods, and use suitable metals to form the metal circuit layer of the thin bonding layer and the solid crystal layer.

圖2為本發明具有金屬導熱凸塊接墊的陶瓷基板組件的第一較佳實施例的示意圖，本例中陶瓷基板組件20的晶粒25為一高功率的絕緣柵雙極電晶體IGBT(Insulated Gate Bipolar Transistor)，並以例如表面安裝(Surface-mount technology，SMT)的方式將晶粒25焊接固定於金屬凸塊接墊22。在本例中，為便於說明起見，將金屬凸塊接墊22的薄型接合層23區分為一個濺鍍成形的下薄型接合層232(或稱之為種子層)，以及一個電鍍在下薄型接合層232上方的上薄型接合層231(或稱之為增厚層)，但當兩者均材用相同的例如單純銅金屬構成，在實務上並不容易清楚分辨。在本例中下薄型接合層232是採用鈦/銅結合於陶瓷基板本體21的上表面，形成厚度小於0.5微米的下薄型接合層232，並透過電鍍的方式將銅增厚為上薄型接合層231，接著根據晶粒25的規格需求，在上薄型接合層231電鍍上厚度符合晶粒25功率的固晶層24，晶粒25設置於固晶層24後，經由金屬引線26，將晶 粒25的電極打線接合至對應的另一金屬接墊27，使得晶粒25能夠電導通運作。 2 is a schematic diagram of a first preferred embodiment of a ceramic substrate assembly with metal thermally conductive bump pads according to the present invention. In this example, the die 25 of the ceramic substrate assembly 20 is a high-power insulated gate bipolar transistor IGBT ( Insulated Gate Bipolar Transistor), and the die 25 is welded and fixed to the metal bump pad 22 in a surface-mount technology (SMT) manner, for example. In this example, for ease of description, the thin bonding layer 23 of the metal bump pad 22 is divided into a lower thin bonding layer 232 (or called a seed layer) formed by sputtering, and a thin bonding layer under electroplating. The upper thin bonding layer 231 (or called the thickened layer) above the layer 232, but when both are made of the same material, such as pure copper, it is not easy to distinguish clearly in practice. In this example, the lower thin bonding layer 232 is combined with titanium/copper on the upper surface of the ceramic substrate body 21 to form the lower thin bonding layer 232 with a thickness of less than 0.5 microns, and the copper is thickened to the upper thin bonding layer by electroplating 231. Next, according to the specification requirements of the die 25, the upper thin bonding layer 231 is electroplated with a die bond layer 24 whose thickness meets the power of the die 25. After the die 25 is placed on the die bond layer 24, the die The electrode of the die 25 is wire-bonded to another corresponding metal pad 27, so that the die 25 can be electrically conductive.

由於IGBT具有高效率以及切換速度快等優點，常應用於作功量較大的電子設備，如：冷氣機、電冰箱、音響、以及馬達驅動器等，因此前述電子設備運作時，IGBT將產生大量的熱能，透過厚度較大的固晶層24，一方面使金屬凸塊接墊22能夠承受更大的電流所帶來的熱能，另一方面由於固晶層24下方是接合上薄型接合層231，兩者的熱膨脹係數接近，故接合的介面熱應力較低，不易損壞；薄型接合層23由於尺寸大於上方的固晶層24，未被固晶層24所覆蓋的邊緣部分厚度較薄，相對延展性較佳，即使跟接合陶瓷基板本體21接合處膨脹情況不一，也可以自行展延吸收應力，而降低易因為熱應力所造成介面破裂或斷裂的風險。 Because IGBT has the advantages of high efficiency and fast switching speed, it is often used in electronic equipment with a large amount of work, such as: air conditioners, refrigerators, stereos, and motor drivers. Therefore, when the aforementioned electronic equipment operates, IGBTs will generate a lot of The heat energy, through the larger thickness of the die bond layer 24, on the one hand enables the metal bump pads 22 to withstand the heat caused by a larger current, on the other hand, because the die bond layer 24 is bonded with the upper thin bonding layer 231 , The thermal expansion coefficients of the two are close, so the thermal stress of the joint interface is low, and it is not easy to be damaged. Because the size of the thin joint layer 23 is larger than the upper die bonding layer 24, the thickness of the edge part not covered by the die bonding layer 24 is relatively thin. The ductility is better. Even if the expansion of the joint with the ceramic substrate body 21 is different, it can stretch to absorb stress by itself, thereby reducing the risk of interface cracking or fracture caused by thermal stress.

本發明一種具有金屬導熱凸塊接墊的陶瓷基板製法如圖3A至圖3K所示，本例中的製法是透過DPC(Direct Plating Copper)製程來執行，相較於DBC(Direct Bonding Copper)製程，DPC製程所完成的金屬導熱凸塊接墊的陶瓷基板能提供更佳的材料穩定性和設計靈活度，且金屬和陶瓷基板之間具有優越的黏合強度，其介面空隙率也較低。 The manufacturing method of a ceramic substrate with metal thermally conductive bump pads of the present invention is shown in FIGS. 3A to 3K. The manufacturing method in this example is performed through the DPC (Direct Plating Copper) process, which is compared with the DBC (Direct Bonding Copper) process. , The ceramic substrate of the metal thermally conductive bump pad completed by the DPC process can provide better material stability and design flexibility, and has superior bonding strength between the metal and ceramic substrate, and its interface porosity is also lower.

圖3A中是以氧化鋁(Al2O3)氮化鋁(AlN)為基板材料的陶瓷基板本體30，陶瓷基板本體30在經過V型槽(V-cut)或導通孔(via)加工後形成如圖3B所示的通孔31，再透過濺鍍方式將鈦/銅靶材擊打加速，結合於陶瓷基板本體30上，形成圖3C所示的下薄型接合層32。隨後，如圖3D所示塗佈光阻並經曝光、顯影後，形成如圖3E所示的光阻層33，再以例如電鍍的方 式增厚下薄型接合層32，構成圖3F中的上薄型接合層34，並由下薄型接合層32和上薄型接合層34共同構成薄型接合層。 3A is a ceramic substrate body 30 with aluminum oxide (Al 2 O 3 ) and aluminum nitride (AlN) as the substrate material. The ceramic substrate body 30 is processed by a V-cut or via. The through hole 31 as shown in FIG. 3B is formed, and the titanium/copper target is hit and accelerated by sputtering, and is bonded to the ceramic substrate body 30 to form the lower thin bonding layer 32 as shown in FIG. 3C. Subsequently, after coating photoresist as shown in FIG. 3D, exposure and development, a photoresist layer 33 as shown in FIG. 3E is formed, and then the lower thin bonding layer 32 is thickened by, for example, electroplating to form the upper part in FIG. 3F The thin bonding layer 34 is composed of the lower thin bonding layer 32 and the upper thin bonding layer 34 to form a thin bonding layer.

如圖3G所示再度塗佈光阻，經曝光、顯影後形成如圖3H所示的二次光阻層35，由於二次光阻層35的範圍較原先第一次的光阻層33大，所以如圖3I所示，接下來電鍍形成的固晶層36，其橫截面之面積會小於薄型接合層34，接下來則進行去光阻與蝕刻，如圖3J所示，使得未被增厚的濺鍍金屬層被蝕刻去除，讓在電路佈局上的金屬電極彼此獨立分離，最後，如圖3K所示，將晶粒37焊接打件於固晶層36上，由於本例中的晶粒37有一處電極是直接經由焊接而導接至固晶層36，另一極則經由金屬引線38，打線接合至另一金屬接墊39。而後續點膠、灌膠或烘烤等封裝程序則可依晶粒37的種類而進行。 The photoresist is coated again as shown in FIG. 3G, and after exposure and development, the secondary photoresist layer 35 as shown in FIG. 3H is formed. Because the range of the secondary photoresist layer 35 is larger than that of the original first photoresist layer 33 Therefore, as shown in FIG. 3I, the cross-sectional area of the bonding layer 36 formed by electroplating will be smaller than that of the thin bonding layer 34, and then the photoresist and etching will be performed, as shown in FIG. 3J, so that it is not increased. The thick sputtered metal layer is etched and removed, so that the metal electrodes on the circuit layout are separated from each other independently. Finally, as shown in FIG. 3K, the die 37 is welded to the die bond layer 36, because the crystal in this example One electrode of the pellet 37 is directly connected to the die bonding layer 36 by welding, and the other electrode is wire-bonded to another metal pad 39 through a metal lead 38. The subsequent packaging procedures such as glue dispensing, glue filling, or baking can be performed according to the type of die 37.

當然，如熟悉本技術領域人士所能輕易理解，此處的每一步驟並非侷限於上述實施例，例如薄型接合層也可以不需要區分上下，而在陶瓷基板表面單純的結合銅箔。此外，固晶層也可以跟薄型接合層或上薄型接合層一同鍍厚成形，並且在光阻遮蔽下，保留固晶層的部分而蝕刻形成固晶層與薄型接合層間的差異尺寸，均可製造出本案結構。 Of course, as those skilled in the art can easily understand, each step here is not limited to the above-mentioned embodiment. For example, the thin bonding layer does not need to be distinguished from the top and bottom, and the copper foil is simply combined on the surface of the ceramic substrate. In addition, the die bonding layer can also be plated and formed together with the thin bonding layer or the upper thin bonding layer, and under the shielding of the photoresist, the part of the bonding layer is retained and etched to form the difference in size between the bonding layer and the thin bonding layer. Created the structure of this case.

本發明所述具有金屬導熱凸塊接墊的陶瓷基板元件的第二較佳實施例如圖4所示，本例中陶瓷基板元件40除了具有與圖3J中元件相同的結構外，金屬凸塊接墊41的外表面更覆蓋有保護層42，保護層42的材質可為金(Au)、銀(Ag)、鈀(Pd)或鎳(Ni)等材質，透過熱風整平、有機塗覆、化學鍍鎳/浸金或浸銀等方式形成保護層42於金屬凸塊接墊41的外表面，可 避免銅材質的金屬凸塊接墊41因氧化而影響可焊性或導電性。 The second preferred embodiment of the ceramic substrate component with metal thermally conductive bump pads according to the present invention is shown in FIG. 4. In this example, the ceramic substrate component 40 has the same structure as the component in FIG. The outer surface of the pad 41 is further covered with a protective layer 42. The material of the protective layer 42 can be gold (Au), silver (Ag), palladium (Pd) or nickel (Ni), etc., which are leveled by hot air, organically coated, The protective layer 42 is formed on the outer surface of the metal bump pad 41 by electroless nickel plating/immersion gold or silver immersion. Prevent the copper metal bump pad 41 from affecting the solderability or conductivity due to oxidation.

綜上所述，本發明所提供之具有金屬導熱凸塊接墊的陶瓷基板組件、元件及其製法，透過雙層結構的金屬凸塊接墊，利用固晶層厚度而減緩單位厚度的溫度差、以及利用薄型接合層面積超過固晶層的厚度受限結構，展現薄型接合層的延展性，減緩金屬電路層與陶瓷基板的結合界面破裂的問題，而固晶層可根據晶粒的功率或發熱量，設計合適的厚度，使金屬凸塊接墊符合高電流密度均勻性的要求。 In summary, the ceramic substrate assembly and device with metal thermal conductive bump pads provided by the present invention and the manufacturing method thereof use the double-layer structure of the metal bump pads to reduce the temperature difference per unit thickness by using the thickness of the die bond layer , And use the thin bonding layer area to exceed the thickness limit structure of the die bond layer to show the ductility of the thin bond layer and slow down the problem of cracking of the bonding interface between the metal circuit layer and the ceramic substrate. The die bond layer can be based on the power or Heat generation and design an appropriate thickness to make the metal bump pad meet the requirements of high current density uniformity.

惟以上所述者，僅為本發明之較佳實施例而已，不能以此限定本發明實施之範圍，凡是依本發明申請專利範圍及說明書內容所作之簡單的等效變化與修飾，皆應仍屬本發明涵蓋之範圍內。經過本發明較佳實施例之描述後，熟悉此一技術領域人員應可瞭解到，本案實為一新穎、進步且具產業實用性之發明，深具發展價值。 However, the above are only the preferred embodiments of the present invention, and cannot be used to limit the scope of implementation of the present invention. All simple equivalent changes and modifications made in accordance with the scope of the patent application of the present invention and the contents of the specification should remain It falls within the scope of the present invention. After the description of the preferred embodiments of the present invention, those familiar with this technical field should be able to understand that this case is indeed a novel, progressive, and industrially applicable invention with deep development value.

10:陶瓷基板元件 10: Ceramic substrate components

11:陶瓷基板本體 11: Ceramic substrate body

12:金屬凸塊接墊 12: Metal bump pad

13:薄型接合層 13: Thin bonding layer

14:固晶層 14: Bonding layer

111:上表面 111: upper surface

112:下表面 112: lower surface

Claims (3)

一種製造如申請專利範圍第1項所述之具有金屬導熱凸塊接墊的陶瓷基板元件的製法，使至少一金屬凸塊接墊接合於一陶瓷基板本體，並供設置至少一高功率的晶粒，該陶瓷基板本體具有一上表面和相反於前述上表面的一下表面，供上述晶粒焊錫焊接結合的固晶層，該固晶層具有一個第二熱膨脹係數，該製法包括下列步驟：a)在前述上表面上濺鍍一層厚度小於1微米的金屬的種子層；b)在上述種子層上成型一層金屬的增厚層，使得該增厚層與上述種子層共同構成一厚度介於10至300微米的薄型接合層，該薄型接合層具有一個預訂橫截面之面積，以及該薄型接合層具有一個大於上述陶瓷基板本體熱膨脹係數的第一熱膨脹係數，藉此減緩上述薄型接合層與該陶瓷基板本體的界面受熱應力破裂；c)在上述薄型接合層上形成一層面積不小於上述高功率晶粒的金屬的固晶層，且該固晶層的前述面積小於上述薄型接合層預訂橫截面之面積，使得該固晶層和上述薄型接合層共同構成一金屬導熱凸塊接墊，該固晶層具有一個大於上述陶瓷基板本體熱膨脹係數的第二熱膨脹係數。 A method for manufacturing a ceramic substrate element with metal thermally conductive bump pads as described in the first item of the scope of patent application. At least one metal bump pad is joined to a ceramic substrate body, and at least one high-power crystal is provided. The ceramic substrate body has an upper surface and a lower surface opposite to the foregoing upper surface, and a solid crystal layer for soldering and bonding of the above-mentioned crystal grains, and the solid crystal layer has a second thermal expansion coefficient. The manufacturing method includes the following steps: a ) Sputtering a metal seed layer with a thickness of less than 1 micron on the aforementioned upper surface; b) forming a thickened metal layer on the aforementioned seed layer, so that the thickened layer and the aforementioned seed layer together form a thickness of 10 A thin bonding layer of 300 microns, the thin bonding layer has a predetermined cross-sectional area, and the thin bonding layer has a first thermal expansion coefficient greater than the thermal expansion coefficient of the ceramic substrate body, thereby slowing the thin bonding layer and the ceramic The interface of the substrate body is cracked by thermal stress; c) A die-bonding layer of metal with an area not less than the high-power crystal grains is formed on the thin bonding layer, and the aforementioned area of the die-bonding layer is smaller than the predetermined cross-section of the thin bonding layer The area is such that the die bond layer and the thin bonding layer together form a metal thermally conductive bump pad, and the die bond layer has a second thermal expansion coefficient greater than the thermal expansion coefficient of the ceramic substrate body. 如申請專利範圍第1項所述之製法，進一步包含步驟d)上述薄型接合層和該固晶層之表面鍍上一保護層。 The manufacturing method described in item 1 of the scope of the patent application further includes step d) the surface of the thin bonding layer and the bonding layer is coated with a protective layer. 如申請專利範圍第1項所述之製法，進一步包含步驟d)將該晶粒設置於該固晶層，該晶粒焊錫焊接打線接合至對應的上述金屬凸塊接墊；及步驟e)封裝該晶粒對應於該陶瓷基板本體之處。 The manufacturing method described in item 1 of the scope of patent application further includes step d) disposing the die on the die bonding layer, soldering the die die and wire bonding to the corresponding metal bump pad; and step e) packaging The crystal grain corresponds to the ceramic substrate body.
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Ning Zhu；「Planar Metallization Failure Modes in Integrated Power Electronics Modules」

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