TWI701789B - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

Info

Publication number
TWI701789B
TWI701789B TW108125933A TW108125933A TWI701789B TW I701789 B TWI701789 B TW I701789B TW 108125933 A TW108125933 A TW 108125933A TW 108125933 A TW108125933 A TW 108125933A TW I701789 B TWI701789 B TW I701789B
Authority
TW
Taiwan
Prior art keywords
trench
substrate
layer
dielectric layer
gate
Prior art date
Application number
TW108125933A
Other languages
Chinese (zh)
Other versions
TW202105659A (en
Inventor
姜文萍
龔進安
車行遠
張元愷
Original Assignee
力晶積成電子製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力晶積成電子製造股份有限公司 filed Critical 力晶積成電子製造股份有限公司
Priority to TW108125933A priority Critical patent/TWI701789B/en
Priority to CN201910715947.3A priority patent/CN112289861B/en
Application granted granted Critical
Publication of TWI701789B publication Critical patent/TWI701789B/en
Publication of TW202105659A publication Critical patent/TW202105659A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors

Abstract

Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes isolation structures, lightly doped regions, a gate, a gate dielectric layer, heavily doped regions, a dielectric layer, a first contact, second contacts and a connection line. The isolation structure is disposed in a substrate to define an active area. The lightly doped region is disposed in the substrate in the active area. The gate is disposed in the substrate in the active area, and a bottom surface of the gate is lower than a bottom surface of the lightly doped regions. The gate dielectric layer is disposed between the gate and the substrate. The heavily doped regions are disposed in the lightly doped regions and are located at opposite sides of the gate. The dielectric layer is disposed on the substrate. The first contact is disposed in the dielectric layer and connected to the gate. The second contacts are disposed in the dielectric layer and connected to the heavily doped regions. The connecting line is disposed in the dielectric layer and the isolation structure therebelow.

Description

半導體結構及其製造方法Semiconductor structure and manufacturing method thereof

本發明是有關於一種半導體結構及其製造方法。The present invention relates to a semiconductor structure and its manufacturing method.

在目前的半導體製程中，在形成閘極結構之後，會於基底上形成介電層，然後於介電層中形成與閘極結構中的源極/汲極連接的接觸窗，之後於介電層上形成與接觸窗連接的連接線。然而，在形成接觸窗的過程中，往往會因為製程偏差的關係而造成接觸窗的位置偏移。如此一來，導致接觸窗可能會部分地形成於閘極結構中的間隙壁上，而影響接觸窗的電性表現。此外，若接觸窗的位置偏移過大，則有可能使得接觸窗與閘極接觸而產生短路的問題。In the current semiconductor manufacturing process, after the gate structure is formed, a dielectric layer is formed on the substrate, and then a contact window connected to the source/drain of the gate structure is formed in the dielectric layer. A connecting line connected with the contact window is formed on the layer. However, in the process of forming the contact window, the position of the contact window is often shifted due to process deviation. As a result, the contact window may be partially formed on the gap wall in the gate structure, which affects the electrical performance of the contact window. In addition, if the position of the contact window is too large, the contact window may contact the gate electrode and cause a short circuit.

此外，在上述的製程中，閘極、接觸窗與連接線是在不同的製程步驟中形成，因此需要使用到不同的光罩來分別定義出閘極、接觸窗與連接線。如此一來，上述的接觸窗位置偏移的問題無法有效地解決，且製程步驟亦無法簡化。In addition, in the above-mentioned manufacturing process, the gate electrode, the contact window and the connecting line are formed in different process steps, so different masks need to be used to define the gate electrode, the contact window and the connecting line respectively. As a result, the above-mentioned problem of the positional deviation of the contact window cannot be effectively solved, and the manufacturing process cannot be simplified.

本發明提供一種半導體結構，其中閘極、接觸窗與連接現在相同的製程步驟中形成。The present invention provides a semiconductor structure in which gates, contact windows and connections are formed in the same process steps.

本發明提供一種半導體結構的製造方法，其中閘極、接觸窗與連接現在相同的製程步驟中形成。The present invention provides a method for manufacturing a semiconductor structure, in which the gate, contact window and connection are formed in the same process step.

本發明的半導體結構包括隔離結構、淡摻雜區、閘極、閘介電層、重摻雜區、介電層、第一接觸窗、第二接觸窗以及連接線。所述隔離結構設置於基底中以定義出主動區。所述淡摻雜區設置於所述主動區中的所述基底中。所述閘極設置於於所述主動區中的所述基底中，且所述閘極的底面低於所述淡摻雜區的底面。所述閘介電層設置於所述閘極與所述基底之間。所述重摻雜區設置於所述淡摻雜區中，且位於所述閘極的相對兩側。所述介電層設置於所述基底上。所述第一接觸窗設置於所述介電層中，且與所述閘極連接。所述第二接觸窗設置於所述介電層中，且與所述重摻雜區連接。所述連接線設置於所述介電層及其下方的所述隔離結構中。The semiconductor structure of the present invention includes an isolation structure, a lightly doped region, a gate electrode, a gate dielectric layer, a heavily doped region, a dielectric layer, a first contact window, a second contact window, and connecting lines. The isolation structure is arranged in the substrate to define an active area. The lightly doped region is disposed in the substrate in the active region. The gate is disposed in the substrate in the active region, and the bottom surface of the gate is lower than the bottom surface of the lightly doped region. The gate dielectric layer is disposed between the gate electrode and the substrate. The heavily doped region is arranged in the lightly doped region and located on opposite sides of the gate electrode. The dielectric layer is disposed on the substrate. The first contact window is disposed in the dielectric layer and connected to the gate electrode. The second contact window is disposed in the dielectric layer and connected to the heavily doped region. The connecting line is arranged in the dielectric layer and the isolation structure below it.

在本發明的半導體結構的一實施例中，所述閘極、所述第一接觸窗、所述第二接觸窗與所述連接線各自包括多晶矽層以及所述多晶矽層上的金屬層。In an embodiment of the semiconductor structure of the present invention, the gate electrode, the first contact window, the second contact window, and the connecting line each include a polysilicon layer and a metal layer on the polysilicon layer.

在本發明的半導體結構的一實施例中，所述閘極、所述第一接觸窗、所述第二接觸窗與所述連接線各自包括金屬層。In an embodiment of the semiconductor structure of the present invention, the gate electrode, the first contact window, the second contact window, and the connecting line each include a metal layer.

在本發明的半導體結構的一實施例中，位於所述閘極的一側的所述第二接觸窗與所述閘極之間具有第一距離，位於所述閘極的另一側的所述第二接觸窗與所述閘極之間具有第二距離，且所述第一距離等於所述第二距離。In an embodiment of the semiconductor structure of the present invention, there is a first distance between the second contact window located on one side of the gate and the gate, and all located on the other side of the gate There is a second distance between the second contact window and the gate, and the first distance is equal to the second distance.

在本發明的半導體結構的一實施例中，更包括設置於所述介電層與所述淡摻雜區之間的墊層。In an embodiment of the semiconductor structure of the present invention, it further includes a pad layer disposed between the dielectric layer and the lightly doped region.

本發明的半導體結構的製造方法包括以下步驟：於基底中形成隔離結構，以定義出主動區；於所述主動區中的所述基底中形成淡摻雜區；於所述基底上形成介電層；於所述介電層中形成第一溝槽與第二溝槽並且同時於所述介電層與所述隔離結構中形成第三溝槽，其中所述第二溝槽位於所述第一溝槽的相對兩側，且所述第一溝槽與所述第二溝槽暴露出部分所述基底；移除所述第一溝槽暴露出的所述基底的一部分，以形成第四溝槽，其中所述第四溝槽的底面低於所述淡摻雜區的底面；於所述第四溝槽暴露的所述基底的表面上形成閘介電層；於所述第二溝槽下方的所述基底中形成重摻雜區；於所述第一溝槽、所述第二溝槽、所述第三溝槽與所述第四溝槽中形成導電層。The manufacturing method of the semiconductor structure of the present invention includes the following steps: forming an isolation structure in a substrate to define an active region; forming a lightly doped region in the substrate in the active region; forming a dielectric on the substrate Layer; a first trench and a second trench are formed in the dielectric layer and a third trench is simultaneously formed in the dielectric layer and the isolation structure, wherein the second trench is located in the first Opposite sides of a trench, and the first trench and the second trench expose part of the substrate; a part of the substrate exposed by the first trench is removed to form a fourth A trench, wherein the bottom surface of the fourth trench is lower than the bottom surface of the lightly doped region; a gate dielectric layer is formed on the surface of the substrate exposed by the fourth trench; in the second trench A heavily doped region is formed in the substrate below the trench; a conductive layer is formed in the first trench, the second trench, the third trench, and the fourth trench.

在本發明的半導體結構的製造方法的一實施例中，位於所述第一溝槽的一側的所述第二溝槽與所述第一溝槽之間具有第一距離，位於所述第一溝槽的另一側的所述第二溝槽與所述第一溝槽之間具有第二距離，且所述第一距離等於所述第二距離。In an embodiment of the method of manufacturing a semiconductor structure of the present invention, the second trench located on one side of the first trench has a first distance between the first trench, and is located at the first trench. There is a second distance between the second groove on the other side of a groove and the first groove, and the first distance is equal to the second distance.

在本發明的半導體結構的製造方法的一實施例中，所述第四溝槽的形成方法包括以下步驟：於所述介電層上形成保護層，其中所述保護層填滿所述第二溝槽與所述第三溝槽，且暴露出所述第一溝槽；以所述保護層為蝕刻罩幕，進行非等向性蝕刻製程，以移除所述第一溝槽暴露出的所述基底的一部分。In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method for forming the fourth trench includes the following steps: forming a protective layer on the dielectric layer, wherein the protective layer fills the second The trench and the third trench are exposed, and the first trench is exposed; an anisotropic etching process is performed using the protective layer as an etching mask to remove the exposed portion of the first trench Part of the substrate.

在本發明的半導體結構的製造方法的一實施例中，所述導電層的形成方法包括以下步驟：於所述第一溝槽、所述第二溝槽、所述第三溝槽與所述第四溝槽的側壁與底部上形成多晶矽層；於所述多晶矽層上形成金屬層。In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method for forming the conductive layer includes the following steps: in the first trench, the second trench, the third trench, and the A polysilicon layer is formed on the sidewall and bottom of the fourth trench; a metal layer is formed on the polysilicon layer.

在本發明的半導體結構的製造方法的一實施例中，在形成所述淡摻雜區之後以及在形成所述介電層之前，更包括於所述基底上形成墊層。In an embodiment of the manufacturing method of the semiconductor structure of the present invention, after forming the lightly doped region and before forming the dielectric layer, it further includes forming a pad layer on the substrate.

基於上述，在本發明中，僅使用一個光罩即可同時形成分別界定閘極位置、接觸窗位置與連接線位置的溝槽，因此製程較為簡單且降低了成本，且可以有效地避免閘極與接觸窗的位置重疊而產生短路。此外，以此方式來界定接觸窗的位置，可以不需要額外地進行對準即可將接觸窗形成於準確的位置。Based on the above, in the present invention, only one photomask can be used to simultaneously form the trenches defining the gate position, contact window position, and connection line position. Therefore, the manufacturing process is relatively simple, the cost is reduced, and the gate can be effectively avoided. It overlaps with the contact window and causes a short circuit. In addition, by defining the position of the contact window in this way, the contact window can be formed at an accurate position without additional alignment.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

下文列舉實施例並配合所附圖式來進行詳細地說明，但所提供的實施例並非用以限制本發明所涵蓋的範圍。此外，圖式僅以說明為目的，並未依照原尺寸作圖。為了方便理解，在下述說明中相同的元件將以相同的符號標示來說明。The following examples are listed in conjunction with the accompanying drawings for detailed description, but the provided examples are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn according to the original size. To facilitate understanding, the same elements will be described with the same symbols in the following description.

關於文中所提到「包含」、「包括」、「具有」等的用語均為開放性的用語，也就是指「包含但不限於」。The terms "include", "include", "have", etc. mentioned in the text are all open terms, which means "including but not limited to".

此外，文中所提到「上」、「下」等的方向性用語，僅是用以參考圖式的方向，並非用以限制本發明。In addition, the directional terms such as "上" and "下" mentioned in the text are only used to refer to the direction of the drawings, and are not used to limit the present invention.

當以「第一」、「第二」等的用語來說明元件時，僅用於將這些元件彼此區分，並不限制這些元件的順序或重要性。因此，在一些情況下，第一元件亦可稱作第二元件，第二元件亦可稱作第一元件，且此不偏離申請專利範圍的範疇。When the terms "first", "second", etc. are used to describe elements, they are only used to distinguish these elements from each other, and do not limit the order or importance of these elements. Therefore, in some cases, the first element can also be referred to as the second element, and the second element can also be referred to as the first element, and this does not deviate from the scope of the patent application.

在以下實施例中，所提及的數量與形狀僅用以具體地說明本發明以便於了解其內容，而非用以限定本發明。In the following embodiments, the numbers and shapes mentioned are only used to illustrate the present invention in detail to facilitate understanding of the content, but not to limit the present invention.

圖1A至圖1E為依照本發明實施例的半導體結構的製造流程剖面示意圖。1A to 1E are schematic cross-sectional views of a manufacturing process of a semiconductor structure according to an embodiment of the invention.

首先，請參照圖1A，提供基底100。基底100例如為矽基底或絕緣層上矽（silicon-on-insulator，SOI）基底。此外，基底100中可視實際需求而形成有P型井區及/或N型井區（未繪示）。然後，於基底100中形成隔離結構102，以定義出主動區100a。主動區100a為用以形成各種半導體元件（例如邏輯元件、記憶體元件等）的區域。隔離結構102例如為淺溝槽隔離（shallow trench isolation，STI）結構。隔離結構102的形成方法為本領域技術人員所熟知，於此不再贅述。First, referring to FIG. 1A, a substrate 100 is provided. The substrate 100 is, for example, a silicon substrate or a silicon-on-insulator (SOI) substrate. In addition, a P-type well area and/or an N-type well area (not shown) may be formed in the substrate 100 according to actual needs. Then, an isolation structure 102 is formed in the substrate 100 to define the active region 100a. The active region 100a is a region for forming various semiconductor devices (such as logic devices, memory devices, etc.). The isolation structure 102 is, for example, a shallow trench isolation (STI) structure. The formation method of the isolation structure 102 is well known to those skilled in the art, and will not be repeated here.

然後，於主動區100a中的基底100中形成淡摻雜區104。淡摻雜區104鄰近於基底100的表面。淡摻雜區104的形成方法例如是進行離子植入製程，將摻質植入基底100中。淡摻雜區104可為P型摻雜區或N型摻雜區，本發明不對此作限定。接著，選擇性地於主動區100a中的基底100上形成墊層106。在本實施例中，墊層106例如為氧化矽層，其形成方法例如為進行熱氧化製程或化學氣相沉積製程。然後，選擇性地於墊層106上形成硬罩幕層108。在本實施例中，硬罩幕層108例如為氮化矽層，其形成方法例如為進行化學氣相沉積製程。在本實施例中，在形成墊層106與硬罩幕層108之後，硬罩幕層108的頂表面低於隔離結構102的頂表面，但本發明不限於此。在其他實施例中，硬罩幕層108的頂表面與隔離結構102的頂表面也可以是共平面的，或者硬罩幕層108的頂表面也可以是高於隔離結構102的頂表面。之後，於基底100上形成介電層110。在本實施例中，介電層110例如為氧化矽層，其形成方法例如為進行化學氣相沉積製程。接著，可選擇性地對介電層110進行平坦化製程。平坦化製程例如為化學機械研磨（chemical mechanical polishing，CMP）製程。Then, a lightly doped region 104 is formed in the substrate 100 in the active region 100a. The lightly doped region 104 is adjacent to the surface of the substrate 100. The method for forming the lightly doped region 104 is, for example, an ion implantation process to implant dopants into the substrate 100. The lightly doped region 104 may be a P-type doped region or an N-type doped region, which is not limited in the present invention. Next, a cushion layer 106 is selectively formed on the substrate 100 in the active region 100a. In this embodiment, the pad layer 106 is, for example, a silicon oxide layer, and its formation method is, for example, a thermal oxidation process or a chemical vapor deposition process. Then, a hard mask layer 108 is selectively formed on the cushion layer 106. In this embodiment, the hard mask layer 108 is, for example, a silicon nitride layer, and its formation method is, for example, a chemical vapor deposition process. In this embodiment, after the cushion layer 106 and the hard mask layer 108 are formed, the top surface of the hard mask layer 108 is lower than the top surface of the isolation structure 102, but the invention is not limited thereto. In other embodiments, the top surface of the hard mask layer 108 and the top surface of the isolation structure 102 may also be coplanar, or the top surface of the hard mask layer 108 may also be higher than the top surface of the isolation structure 102. After that, a dielectric layer 110 is formed on the substrate 100. In this embodiment, the dielectric layer 110 is, for example, a silicon oxide layer, and its formation method is, for example, a chemical vapor deposition process. Then, the dielectric layer 110 can be selectively planarized. The planarization process is, for example, a chemical mechanical polishing (CMP) process.

然後，請參照圖1B，於介電層110與硬罩幕層108中形成第一溝槽112與第二溝槽114並且同時於介電層110與隔離結構102中形成第三溝槽116。在本實施例中，第二溝槽114位於第一溝槽112的相對兩側，且第一溝槽112與第二溝槽114暴露出部分墊層106。在未形成墊層106的情況下，第一溝槽112與第二溝槽114則暴露出部分基底100（淡摻雜區104）。第一溝槽112用以界定後續形成閘極的位置，第二溝槽114用以界定後續形成接觸窗的位置，而第三溝槽116用以界定後續形成連接線的位置。在本實施例中，第一溝槽112、第二溝槽114與第三溝槽116的形成方法例如是先於介電層110上形成圖案化光阻層（未繪示）。然後，以圖案化光阻層為蝕刻罩幕，進行非等向性蝕刻製程，移除部分介電層110及其下方的硬罩幕層108，以及移除部分介電層110及其下方的部分隔離結構102，並以墊層106作為蝕刻停止層。之後，移除圖案化光阻層。Then, referring to FIG. 1B, a first trench 112 and a second trench 114 are formed in the dielectric layer 110 and the hard mask layer 108, and a third trench 116 is formed in the dielectric layer 110 and the isolation structure 102 at the same time. In this embodiment, the second trench 114 is located on opposite sides of the first trench 112, and the first trench 112 and the second trench 114 expose a part of the cushion layer 106. When the pad layer 106 is not formed, the first trench 112 and the second trench 114 expose a part of the substrate 100 (the lightly doped region 104). The first trench 112 is used to define the position where the gate is subsequently formed, the second trench 114 is used to define the position where the contact window is subsequently formed, and the third trench 116 is used to define the position where the connection line is subsequently formed. In this embodiment, the first trench 112, the second trench 114, and the third trench 116 are formed by forming a patterned photoresist layer (not shown) on the dielectric layer 110, for example. Then, using the patterned photoresist layer as an etching mask, an anisotropic etching process is performed to remove part of the dielectric layer 110 and the hard mask layer 108 underneath, and remove part of the dielectric layer 110 and the underneath The structure 102 is partially isolated, and the pad layer 106 is used as an etch stop layer. After that, the patterned photoresist layer is removed.

在本實施例中，僅進行一次圖案化製程（亦即僅使用一個光罩）即可同時形成分別界定閘極位置、接觸窗位置與連接線位置的第一溝槽112、第二溝槽114與第三溝槽116，因此簡化了製程步驟以及降低了成本，且可以確保閘極位置與接觸窗位置不會重疊，以避免接觸窗與閘極之間產生短路。此外，以此方式來界定接觸窗的位置，可以不需要額外地進行對準即可將接觸窗形成於準確的位置。In this embodiment, only one patterning process (that is, only one photomask is used) can simultaneously form the first groove 112 and the second groove 114 respectively defining the gate position, the contact window position, and the connecting line position. With the third trench 116, the process steps are simplified and the cost is reduced, and the gate position and the contact window position can be ensured not to overlap, so as to avoid a short circuit between the contact window and the gate electrode. In addition, by defining the position of the contact window in this way, the contact window can be formed at an accurate position without additional alignment.

此外，在本實施例中，藉由調整光罩圖案可調整所形成的第一溝槽112、第二溝槽114與第三溝槽116的位置。舉例來說，在本實施例中，可使第一溝槽112與其一側的第二溝槽114之間的距離等於第一溝槽112與其另一側的第二溝槽114之間的距離。如此一來，後續所形成的閘極與分別位於其兩側的接觸窗之間的距離會相等，因此可容易地形成具有對稱結構的半導體元件。在其他實施例中，也可視實際需求使得第一溝槽112與其一側的第二溝槽114之間的距離不等於第一溝槽112與其另一側的第二溝槽114之間的距離，以形成具有非對稱結構的半導體元件。In addition, in this embodiment, the positions of the first groove 112, the second groove 114, and the third groove 116 formed can be adjusted by adjusting the mask pattern. For example, in this embodiment, the distance between the first trench 112 and the second trench 114 on one side can be equal to the distance between the first trench 112 and the second trench 114 on the other side. . In this way, the distance between the gate electrode to be formed later and the contact windows located on both sides of the gate electrode will be equal, so that a semiconductor device with a symmetric structure can be easily formed. In other embodiments, the distance between the first groove 112 and the second groove 114 on one side may not be equal to the distance between the first groove 112 and the second groove 114 on the other side according to actual needs. , To form a semiconductor element with an asymmetric structure.

接著，請參照圖1C，於介電層110上形成保護層118，且使得保護層118填滿第二溝槽114與第三溝槽116，並暴露出第一溝槽112。在本實施例中，保護層118例如為光阻層。然後，以保護層118為蝕刻罩幕，進行非等向性蝕刻製程，移除第一溝槽112暴露出的基底100的一部分，以形成第四溝槽120。第四溝槽120為後續形成閘極的區域。在本實施例中，第四溝槽120的底面低於淡摻雜區104的底面。如此一來，當後續於第四溝槽120中形成閘極時，位於閘極的相對兩側的淡摻雜區104即可作為淡摻雜汲極（lightly doped drain，LDD）。Next, referring to FIG. 1C, a protective layer 118 is formed on the dielectric layer 110 so that the protective layer 118 fills the second trench 114 and the third trench 116 and exposes the first trench 112. In this embodiment, the protective layer 118 is, for example, a photoresist layer. Then, using the protective layer 118 as an etching mask, an anisotropic etching process is performed to remove a part of the substrate 100 exposed by the first trench 112 to form the fourth trench 120. The fourth trench 120 is a region where the gate electrode is subsequently formed. In this embodiment, the bottom surface of the fourth trench 120 is lower than the bottom surface of the lightly doped region 104. In this way, when a gate is subsequently formed in the fourth trench 120, the lightly doped regions 104 located on opposite sides of the gate can serve as a lightly doped drain (LDD).

然後，請參照圖1D，移除保護層118。此時，第一溝槽與112與第四溝槽120連通且暴露出部分基底100，第二溝槽114暴露出部分淡摻雜區104，第三溝槽116暴露出部分隔離結構102，且第一溝槽與112、第二溝槽114與第三溝槽116的深度相同。接著，於第四溝槽120暴露的基底100的表面上形成閘介電層121。在本實施例中，閘介電層121例如為氧化矽層，其形成方法例如為進行熱氧化法。此外，在形成閘介電層121的同時，第二溝槽114所暴露出的淡摻雜區104上也會形成氧化矽層。因此，接著於第一溝槽112與第四溝槽120中形成保護層122，然後進行蝕刻製程來移除淡摻雜區104上的氧化矽層。在本實施例中，保護層122例如為光阻層。Then, referring to FIG. 1D, the protective layer 118 is removed. At this time, the first trench 112 communicates with the fourth trench 120 and exposes a part of the substrate 100, the second trench 114 exposes a part of the lightly doped region 104, and the third trench 116 exposes a part of the isolation structure 102, and The depths of the first trench 112 and the second trench 114 and the third trench 116 are the same. Next, a gate dielectric layer 121 is formed on the surface of the substrate 100 exposed by the fourth trench 120. In this embodiment, the gate dielectric layer 121 is, for example, a silicon oxide layer, and its formation method is, for example, a thermal oxidation method. In addition, when the gate dielectric layer 121 is formed, a silicon oxide layer is also formed on the lightly doped region 104 exposed by the second trench 114. Therefore, a protective layer 122 is formed in the first trench 112 and the fourth trench 120, and then an etching process is performed to remove the silicon oxide layer on the lightly doped region 104. In this embodiment, the protective layer 122 is, for example, a photoresist layer.

之後，請參照圖1E，移除保護層122。接著，於第一溝槽112、第二溝槽114、第三溝槽116與第四溝槽120的側壁與底部上形成多晶矽層123。多晶矽層123的形成方法例如是進行化學氣相沉積製程，於基底100上共形地形成一層多晶矽層，然後進行化學機械研磨製程，移除位於介電層110的頂面上的多晶矽層。此外，在進行化學機械研磨製程之前，還可先於第一溝槽與112、第二溝槽114、第三溝槽116與第四溝槽120內形成保護層，以避免位於第一溝槽與112、第二溝槽114、第三溝槽116與第四溝槽120中的多晶矽層在化學機械研磨製程的期間受損，且在化學機械研磨製程結束後移除保護層。After that, referring to FIG. 1E, the protective layer 122 is removed. Next, a polysilicon layer 123 is formed on the sidewalls and bottoms of the first trench 112, the second trench 114, the third trench 116, and the fourth trench 120. The formation method of the polysilicon layer 123 is, for example, a chemical vapor deposition process to form a polysilicon layer conformally on the substrate 100, and then a chemical mechanical polishing process is performed to remove the polysilicon layer on the top surface of the dielectric layer 110. In addition, before performing the chemical mechanical polishing process, a protective layer may be formed in the first trench and 112, the second trench 114, the third trench 116, and the fourth trench 120 to avoid being located in the first trench. The polysilicon layers in the AND 112, the second trench 114, the third trench 116, and the fourth trench 120 are damaged during the chemical mechanical polishing process, and the protective layer is removed after the chemical mechanical polishing process is completed.

在形成多晶矽層123之後，於第二溝槽114下方的基底100中形成重摻雜區124。重摻雜區124位於淡摻雜區104中，且具有與淡摻雜區104相同的導電類型（N型或P型）。重摻雜區124的形成方法例如為進行離子植入製程。然後，於第一溝槽112、第二溝槽114、第三溝槽116與第四溝槽120中形成金屬層126，且金屬層126填滿第一溝槽112、第二溝槽114、第三溝槽116與第四溝槽120。金屬層126的形成方法例如是進行化學氣相沉積製程，於介電層110上共形地形成一層金屬層並填滿第一溝槽112、第二溝槽114、第三溝槽116與第四溝槽120，然後進行化學機械研磨製程，移除位於介電層110的頂面上的金屬層。如此一來，即完成了本實施例的半導體結構。在本實施例中，金屬層126例如為鎢層，但本發明不限於此。在另一實施例中，金屬層126也可以替換為鈦層/氮化鈦層/鎢層所構成的複合導電層。After the polysilicon layer 123 is formed, a heavily doped region 124 is formed in the substrate 100 under the second trench 114. The heavily doped region 124 is located in the lightly doped region 104 and has the same conductivity type (N type or P type) as the lightly doped region 104. The method for forming the heavily doped region 124 is, for example, an ion implantation process. Then, a metal layer 126 is formed in the first trench 112, the second trench 114, the third trench 116, and the fourth trench 120, and the metal layer 126 fills the first trench 112, the second trench 114, The third trench 116 and the fourth trench 120. The method for forming the metal layer 126 is, for example, a chemical vapor deposition process to form a metal layer conformally on the dielectric layer 110 and fill the first trench 112, the second trench 114, the third trench 116, and the The four trenches 120 are then subjected to a chemical mechanical polishing process to remove the metal layer on the top surface of the dielectric layer 110. In this way, the semiconductor structure of this embodiment is completed. In this embodiment, the metal layer 126 is, for example, a tungsten layer, but the invention is not limited to this. In another embodiment, the metal layer 126 can also be replaced with a composite conductive layer composed of a titanium layer/titanium nitride layer/tungsten layer.

在本實施例的半導體結構中，位於第四溝槽120中的多晶矽層123與金屬層126作為閘極128a，重摻雜區124作為源極/汲極，位於第一溝槽112中的多晶矽層123與金屬層126作為與閘極128a連接的第一接觸窗128b，位於第二溝槽114中的多晶矽層123與金屬層126作為與源極/汲極連接的第二接觸窗128c，且位於第三溝槽116中的多晶矽層123與金屬層126作為連接線128d。In the semiconductor structure of this embodiment, the polysilicon layer 123 and the metal layer 126 in the fourth trench 120 serve as the gate 128a, the heavily doped region 124 serves as the source/drain, and the polysilicon layer in the first trench 112 The layer 123 and the metal layer 126 serve as the first contact 128b connected to the gate 128a, and the polysilicon layer 123 and the metal layer 126 located in the second trench 114 serve as the second contact 128c connected to the source/drain, and The polysilicon layer 123 and the metal layer 126 located in the third trench 116 serve as a connecting line 128d.

在本實施例中，閘極128a與其一側的第二接觸窗128c之間的距離等於閘極128a與其另一側的第二接觸窗128c之間的距離。因此，本實施例的半導體結構可具有對稱的結構，且第二接觸窗128c不會與閘極128a接觸而造成短路。此外，第二接觸窗128c也可精準地與源極/汲極連接，避免因位置偏移而影響半導體結構的電性表現。In this embodiment, the distance between the gate electrode 128a and the second contact window 128c on one side is equal to the distance between the gate electrode 128a and the second contact window 128c on the other side. Therefore, the semiconductor structure of this embodiment may have a symmetrical structure, and the second contact window 128c will not contact the gate electrode 128a to cause a short circuit. In addition, the second contact window 128c can also be accurately connected with the source/drain to prevent the positional deviation from affecting the electrical performance of the semiconductor structure.

在本實施例中，閘極128a、第一接觸窗128b、第二接觸窗128c與連接線128d皆由多晶矽層123與金屬層126構成，但本發明不限於此。在其他實施例中，閘極128a、第一接觸窗128b、第二接觸窗128c與連接線128d也可以是由其他導電層所構成。舉例來說，在一實施例中，在圖1E所述的步驟中，可省略形成多晶矽層123的步驟，且在形成重摻雜區124之後，形成導電層來填滿第一溝槽112、第二溝槽114、第三溝槽116與第四溝槽120。In this embodiment, the gate electrode 128a, the first contact window 128b, the second contact window 128c and the connecting line 128d are all composed of the polysilicon layer 123 and the metal layer 126, but the invention is not limited thereto. In other embodiments, the gate electrode 128a, the first contact window 128b, the second contact window 128c, and the connecting line 128d may also be composed of other conductive layers. For example, in one embodiment, in the step described in FIG. 1E, the step of forming the polysilicon layer 123 may be omitted, and after the heavily doped region 124 is formed, a conductive layer is formed to fill the first trench 112, The second trench 114, the third trench 116 and the fourth trench 120.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100:基底100: base

100a:主動區100a: active area

102:隔離結構102: Isolation structure

104:淡摻雜區104: Lightly doped area

106:墊層106: cushion

108:硬罩幕層108: hard mask layer

110:介電層110: Dielectric layer

112:第一溝槽112: The first groove

114:第二溝槽114: second groove

116:第三溝116: The Third Ditch

118、122:保護層118, 122: protective layer

120:第四溝槽120: The fourth groove

121:閘介電層121: gate dielectric layer

123:多晶矽層123: Polysilicon layer

124:重摻雜區124: heavily doped area

126:金屬層126: Metal layer

128a:閘極128a: gate

128b:第一接觸窗128b: first contact window

128c:第二接觸窗128c: second contact window

128d:連接線128d: connection line

圖1A至圖1E為依照本發明實施例的半導體結構的製造流程剖面示意圖。1A to 1E are schematic cross-sectional views of a manufacturing process of a semiconductor structure according to an embodiment of the invention.

100:基底 100: base

100a:主動區 100a: active area

102:隔離結構 102: Isolation structure

104:淡摻雜區 104: Lightly doped area

106:墊層 106: cushion

108:硬罩幕層 108: hard mask layer

110:介電層 110: Dielectric layer

112:第一溝槽 112: The first groove

114:第二溝槽 114: second groove

116:第三溝 116: The Third Ditch

120:第四溝槽 120: The fourth groove

121:閘介電層 121: gate dielectric layer

123:多晶矽層 123: Polysilicon layer

124:重摻雜區 124: heavily doped area

126:金屬層 126: Metal layer

128a:閘極 128a: gate

128b:第一接觸窗 128b: first contact window

128c:第二接觸窗 128c: second contact window

128d:連接線 128d: connection line

Claims (10)

一種半導體結構，包括：隔離結構，設置於基底中以定義出主動區；淡摻雜區，設置於所述主動區中的所述基底中；閘極，設置於所述主動區中的所述基底中，且所述閘極的底面低於所述淡摻雜區的底面；閘介電層，設置於所述閘極與所述基底之間；重摻雜區，設置於所述淡摻雜區中，且位於所述閘極的相對兩側；介電層，設置於所述基底上；第一接觸窗，設置於所述介電層中，且與所述閘極連接，其中所述第一接觸窗與所述閘極的材料相同且同時形成；第二接觸窗，設置於所述介電層中，且與所述重摻雜區連接；以及連接線，設置於所述介電層及其下方的所述隔離結構中，且藉由所述隔離結構與所述基底隔離。 A semiconductor structure includes: an isolation structure arranged in a substrate to define an active area; a lightly doped area arranged in the substrate in the active area; a gate electrode arranged in the active area In the substrate, and the bottom surface of the gate is lower than the bottom surface of the lightly doped region; the gate dielectric layer is disposed between the gate and the substrate; the heavily doped region is disposed on the lightly doped region The miscellaneous region is located on opposite sides of the gate; a dielectric layer is disposed on the substrate; a first contact window is disposed in the dielectric layer and is connected to the gate, wherein The first contact window and the gate electrode are made of the same material and formed at the same time; a second contact window is provided in the dielectric layer and connected to the heavily doped region; and a connecting line is provided in the dielectric The electrical layer and the isolation structure underneath are isolated from the substrate by the isolation structure. 如申請專利範圍第1項所述的半導體結構，其中所述閘極、所述第一接觸窗、所述第二接觸窗與所述連接線各自包括多晶矽層以及所述多晶矽層上的金屬層。 The semiconductor structure according to claim 1, wherein the gate electrode, the first contact window, the second contact window, and the connecting line each include a polysilicon layer and a metal layer on the polysilicon layer . 如申請專利範圍第1項所述的半導體結構，其中所述閘極、所述第一接觸窗、所述第二接觸窗與所述連接線各自包括金屬層。 The semiconductor structure according to claim 1, wherein the gate electrode, the first contact window, the second contact window, and the connecting line each include a metal layer. 如申請專利範圍第1項所述的半導體結構，其中位於所述閘極的一側的所述第二接觸窗與所述閘極之間具有第一距離，位於所述閘極的另一側的所述第二接觸窗與所述閘極之間具有第二距離，且所述第一距離等於所述第二距離。 The semiconductor structure according to claim 1, wherein there is a first distance between the second contact window located on one side of the gate electrode and the gate electrode, and is located on the other side of the gate electrode There is a second distance between the second contact window and the gate, and the first distance is equal to the second distance. 如申請專利範圍第1項所述的半導體結構，更包括墊層，設置於所述介電層與所述淡摻雜區之間。 The semiconductor structure described in item 1 of the scope of the patent application further includes a pad layer disposed between the dielectric layer and the lightly doped region. 一種半導體結構的製造方法，包括：於基底中形成隔離結構，以定義出主動區；於所述主動區中的所述基底中形成淡摻雜區；於所述基底上形成介電層；於所述介電層中形成第一溝槽與第二溝槽並且同時於所述介電層與所述隔離結構中形成第三溝槽，其中所述第二溝槽位於所述第一溝槽的相對兩側，且所述第一溝槽與所述第二溝槽暴露出部分所述基底；移除所述第一溝槽暴露出的所述基底的一部分，以形成第四溝槽，其中所述第四溝槽的底面低於所述淡摻雜區的底面；於所述第四溝槽暴露的所述基底的表面上形成閘介電層；於所述第二溝槽下方的所述基底中形成重摻雜區；以及於所述第一溝槽、所述第二溝槽、所述第三溝槽與所述第四溝槽中形成導電層。 A method for manufacturing a semiconductor structure includes: forming an isolation structure in a substrate to define an active region; forming a lightly doped region in the substrate in the active region; forming a dielectric layer on the substrate; A first trench and a second trench are formed in the dielectric layer and a third trench is simultaneously formed in the dielectric layer and the isolation structure, wherein the second trench is located in the first trench And the first groove and the second groove expose part of the substrate; removing a part of the substrate exposed by the first groove to form a fourth groove, The bottom surface of the fourth trench is lower than the bottom surface of the lightly doped region; a gate dielectric layer is formed on the surface of the substrate exposed by the fourth trench; A heavily doped region is formed in the substrate; and a conductive layer is formed in the first trench, the second trench, the third trench, and the fourth trench. 如申請專利範圍第6項所述的半導體結構的製造方法，其中位於所述第一溝槽的一側的所述第二溝槽與所述第一溝槽之 間具有第一距離，位於所述第一溝槽的另一側的所述第二溝槽與所述第一溝槽之間具有第二距離，且所述第一距離等於所述第二距離。 The method for manufacturing a semiconductor structure as described in the scope of the patent application, wherein the second trench located on one side of the first trench and the first trench There is a first distance between them, and there is a second distance between the second groove on the other side of the first groove and the first groove, and the first distance is equal to the second distance . 如申請專利範圍第6項所述的半導體結構的製造方法，其中所述第四溝槽的形成方法包括：於所述介電層上形成保護層，其中所述保護層填滿所述第二溝槽與所述第三溝槽，且暴露出所述第一溝槽；以及以所述保護層為蝕刻罩幕，進行非等向性蝕刻製程，以移除所述第一溝槽暴露出的所述基底的一部分。 According to the manufacturing method of the semiconductor structure described in claim 6, wherein the method for forming the fourth trench includes: forming a protective layer on the dielectric layer, wherein the protective layer fills the second A trench and the third trench, and the first trench is exposed; and an anisotropic etching process is performed using the protective layer as an etching mask to remove the first trench and expose Part of the substrate. 如申請專利範圍第6項所述的半導體結構的製造方法，其中所述導電層的形成方法包括：於所述第一溝槽、所述第二溝槽、所述第三溝槽與所述第四溝槽的側壁與底部上形成多晶矽層；以及於所述多晶矽層上形成金屬層。 According to the manufacturing method of the semiconductor structure described in claim 6, wherein the method of forming the conductive layer includes: in the first trench, the second trench, the third trench, and the A polysilicon layer is formed on the sidewall and bottom of the fourth trench; and a metal layer is formed on the polysilicon layer. 如申請專利範圍第6項所述的半導體結構的製造方法，其中在形成所述淡摻雜區之後以及在形成所述介電層之前，更包括於所述基底上形成墊層。 According to the manufacturing method of the semiconductor structure described in the scope of the patent application, after forming the lightly doped region and before forming the dielectric layer, it further includes forming a cushion layer on the substrate.
TW108125933A 2019-07-23 2019-07-23 Semiconductor structure and manufacturing method thereof TWI701789B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW108125933A TWI701789B (en) 2019-07-23 2019-07-23 Semiconductor structure and manufacturing method thereof
CN201910715947.3A CN112289861B (en) 2019-07-23 2019-08-05 Semiconductor structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW108125933A TWI701789B (en) 2019-07-23 2019-07-23 Semiconductor structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TWI701789B true TWI701789B (en) 2020-08-11
TW202105659A TW202105659A (en) 2021-02-01

Family

ID=73003150

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108125933A TWI701789B (en) 2019-07-23 2019-07-23 Semiconductor structure and manufacturing method thereof

Country Status (2)

Country Link
CN (1) CN112289861B (en)
TW (1) TWI701789B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1674292A (en) * 2004-03-26 2005-09-28 力晶半导体股份有限公司 Non-volatile memory location and producing method thereof
TW200830471A (en) * 2007-01-02 2008-07-16 Powerchip Semiconductor Corp Self-aligned contact and manufacturing method thereof
TW201923917A (en) * 2017-11-16 2019-06-16 台灣積體電路製造股份有限公司 Integrated circuit device and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI254409B (en) * 2005-02-16 2006-05-01 Powerchip Semiconductor Corp Semiconductor device having self-aligned contact and manufacturing method thereof
CN100421218C (en) * 2005-04-18 2008-09-24 力晶半导体股份有限公司 Semiconductor with self-aligning contact window and its production

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1674292A (en) * 2004-03-26 2005-09-28 力晶半导体股份有限公司 Non-volatile memory location and producing method thereof
TW200830471A (en) * 2007-01-02 2008-07-16 Powerchip Semiconductor Corp Self-aligned contact and manufacturing method thereof
TW201923917A (en) * 2017-11-16 2019-06-16 台灣積體電路製造股份有限公司 Integrated circuit device and manufacturing method thereof

Also Published As

Publication number Publication date
TW202105659A (en) 2021-02-01
CN112289861A (en) 2021-01-29
CN112289861B (en) 2024-03-26

Similar Documents

Publication Publication Date Title
JP3860672B2 (en) Transistor manufacturing method and transistor manufactured by the manufacturing method
KR100515061B1 (en) Semiconductor devices having a fin field effect transistor and methods for forming the same
US9390975B2 (en) Methods for producing a tunnel field-effect transistor
US20180323282A1 (en) Power device with high aspect ratio trench contacts and submicron pitches between trenches
KR101466846B1 (en) Mos transistor and method for forming the same
TWI749363B (en) Finfet having insulating layers between gate and source/drain contacts
US8378395B2 (en) Methods of fabricating field effect transistors having protruded active regions
KR100668838B1 (en) Method for forming gate in semiconductor device
KR20030050995A (en) Method for fabricating high-integrated transistor
KR100414735B1 (en) A semiconductor device and A method for forming the same
US7649218B2 (en) Lateral MOS transistor and method for manufacturing thereof
KR20070020919A (en) Recess channel array transistor and method for fabricating the same
TWI701789B (en) Semiconductor structure and manufacturing method thereof
JP2010165907A (en) Method of manufacturing semiconductor device
US11152370B2 (en) Memory structure having transistors and capacitor and manufacturing method thereof
TWI701832B (en) Semiconductor apparatus and manufacturing method thereof
KR100373709B1 (en) Semiconductor devices and manufacturing method thereof
KR100386452B1 (en) Method for manufacturing semiconductor device
KR100504948B1 (en) Method of forming contact plug in semiconductor devices
KR100485172B1 (en) Semiconductor device and method for the same
JPH11214497A (en) Trench structure for isolating elements of semiconductor device
JP2008053275A (en) Semiconductor device and its manufacturing method
KR20180010653A (en) Sens-amp transister of semiconductor deviceand manufacturing method
KR20030000668A (en) Method for forming a contact hole of a semiconductor device
KR20050042698A (en) Semiconductor device having contact structure of the gate electrodes and the junction region using directly contact type, and method for manufacturing the same