TWI701719B

TWI701719B - Method for making a semiconductor device

Info

Publication number: TWI701719B
Application number: TW108114844A
Authority: TW
Inventors: 林羿宏; 陳孟揚; 李榮仁; 徐子傑
Original assignee: 晶元光電股份有限公司
Priority date: 2016-09-09
Filing date: 2016-09-09
Publication date: 2020-08-11
Also published as: TW201935529A

Abstract

The present disclosure provides a method for making a semiconductor device. The method for making a semiconductor device comprises : providing a first semiconductor layer comprising a first area; forming a second semiconductor layer on the first area, wherein the second semiconductor layer comprising a dopant, and a doping concentration of the dopant in the second semiconductor layer is higher than a doping concentration of the dopant in the first semiconductor layer; introducing the dopant of the second semiconductor layer into the first area of the first semiconductor layer.

Description

製造半導體元件的方法Method of manufacturing semiconductor element

本申請內容有關於一種製造半導體元件的方法，尤指一種使摻雜物進入一半導體層的方法。 The content of this application relates to a method of manufacturing a semiconductor device, in particular to a method of introducing dopants into a semiconductor layer.

在製造半導體元件的製程中，摻雜為一常見的步驟。既有技術中，若欲摻雜一摻雜物至所需的區域，係利用遮蔽物將不欲摻雜的區域遮蔽而裸露出所需的區域，並將裸露出的區域暴露至一充滿摻雜物的環境中，而使裸露出的區域與摻雜物接觸，進而使摻雜物擴散進入裸露出的區域。 In the process of manufacturing semiconductor devices, doping is a common step. In the existing technology, if a dopant is to be doped to a desired area, a mask is used to cover the area not to be doped to expose the desired area, and the exposed area is exposed to a full dopant. In the environment of impurities, the exposed area is in contact with the dopant, and the dopant diffuses into the exposed area.

本申請提供一種製造半導體元件的方法，其包含：提供一第一半導體層，其包含一第一區域；形成一第二半導體層於第一區域上，第二半導體層包含一摻雜物，且摻雜物在第二半導體層內的濃度高於摻雜物在第一半導體層內的濃度；以及使第二半導體層的摻雜物進入第一半導體層的第一區域，以提升摻雜物在第一區域內的濃度。 The present application provides a method of manufacturing a semiconductor device, which includes: providing a first semiconductor layer including a first region; forming a second semiconductor layer on the first region, the second semiconductor layer including a dopant, and The concentration of the dopant in the second semiconductor layer is higher than the concentration of the dopant in the first semiconductor layer; and the dopant of the second semiconductor layer enters the first region of the first semiconductor layer to increase the dopant The concentration in the first zone.

本發明提供一種製造半導體元件的方法，其包含：提供一第一半導體層，其包含一第一區域；形成一第二半導體層於第一區域上，第二半導體層包含一摻雜物，且摻雜物在第二半導體層內的濃度高於摻雜物在第一半導體層內的濃度；使第二半導體層的摻雜物進入第一半導體層的第一區域，以提升摻雜物在第一區域內的濃度；以及形成一發光結構，其包括一第一導電型半導體層、一第二導電型半導體層以及一位於第一導電型半導體層以及第二導電型半導體層之間的活性區域。 The present invention provides a method of manufacturing a semiconductor device, which includes: providing a first semiconductor layer including a first region; forming a second semiconductor layer on the first region, the second semiconductor layer including a dopant, and The concentration of the dopant in the second semiconductor layer is higher than the concentration of the dopant in the first semiconductor layer; the dopant of the second semiconductor layer enters the first semiconductor layer Area to increase the concentration of dopants in the first area; and to form a light emitting structure, which includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and a first conductivity type semiconductor layer and a second conductivity type semiconductor layer. Active area between conductive semiconductor layers.

本發明提供一種製造半導體發光元件的方法，其包含：提供一第一半導體結構，第一半導體結構包含一第一區域；形成一半導體層於第一半導體結構上，半導體層包含一摻雜物，且摻雜物在半導體層內的濃度高於摻雜物在第一半導體結構內的濃度；以及使半導體層的摻雜物擴散進入第一半導體結構的第一區域，以提升摻雜物在第一區域內的濃度。 The present invention provides a method of manufacturing a semiconductor light emitting element, which includes: providing a first semiconductor structure, the first semiconductor structure including a first region; forming a semiconductor layer on the first semiconductor structure, the semiconductor layer including a dopant, And the concentration of the dopant in the semiconductor layer is higher than the concentration of the dopant in the first semiconductor structure; and the dopant of the semiconductor layer is diffused into the first region of the first semiconductor structure to improve the dopant in the first semiconductor structure. The concentration in an area.

10、40:成長基板 10.40: Growth substrate

401、101:上表面 401, 101: upper surface

20:第一半導體層 20: The first semiconductor layer

21、91:第一區域 21, 91: The first area

22、92:第二區域 22, 92: second area

30:第二半導體層 30: second semiconductor layer

50:磊晶結構 50: epitaxial structure

60:第一反射鏡 60: The first mirror

70:第二反射鏡 70: second mirror

80:發光結構 80: light-emitting structure

90:第一半導體結構 90: The first semiconductor structure

100:半導體層 100: semiconductor layer

110:第三反射鏡 110: third mirror

120:半導體接觸層 120: Semiconductor contact layer

130:第一電極 130: first electrode

140:第二電極 140: second electrode

第1A圖至第1D圖為本申請內容之製造半導體元件的方法之一實施例；第2圖為使用第1A圖至第1D圖所示方法製成之一半導體元件實施例的摻雜物濃度與摻雜深度關係圖；第3A圖至第3G圖為本申請內容之製造半導體元件的方法之另一實施例；第4圖為第3D圖所示之一實施例的第一半導體結構中的第一摻雜物濃度與摻雜深度關係圖；以及第5圖為第3A圖至第3G圖之方法製造的半導體元件的實施例。 Fig. 1A to Fig. 1D are an embodiment of the method of manufacturing a semiconductor device according to the application; Fig. 2 is the dopant concentration of an embodiment of a semiconductor device manufactured by the method shown in Fig. 1A to Fig. 1D Figure 3A to Figure 3G is another embodiment of the method for manufacturing a semiconductor device according to the content of this application; Figure 4 is a diagram of the first semiconductor structure of one embodiment shown in Figure 3D The relationship between the first dopant concentration and the doping depth; and FIG. 5 is an embodiment of the semiconductor device manufactured by the method in FIG. 3A to FIG. 3G.

以下實施例將伴隨著圖式說明本申請之概念，在圖式或說明中，相似或相同之部分係使用相同之標號，並且在圖式中，元件之形狀或厚度可擴大或縮小。需特別注意的是，圖中未繪示或說明書未描述之元件，可以是熟習此技藝之人士所知之形式，且各實施例間為避免贅述而對於相同技術特徵描述可能有所省略。 The following embodiments will accompany the drawings to illustrate the concept of the application. In the drawings or descriptions, similar or identical parts use the same reference numerals, and in the drawings, the shape or thickness of the element Can be expanded or contracted. It should be noted that elements not shown in the figure or not described in the specification can be in the form known to those skilled in the art, and the description of the same technical features may be omitted in each embodiment in order to avoid redundancy.

在本申請內容中，如果沒有特別的說明，本申請所揭露之半導體材料可包含各種元素的組合，例如通式AlGaAs代表Al_xGa_(1-x)As，其中0≦x≦1；通式AlInP代表Al_xIn_(1-x)P，其中0≦x≦1；通式AlGaInP代表(Al_yGa_(1-y))_1-xIn_xP，其中0≦x≦1，0≦y≦1；通式AlGaN代表Al_xGa_(1-x)N，其中0≦x≦1；通式AlAsSb代表AlAs_(1-x)Sb_x，其中0≦x≦1；通式InGaAsP代表In_xGa_1-xAs_1-yP_y，其中0≦x≦1，0≦y≦1；通式AlGaAsP代表Al_xGa_1-xAs_1-yP_y，其中0≦x≦1，0≦y≦1；通式InGaAsN代表In_xGa_1-xAs_1-yN_y,，其中0≦x≦1，0≦y≦1；通式InGaAs代表In_xGa_1-xAs_,，其中0≦x≦1；通式InGaN代表In_xGa_1-xN,，其中0≦x≦1；以及通式InGaP代表In_xGa_1-xP，其中0≦x≦1。調整元素的含量可以達到不同的目的，例如調整能階或是調整主波長或峰值波長。 In the content of this application, unless otherwise specified, the semiconductor material disclosed in this application may contain a combination of various elements. For example, the general formula AlGaAs represents Al _x Ga _(1-x) As, where 0≦x≦1; AlInP stands for Al _x In _(1-x) P, where 0≦x≦1; the general formula AlGaInP stands for (Al _y Ga _(1-y) ) _1-x In _x P, where 0≦x≦1, 0≦y ≦1; the general formula AlGaN represents Al _x Ga _(1-x) N, where 0≦x≦1; the general formula AlAsSb represents AlAs _(1-x) Sb _x , where 0≦x≦1; the general formula InGaAsP represents In _x Ga _1-x As _1-y P _y , where 0≦x≦1, 0≦y≦1; the general formula AlGaAsP represents Al _x Ga _1-x As _1-y P _y , where 0≦x≦1, 0≦ y ≦ 1; InGaAsN representative of the general formula _{_{_{In x Ga 1-x As 1}}} -y N y,, where 0 ≦ x ≦ 1,0 ≦ y ≦ 1; InGaAs on behalf of the general formula _{_{_{In x Ga 1-x As,}}} , wherein 0 ≦x≦1; the general formula InGaN represents In _x Ga _1-x N, where 0≦x≦1; and the general formula InGaP represents In _x Ga _1-x P, where 0≦x≦1. Adjusting the content of elements can achieve different purposes, such as adjusting the energy level or adjusting the main wavelength or peak wavelength.

第1A圖至第1D圖為本申請內容之製造半導體元件的方法之一實施例。在此實施例中，製造半導體元件的方法包含步驟：a.如第1A圖所示，提供一成長基板10，其具有一上表面101；b.如第1A圖所示，形成一第一半導體層20於成長基板10的上表面101上，第一半導體層20包含一第一區域21與一第二區域22，其中形成第一半導體層20的方式包含磊晶成長；c.如第1A圖所示，形成一第二半導體層30於第一半導體層20上，其中第二半導體層30包含一第一摻雜物，且第一摻雜物在第二半導體層30 內的濃度高於第一摻雜物在第一半導體層20內的濃度；在一實施例中，第一摻雜物在第二半導體層30內的濃度不小於1x10¹⁸/cm³，且較佳地，介於1x10¹⁹/cm³至1x10²²/cm³之間(兩者皆含)，其中形成第二半導體層30的方式包含磊晶成長；在一實施例中，第二半導體層30的厚度可大於第一半導體層20的厚度，較佳地，第二半導體層30的厚度不小於300埃(Å)，且較佳地，不大於0.5微米(um)；在一實施例中，第二半導體層30的厚度也可小於第一半導體層20的厚度；d.如第1B圖所示，對第二半導體層30進行圖案化，以使圖案化的第二半導體層30位於第一半導體層20之第一區域21的正上方，即，第一半導體層20之第一區域21於垂直方向與圖案化的第二半導體層30重疊，而第一半導體層20之第二區域22上並未覆蓋有第二半導體層30，具體地，垂直方向是指垂直於成長基板10的上表面101的方向，其中對第二半導體層30進行圖案化的方式包含，但不限於微影光罩、壓印、電子束或雷射光束；以及e.如第1C圖所示，使圖案化的第二半導體層30的第一摻雜物進入第一半導體層20的第一區域21，以提升第一摻雜物在第一區域21內的濃度，其中使圖案化的第二半導體層30的第一摻雜物進入第一半導體層20的第一區域21的方式包含，但不限於加熱處理及/或加壓處理。 FIG. 1A to FIG. 1D are an embodiment of the method for manufacturing a semiconductor device according to the application. In this embodiment, the method for manufacturing a semiconductor device includes the steps: a. As shown in FIG. 1A, a growth substrate 10 is provided, which has an upper surface 101; b. As shown in FIG. 1A, a first semiconductor is formed The layer 20 is on the upper surface 101 of the growth substrate 10. The first semiconductor layer 20 includes a first region 21 and a second region 22. The method of forming the first semiconductor layer 20 includes epitaxial growth; c. as shown in Figure 1A As shown, a second semiconductor layer 30 is formed on the first semiconductor layer 20, wherein the second semiconductor layer 30 includes a first dopant, and the concentration of the first dopant in the second semiconductor layer 30 is higher than that of the first dopant. The concentration of a dopant in the first semiconductor layer 20; in one embodiment, the concentration of the first dopant in the second semiconductor layer 30 is not less than 1×10 ¹⁸ /cm ³ , and preferably, is between 1×10 ¹⁹ /cm ³ to 1x10 ²² /cm ³ (both included), wherein the method of forming the second semiconductor layer 30 includes epitaxial growth; in one embodiment, the thickness of the second semiconductor layer 30 may be greater than that of the first semiconductor layer 30. The thickness of the semiconductor layer 20, preferably, the thickness of the second semiconductor layer 30 is not less than 300 angstroms (Å), and preferably, not more than 0.5 microns (um); in one embodiment, the thickness of the second semiconductor layer 30 The thickness may also be less than the thickness of the first semiconductor layer 20; d. As shown in Figure 1B, the second semiconductor layer 30 is patterned so that the patterned second semiconductor layer 30 is located on the first semiconductor layer 20 Right above the area 21, that is, the first area 21 of the first semiconductor layer 20 overlaps the patterned second semiconductor layer 30 in the vertical direction, and the second area 22 of the first semiconductor layer 20 is not covered with the second area The semiconductor layer 30, specifically, the vertical direction refers to the direction perpendicular to the upper surface 101 of the growth substrate 10, and the method of patterning the second semiconductor layer 30 includes, but is not limited to, photolithography, imprinting, and electron beam Or a laser beam; and e. As shown in Figure 1C, the first dopant of the patterned second semiconductor layer 30 enters the first region 21 of the first semiconductor layer 20 to enhance the first dopant in The concentration in the first region 21, where the first dopant of the patterned second semiconductor layer 30 enters the first region 21 of the first semiconductor layer 20 includes, but is not limited to, heat treatment and/or pressure treatment .

於步驟e之後，第一半導體層20的第一區域21中的第一摻雜物之濃度大於第二區域22中第一摻雜物的濃度。在一實施例中，第二區域22中第一摻雜物的濃度可以為零或接近零。在一實施例中，較佳地，第一區域21中的第一摻雜物之濃度與第二區域22中第一摻雜物的濃度之差異大於 1x10¹⁶/cm³，又更佳地，大於1x10¹⁸/cm³。在一實施例中，較佳地，第一半導體層20的第一區域21中的第一摻雜物之濃度大於1x10¹⁶/cm³，又更佳地，大於1x10¹⁸/cm³。於前述步驟c的一實施例中，當第二半導體層30的厚度大於第一半導體層20的厚度時，進行步驟e可使第一摻雜物的擴散更有效率，進而更容易使第一摻雜物在第一區域21中之濃度與在第二區域22中之濃度的差異大於1x10¹⁶/cm³。 After step e, the concentration of the first dopant in the first region 21 of the first semiconductor layer 20 is greater than the concentration of the first dopant in the second region 22. In an embodiment, the concentration of the first dopant in the second region 22 may be zero or close to zero. In an embodiment, preferably, the difference between the concentration of the first dopant in the first region 21 and the concentration of the first dopant in the second region 22 is greater than 1×10 ¹⁶ /cm ³ , and more preferably, Greater than 1x10 ¹⁸ /cm ³ . In an embodiment, preferably, the concentration of the first dopant in the first region 21 of the first semiconductor layer 20 is greater than 1×10 ¹⁶ /cm ³ , and more preferably, greater than 1×10 ¹⁸ /cm ³ . In an embodiment of the foregoing step c, when the thickness of the second semiconductor layer 30 is greater than the thickness of the first semiconductor layer 20, performing step e can make the diffusion of the first dopant more efficient, thereby making it easier to make the first dopant diffuse more efficiently. The difference between the concentration of the dopant in the first region 21 and the concentration in the second region 22 is greater than 1×10 ¹⁶ /cm ³ .

具體地，於步驟b中，第一區域21為預定於步驟e中使第一摻雜物擴散進入的區域。 Specifically, in step b, the first region 21 is a region scheduled to diffuse the first dopant into step e.

於一實施例中，於步驟e之前，第一半導體層20具有一第一導電型態，即，第一區域21以及第二區域22皆具有第一導電型態，第二半導體層30具有一不同於第一導電型態的第二導電型態。例如，第一半導體層20為p型時，第二半導體層30為n型，於此態樣中，第二半導體層30中的第一摻雜物為n型摻雜物，例如矽(Si)或碲(Te)。又例如，第一半導體層20為n型時，第二半導體層30為p型，於此態樣中，第二半導體層30中的第一摻雜物為p型摻雜物，例如鋅(Zn)、鎂(Mg)或碳(C)。接著，於步驟e之後，第一半導體層20的第一區域21被改變為具有一第三導電型態，第三導電型態可相同於第二導電型態，且不同於第一導電型態，而第一半導體層20的第二區域22依然具有第一導電型態。例如，於步驟e之後，第一半導體層20的第一區域21為n型，第一半導體層20的第二區域22為p型，又例如，於步驟e之後，第一半導體層20的第一區域21為p型，第一半導體層20的第二區域22為n型。詳言之，由於圖案化的第二半導體層30位於第一半導體層20之第一區域21的正上方並與第一區域21的上表面間接接觸或直接接觸，而第一半導體層20之第二區域22上並未覆蓋有第二半導體層30，因此，在步驟e中，第二半導體層30的第一摻雜物會進入第一半導體層20的第一區域21，而第一半導體層20之第二區域22實質上並未被影響。故，於步驟e之後，第一半導體層20的第一區域21的導電型態會改變成為第三導電型態，且此第三導電型態可相同於第二半導體層30的第二導電型態，而第一半導體層20的第二區域22依然具有第一導電型態。本申請中所指之「間接接觸」是指第一區域21的上表面和第一半導體層20之間可以有一或複數緩衝層，但第一摻雜物仍能穿過緩衝層進入第一區域21。在第一區域21的第三導電型態不同於第二區域22的第一導電型態的實施例應用於半導體元件時，第一半導體層20可作為一電流限制結構，使電流選擇性地流入第一區域21或第二區域22。 In one embodiment, before step e, the first semiconductor layer 20 has a first conductivity type, that is, both the first region 21 and the second region 22 have the first conductivity type, and the second semiconductor layer 30 has a A second conductivity type different from the first conductivity type. For example, when the first semiconductor layer 20 is p-type, the second semiconductor layer 30 is n-type. In this aspect, the first dopant in the second semiconductor layer 30 is an n-type dopant, such as silicon (Si ) Or tellurium (Te). For another example, when the first semiconductor layer 20 is n-type, the second semiconductor layer 30 is p-type. In this aspect, the first dopant in the second semiconductor layer 30 is a p-type dopant, such as zinc ( Zn), magnesium (Mg) or carbon (C). Then, after step e, the first region 21 of the first semiconductor layer 20 is changed to have a third conductivity type, which can be the same as the second conductivity type and different from the first conductivity type , And the second region 22 of the first semiconductor layer 20 still has the first conductivity type. For example, after step e, the first region 21 of the first semiconductor layer 20 is n-type, and the second region 22 of the first semiconductor layer 20 is p-type. For another example, after step e, the first region 21 of the first semiconductor layer 20 is One region 21 is p-type, and the second region 22 of the first semiconductor layer 20 is n-type. In detail, since the patterned second semiconductor layer 30 is located directly above the first region 21 of the first semiconductor layer 20 and is in indirect or direct contact with the upper surface of the first region 21, the first semiconductor layer The second region 22 of the body layer 20 is not covered with the second semiconductor layer 30. Therefore, in step e, the first dopant of the second semiconductor layer 30 enters the first region 21 of the first semiconductor layer 20, and The second region 22 of the first semiconductor layer 20 is not substantially affected. Therefore, after step e, the conductivity type of the first region 21 of the first semiconductor layer 20 will be changed to a third conductivity type, and this third conductivity type may be the same as the second conductivity type of the second semiconductor layer 30 The second region 22 of the first semiconductor layer 20 still has the first conductivity type. The "indirect contact" in this application means that there may be one or more buffer layers between the upper surface of the first region 21 and the first semiconductor layer 20, but the first dopant can still pass through the buffer layer and enter the first region twenty one. When the embodiment in which the third conductivity type of the first region 21 is different from the first conductivity type of the second region 22 is applied to a semiconductor device, the first semiconductor layer 20 can be used as a current confinement structure to allow current to flow selectively The first area 21 or the second area 22.

於一實施例中，於步驟e之前，第一半導體層20具有一第一導電型態，即，第一區域21以及第二區域22皆具有第一導電型態，第二半導體層30具有一相同於第一導電型態的第二導電型態，例如第一導電型態及第二導電型態均為p型或均為n型。由於圖案化的第二半導體層30位於第一半導體層20之第一區域21的正上方並與第一區域21的上表面間接接觸或直接接觸，而第一半導體層20之第二區域22上並未覆蓋有第二半導體層30，因此在步驟e中，第二半導體層30的第一摻雜物會進入第一半導體層20的第一區域21，而第一半導體層20之第二區域22實質上並未被影響。本申請中所指之「間接接觸」是指第一區域21的上表面和第一半導體層20之間有一或複數緩衝層，但第一摻雜物仍能穿過緩衝層進入第一區域21。故，於步驟e之後，第一半導體層20的第一區域21的第一摻雜物的濃度會增加，例如，濃度大於於1x10¹⁶/cm³，且第一半導體層20的第一區域21中的第一摻雜物之濃度大於第二區域22中第一摻雜物的濃度，其中第二區域22中第一摻雜物的濃度例如可以為零或接近零。故，於步驟e之後，第一半導體層20的第一區域21以及第二區域22具有不同的電性阻值。在第一區域21以及第二區域22具有不同的電性阻值的實施例應用於半導體元件時，第一半導體層20可作為一電流分佈結構，使流入第一區域21與第二區域22的電流值大小不同。 In one embodiment, before step e, the first semiconductor layer 20 has a first conductivity type, that is, both the first region 21 and the second region 22 have the first conductivity type, and the second semiconductor layer 30 has a The second conductivity type that is the same as the first conductivity type, for example, the first conductivity type and the second conductivity type are both p-type or both n-type. Since the patterned second semiconductor layer 30 is located directly above the first region 21 of the first semiconductor layer 20 and in indirect or direct contact with the upper surface of the first region 21, the second region 22 of the first semiconductor layer 20 Is not covered with the second semiconductor layer 30, so in step e, the first dopant of the second semiconductor layer 30 will enter the first region 21 of the first semiconductor layer 20, and the second region of the first semiconductor layer 20 22 has not been substantially affected. The "indirect contact" referred to in this application means that there is one or more buffer layers between the upper surface of the first region 21 and the first semiconductor layer 20, but the first dopant can still pass through the buffer layer and enter the first region 21 . Therefore, after step e, the concentration of the first dopant in the first region 21 of the first semiconductor layer 20 will increase, for example, the concentration is greater than 1×10 ¹⁶ /cm ³ , and the first region 21 of the first semiconductor layer 20 The concentration of the first dopant in the second region 22 is greater than the concentration of the first dopant in the second region 22, and the concentration of the first dopant in the second region 22 may be zero or close to zero, for example. Therefore, after step e, the first region 21 and the second region 22 of the first semiconductor layer 20 have different electrical resistances. When the embodiment in which the first region 21 and the second region 22 have different electrical resistance values is applied to a semiconductor device, the first semiconductor layer 20 can be used as a current distribution structure to make the flow into the first region 21 and the second region 22 The current value is different.

於一實施例中，在步驟b形成第一半導體層20於成長基板10的上表面101上之前，製造半導體元件的方法更包含藉由磊晶成長形成一第三半導體層(圖未示)於成長基板10的上表面101上，第三半導體層具有一第四導電型態，其相同於在步驟c所形成一第二半導體30所具有的第二導電型態，且不同於第一半導體層20所具有的第一導電型態，例如，第四導電型態為n型時，第一導電型態為p型，第二導電型態為n型。 In one embodiment, before forming the first semiconductor layer 20 on the upper surface 101 of the growth substrate 10 in step b, the method of manufacturing the semiconductor device further includes forming a third semiconductor layer (not shown) by epitaxial growth. On the upper surface 101 of the growth substrate 10, the third semiconductor layer has a fourth conductivity type, which is the same as the second conductivity type of the second semiconductor 30 formed in step c and different from the first semiconductor layer The first conductivity type 20 has, for example, when the fourth conductivity type is n-type, the first conductivity type is p-type, and the second conductivity type is n-type.

於一實施例中，於步驟e之後，製造半導體元件的方法更可包含一步驟f，將圖案化的第二半導體層30移除，如第1D圖所示。例如，以蝕刻、研磨或雷射切割等等的方式移除圖案化的第二半導體層30。 In one embodiment, after step e, the method for manufacturing a semiconductor device may further include a step f, removing the patterned second semiconductor layer 30, as shown in FIG. 1D. For example, the patterned second semiconductor layer 30 is removed by etching, grinding, laser cutting, or the like.

第2圖為使用第1A圖至第1D圖所示方法製成之一半導體元件實施例的摻雜物濃度與摻雜深度關係圖，於本實施例中，成長基板10的厚度約為350um，且成長基板為具有一摻雜物的n型導電型基板，第一半導體層20之厚度約為500埃。第2圖中的圓形記號顯示為成長基板10的摻雜物濃度對摻雜深度關係，三角形記號顯示為第一半導體層20之第一區域21中的第一摻雜物的濃度與摻雜深度的關係。深度0um的位置為第一半導體層20之上表面，由圖可得知，本實施例的第一半導體層20的第一區域21中的至少一部份，較佳地，第一區域21中鄰近第一半導體層20之上表面的區域中，第一摻雜物之濃度隨摻雜深度增加而增加，即，於第一區域21中至少有一部分，越遠離第一半導體層20之上表面的位置，第一摻雜物之濃度越高。 Figure 2 is a diagram showing the relationship between the dopant concentration and the doping depth of an embodiment of a semiconductor device fabricated using the method shown in Figures 1A to 1D. In this embodiment, the thickness of the growth substrate 10 is about 350um. The growth substrate is an n-type conductive substrate with a dopant, and the thickness of the first semiconductor layer 20 is about 500 angstroms. The circular mark in Figure 2 shows the relationship between the dopant concentration of the growth substrate 10 and the doping depth, and the triangle mark shows the concentration and doping of the first dopant in the first region 21 of the first semiconductor layer 20 Deep relationship. The position with a depth of 0um is the upper surface of the first semiconductor layer 20. It can be seen from the figure that at least a part of the first region 21 of the first semiconductor layer 20 of this embodiment, preferably, in the first region 21 In a region adjacent to the upper surface of the first semiconductor layer 20, The concentration of the first dopant increases as the doping depth increases, that is, at least a part of the first region 21 is farther away from the upper surface of the first semiconductor layer 20, the higher the concentration of the first dopant is.

於一實施例中，在移除圖案化的第二半導體層30的步驟之後，製造半導體元件的方法更包含形成一發光結構(圖未示)於第一半導體層20之上，發光結構包括一第一導電型半導體層、一第二導電型半導體層以及一位於第一導電型半導體層以及第二導電型半導體層之間的活性區域。第一導電型半導體層和第二導電型半導體層具有不同的導電型態。例如，第一導電型半導體層為提供電子的n型，第二導電型半導體層為提供電子洞的p型，且第一導電型半導體層的能隙與第二導電型半導體層能隙皆大於活性區域的能隙。 In one embodiment, after the step of removing the patterned second semiconductor layer 30, the method of manufacturing a semiconductor device further includes forming a light emitting structure (not shown) on the first semiconductor layer 20, the light emitting structure including a The first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active region located between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. The first conductivity type semiconductor layer and the second conductivity type semiconductor layer have different conductivity types. For example, the first conductivity type semiconductor layer is n-type that provides electrons, and the second conductivity type semiconductor layer is p-type that provides electron holes, and the energy gap of the first conductivity type semiconductor layer and the energy gap of the second conductivity type semiconductor layer are both larger than The energy gap of the active area.

於一實施例中，於形成第一半導體層20之前，製造半導體元件的方法更包含形成一發光結構(圖未示)於成長基板10之上，本實施例之發光結構可與前述實施例的發光結構相同或近似。 In one embodiment, before forming the first semiconductor layer 20, the method of manufacturing a semiconductor device further includes forming a light-emitting structure (not shown) on the growth substrate 10. The light-emitting structure of this embodiment can be the same as that of the previous embodiment. The light-emitting structure is the same or similar.

本申請之活性區域可發出一具有峰值波長(peak wavelength)的輻射。於一實施例中，當發光元件為發光二極體時，輻射為遠場角(far field angle)大於60度的非同調光，較佳地，大於80度。於另一實施例中，當發光元件為雷射發光元件時，輻射為遠場角小於25度的同調光，較佳地，小於20度，又更佳地，小於15度。 The active area of the present application can emit radiation with a peak wavelength. In one embodiment, when the light-emitting element is a light-emitting diode, the radiation is non-coordinated dimming with a far field angle greater than 60 degrees, preferably greater than 80 degrees. In another embodiment, when the light-emitting element is a laser light-emitting element, the radiation is co-dimmable with a far field angle of less than 25 degrees, preferably less than 20 degrees, and more preferably, less than 15 degrees.

於一實施例中，於步驟c中，第二半導體層30是於一第一溫度下形成於第一半導體層20上，較佳地，第一溫度不低於550℃，且不高於700℃，又更佳地，第一溫度不低於580℃，且不高於670℃。 In one embodiment, in step c, the second semiconductor layer 30 is formed on the first semiconductor layer 20 at a first temperature. Preferably, the first temperature is not lower than 550° C. and not higher than 700 ℃, and more preferably, the first temperature is not lower than 580℃ and not higher than 670℃.

於一實施例中，加熱處理使圖案化的第二半導體層30的第一摻雜物進入第一半導體層20的第一區域21中是操作於一第二溫度中，第二溫度低於形成第二半導體層30的第一溫度。較佳地，第一溫度與第二溫度的差異不大於50℃，且不小於5℃，又更佳地，不大於30℃。具體地，加熱處理的方式包含，但不限於將步驟d形成的結構放入爐管中進行加熱處理，或是將步驟d形成的結構放入有機金屬化學氣相沉積(Metalorganic Chemical Vapor Phase Deposition；MOCVD)的機台之腔室中進行加熱處理。 In one embodiment, the heat treatment to make the first dopant of the patterned second semiconductor layer 30 enter the first region 21 of the first semiconductor layer 20 is operated at a second temperature, which is lower than the formation temperature. The first temperature of the second semiconductor layer 30. Preferably, the difference between the first temperature and the second temperature is not more than 50°C, and not less than 5°C, and more preferably, not more than 30°C. Specifically, the heating treatment method includes, but is not limited to, putting the structure formed in step d into a furnace tube for heating treatment, or putting the structure formed in step d into metal organic chemical vapor deposition (Metalorganic Chemical Vapor Phase Deposition; MOCVD) heat treatment in the chamber of the machine.

第一半導體層20、第二半導體層30以及第三半導體層包含三五族半導體材料，例如，包含本質三五族半導體材料或是具有一摻雜物的三五族半導體材料，例如，包含濃度大於1x10¹⁶/cm³之摻雜物的三五族半導體材料，或包含濃度介於1x10¹⁸/cm³至1x10²²/cm³之間(兩者皆含)的摻雜物的三五族半導體材料。又例如，三五族半導體材料可包含鋁砷化鎵(AlGaAs)、磷化鋁鎵銦(AlGaInP)、磷砷化鎵(GaAsP)、InGaN(氮化銦鎵)或AlGaN(氮化鋁鎵)等。於一實施例中，第一半導體層20包含磷化鋁鎵銦(AlGaInP)，第二半導體層30包含鋁砷化鎵(AlGaAs)，以及第三半導體層包含鋁砷化鎵(AlGaAs)，其中第二半導體層30中的第一摻雜物為鋅(Zn)。 The first semiconductor layer 20, the second semiconductor layer 30, and the third semiconductor layer include three-five-five semiconductor materials, for example, include intrinsic three-five five semiconductor materials or three-five five semiconductor materials with a dopant, for example, include a concentration Group ^III- V semiconductor materials with dopants greater than 1x10 ¹⁶ /cm ³ , or group ^III- V semiconductors containing dopants with a concentration between 1x10 ¹⁸ /cm ³ and 1x10 ²² /cm ³ (both included) material. For another example, the third and fifth group semiconductor material may include aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), gallium arsenide phosphate (GaAsP), InGaN (indium gallium nitride), or AlGaN (aluminum gallium nitride) Wait. In one embodiment, the first semiconductor layer 20 includes aluminum gallium indium phosphide (AlGaInP), the second semiconductor layer 30 includes aluminum gallium arsenide (AlGaAs), and the third semiconductor layer includes aluminum gallium arsenide (AlGaAs). The first dopant in the second semiconductor layer 30 is zinc (Zn).

本申請內容的半導體元件可包括，但不限於，發光二極體、雷射元件、光感測器、太陽能電池、場效電晶體或功率元件等等。本申請內容的方法藉由圖案化的第二半導體層30覆蓋第一半導體層20的第一區域21，且於步驟e中，使圖案化的第二半導體層30中的第一摻雜物擴散進入第一半導體層20的第一區域21，進而使第一半導體層20的第一區域21於步驟e之後包含第一摻雜物。本申請內容的方法利用圖案化的半導體層作為摻雜物的來源，可使步驟a至c以及步驟e皆在有機金屬化學氣相沉積(Metalorganic Chemical Vapor Phase Deposition；MOCVD)的機台之腔室中進行，而可減少使用額外的製程設備如蒸鍍機與高溫爐等，因此本申請之技術相較傳統摻雜製程至少包含可大幅減少製造半導體元件的設備成本、同時減少摻雜製程在不同製程設備間的傳遞時間、增加製程便利性與單位時間內的產量等等的效益。 The semiconductor elements of the present application may include, but are not limited to, light-emitting diodes, laser elements, light sensors, solar cells, field-effect transistors or power elements, etc. The method of the present application covers the first region 21 of the first semiconductor layer 20 by the patterned second semiconductor layer 30, and in step e, diffuses the first dopant in the patterned second semiconductor layer 30 The first region 21 of the first semiconductor layer 20 is entered, so that the first region 21 of the first semiconductor layer 20 includes the first dopant after step e. The method of the present application uses a patterned semiconductor layer as a dopant Source, steps a to c and step e can be carried out in the chamber of a metalorganic chemical vapor deposition (MOCVD) machine, which can reduce the use of additional process equipment such as vapor deposition machine and High-temperature furnaces, etc., therefore, compared with the traditional doping process, the technology of this application at least includes that it can greatly reduce the equipment cost of manufacturing semiconductor devices, while reducing the transfer time of the doping process between different process equipment, increasing the convenience of the process and the unit time. Yield and so on.

第3A圖至第3G圖為本申請內容之製造半導體元件的方法之一實施例。於本實施例中，半導體元件為半導體發光元件，例如為雷射發光元件。製造半導體發光元件的方法包含步驟：a.如第3A圖所示，提供一成長基板40，其具有一上表面401；b.如第3A圖所示，於上表面401上形成一磊晶結構50，其包含一第一反射鏡60、一第二反射鏡70以及一位於第一反射鏡60以及第二反射鏡70之間的發光結構80，其中發光結構80大致上可與本申請先前所述實施例中提及的發光結構相同或近似。第一反射鏡60以及第二反射鏡70各具有一導電型態，且第一反射鏡60的導電型態不同於第二反射鏡70的導電型態，例如第一反射鏡60為n型，第二反射鏡70為p型；c.如第3A圖所示，形成一第一半導體結構90，第一半導體結構90包含一第一區域91與一第二區域92，其中形成第一半導體結構90的方式包含磊晶成長；較佳地，在執行後續摻雜步驟f之前，第一半導體結構90的導電型態不同於第二反射鏡70的導電型態，例如，第二反射鏡70為p型，第一半導體結構90的導電型態為n型，即，第一半導體結構90的第一區域91以及第二區域92的導電型態均為n型； d.如第3A圖所示，形成一半導體層100於第一半導體結構90上，半導體層100包含一第一摻雜物，且第一摻雜物在半導體層100內的濃度高於第一摻雜物在第一半導體結構90內的濃度。在一實施例中，第一摻雜物在半導體層100內的濃度不小於1x10¹⁸/cm³，且較佳地，介於1x10¹⁹/cm³至1x10²²/cm³之間(兩者皆含)，其中形成半導體層100的方式包含磊晶成長；在一實施例中，半導體層100的厚度可大於第一半導體結構90的厚度，較佳地，半導體層100的厚度不小於300埃(Å)，且更佳地，半導體層100的厚度不大於0.5微米(um)；在一實施例中，第二半導體層30的厚度也可小於第一半導體層20的厚度；e.如第3B圖所示，對半導體層100進行圖案化，以使圖案化的半導體層100位於第一半導體結構90之第一區域91的正上方，即，第一半導體結構90之第一區域91於垂直方向與圖案化的半導體層100重疊，而第一半導體結構90之第二區域92上並未覆蓋有半導體層100，具體地，垂直方向是指垂直於成長基40板的上表面401的方向，其中對第一半導體層100進行圖案化的方式包含，但不限於微影光罩、壓印、電子束或雷射光束；f.如第3C圖所示，使圖案化的半導體層100的第一摻雜物擴散進入第一半導體結構90的第一區域91，以提升第一摻雜物在第一區域91內的濃度，其中使圖案化的半導體層100的第一摻雜物進入第一半導體層的第一區域91的方式包含，但不限於加熱處理及/或加壓處理；g.如第3D圖所示，選擇性地，但較佳地，移除圖案化的半導體層100，例如，以蝕刻、研磨或雷射切割等等的方式移除圖案化的半導體層100； h.如第3E圖所示，於第一半導體結構90上形成一第三反射鏡110，第三反射鏡110具有一導電型態，其相同於第二反射鏡70的導電型態，例如，於本實施例中，第三反射鏡110為p型，第二反射鏡70為p型；i.如第3F圖所示，選擇性地，但較佳地，於第三反射鏡110上形成一半導體接觸層120，其中形成半導體接觸層120的方式包含磊晶成長；以及j.如第3G圖所示，選擇性地，但較佳地，於半導體接觸層120上形成一第一電極130以及於成長基板40相反於磊晶結構50的另一側上形成一第二電極140，其中形成第一電極130以及第二電極140的方式包含蒸鍍。 3A to 3G are an embodiment of the method of manufacturing a semiconductor device according to the application. In this embodiment, the semiconductor device is a semiconductor light emitting device, for example, a laser light emitting device. The method of manufacturing a semiconductor light emitting device includes the steps: a. As shown in FIG. 3A, a growth substrate 40 is provided, which has an upper surface 401; b. As shown in FIG. 3A, an epitaxial structure is formed on the upper surface 401 50, which includes a first reflector 60, a second reflector 70, and a light emitting structure 80 located between the first reflector 60 and the second reflector 70, wherein the light emitting structure 80 can be substantially the same as previously described in this application. The light-emitting structures mentioned in the above embodiments are the same or similar. The first reflecting mirror 60 and the second reflecting mirror 70 each have a conductivity type, and the conductivity type of the first reflecting mirror 60 is different from the conductivity type of the second reflecting mirror 70, for example, the first reflecting mirror 60 is an n-type, The second mirror 70 is p-type; c. As shown in FIG. 3A, a first semiconductor structure 90 is formed. The first semiconductor structure 90 includes a first region 91 and a second region 92, in which the first semiconductor structure is formed The method 90 includes epitaxial growth; preferably, before performing the subsequent doping step f, the conductivity type of the first semiconductor structure 90 is different from the conductivity type of the second mirror 70, for example, the second mirror 70 is p-type, the conductivity type of the first semiconductor structure 90 is n-type, that is, the conductivity types of the first region 91 and the second region 92 of the first semiconductor structure 90 are both n-type; d. as shown in Figure 3A , Forming a semiconductor layer 100 on the first semiconductor structure 90, the semiconductor layer 100 includes a first dopant, and the concentration of the first dopant in the semiconductor layer 100 is higher than that of the first dopant in the first semiconductor structure Concentration within 90. In an embodiment, the concentration of the first dopant in the semiconductor layer 100 is not less than 1x10 ¹⁸ /cm ³ , and preferably, it is between 1x10 ¹⁹ /cm ³ and 1x10 ²² /cm ³ (both are Including), wherein the method of forming the semiconductor layer 100 includes epitaxial growth; in one embodiment, the thickness of the semiconductor layer 100 may be greater than the thickness of the first semiconductor structure 90, preferably, the thickness of the semiconductor layer 100 is not less than 300 angstroms ( Å), and more preferably, the thickness of the semiconductor layer 100 is not greater than 0.5 micrometer (um); in one embodiment, the thickness of the second semiconductor layer 30 may also be less than the thickness of the first semiconductor layer 20; e. such as section 3B As shown in the figure, the semiconductor layer 100 is patterned so that the patterned semiconductor layer 100 is located directly above the first region 91 of the first semiconductor structure 90, that is, the first region 91 of the first semiconductor structure 90 is in the vertical direction It overlaps with the patterned semiconductor layer 100, and the second region 92 of the first semiconductor structure 90 is not covered with the semiconductor layer 100. Specifically, the vertical direction refers to the direction perpendicular to the upper surface 401 of the growth substrate 40, where The method of patterning the first semiconductor layer 100 includes, but is not limited to, lithography, imprinting, electron beam or laser beam; f. As shown in Figure 3C, the first patterned semiconductor layer 100 The dopant diffuses into the first region 91 of the first semiconductor structure 90 to increase the concentration of the first dopant in the first region 91, wherein the first dopant of the patterned semiconductor layer 100 enters the first semiconductor The method of the first region 91 of the layer includes, but is not limited to, heat treatment and/or pressure treatment; g. As shown in FIG. 3D, selectively, but preferably, removing the patterned semiconductor layer 100, for example , The patterned semiconductor layer 100 is removed by etching, grinding or laser cutting, etc.; h. As shown in Figure 3E, a third mirror 110 is formed on the first semiconductor structure 90, the third mirror 110 has a conductivity type, which is the same as the conductivity type of the second mirror 70. For example, in this embodiment, the third mirror 110 is p-type and the second mirror 70 is p-type; i. As shown in FIG. 3F, optionally, but preferably, a semiconductor contact layer 120 is formed on the third mirror 110, wherein the method of forming the semiconductor contact layer 120 includes epitaxial growth; and j. As shown in FIG. 3G Optionally, but preferably, a first electrode 130 is formed on the semiconductor contact layer 120 and a second electrode 140 is formed on the other side of the growth substrate 40 opposite to the epitaxial structure 50, wherein the first electrode is formed The method of 130 and the second electrode 140 includes vapor deposition.

於步驟f之後，第一半導體結構90的第一區域91中的第一摻雜物之濃度大於第一半導體結構90的第二區域92中第一摻雜物的濃度。在一實施例中第二區域92中第一摻雜物的濃度可以為零或接近零。在一實施例中，較佳地，第一區域91中的第一摻雜物之濃度與第二區域92中第一摻雜物的濃度之差異大於1x10¹⁶/cm³，又更佳地，大於1x10¹⁸/cm³。在一實施例中，較佳地，第一半導體結構90的第一區域91中的第一摻雜物之濃度大於1x10¹⁶/cm³，又更佳地，大於1x10¹⁸/cm³。 After step f, the concentration of the first dopant in the first region 91 of the first semiconductor structure 90 is greater than the concentration of the first dopant in the second region 92 of the first semiconductor structure 90. In an embodiment, the concentration of the first dopant in the second region 92 may be zero or close to zero. In an embodiment, preferably, the difference between the concentration of the first dopant in the first region 91 and the concentration of the first dopant in the second region 92 is greater than 1×10 ¹⁶ /cm ³ , and more preferably, Greater than 1x10 ¹⁸ /cm ³ . In an embodiment, preferably, the concentration of the first dopant in the first region 91 of the first semiconductor structure 90 is greater than 1×10 ¹⁶ /cm ³ , and more preferably, greater than 1×10 ¹⁸ /cm ³ .

具體地，於步驟c中，第一區域91為預定於步驟f中使第一摻雜物擴散進入的區域。 Specifically, in step c, the first region 91 is a region scheduled to diffuse the first dopant into step f.

第4圖為第3D圖所示之一實施例的第一半導體結構90中的第一摻雜物濃度與深度的關係圖。深度0um的位置為第一半導體結構90之上表面，如第4圖所示，於第一區域91中的至少一部份，較佳地，第一區域91中鄰近第一半導體結構90之上表面的區域中，第一摻雜物之濃度隨摻雜深度增加而增加，即，於第一區域91中至少有一部分，越遠離第一半導體結構90之上表面的位置，第一摻雜物之濃度越高。 FIG. 4 is a diagram showing the relationship between the concentration of the first dopant and the depth in the first semiconductor structure 90 of the embodiment shown in FIG. 3D. The position with a depth of 0um is the upper surface of the first semiconductor structure 90, as shown in Figure 4, at least a part of the first region 91, preferably, the first region 91 is adjacent to the first semiconductor structure 90 In the surface area, the concentration of the first dopant increases with the depth of doping As the degree increases, the concentration of the first dopant increases, that is, at least a part of the first region 91 is farther away from the upper surface of the first semiconductor structure 90, the higher the concentration of the first dopant is.

於一實施例中，於步驟f之前，圖案化的半導體層100的導電型態與第一半導體結構90的導電型態兩者不同，例如，圖案化的半導體層100的導電型態為p型，第一半導體結構90為n型，於此態樣中，圖案化的半導體層100中的第一摻雜物為p型摻雜物，例如鋅(Zn)、鎂(Mg)、碳(C)或鈹(Be)，在此例中，第一摻雜物為鋅(Zn)。又例如，圖案化的半導體層100的導電型態為n型，第一半導體結構90為p型，於此態樣中，圖案化的半導體層100中的第一摻雜物為n型摻雜物，例如矽(Si)、碲(Te)或鍺(Ge)。接著，在步驟f中，由於圖案化的半導體層100位於第一半導體結構90的第一區域91的正上方並與第一區域91的上表面間接接觸或直接接觸，而第一半導體結構90之第二區域92上並未覆蓋有半導體層100，因此，圖案化的半導體層100中的第一摻雜物會進入第一半導體結構90的第一區域91，而第一半導體結構90之第二區域92實質上並未被影響。本申請中所指之「間接接觸」是指第一區域91的上表面和半導體層100之間可以有一或複數緩衝層，但第一摻雜物仍能穿過緩衝層進入第一區域91。故，於步驟f之後，第一半導體結構90的第一區域91的導電型態會改變，進而與第二反射鏡70的導電型態相同，而第一半導體結構90的第二區域92的導電型態依然與第二反射鏡70的導電型態不同。具體地，於步驟e之後，第一半導體結構90的第一區域91的導電型態相同於第二反射鏡70的導電型態，而第一區域91的導電型態不同於第二區域92的導電型態。例如，於步驟e之後，第二反射鏡70的導電型態為p型，第一半導體結構90的第一區域91的導電型態為p型，但第一半導體結構90的第二區域92的導電型態為n型。又例如，第二反射鏡70的導電型態為n型，第一半導體結構90的第一區域91的導電型態為n型，但第一半導體結構90的第二區域92的導電型態為p型。 In one embodiment, before step f, the conductivity type of the patterned semiconductor layer 100 is different from the conductivity type of the first semiconductor structure 90, for example, the conductivity type of the patterned semiconductor layer 100 is p-type , The first semiconductor structure 90 is n-type. In this aspect, the first dopant in the patterned semiconductor layer 100 is a p-type dopant, such as zinc (Zn), magnesium (Mg), carbon (C ) Or beryllium (Be). In this example, the first dopant is zinc (Zn). For another example, the conductivity type of the patterned semiconductor layer 100 is n-type, and the first semiconductor structure 90 is p-type. In this aspect, the first dopant in the patterned semiconductor layer 100 is n-type doping. Materials such as silicon (Si), tellurium (Te) or germanium (Ge). Next, in step f, since the patterned semiconductor layer 100 is located directly above the first region 91 of the first semiconductor structure 90 and in indirect or direct contact with the upper surface of the first region 91, the first semiconductor structure 90 The second region 92 is not covered with the semiconductor layer 100. Therefore, the first dopant in the patterned semiconductor layer 100 will enter the first region 91 of the first semiconductor structure 90, and the second region of the first semiconductor structure 90 Area 92 is not substantially affected. The “indirect contact” in this application means that there may be one or more buffer layers between the upper surface of the first region 91 and the semiconductor layer 100, but the first dopant can still pass through the buffer layer and enter the first region 91. Therefore, after step f, the conductivity type of the first region 91 of the first semiconductor structure 90 will be changed to be the same as the conductivity type of the second mirror 70, and the conductivity of the second region 92 of the first semiconductor structure 90 will be changed. The type is still different from the conductivity type of the second mirror 70. Specifically, after step e, the conductivity type of the first region 91 of the first semiconductor structure 90 is the same as that of the second reflector 70, and the conductivity type of the first region 91 is different from that of the second region 92 Conductivity type. For example, after step e, the conductivity type of the second mirror 70 is p-type, the conductivity type of the first region 91 of the first semiconductor structure 90 is p-type, but the first semiconductor structure The conductivity type of the second region 92 of the body structure 90 is n-type. For another example, the conductivity type of the second reflector 70 is n type, the conductivity type of the first region 91 of the first semiconductor structure 90 is n type, but the conductivity type of the second region 92 of the first semiconductor structure 90 is p-type.

於一實施例中，於步驟d中，半導體層100是於一第一溫度下形成於第一半導體結構90上，較佳地，第一溫度不低於550℃，且不高於700℃，又更佳地，第一溫度不低於580℃，且不高於670℃。 In one embodiment, in step d, the semiconductor layer 100 is formed on the first semiconductor structure 90 at a first temperature. Preferably, the first temperature is not lower than 550°C and not higher than 700°C, More preferably, the first temperature is not lower than 580°C and not higher than 670°C.

於一實施例中，加熱處理使圖案化的半導體層100的第一摻雜物進入第一半導體結構90的第一區域91中是操作於一第二溫度中，第二溫度低於形成半導體層100的第一溫度。較佳地，第一溫度與第二溫度的差異不大於50℃，且不小於5℃，又更佳地，不大於30℃。具體地，加熱處理的方式包含，但不限於將步驟e形成的結構放入爐管中進行加熱處理，或是將步驟d形成的結構放入有機金屬化學氣相沉積(Metalorganic Chemical Vapor Phase Deposition；MOCVD)的機台之腔室中進行加熱處理。 In one embodiment, the heat treatment to cause the first dopant of the patterned semiconductor layer 100 to enter the first region 91 of the first semiconductor structure 90 is operated at a second temperature, which is lower than the formation of the semiconductor layer The first temperature of 100. Preferably, the difference between the first temperature and the second temperature is not more than 50°C, and not less than 5°C, and more preferably, not more than 30°C. Specifically, the heating treatment method includes, but is not limited to, putting the structure formed in step e into a furnace tube for heating treatment, or putting the structure formed in step d into metal organic chemical vapor deposition (Metalorganic Chemical Vapor Phase Deposition; MOCVD) heat treatment in the chamber of the machine.

於一實施例中，發光結構可更包含一間隔層(圖未示)位於活性區域和第一導電型半導體層之間和/或位於活性區域和第二導電型半導體層之間，藉以調整發光結構的厚度以實質上接近或等於為nλ/2的厚度，其中λ為活性區域發射的輻射之峰值波長，並且n為正整數。間隔層材料為包含一三五族半導體材料，例如鋁砷化鎵(AlGaAs)。 In one embodiment, the light-emitting structure may further include a spacer layer (not shown) located between the active area and the first conductivity type semiconductor layer and/or between the active area and the second conductivity type semiconductor layer, so as to adjust the light emission. The thickness of the structure is substantially close to or equal to a thickness of nλ/2, where λ is the peak wavelength of radiation emitted by the active region, and n is a positive integer. The material of the spacer layer includes a Group III, Group 5 semiconductor material, such as aluminum gallium arsenide (AlGaAs).

第5圖為第3A圖至第3G圖之方法製造的半導體元件的實施例。當驅動如第5圖所示之雷射發光元件時，由於第一半導體結構90的第一區域91的導電型態相同於分別位於第一半導體結構90兩側的第二反射鏡70以及第三反射鏡110的導電型態，而第一半導體結構90的第二區域92的導電型態不同於分別位於第一半導體結構90兩側的第二反射鏡70以及第三反射鏡110的導電型態，因此電流會被第一半導體結構90的第二區域92限制而不能通過，進而集中由第一半導體結構90的第一區域91通過而流入發光結構80。換言之，第一半導體結構90於本實施例中可作為一電流限制結構，使電流通過預定的第一區域91。 Fig. 5 is an embodiment of a semiconductor device manufactured by the method shown in Fig. 3A to Fig. 3G. When driving the laser light emitting element as shown in Figure 5, since the conductivity type of the first region 91 of the first semiconductor structure 90 is the same as that of the second mirror 70 and the third mirror 70 located on both sides of the first semiconductor structure 90, respectively. The conductivity type of the reflector 110, while the conductivity type of the second region 92 of the first semiconductor structure 90 is not Same as the conductivity type of the second mirror 70 and the third mirror 110 located on both sides of the first semiconductor structure 90, so the current will be restricted by the second region 92 of the first semiconductor structure 90 and cannot pass through, and then concentrated by The first region 91 of the first semiconductor structure 90 passes and flows into the light emitting structure 80. In other words, the first semiconductor structure 90 can be used as a current limiting structure in this embodiment to allow current to pass through the predetermined first region 91.

第一反射鏡60、第二反射鏡70以及第三反射鏡110分別包含複數交替的第一折射率半導體層(圖未標)以及第二折射率半導體層(圖未標)，第一折射率半導體層具有一第一折射率，第二折射率半導體層具有一第二折射率，其中第一折射率高於第二折射率。第一反射鏡60、第二反射鏡70以及第三反射鏡110的材料包含一三五族半導體材料，例如鋁砷化鎵Al_xGa_(1-x)As/Al_yGa_(1-y)As，其中x不等於y，且鋁和鎵的含量可以調整藉以反射一欲反射的波長範圍。第一折射率半導體層以及第二折射率半導體層具有一接近或等於λ/4n的厚度，其中λ為活性區域22發射的輻射的峰值波長，n為層的折射率。第一反射鏡60在峰值波長具有一超過99%的反射率。第二反射鏡70以及第三反射鏡110在峰值波長具有一超過98%的反射率。較佳地，對於峰值波長，第一反射鏡60的反射率大於第二反射鏡70以及第三反射鏡110的反射率。第一反射鏡60的對數大於第二反射鏡70與第三反射鏡110對數的總和，其中一第一折射率半導體層與一相鄰第一折射率半導體層的第二折射率半導體層視為一對。在一實施例中，較佳地，第一反射鏡60的對數大於15，且更佳地，大於30且小於80。在一實施例中，較佳地，第二反射鏡70與第三反射鏡110的對數總和大於15，且更佳地，大於20且小於80。 The first reflector 60, the second reflector 70, and the third reflector 110 respectively include a plurality of alternating first refractive index semiconductor layers (not shown) and second refractive index semiconductor layers (not shown). The first refractive index The semiconductor layer has a first refractive index, and the second refractive index semiconductor layer has a second refractive index, wherein the first refractive index is higher than the second refractive index. The materials of the first reflector 60, the second reflector 70, and the third reflector 110 include a group-three-five semiconductor material, such as aluminum gallium arsenide Al _x Ga _(1-x) As/Al _y Ga _(1-y) As, where x is not equal to y, and the content of aluminum and gallium can be adjusted to reflect a wavelength range to be reflected. The first refractive index semiconductor layer and the second refractive index semiconductor layer have a thickness close to or equal to λ/4n, where λ is the peak wavelength of the radiation emitted by the active region 22, and n is the refractive index of the layer. The first mirror 60 has a reflectivity exceeding 99% at the peak wavelength. The second reflecting mirror 70 and the third reflecting mirror 110 have a reflectivity exceeding 98% at the peak wavelength. Preferably, for the peak wavelength, the reflectivity of the first reflector 60 is greater than the reflectivity of the second reflector 70 and the third reflector 110. The logarithm of the first mirror 60 is greater than the sum of the logarithms of the second mirror 70 and the third mirror 110, wherein a first refractive index semiconductor layer and a second refractive index semiconductor layer adjacent to the first refractive index semiconductor layer are regarded as A pair. In an embodiment, preferably, the logarithm of the first mirror 60 is greater than 15, and more preferably, greater than 30 and less than 80. In an embodiment, preferably, the sum of the logarithms of the second mirror 70 and the third mirror 110 is greater than 15, and more preferably, greater than 20 and less than 80.

於一實施例中，第一半導體結構90和半導體層100包含三五族半導體材料，例如鋁砷化鎵(AlGaAs)、磷化鋁鎵銦(AlGaInP)、磷砷化鎵(GaAsP)、InGaN(氮化銦鎵)或AlGaN(氮化鋁鎵)。於一實施例中，第一半導體結構90包含磷化鋁鎵銦(AlGaInP)，半導體層100包含鋁砷化鎵(AlGaAs)。更佳地，於一實施例中，第一半導體結構90包含(Al_yGa_(1-y))_1-xIn_xP，其中0.4≦x≦1，0≦y≦1。又於一實施例中，第一半導體結構90包含(Al_yGa_(1-y))_1-xIn_xP，其中0.49≦x≦0.51，0≦y≦0.6。於一實施例中，半導體層100中的第一摻雜物為鋅(Zn)。於一實施例中，第一半導體結構90具有一接近或等於λ/4n的厚度，其中λ為活性區域22發射的輻射的峰值波長，並且n為層的折射率。於一實施例中，第一半導體結構90可取代第二反射鏡70或第三反射鏡110的其中一第一折射率半導體層或第二折射率半導體層。 In one embodiment, the first semiconductor structure 90 and the semiconductor layer 100 include Group III and V semiconductor materials, such as aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), gallium arsenide phosphate (GaAsP), InGaN ( Indium gallium nitride) or AlGaN (aluminum gallium nitride). In one embodiment, the first semiconductor structure 90 includes aluminum gallium indium phosphide (AlGaInP), and the semiconductor layer 100 includes aluminum gallium arsenide (AlGaAs). More preferably, in one embodiment, the first semiconductor structure 90 includes (Al _y Ga _(1-y) ) _1-x In _x P, where 0.4≦x≦1 and 0≦y≦1. In another embodiment, the first semiconductor structure 90 includes (Al _y Ga _(1-y) ) _1-x In _x P, where 0.49≦x≦0.51, 0≦y≦0.6. In one embodiment, the first dopant in the semiconductor layer 100 is zinc (Zn). In one embodiment, the first semiconductor structure 90 has a thickness close to or equal to λ/4n, where λ is the peak wavelength of the radiation emitted by the active region 22, and n is the refractive index of the layer. In one embodiment, the first semiconductor structure 90 can replace one of the first refractive index semiconductor layer or the second refractive index semiconductor layer of the second mirror 70 or the third mirror 110.

於一實施例中，第二反射鏡70中其中一對中的第一折射率半導體層為一含鋁半導體層，且其鋁含量相較於其他對中的第一折射率半導體層中的鋁含量高。較佳地，含鋁半導體層包含Al_xGa_(1-x)As，其中0.9≦x≦1.0。於本實施例中，於步驟j之前，製造半導體發光元件的方法更包含氧化含鋁半導體層，使含鋁半導體層的周圍最外邊且裸露的部分開始氧化，並漸漸往內側氧化以使含鋁半導體層包含一未被氧化的半導體部分以及環繞半導體部分的氧化物部分。氧化物部分之材料包含氧化鋁，其化學式係為Al_aO_b，其中a與b為不為0之自然數。具體地，氧化方法包含濕熱氧化法(wet thermal oxidation)。當驅動本實施例之雷射發光元件時，由於第一半導體結構90的第一區域91的導電型態相同於位於兩側的第二反射鏡70以及第三反射鏡110的導電型態，而第一半導體結構90的第二區域92的導電型態不同於位於兩側的第二反射鏡70以及第三反射鏡110的導電型態，因此電流會被第一半導體結構90的第二區域92限制而不能通過，進而通過第一半導體結構90的第一區域91而進入於第二反射鏡70。進一步地，由於氧化物部分為絕緣材料，進入於第二反射鏡70的電流會再被氧化物部分限制而不能通過，進而從含鋁半導體層中的半導體部分通過而進入發光結構80。換言之，第一半導體結構90於本實施例中可作為一電流限制結構，使電流通過預定的第一區域91。 In one embodiment, the first refractive index semiconductor layer in one pair of the second mirror 70 is an aluminum-containing semiconductor layer, and its aluminum content is compared with the aluminum in the first refractive index semiconductor layer in other pairs. High content. Preferably, the aluminum-containing semiconductor layer includes Al _x Ga _(1-x) As, where 0.9≦x≦1.0. In this embodiment, before step j, the method for manufacturing a semiconductor light-emitting element further includes oxidizing the aluminum-containing semiconductor layer, so that the outermost and exposed part of the aluminum-containing semiconductor layer begins to oxidize, and gradually oxidizes to the inside to make the aluminum-containing semiconductor layer. The semiconductor layer includes an unoxidized semiconductor portion and an oxide portion surrounding the semiconductor portion. The material of the oxide part includes alumina, and its chemical formula is Al _a O _b , where a and b are natural numbers other than zero. Specifically, the oxidation method includes wet thermal oxidation (wet thermal oxidation). When driving the laser light emitting element of this embodiment, since the conductivity type of the first region 91 of the first semiconductor structure 90 is the same as the conductivity type of the second mirror 70 and the third mirror 110 located on both sides, The conductivity type of the second region 92 of the first semiconductor structure 90 is different from the conductivity type of the second mirror 70 and the third mirror 110 on both sides, so the current will be absorbed by the second region 92 of the first semiconductor structure 90 It is restricted and cannot pass, and then enters the second mirror 70 through the first region 91 of the first semiconductor structure 90. Further, since the oxide part is an insulating material, the current entering the second reflector 70 will be restricted by the oxide part and cannot pass, and then passes through the semiconductor part in the aluminum-containing semiconductor layer and enters the light emitting structure 80. In other words, the first semiconductor structure 90 can be used as a current limiting structure in this embodiment to allow current to pass through the predetermined first region 91.

於一實施例中，第三反射鏡110中其中一對的第一折射率半導體層為一含鋁半導體層，且其鋁含量相較於其他對中的第一折射率半導體層中的鋁含量高。較佳地，含鋁半導體層包含Al_xGa_(1-x)As，其中0.9≦x≦1.0。於本實施例中，於步驟j之前，製造半導體發光元件的方法更包含氧化含鋁半導體層，使含鋁半導體層的周圍最外邊且裸露的部分開始氧化，並漸漸往內側氧化以使含鋁半導體層包含一未被氧化的半導體部分以及環繞半導體部分的氧化物部分。氧化物部分之材料包含氧化鋁，其化學式係為Al_aO_b，其中a與b為不為0之自然數。具體地，氧化方法包含濕熱氧化法(wet thermal oxidation)。當驅動本實施例之雷射發光元件時，由於氧化物部分為絕緣材料，進入於第三反射鏡110的電流會被氧化物部分限制而不能通過，進而從含鋁半導體層中的半導體部分通過而進入第一半導體結構90，進一步地，由於第一半導體結構90的第一區域91的導電型態相同於位於兩側的第二反射鏡70以及第三反射鏡110的導電型態，而第一半導體結構90的第二區域92的導電型態不同於位於兩側的第二反射鏡70以及第三反射鏡110的導電型態，因此電流會被第一半導體結構90的第二區域92限制而不能通過，進而通過第一半導體結構90的第一區域91而進入發光結構80。 In one embodiment, the first refractive index semiconductor layer of one pair of the third mirror 110 is an aluminum-containing semiconductor layer, and its aluminum content is compared with the aluminum content of the first refractive index semiconductor layer of the other pairs high. Preferably, the aluminum-containing semiconductor layer includes Al _x Ga _(1-x) As, where 0.9≦x≦1.0. In this embodiment, before step j, the method of manufacturing a semiconductor light-emitting element further includes oxidizing the aluminum-containing semiconductor layer, so that the outermost and exposed part of the aluminum-containing semiconductor layer begins to oxidize, and gradually oxidizes to the inside to make the aluminum-containing semiconductor layer. The semiconductor layer includes an unoxidized semiconductor portion and an oxide portion surrounding the semiconductor portion. The material of the oxide part includes alumina, and its chemical formula is Al _a O _b , where a and b are natural numbers other than zero. Specifically, the oxidation method includes wet thermal oxidation (wet thermal oxidation). When the laser light emitting element of this embodiment is driven, since the oxide part is an insulating material, the current entering the third mirror 110 is restricted by the oxide part and cannot pass, and then passes through the semiconductor part in the aluminum-containing semiconductor layer Into the first semiconductor structure 90, further, since the conductivity type of the first region 91 of the first semiconductor structure 90 is the same as the conductivity type of the second mirror 70 and the third mirror 110 on both sides, The conductivity type of the second region 92 of a semiconductor structure 90 is different from the conductivity types of the second mirror 70 and the third mirror 110 on both sides, so the current will be limited by the second region 92 of the first semiconductor structure 90 It cannot pass, and then enters the light emitting structure 80 through the first region 91 of the first semiconductor structure 90.

活性區域包含單異質結構(single heterostructure，SH)、雙異質結構(double heterostructure，DH)或多重量子井(MQW)。較佳的，活性區域包含多重量子井(MQW)，其包含交替的井層以及阻障層。每一阻障層的能階大於其中一井層的能階。活性區域發出的峰值波長可以藉由改變井層的厚度或是材料而改變。較佳地，井層的材料包含一三五族半導體材料，例如鋁砷化鎵(AlGaAs)、磷化鋁鎵銦(AlGaInP)、磷砷化鎵(GaAsP)或InGaN(氮化銦鎵)。阻障層的材料包含三五族半導體材料，例如鋁砷化鎵(AlGaAs)、磷化鋁鎵銦(AlGaInP)或AlGaN(氮化鋁鎵)。 The active region includes single heterostructure (SH), double heterostructure (DH) or multiple quantum well (MQW). Preferably, the active region includes a multiple quantum well (MQW), which includes alternating well layers and barrier layers. The energy level of each barrier layer is greater than the energy level of one of the well layers. The peak wavelength emitted by the active region can be changed by changing the thickness or material of the well layer. Preferably, the material of the well layer includes a group III-V semiconductor material, such as aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), gallium arsenide phosphate (GaAsP), or InGaN (indium gallium nitride). The barrier layer includes three-five group semiconductor materials, such as aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), or AlGaN (aluminum gallium nitride).

於一實施例中，成長基板10或40具有一足夠的厚度以支撐之後成長在基板10或40上的層或是結構。較佳地，成長基板10或40之厚度不小於100微米，且較佳地，不超過250微米。成長基板10或40是單晶且包含半導體材料，例如，包含一個三五族半導體材料或是四族半導體材料。於一實施例中，成長基板10或40包含一具有一n型或p型的三五族半導體材料。例如，三五族半導體材料包含n型的砷化鎵(GaAs)，n型摻雜物為矽(Si)。 In one embodiment, the growth substrate 10 or 40 has a sufficient thickness to support the layer or structure to be grown on the substrate 10 or 40 later. Preferably, the thickness of the growth substrate 10 or 40 is not less than 100 microns, and preferably, it does not exceed 250 microns. The growth substrate 10 or 40 is a single crystal and includes a semiconductor material, for example, includes a group three or five semiconductor material or a group four semiconductor material. In one embodiment, the growth substrate 10 or 40 includes a group III-V semiconductor material having an n-type or p-type. For example, the third and fifth group semiconductor materials include n-type gallium arsenide (GaAs), and the n-type dopant is silicon (Si).

第一電極130以及第二電極140用於與一外接電源連接且傳導一在兩者之間的電流。第一電極130以及第二電極140的材料包含透明導電材料或是金屬材料。透明導電材料包含透明導電氧化物，金屬材料包含金(Au)、鉑(Pt)、鍺金鎳(GeAuNi)、鈦(Ti)、鈹金(BeAu)、鍺金(GeAu)、鋁(Al)、鋅金(ZnAu)或鎳。 The first electrode 130 and the second electrode 140 are used to connect to an external power source and conduct a current between them. The material of the first electrode 130 and the second electrode 140 includes a transparent conductive material or a metal material. Transparent conductive materials include transparent conductive oxides, metal materials include gold (Au), platinum (Pt), germanium gold nickel (GeAuNi), titanium (Ti), beryllium gold (BeAu), germanium gold (GeAu), aluminum (Al) , Zinc gold (ZnAu) or nickel.

第一電極130藉由半導體接觸層120與第三反射鏡110形成一低電阻接觸或是歐姆接觸，其中第一電極130與第三反射鏡110之間的電阻低於10^-2ohm-cm。半導體接觸層120的導電型態與第三反射鏡110導電型態相同。於一實施例中，半導體接觸層120為p型且具有一高p型摻雜濃度，例如高於1x10¹⁸/cm³，且較佳地，高於1x10¹⁹/cm³，且更佳地，介於1x10¹⁹/cm³以及5x10²²/cm³之間(兩者皆含)。半導體接觸層120的材料包含一三五族半導體材料，例如砷化鎵(GaAs)或鋁砷化鎵(AlGaAs)。 The first electrode 130 forms a low-resistance contact or ohmic contact with the third mirror 110 through the semiconductor contact layer 120, wherein the resistance between the first electrode 130 and the third mirror 110 is lower than 10 ^-2 ohm-cm. The conductivity type of the semiconductor contact layer 120 is the same as the conductivity type of the third mirror 110. In one embodiment, the semiconductor contact layer 120 is p-type and has a high p-type doping concentration, for example, higher than 1x10 ¹⁸ /cm ³ , and preferably, higher than 1x10 ¹⁹ /cm ³ , and more preferably, Between 1x10 ¹⁹ /cm ³ and 5x10 ²² /cm ³ (both included). The material of the semiconductor contact layer 120 includes a group III-V semiconductor material, such as gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs).

磊晶成長的方法包含，但不限於，金屬有機化學氣相沉積(metal-organic chemical vapor deposition，MOCVD)、氫化物氣相磊晶法(hydride vapor phase epitaxy，HVPE)、分子束磊晶(molecular beam epitaxy，MBE)或液相磊晶法(liquid-phase epitaxy，LPE)。 Methods of epitaxy growth include, but are not limited to, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), and molecular beam epitaxy (molecular beam epitaxy). beam epitaxy, MBE) or liquid-phase epitaxy (LPE).

需注意的是，本申請所列舉之各實施例僅用以說明本申請，並非用以限制本申請之範圍。任何人對本申請所作顯而易見的修飾或變更皆不脫離本申請之精神與範圍。不同實施例中相同或相似的構件，或者不同實施例中具相同標號的構件皆具有相同的物理或化學特性。此外，本申請中上述之實施例在適當的情況下，是可互相組合或替換，而非僅限於所描述之特定實施例。在一實施例中詳細描述之特定構件與其他構件的連接關係亦可以應用於其他實施例中，且均落於如後之本申請之權利保護範圍的範疇中。 It should be noted that the embodiments listed in this application are only used to illustrate the application, and are not used to limit the scope of the application. Any obvious modification or alteration of this application by anyone does not depart from the spirit and scope of this application. The same or similar components in different embodiments, or components with the same number in different embodiments have the same physical or chemical properties. In addition, the above-mentioned embodiments in this application can be combined or replaced with each other under appropriate circumstances, and are not limited to the specific embodiments described. The connection relationship between specific components and other components described in detail in one embodiment can also be applied to other embodiments, and all fall within the scope of the protection of the rights of this application as follows.

40‧‧‧成長基板 40‧‧‧Growth substrate

50‧‧‧磊晶結構 50‧‧‧Epitaxial structure

60‧‧‧第一反射鏡 60‧‧‧First reflector

92‧‧‧第二區域 92‧‧‧Second area

70‧‧‧第二反射鏡 70‧‧‧Second mirror

80‧‧‧發光結構 80‧‧‧Light-emitting structure

90‧‧‧第一半導體結構 90‧‧‧First semiconductor structure

91‧‧‧第一區域 91‧‧‧First area

100‧‧‧半導體層 100‧‧‧Semiconductor layer

Claims

一種製造半導體元件的方法，包含：提供一活性區域；形成一第一反射鏡及一第二反射鏡，分別位於該活性區域兩側；形成一第一半導體結構，其包含一第一區域以及一第二區域；形成一第二半導體層於該第一半導體結構上；使一摻雜物進入該第一半導體結構；以及完全移除該第二半導體層。A method of manufacturing semiconductor components, including: Provide an active area; Forming a first reflecting mirror and a second reflecting mirror, respectively located on both sides of the active area; Forming a first semiconductor structure including a first region and a second region; Forming a second semiconductor layer on the first semiconductor structure; Allowing a dopant to enter the first semiconductor structure; and The second semiconductor layer is completely removed.

如申請專利範圍第1項所述之製造半導體元件的方法，其中該第二半導體層形成於該第一區域上。According to the method of manufacturing a semiconductor device described in the first item of the scope of the patent application, the second semiconductor layer is formed on the first region.

如申請專利範圍第2項所述之製造半導體元件的方法，更包含加熱處理及/或加壓處理該第二半導體層使該摻雜物從第二半導體進入該第一半導體結構之該第一區域。The method of manufacturing a semiconductor device as described in the second item of the scope of the patent application further includes heat treatment and/or pressure treatment of the second semiconductor layer so that the dopant enters the first semiconductor structure from the second semiconductor. area.

如申請專利範圍第3項所述之製造半導體元件的方法，其中該第一區域的導電型態與該第一反射鏡或該第二反射鏡的導電型態相同。According to the method of manufacturing a semiconductor device as described in item 3 of the scope of patent application, the conductivity type of the first region is the same as the conductivity type of the first mirror or the second mirror.

如申請專利範圍第1項所述之製造半導體元件的方法，其中，該第一區域中的該摻雜物之濃度大於該第二區域中該摻雜物的濃度，且該第一區域中的該摻雜物之濃度與該第二區域中該摻雜物的濃度差異大於1´10¹⁶ /cm³ 。The method for manufacturing a semiconductor device as described in claim 1, wherein the concentration of the dopant in the first region is greater than the concentration of the dopant in the second region, and the concentration of the dopant in the first region The difference between the concentration of the dopant and the concentration of the dopant in the second region is greater than 1´10 ¹⁶ /cm ³ .

如申請專利範圍第1項所述之製造半導體元件的方法，其中該第一區域中的該摻雜物之濃度大於1´10¹⁸ /cm³ 。According to the method for manufacturing a semiconductor device as described in item 1 of the scope of the patent application, the concentration of the dopant in the first region is greater than 1´10 ¹⁸ /cm ³ .

如申請專利範圍第1項所述之製造半導體元件的方法，更包括於該第一半導體結構上形成一第三反射鏡。The method of manufacturing a semiconductor device as described in the first item of the scope of the patent application further includes forming a third mirror on the first semiconductor structure.

如申請專利範圍第1項所述之製造半導體元件的方法，其中該摻雜物包含鋅(Zn)、鎂(Mg)或碳(C) 。The method for manufacturing a semiconductor device as described in the first item of the patent application, wherein the dopant contains zinc (Zn), magnesium (Mg) or carbon (C).

如申請專利範圍第1項所述之製造半導體元件的方法，其中該第一半導體結構包含三五族半導體材料。According to the method for manufacturing a semiconductor device as described in claim 1, wherein the first semiconductor structure includes Group III or V semiconductor materials.

如申請專利範圍第1項所述之製造半導體元件的方法，其中該半導體元件可發出遠場角大於60度的非同調光或遠場角小於25度的同調光。According to the method of manufacturing a semiconductor device described in the first item of the scope of the patent application, the semiconductor device can emit non-coherent dimming with a far field angle greater than 60 degrees or co-dimming with a far field angle less than 25 degrees.