TWI698785B - Touch panel driving device and touch panel device - Google Patents
Touch panel driving device and touch panel device Download PDFInfo
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Abstract
[課題]觸控面板的感測精度之提升。 [解決手段]觸控面板驅動裝置具備接收電路，前述接收電路是接收來自觸控面板的一對接收訊號線之藉由伴隨於操作的電容變化而使波形變化的各接收訊號，並且生成用於觸控面板操作監視的檢測值。 在此接收電路中設置有測量用電容部，前述測量用電容部具有可各自並聯地連接於一邊的接收訊號線之電容值不同的第1至第X電容部、及對應於該等電容部的第1至第X開關。並且進行下述動作來生成檢測值：一面藉由第1至第X開關來依序切換連接於一邊的接收訊號線的電容值，一面比較各接收訊號的位準。在此情況下在積體電路中是設成設置有：第1區域，配置構成第1至第X電容部的電容元件；第2區域，配置與較小類型的電容部相對應的開關；及第3區域，配置與較大類型的電容部相對應的開關，第2區域是形成在比第3區域更接近於第1的位置。[Subject] Improvement of the sensing accuracy of the touch panel. [Solution] The touch panel driving device is equipped with a receiving circuit. The receiving circuit receives each received signal from a pair of receiving signal lines from the touch panel whose waveform changes due to a change in capacitance accompanying the operation, and generates The detection value of touch panel operation monitoring. The receiving circuit is provided with a measuring capacitor section, and the above-mentioned measuring capacitor section has first to Xth capacitor sections that can be connected in parallel to one side of the receiving signal line with different capacitance values, and corresponding capacitor sections. 1st to Xth switches. And perform the following actions to generate the detection value: while sequentially switching the capacitance value of the receiving signal line connected to one side by the first to Xth switches, while comparing the level of each received signal. In this case, the integrated circuit is provided with: a first area where the capacitive elements constituting the first to X-th capacitor parts are arranged; the second area where switches corresponding to smaller types of capacitor parts are arranged; and In the third area, a switch corresponding to a larger type of capacitor portion is arranged, and the second area is formed at a position closer to the first than the third area.
Description
本發明是有關於一種觸控面板驅動裝置及觸控面板裝置，特別是有關於一種用於觸控面板操作檢測的技術。 The present invention relates to a touch panel driving device and a touch panel device, and more particularly to a technology used for touch panel operation detection.
有關於觸控面板已知有各種技術，在下述專利文獻1中揭示有一種感測技術，前述感測技術是藉由同時地進行2組(一對發送訊號線與一對接收訊號線)的訊號線(電極)之感測來進行觸控操作位置的檢測，以提升解析度。
There are various technologies known for touch panels. The following
又，在下述專利文獻2中揭示有所謂的單層方式的構造，前述構造是設成在X、Y方向的電極配線中不設置電極交叉的部分。
In addition, the following
專利文獻1：日本專利特開2014-219961號公報 Patent Document 1: Japanese Patent Laid-Open No. 2014-219961
專利文獻2：日本專利特開2010-182277號公報 Patent Document 2: Japanese Patent Laid-Open No. 2010-182277
在觸控面板中維持或提升感測精度是重要的。並且，為了操作的檢測會變得要進行觸控面板的訊號線的掃描，且在靜電電容方式的觸控面板之情況下，是形成為在掃描時，檢測因應於觸控操作所造成的電容變化之來自訊號線的訊號電壓的變化或差分。因此，形成下述情形：成為用於檢測訊號電壓的變化或差分的基準之值的精度，會支配觸控面板操作的感測精度。 It is important to maintain or improve the sensing accuracy in the touch panel. In addition, it is necessary to scan the signal lines of the touch panel for operation detection. In the case of an electrostatic capacitive touch panel, it is formed to detect the capacitance caused by the touch operation during scanning. The change comes from the change or difference of the signal voltage of the signal line. Therefore, there is a situation in which the accuracy of the reference value for detecting the change or difference of the signal voltage will dominate the sensing accuracy of the touch panel operation.
在本發明中，是考慮下述作法：接收來自觸控面板的一對接收訊號線的各接收訊號並進行檢測。特別是進行包含下述動作的感測動作：一面依序切換連接於一邊的接收訊號線之測量用電容部之電容值，一面比較來自一邊與另一邊的接收訊號線的各接收訊號之位準。在此情況下，目的是提高電容值的精度並且提升感測精度。 In the present invention, the following method is considered: receiving and detecting each receiving signal from a pair of receiving signal lines of the touch panel. In particular, the sensing operation includes the following actions: while sequentially switching the capacitance value of the measuring capacitor connected to the receiving signal line on one side, and comparing the level of each received signal from the receiving signal line on one side and the other side . In this case, the purpose is to improve the accuracy of the capacitance value and improve the sensing accuracy.
本發明之觸控面板驅動裝置，是對觸控面板進行掃描的觸控面板驅動裝置，前述掃描是依序選擇相鄰的一對發送訊號線與相鄰的一對接收訊號線之掃描，前述觸控面板驅動裝置具備接收電路，前述接收電路是接收來自前述觸控面板的一對接收訊號線之藉由伴隨於操作的電容變化而使波形變化的各接收訊號，並且生成用於觸控面板操作監視的檢測值。在前述接收電路中設置有測量用電 容部，前述測量用電容部具有複數個電容部及複數個開關，前述電容部是電容值不同的第1電容部至第X電容部，且可各自並聯地連接於一邊的接收訊號線，前述開關是對應於前述第1電容部至前述第X電容部的每一個的第1開關至第X開關(X為2以上的自然數)。 The touch panel driving device of the present invention is a touch panel driving device that scans the touch panel. The aforementioned scanning is to sequentially select a pair of adjacent transmitting signal lines and a pair of adjacent receiving signal lines. The touch panel driving device is provided with a receiving circuit, and the receiving circuit receives each received signal whose waveform is changed by the capacitance change accompanying the operation from a pair of receiving signal lines from the touch panel, and generates it for the touch panel Operation monitoring detection value. The measuring power is provided in the aforementioned receiving circuit The capacitance portion, the capacitance portion for measurement has a plurality of capacitance portions and a plurality of switches, the capacitance portions are the first to Xth capacitance portions with different capacitance values, and each of them can be connected in parallel to the receiving signal line on one side, The switches are the first switch to the Xth switch (X is a natural number greater than or equal to 2) corresponding to each of the first capacitor portion to the Xth capacitor portion.
前述接收電路是設成進行下述動作來生成前述檢測值：一面藉由前述第1開關至第X開關來選擇連接於前述一邊的接收訊號線的電容部，藉此依序切換前述測量用電容部的電容值，一面比較來自前述一邊的接收訊號線與另一邊的接收訊號線的各接收訊號之位準。在包含前述接收電路的積體電路中設置有：第1區域，配置構成前述第1電容部至第X電容部的電容元件；第2區域，配置與前述第1電容部至第X電容部當中被分在電容值較小之側的電容部相對應的前述開關；及第3區域，配置與前述第1電容部至第X電容部當中被分在電容值較大之側的電容部相對應的前述開關，前述第2區域是形成在比前述第3區域更接近前述第1區域的位置。 The receiving circuit is configured to perform the following actions to generate the detection value: while selecting the capacitor connected to the receiving signal line on the one side by the first switch to the Xth switch, the measurement capacitor is sequentially switched The capacitance value of the part is compared with the level of each received signal from the receiving signal line on one side and the receiving signal line on the other side. The integrated circuit including the receiving circuit is provided with: a first area where the capacitive elements constituting the first capacitor portion to the X-th capacitor portion are arranged; the second area is arranged between the first capacitor portion to the X-th capacitor portion The aforementioned switch corresponding to the capacitor portion on the side with the smaller capacitance value; and the third area is arranged corresponding to the capacitor portion on the side with the larger capacitance value among the first to Xth capacitor portions In the switch, the second area is formed at a position closer to the first area than the third area.
在像這樣的本發明中是利用差動方式來作為觸控面板的感測。亦即，生成相當於來自一對接收訊號線的接收訊號的差分之檢測值。作為用於此的手法，是一面依序切換連接於一邊的接收訊號線的測量用電容部之電容值，一面比較來自一邊與另一邊的接收訊號線的各接收訊號之位準。根據此動作，各接收訊號的位準成為大致同等時的電容值(或電容值的選擇控制訊號)，會成為相當於各接收訊 號的差分之值。從而，可以藉由上述動作來生成用於觸控面板操作監視的檢測值。然而，若測量用電容部的各階段的電容值之線性度(linearity)較差，會無法作正確的檢測。在此，電容元件與開關元件的寄生電容成為電容誤差的一個原因。並且，越小的電容的電容器，越會讓由寄生電容的影響所造成的電容誤差變大。又，寄生電容是配線變長即增加。於是，設成藉由將第2區域設為比第3區域更接近於第1區域的位置，以使較小電容的電容部與開關之間的配線長度變得較短。 In the present invention like this, a differential method is used as the sensing of the touch panel. That is, a detection value corresponding to the difference of the received signal from a pair of received signal lines is generated. The method used for this is to sequentially switch the capacitance values of the measuring capacitors connected to the receiving signal line on one side, and to compare the levels of the respective received signals from the receiving signal line on one side and the other side. According to this action, the capacitance value (or the selection control signal of the capacitance value) when the levels of each received signal become approximately the same, will become equivalent to each received signal The difference of the number. Therefore, it is possible to generate a detection value for monitoring the operation of the touch panel through the above-mentioned operation. However, if the linearity of the capacitance value of each stage of the capacitance portion for measurement is poor, accurate detection may not be performed. Here, the parasitic capacitance of the capacitive element and the switching element becomes a cause of capacitance error. In addition, a capacitor with a smaller capacitance will increase the capacitance error caused by the influence of parasitic capacitance. In addition, the parasitic capacitance increases as the wiring becomes longer. Therefore, by setting the second region to a position closer to the first region than the third region, the wiring length between the capacitor portion with a smaller capacitance and the switch becomes shorter.
在上述之觸控面板驅動裝置中，可考慮下述作法：在前述第1區域內，在前述第1電容部至前述第X電容部之電容部當中，將形成電容值較小的電容部之電容元件，配置在比形成電容值較大的電容部之電容元件更接近於前述第2區域的位置。 In the above-mentioned touch panel driving device, the following method can be considered: in the first region, among the capacitor portions from the first capacitor portion to the X-th capacitor portion, a capacitor portion with a smaller capacitance value will be formed The capacitor element is arranged at a position closer to the aforementioned second region than the capacitor element forming the capacitor portion with a larger capacitance value.
在積體電路的第1區域中，雖然形成有構成第1電容部至第X電容部之各電容部的電容元件，但此時是設成讓構成較小電容的電容部之電容元件儘量接近於第2區域。 In the first area of the integrated circuit, although the capacitor elements constituting the first capacitor portion to the X-th capacitor portion are formed, in this case, the capacitor elements constituting the capacitor portion of the smaller capacitor are set as close as possible In the second area.
在上述之觸控面板驅動裝置中，可考慮下述作法：形成前述第1電容部至前述第X電容部之各電容部的複數個電容元件，全部都是藉由特定的電容值的電容元件所形成，且在前述第1區域中，構成每一個電容部的電容元件是配置成點對稱。 In the above-mentioned touch panel driving device, the following method may be considered: the plurality of capacitive elements forming each of the first capacitive part to the aforementioned Xth capacitive part are all capacitive elements with specific capacitance values It is formed, and in the aforementioned first region, the capacitive elements constituting each capacitive part are arranged in point symmetry.
將用於得到各電容部CM的電容值的電容元件(電容器)，全部設為特定的電容值的電容器，亦即相同面積的電 容器。並且，藉由並聯連接或直接連接來形成各電容部的電容。並且，在各電容部中，雖然配置有複數個構成該電容部的電容元件，但是將該等複數個電容元件配置成在第1區域中相對於例如中央點而成為點對稱。 The capacitance elements (capacitors) used to obtain the capacitance value of each capacitance portion CM are all set as capacitors of a specific capacitance value, that is, the capacitance of the same area container. In addition, the capacitance of each capacitor portion is formed by parallel connection or direct connection. In addition, in each capacitor portion, although a plurality of capacitor elements constituting the capacitor portion are arranged, the plurality of capacitor elements are arranged so as to be point-symmetrical with respect to, for example, a central point in the first region.
在上述之觸控面板驅動裝置中，可考慮下述作法：在前述第1電容部至前述第X電容部之各電容部當中，預定值以上的電容值的電容部是藉由複數個電容元件的並聯連接所形成。 In the above-mentioned touch panel driving device, the following method can be considered: among the capacitor portions from the first capacitor portion to the X-th capacitor portion, a capacitor portion having a capacitance value of a predetermined value or more is made of a plurality of capacitor elements Formed by the parallel connection.
越包含較大的電容的電容元件(電容器)，作為整體面積比變得越大。藉由針對預定值以上的電容部，是以電容元件的並聯連接來形成必要的電容，可以將在整體上的面積比變小。 The larger the capacitance element (capacitor) is included, the larger the overall area ratio becomes. By connecting the capacitor elements in parallel to form the necessary capacitance for the capacitor portion having a predetermined value or more, the overall area ratio can be reduced.
本發明的觸控面板裝置是具有觸控面板、及上述的觸控面板驅動裝置而構成。 The touch panel device of the present invention includes a touch panel and the above-mentioned touch panel driving device.
亦即，藉由利用已提高電容精度的觸控面板驅動裝置，以實現感測精度較佳的觸控面板裝置。 That is, by using the touch panel driving device with improved capacitance accuracy, a touch panel device with better sensing accuracy is realized.
根據本發明，可以藉由將寄生電容的影響較大，而為較小的類型的電容部之電容元件與開關的距離相對地縮短，以作為整體來緩和電容的誤差的程度之差，並藉此將測量用電容部賦與至接收訊號線之各階段的電容的線性度提升。從而，可以提升觸控面板的感測精度，並且可以提升作為操作位置的座標的再現性或正確性。 According to the present invention, the distance between the capacitive element and the switch of the capacitive part of a relatively small type of capacitive part having a relatively large influence of parasitic capacitance can be relatively shortened, so as to alleviate the difference in the degree of capacitance error as a whole. This improves the linearity of the capacitance assigned to each stage of the receiving signal line by the measurement capacitor. Thus, the sensing accuracy of the touch panel can be improved, and the reproducibility or accuracy of the coordinates as the operating position can be improved.
1:觸控面板裝置 1: Touch panel device
2:觸控面板 2: Touch panel
3:觸控面板驅動裝置 3: Touch panel drive device
4:感測器IC 4: Sensor IC
5:MCU 5: MCU
21、21-1~21-n:發送訊號線 21, 21-1~21-n: Send signal line
22、22-1~22-m:接收訊號線 22, 22-1~22-m: receiving signal line
31:觸控面板側連接端子部 31: Connecting terminal on the touch panel side
32:製品側連接端子部 32: Product side connection terminal part
41:發送電路 41: sending circuit
42:接收電路 42: receiving circuit
43:多工器 43: Multiplexer
44:介面暫存器電路 44: Interface register circuit
45:電源電路 45: power circuit
90:製品側MCU 90: Product side MCU
411、412:驅動器 411, 412: Drive
421:比較器 421: Comparator
422:基準電容部 422: Reference capacitor
423、425、SW、SW0~SW10:開關 423, 425, SW, SW0~SW10: switch
424:測量用電容部 424: Capacitance part for measurement
426:運算控制部 426: Operation Control Department
A1、A2:位置 A1, A2: location
AR1:第1區域
AR1:
AR2:第2區域
AR2:
AR3:第3區域
AR3:
C22、C23、C32、C33:電容 C22, C23, C32, C33: capacitance
CM、CM0~CM10:電容部 CM, CM0~CM10: Capacitor
CAR:粗線(第1區域的中央部) CAR: Thick line (the center of the first area)
Cs:寄生電容 Cs: Parasitic capacitance
CT:中心點 CT: center point
S100、S101、S102、S103、S104、S105、S106、S107、 S108、S109:步驟 S100, S101, S102, S103, S104, S105, S106, S107, S108, S109: steps
Sg1、Sg2、Sg3:波形 Sg1, Sg2, Sg3: Waveform
Ta、Ti:端子 Ta, Ti: terminal
x、y:方向 x, y: direction
圖1是本發明之實施形態的觸控面板裝置之方塊圖。 Fig. 1 is a block diagram of a touch panel device according to an embodiment of the present invention.
圖2是實施形態的觸控面板的訊號線構造之說明圖。 2 is an explanatory diagram of the signal line structure of the touch panel of the embodiment.
圖3是實施形態的感測動作之說明圖。 Fig. 3 is an explanatory diagram of the sensing operation of the embodiment.
圖4是實施形態之第1例的測量用電容部之說明圖。 Fig. 4 is an explanatory diagram of a measuring capacitor part of the first example of the embodiment.
圖5是實施形態的感測動作順序之流程圖。 Fig. 5 is a flowchart of the sensing operation sequence of the embodiment.
圖6是不同的電容的佈置影像之說明圖。 Fig. 6 is an explanatory diagram of the layout images of different capacitors.
圖7是實施形態的感測器IC中的測量用電容部的元件配置之說明圖。 Fig. 7 is an explanatory diagram of the element arrangement of the measuring capacitor portion in the sensor IC of the embodiment.
圖8是實施形態中的座標檢測精度提升之說明圖。 Fig. 8 is an explanatory diagram of an improvement in the accuracy of coordinate detection in the embodiment.
圖9是實施形態的測量用電容部的第2例的構成之說明圖。 Fig. 9 is an explanatory diagram of the configuration of a second example of the measuring capacitor portion of the embodiment.
圖10是實施形態的測量用電容部的第3例的構成之說明圖。 Fig. 10 is an explanatory diagram of the configuration of a third example of the measuring capacitor portion of the embodiment.
圖11是實施形態的測量用電容部的第4例的構成之說明圖。 Fig. 11 is an explanatory diagram of the configuration of a fourth example of the measuring capacitor portion of the embodiment.
圖12是電容器的設計尺寸與成品尺寸的差之說明圖。 Fig. 12 is an explanatory diagram of the difference between the design size of the capacitor and the finished size.
圖13是實施形態的第4例的元件配置之說明圖。 Fig. 13 is an explanatory diagram of the element arrangement of the fourth example of the embodiment.
圖14是實施形態的測量用電容部的第5例的構成之說明圖。 Fig. 14 is an explanatory diagram of the configuration of the fifth example of the measurement capacitor portion of the embodiment.
圖15是實施形態的測量用電容部的第6例的構成之說明圖。 Fig. 15 is an explanatory diagram of the configuration of a sixth example of the measurement capacitor portion of the embodiment.
以下，以如下的順序來說明本發明的實施形態。 Hereinafter, the embodiments of the present invention will be described in the following order.
<1.觸控面板裝置之構成> <1. Structure of touch panel device>
<2.感測動作> <2. Sensing action>
<3.用於線性度改善的構成> <3. Composition for linearity improvement>
[3-1：第1例] [3-1: The first example]
[3-2：第2例] [3-2: The second example]
[3-3：第3例] [3-3: Example 3]
[3-4：第4例] [3-4: Example 4]
[3-5：第5例] [3-5: Example 5]
[3-6：第6例] [3-6: The sixth example]
<4.實施形態之效果及變形例> <4. Effects and Modifications of the Implementation Mode>
<1.觸控面板裝置之構成> <1. Structure of touch panel device>
將實施形態的觸控面板裝置1的構成例顯示於圖1。
A configuration example of the
觸控面板裝置1是在各種機器中作為使用者介面裝置而裝設。在此，所謂各種機器，可設想的是例如電子機器、通訊機器、資訊處理裝置、製造設備機器、工作機械、車輛、航空機、建築設備機器、及其他非常多樣化的領域的機器。觸控面板裝置1是在這些多樣化的機器製品中作為於使用者的操作輸入上所使用的操作輸入器件而被採用。
The
在圖1中顯示有觸控面板裝置1與製品側MCU(微控制單元，Micro Control Unit)90，所謂製品側MCU90是指裝設觸控面板裝置1的機器中的控制裝置。觸控面板裝置1是形成為進行下述動作：對製品側MCU90供給使用者的觸控面板操作之資訊。
In FIG. 1, a
觸控面板裝置1具有觸控面板2及觸控面板驅動裝置3。
The
觸控面板驅動裝置3具有感測器IC(積體電路，Integrated Circuit)4與MCU5。
The touch
此觸控面板驅動裝置3是透過觸控面板側連接端子部31來與觸控面板2連接。觸控面板驅動裝置3是透過此連接來進行觸控面板2的驅動(感測)。
The touch
又，作為操作輸入器件而搭載於機器時，觸控面板驅動裝置3是透過製品側連接端子部32來與製品側MCU90連接。觸控面板驅動裝置3是藉由此連接而將所感測到的操作資訊發送至製品側MCU90。
In addition, when it is installed in a machine as an operation input device, the touch
觸控面板驅動裝置3中的感測器IC4具有發送電路41、接收電路42、多工器43、介面暫存器電路44及電源電路45。
The
感測器IC4的發送電路41是對藉由多工器43所選擇的觸控面板2中的端子輸出發送訊號。又，接收電路42是從藉由多工器43所選擇的觸控面板2中的端子接收訊號，並且進行必要的比較處理。
The sending
在圖2中示意地顯示發送電路41、接收電路42、多工器43與觸控面板2的連接狀態。
FIG. 2 schematically shows the connection state of the transmitting
觸控面板2是在形成觸控面的面板平面中，配設作為發送側的電極之n條發送訊號線21-1至21-n。
The
又，同樣地在面板平面中，配設有作為接收側的電極之m條接收訊號線22-1至22-m。 Also, similarly, in the panel plane, m receiving signal lines 22-1 to 22-m are arranged as electrodes on the receiving side.
再者，在不特別區別發送訊號線21-1...21-n、接收訊號線22-1...22-m的情況下，是統稱並表記為「發送訊號線21」、「接收訊號線22」。
Furthermore, if there is no special distinction between the sending signal line 21-1...21-n and the receiving signal line 22-1...22-m, they are collectively referred to as "transmitting
發送訊號線21-1...21-n、接收訊號線22-1...22-m，會有如圖所示地交叉而配設的情況，也會有作為所謂的單層構造，而如上述之專利文獻2所示地配設成不產生交叉的情況。無論為何種情況，均在配設發送訊號線21與接收訊號線22的範圍內形成觸控操作面，並且形成為藉由觸控操作時的電容變化來檢測操作位置的構造。
The transmitting signal lines 21-1...21-n and the receiving signal lines 22-1...22-m may be crossed and arranged as shown in the figure, and may also have a so-called single-layer structure. As shown in the above-mentioned
雖然在圖中僅例示有一部分在發送訊號線21與接收訊號線22之間所產生的電容(電容C22、C23、C32、C33)，但是在觸控操作面的整體存在有在發送訊號線21與接收訊號線22之間所產生的電容(例如交叉位置中的電容)，而變得可藉由接收電路42來檢測已藉由觸控操作而產生電容變化的位置。
Although only a part of the capacitances (capacitors C22, C23, C32, C33) generated between the transmitting
發送電路41是對多工器43所選擇的發送訊號線21-1...21-n輸出發送訊號。在本實施形態中，是多工器43進行在各個時間點各選擇2條相鄰的發送訊號線21的掃描。
The
接收電路42是接收來自藉由多工器43所選擇的接收訊號線22-1...22-m的接收訊號。在本實施形態中，是多工器43在各時間點各選擇2條相鄰的接收訊號線22。
The receiving
針對藉由發送電路41、接收電路42所進行的感測動作將於後文描述。
The sensing operation performed by the transmitting
返回到圖1來說明。在感測器IC4的介面暫存器電路44中，是藉由MCU5將對發送電路41、多工器43、接收電路42及電源電路45的各種設定資訊寫入。發送電路41、多工器43、接收電路42及電源電路45是各自藉由儲存於介面暫存器電路44的設定資訊而使動作受到控制。
Return to Figure 1 for explanation. In the
又，在介面暫存器電路44中，是設為可儲存藉由接收電路42所檢測的檢測值(在說明上也稱為「RAW值」)，而可以供MCU5取得。
In addition, the
電源電路45是生成驅動電壓AVCC，並且供給至發送電路41及接收電路42。雖然將於後文描述，發送電路41是將利用了驅動電壓AVCC的脈衝，施加於多工器43所選擇的發送訊號線21。
The
又，接收電路42在感測動作之時，也是對藉由多工器43所選擇的接收訊號線22施加驅動電壓AVCC。
In addition, the receiving
關於電源電路45的構成將於之後詳細描述。
The configuration of the
MCU5是進行感測器IC4的設定、控制。具體而言，MCU5是藉由對介面暫存器電路44寫入必要的設定資訊，以控制感測器IC4的各部分的動作。
MCU5 is for setting and controlling the sensor IC4. Specifically, the MCU5 writes necessary setting information into the
又，MCU5是將來自接收電路42的RAW值藉由從介面暫存器電路44讀出以取得。並且，MCU5是利用RAW值來進行座標計算，並且進行將作為使用者的觸控操作位置資訊的座標值發送至製品側MCU90的處理。
Furthermore, the MCU5 obtains the RAW value from the receiving
<2.感測動作> <2. Sensing action>
說明以上的構成之由觸控面板裝置1所進行的感測動
作。
Describe the sensing motion performed by the
首先，藉由圖3來說明發送電路41、接收電路42相對於觸控面板2的動作。在圖中是於觸控面板2中顯示有2個發送訊號線21-2、21-3、及2個接收訊號線22-2、22-3。
First, the operations of the transmitting
在本實施形態的情況下，是成為下述構成：藉由對如之前的圖2所示的發送訊號線21、接收訊號線22，讓發送電路41與接收電路42各自對每相鄰的2條進行發送、接收，來進行觸控操作的檢測。亦即，將一對發送訊號線21與一對接收訊號線22之2條×2條設為基本單元(cell)，並且依序以單元單位來進行檢測掃描。在圖3中是形成為顯示有其中1個單元部分。
In the case of this embodiment, the configuration is as follows: by pairing the transmitting
發送電路41是對2條發送訊號線21(在圖的情況下為21-2、21-3)，從驅動器411、412輸出驅動電壓AVCC1。亦即，將驅動器411、412的輸出即發送訊號T+、T-供給至藉由多工器43所選擇的發送訊號線21-2、21-3。
The
再者，驅動電壓AVCC1是圖1的電源電路45所生成的驅動電壓AVCC本身、或依據驅動電壓AVCC的電壓。
Furthermore, the driving voltage AVCC1 is the driving voltage AVCC itself generated by the
在此情況下，發送電路41是將來自驅動器411的發送訊號T+如圖示地於閒置(Idle)期間設為低位準(以下表記為「L位準」)。例如設為0V。並且，在接著的作動(Active)期間中是設為高位準(以下表記為「H位準」)。在此情況下，作為H位準的訊號具體而言是進行驅動電壓AVCC1的施加。
In this case, the transmitting
又，發送電路41是將來自另一個驅動器412的發送訊
號T-於閒置期間設為H位準(驅動電壓AVCC1的施加)，並且將接著的作動期間設為L位準。
In addition, the transmitting
在此，閒置期間是使接收訊號R+、R-的電位安定的期間，作動期間是成為感測接收訊號R+、R-的電位變化的期間。 Here, the idle period is a period in which the potentials of the received signals R+ and R- are stabilized, and the operating period is a period in which the potential changes of the received signals R+ and R- are sensed.
在此閒置期間、作動期間中，接收電路42是接收來自藉由多工器43所選擇的2個接收訊號線22(在圖的情況下為22-3、22-2)的接收訊號R+、R-。
During this idle period and active period, the receiving
接收電路42具備有比較器421、基準電容部422、開關423、425、測量用電容部424、運算控制部426。
The receiving
來自2個接收訊號線22的接收訊號R+、R-是在比較器421被接收。比較器421是比較接收訊號R+、R-的電位，並且將該比較結果以H位準或L位準的方式輸出至運算控制部426。
The receiving signals R+ and R- from the two receiving
在構成基準電容部422的電容器之一端施加有驅動電壓AVCC2。驅動電壓AVCC2是圖1的電源電路45所生成的驅動電壓AVCC本身、或依據驅動電壓AVCC的電壓。構成基準電容部422的電容器的另一端是透過開關423的端子Ta而連接於比較器421的+輸入端子。
The drive voltage AVCC2 is applied to one end of the capacitor constituting the
又，在測量用電容部424的一端施加有驅動電壓AVCC2。此測量用電容部424的另一端是透過開關425的端子Ta而連接於比較器421的-輸入端子。
In addition, the driving voltage AVCC2 is applied to one end of the
開關423、425在閒置期間中是選擇端子Ti。從而，在閒置期間是將比較器421的+輸入端子(接收訊號
線22-3)、-輸入端子(接收訊號線22-2)進行接地連接，且接收訊號R+、R-是成為接地電位。
The
開關423、425在作動期間是選擇端子Ta。從而，在作動期間中是對比較器421的+輸入端子(接收訊號線22-3)、-輸入端子(接收訊號線22-2)施加驅動電壓AVCC2。
The
在圖3中是以實線來顯示該單元為非觸控狀態時的接收訊號R+、R-的波形。在閒置期間是藉由開關423、425選擇端子Ti，以使接收訊號R+、R-在某個電位(接地電位)安定。
In FIG. 3, the waveforms of the received signals R+ and R- when the unit is in a non-touch state are shown by solid lines. During the idle period, the terminals Ti are selected by the
當成為作動期間時，是藉由開關423、425選擇端子Ta，而對接收訊號線22-3、22-2施加驅動電壓AVCC2。藉此，接收訊號R+、R-的電位為上升△V。在非觸控的狀態下，此△V的電位上升是一起發生於接收訊號R+、R-。
When it becomes the active period, the terminal Ta is selected by the
另一方面，在發送電路41側，當成為作動期間時，是如上所述地發送訊號T+上升，且發送訊號T-下降。藉此，在有觸控操作的情況下，會使接收訊號R+、R-的電位上升的程度變化。
On the other hand, on the side of the
假設對電容C22帶來影響的A1位置已受到觸控的情況下，會使接收訊號R-的電位在作動期間中如虛線所示地上升相當於△VH。 Assuming that the position A1 that affects the capacitor C22 has been touched, the potential of the received signal R- will rise as shown by the dotted line during the operation period, which is equivalent to ΔVH.
又，假設讓電容C32變化的A2位置已受到觸控的情況下，會使接收訊號R-的電位在作動期間中如虛線所示地上升相當於△VL。 Furthermore, assuming that the position A2 where the capacitor C32 changes has been touched, the potential of the received signal R- will rise as indicated by the broken line during the operation period, which corresponds to ΔVL.
像這些這樣，因應於對該單元的觸控操作位置，而讓接收訊號R-的電位變化量變得比接收訊號R+的電位變化量(△V)更大或更小。 Like these, depending on the touch operation position of the unit, the potential change of the received signal R- becomes larger or smaller than the potential change (ΔV) of the received signal R+.
比較器421是形成為對像這樣的接收訊號R+、R-進行比較。
The
再者，雖然也可以設成將像這樣地變化的接收訊號R+、R-的電位差量本身作為RAW值(檢測結果)來輸出，但是在本實施形態中，接收電路42是設成：運算控制部426進行測量用電容部424的設定變更，以得到接收訊號R+、R-的電壓平衡，而得到RAW值。
Furthermore, although the potential difference of the received signals R+ and R- changed in this way may be output as the RAW value (detection result), in this embodiment, the receiving
運算控制部426是依照已寫入介面暫存器電路44的設定資訊，來進行開關423、425的開啟/關閉或測量用電容部424的電容值之切換處理。又，對比較器421的輸出進行監視，並且以後述之處理來算出RAW值。藉由將運算控制部426所算出的RAW值寫入介面暫存器電路44，以設成使MCU5可取得。
The
在以上的圖3中，以可變電容電容器的記號所表示的測量用電容部424，是如例如圖4所示地藉由複數個電容部CM(CM0~CM7)與開關SW(SW0~SW7)所構成。
In the above FIG. 3, the measuring
再者，圖4是顯示已將開關423、425連接於端子Ta的狀態(作動期間)下的等效電路，並且省略開關423、425的圖示。
Furthermore, FIG. 4 shows an equivalent circuit in a state (operating period) in which the
各電容部CM0~CM7是在驅動電壓AVCC2的電位與比較器421的-輸入端子之間並聯地連接。又，對於各電容
部CM0~CM7是各自串聯地連接有開關SW0~SW7。亦即，為可以藉由開關SW0~SW7的開啟/關閉，以變更對接收訊號R-帶來影響的電容部CM之構成。
The capacitor parts CM0 to CM7 are connected in parallel between the potential of the drive voltage AVCC2 and the −input terminal of the
又，在圖4中雖然是以1個電容器的記號來顯示各電容部CM0~CM7，但是如後文所述，也會有各電容部CM0~CM7的每一個是以1個電容器來形成的情況，也會有以複數個電容器來構成的情況。 In addition, although the capacitor parts CM0 to CM7 are shown in the symbol of one capacitor in FIG. 4, as will be described later, each of the capacitor parts CM0 to CM7 is formed with one capacitor. In some cases, it may be composed of multiple capacitors.
開關SW0~SW7雖然是利用例如FET(場效電晶體，Field effect transistor)等之開關元件所構成，但也有如在圖14等中並於後文所描述地設置複數個開關元件來作為1個開關SW的情況。 Although the switches SW0 to SW7 are constructed using switching elements such as FET (Field Effect Transistor), as shown in FIG. 14 etc. and described later, multiple switching elements are provided as one. Switch SW situation.
各電容部CM0~CM7的電容值是設為例如電容部CM0=2fF(毫微微法拉，femtofarad)、CM1=4fF、CM2=8fF、CM3=16fF、CM4=32fF、CM5=64fF、CM6=128fF、CM7=256fF。 The capacitance value of each capacitor part CM0~CM7 is set to, for example, the capacitor part CM0=2fF (femtofarad), CM1=4fF, CM2=8fF, CM3=16fF, CM4=32fF, CM5=64fF, CM6=128fF, CM7=256fF.
電容部CM0至CM7是以位元“0”至位元“7”之8位元之值來進行選擇。電容部CM0及開關SW0是作為位元0來發揮功能，電容部CM1及開關SW1是作為位元“1”來發揮功能，...電容部CM7及開關SW7是作為位元“7”來發揮功能。
The capacitor parts CM0 to CM7 are selected with 8-bit values from bit "0" to bit "7". Capacitor CM0 and switch SW0 function as
並且，作為8位元之值可賦與0(=「00000000」)至255(=「11111111」)之電容設定值。電容設定值是MCU5寫入介面暫存器電路44的設定資訊的一個。
And, as an 8-bit value, a capacitance setting value from 0 (= "00000000") to 255 (= "11111111") can be assigned. The capacitance setting value is one of the setting information written into the
在接收電路42中，是因應於此8位元的電容設定值來將開關SW0~SW7設為開啟/關閉。亦即，開關SW0~SW7
是對應的位元若為「0」時會成為關閉，若為「1」時會成為開啟。藉此，變得可讓測量用電容部424整體的電容值在0fF~510fF的範圍中以可分成256個階段的方式來改變。
In the receiving
再者，在感測器IC4中於實際形成電容部CM與開關SW的配線部分中會產生寄生電容Cs。在圖4中，雖然僅在電容部CM0與開關SW0的電路部分中顯示有寄生電容Cs，但是實際上於其他的電路部分(電容部CM1與開關SW1的電路部分至電容部CM7與開關SW7的電路部分全部)也產生有寄生電容Cs。電容部CM的電容器在實際上是作為配線間的電容而實現。如此一來，與開關SW之間的配線越長，寄生電容Cs會變得越大。 Furthermore, in the sensor IC4, a parasitic capacitance Cs is generated in the wiring part where the capacitance portion CM and the switch SW are actually formed. In FIG. 4, although the parasitic capacitance Cs is shown only in the circuit part of the capacitor part CM0 and the switch SW0, it is actually in other circuit parts (the circuit part of the capacitor part CM1 and the switch SW1 to the capacitor part CM7 and the switch SW7). The whole circuit part) also has parasitic capacitance Cs. The capacitor of the capacitance portion CM is actually realized as a capacitance between wirings. In this way, the longer the wiring with the switch SW, the greater the parasitic capacitance Cs.
此寄生電容Cs是作為使各電容部CM0~CM7的各電容值產生誤差之電容而產生影響。針對此對策將於後文描述。 This parasitic capacitance Cs has an influence as a capacitance that causes errors in the capacitance values of the capacitance parts CM0 to CM7. This countermeasure will be described later.
另一方面，接收訊號R+側的基準電容部422的電容器之電容值是設為例如256fF。
On the other hand, the capacitance value of the capacitor of the
如上述，接收訊號R-是根據觸控的有無及位置來改變作動期間的波形之電位上升的程度。且變得比接收訊號R+的波形上升程度(△V)更大或更小。 As mentioned above, the received signal R- changes the degree of potential rise of the waveform during the actuation period according to the presence or absence and position of the touch. And it becomes larger or smaller than the rise (△V) of the waveform of the received signal R+.
在圖4的構成中，可以藉由變更測量用電容部424的電容設定值來使接收訊號R-的波形之電位上升程度變化，並且可以找出例如成為與接收訊號R+同等的測量用電容部424的電容設定值。
In the configuration of FIG. 4, by changing the capacitance setting value of the
例如，將圖4的接收訊號R-的虛線所示的波形Sg1設為
初始狀態時，若將測量用電容部424的電容減小，接收訊號R-會如波形Sg2所示地變得比波形Sg1更小。又，若將測量用電容部424的電容增大，接收訊號R-會如波形Sg3所示地變得比波形Sg1更大。
For example, set the waveform Sg1 shown by the dotted line of the received signal R- in Fig. 4 as
In the initial state, if the capacitance of the measuring
亦即，在比較器421中接收訊號R+、R-的電壓位準成為同等時的測量用電容部424的電容設定值，是成為與相當於由觸控所造成之接收訊號R-的電壓變化之值等效。從而，一邊觀察比較器421的輸出，一邊使測量用電容部424的電容設定值變化，來搜尋使接收訊號R+、R-的作動期間的電壓成為同等的電容設定值。如此一來，即變得可以讓搜尋出的電容設定值形成作為觸控操作的感測資訊之RAW值。
That is, when the voltage levels of the received signals R+ and R- are equal in the
以圖5來說明以上之感測動作的具體順序。此圖5是顯示依據MCU5已寫入介面暫存器電路44的各種設定資訊，以發送電路41、接收電路42來進行的處理。
Figure 5 illustrates the specific sequence of the above sensing operation. This FIG. 5 shows the processing performed by the sending
在圖5中步驟S100至S109的環路處理是顯示對於1個單元(2個發送訊號線21與2個接收訊號線22之組)的感測之順序。再者，在得到RAW值之前，電容設定值是取8個階段之不同的值(從初始狀態開始變更7次)。
The loop processing of steps S100 to S109 in FIG. 5 shows the sequence of sensing for 1 unit (a group of two transmitting
在步驟S100中首先將變數n作為初始值而設定為n=7。又，接收電路42是依據MCU5的指示(電容設定值)將測量用電容部424的電容值設定為256fF。亦即，設為電容設定值=128(=10000000)，並藉由只有位元“7”為「1」，而僅將開關SW7設為開啟。
In step S100, first, the variable n is set to n=7 as an initial value. In addition, the receiving
在步驟S101中進行閒置期間的設定。 In step S101, the idle period is set.
在發送電路41中，來自驅動器411的發送訊號T+是設為L位準，且發送訊號T-是設為H位準(=驅動電壓AVCC1)。
In the sending
在接收電路42中，是將開關423、425連接於端子Ti。藉此，比較器421的+輸入端子、-輸入端子是進行接地連接。
In the receiving
接著在步驟S102中，是藉由經過預定的期間，以進行從閒置期間至作動期間的切換。 Then, in step S102, a predetermined period is passed to switch from the idle period to the active period.
在發送電路41中，來自驅動器411的發送訊號T+是設為H位準(=驅動電壓AVCC1)，且來自驅動器412的發送訊號T-是設為L位準。
In the
在接收電路42中，是將開關423、425連接於端子Ta。藉此，比較器421的+輸入端子是透過基準電容部422而連接於驅動電壓AVCC2，-輸入端子是透過測量用電容部424而連接於驅動電壓AVCC2。
In the receiving
雖然當成為作動期間時，會使接收訊號R+、R-上升△V，但是會因發送訊號T+上升且發送訊號T-下降，而產生接收訊號R-的變化(上升量成為△VH或△VL)，其中前述接收訊號R-的變化是因應於對於檢測中的單元之觸控操作的有無或觸控操作位置之變化。 Although the receiving signal R+ and R- will rise by △V when it becomes the active period, the receiving signal R- will change as the sending signal T+ rises and the sending signal T- falls (the rising amount becomes △VH or △VL ), wherein the change of the aforementioned received signal R- is due to the presence or absence of the touch operation or the change of the touch operation position of the unit under test.
在步驟S103中，是比較器421比較接收訊號R+、R-，並輸出比較結果。從比較器421為：若為(接收訊號R+)>(接收訊號R-)可得到H位準輸出，若為(接收訊號R+)<
(接收訊號R-)可得到L位準輸出。
In step S103, the
步驟S104是因應於比較器421的輸出而將處理分歧。
Step S104 is to divide the processing according to the output of the
若比較器421的輸出為H位準，則在步驟S105中進行測量用電容部424的電容切換。在此情況下，是在已將位元“n”的開關設為開啟的狀態下，將位元“n-1”的開關設為開啟。
If the output of the
到那之前如上述地在初始狀態下設為電容設定值=「10000000」而僅將位元“7”設為開啟時，是接著設為電容設定值=「11000000」而將位元“7”與位元“6”設為開啟。亦即，將開關SW7、SW6設為開啟，使測量用電容部424的電容值成為384fF。
Before that, set the capacitance setting value = "10000000" in the initial state as described above and only set the bit "7" to on, then set the capacitance setting value = "11000000" and set the bit "7" And bit "6" is set to on. That is, the switches SW7 and SW6 are turned on, so that the capacitance value of the
並且，若在步驟S107中為變數n>0，則在步驟S108中將變數n遞減(decrement)並且返回到步驟S101。亦即，在已將測量用電容部424的電容增大後，進行閒置期間、作動期間的動作並確認比較器421的輸出。
And, if the variable n>0 in step S107, the variable n is decremented in step S108 and the process returns to step S101. That is, after the capacitance of the measuring
又，在步驟S104中若比較器421的輸出為L位準，則在步驟S106中進行測量用電容部424的電容切換。在此情況下，將位元“n”的開關設為關閉，並且將位元“n-1”的開關設為開啟。
In addition, if the output of the
若在那之前在初始狀態下設為電容設定值=「10000000」而僅將位元“7”設為開啟時，接著是設為電容設定值=「01000000」而將位元“7”設為關閉，且將位元“6”設為開啟。亦即，將開關SW7設為關閉並且將開關
SW6設為開啟，使測量用電容部424的電容值成為128fF。
If you set the capacitance setting value = "10000000" in the initial state before then and only set the bit "7" to on, then set the capacitance setting value = "01000000" and set the bit "7" to Turn off, and set bit "6" to on. That is, set switch SW7 to off and set the switch
SW6 is turned on, so that the capacitance value of the
並且，若在步驟S107中為變數n>0，則在步驟S108中將變數n遞減(decrement)並且返回到步驟S101。亦即，在已將測量用電容部424的電容減小後，進行閒置期間、作動期間的動作並且確認比較器421的輸出。
And, if the variable n>0 in step S107, the variable n is decremented in step S108 and the process returns to step S101. That is, after the capacitance of the measuring
藉由將此處理進行到成為變數n=0為止，即可判定已達到接收訊號R-的作動期間的電壓值與接收訊號R+的作動期間的電壓值之平衡時的電容設定值。 By performing this processing until the variable n=0, it can be determined that the voltage value during the operation period of the received signal R- and the voltage value during the operation period of the received signal R+ have reached the balance of the capacitance setting value.
再者，在變數n=0時的步驟S105、S106中，由於位元“n-1”並不存在，因此不進行位元“n-1”的處理。 In addition, in steps S105 and S106 when the variable n=0, since the bit "n-1" does not exist, the bit "n-1" is not processed.
在步驟S107中已成為變數n=0後，即前進至步驟S109，且接收電路42會算出RAW值。這會成為下述之處理：在測量用電容部424中取已成為開啟的開關SW的位元之2的乘冪的總和。例如假設在最後已設為開關SW5、SW3、SW2成為開啟，即成為25+23+22=44，而成為RAW值=44。
After the variable n=0 in step S107, proceed to step S109, and the receiving
如此求出的RAW值是透過介面暫存器電路44作為1個單元的檢測值而被MCU5所取得。
The RAW value thus obtained is obtained by the
針對觸控面板2中的各單元(2條發送訊號線21與2條接收訊號線22之組)可同樣地進行圖5的處理，而求出RAW值。
For each unit in the touch panel 2 (a group of two transmitting
MCU5是取得針對各單元的RAW值，並且進行觸控操作位置的座標計算，而將所求出的座標值發送至製品側MCU90。 The MCU5 obtains the RAW value for each cell, performs the coordinate calculation of the touch operation position, and sends the obtained coordinate value to the product-side MCU90.
在本實施形態中藉由取接收訊號R+、R-的差分來作為如以上的感測動作，可以使所取得的RAW值變得難以受到來自外部環境的影響，且可以提升觸控操作的檢測精度。 In this embodiment, by taking the difference of the received signal R+ and R- as the above-mentioned sensing action, the obtained RAW value can be made difficult to be affected by the external environment, and the detection of touch operation can be improved. Accuracy.
尤其是設成在非觸控時是已達到接收訊號R+、R-的電位之平衡，並設為藉由觸控所造成的電容變化而在接收訊號R+、R-的電位上產生差異。將此進行成使測量用電容部424的電容依序變化，並搜尋可達到接收訊號R+、R-的平衡之電容值，而從指定該電容值的電容設定值中得到RAW值。藉此，可以正確地檢測起因於藉由觸控操作所造成的電容變化之接收訊號R+、R-的差分。
In particular, it is assumed that the balance of the potentials of the received signals R+ and R- has been reached during non-touch, and it is set that the potentials of the received signals R+ and R- are different due to changes in capacitance caused by touch. This is performed so that the capacitance of the measuring
再者，作為從接收電路42施加驅動電壓AVCC2來對所選擇的接收訊號線22充電之理由主要有2個。
Furthermore, there are two main reasons for applying the driving voltage AVCC2 from the receiving
1個是觸控面板2為單層構造時的情形。在單層構造的情況下，在非觸控的狀態下，發送訊號線21與接收訊號線22之間幾乎不會產生電容。亦即，發送訊號線21與接收訊號線22之間(電極間)為絕緣狀態。但是即使在非觸控狀態下，仍然必須設為使接收訊號波形在作動期間上升。藉由為此而發送驅動電壓AVCC2，以進行成即使是對單層的情況也對應並良好地完成上述的感測動作。
One is when the
又，另1個理由並不限定於單層之情形。在上述的感測方式中，雖然是形成為觀看已進入作動期間後的接收訊號R-的電位上升幅度之情形，但是對由發送訊號T-的下降
所造成的影響也欲掌握。亦即，必須也觀測圖3中以虛線表示的△VL的電位上升。當作動期間中的非觸控狀態下的接收訊號R+、R-的電位為0V時，在受到下降的影響之情況下，會使接收訊號R-的電位成為負值，而成為在接收電路42中難以處理的電位。於是，設成先讓接收訊號R-的電位提高以免成為0V以下，且為了容易且適當地觀測由發送訊號T-的下降的影響所造成的接收波形的電位，因而施加有驅動電壓AVCC2。
In addition, the other reason is not limited to the case of a single layer. In the above-mentioned sensing method, although it is formed to observe the rising amplitude of the potential of the received signal R- after the active period has entered, the response to the drop of the transmitted signal T-
I also want to grasp the impact. That is, it is necessary to also observe the potential rise of ΔVL indicated by the broken line in FIG. 3. When the potential of the received signal R+ and R- in the non-touch state during the active period is 0V, under the influence of the drop, the potential of the received signal R- will become a negative value, and it will become in the receiving
<3.用於線性度改善的構成> <3. Composition for linearity improvement>
[3-1：第1例] [3-1: The first example]
然而，在藉由如以上地一面切換測量用電容部424的電容值一面比較接收訊號R+、R-，以檢測觸控時的電容變化的感測動作中，與其檢測精度非常相關的是測量用電容部424的電容值的線性度(Linearity)。
However, in the sensing operation that detects changes in capacitance during touch by switching the capacitance value of the
例如當成為電容設定值=63(=00111111)且開關SW0至SW5為開啟時，測量用電容部424的電容值應該是成為126fF，又，當成為電容設定值=64(=01000000)且僅開關SW6為開啟時，測量用電容部424的電容值應該是成為128fF。
For example, when the capacitance setting value=63 (=00111111) and the switches SW0 to SW5 are on, the capacitance value of the measuring
在此設為假設將電容部CM0~CM7各自以1個電容器來形成。例如電容部CM0是設為2fF的電容器，電容部CM1是設為4fF的電容器，電容部CM2是設為8fF的電容器，...電容部CM7是設為256fF的電容器。 It is assumed here that the capacitance portions CM0 to CM7 are each formed with one capacitor. For example, the capacitance part CM0 is a 2fF capacitor, the capacitance part CM1 is a 4fF capacitor, the capacitance part CM2 is a 8fF capacitor, ... the capacitance part CM7 is a 256fF capacitor.
在圖6中所顯示的是像這樣各自使用1個電容器的情 況下之各電容部CM的電容器之面積。 Figure 6 shows the situation where each capacitor is used like this. In this case, the area of the capacitor of each capacitor CM.
如上述，在電容設定值=63時，是藉由電容部CM0~CM5之6個電容器的並聯連接，以使測量用電容部424的電容值成為126fF，且在電容設定值=64時是藉由電容部CM6以使測量用電容部424的電容值成為128fF。
As mentioned above, when the capacitance setting value=63, the 6 capacitors of the capacitance parts CM0~CM5 are connected in parallel so that the capacitance value of the measuring
然而，有例如2fF之類的極小電容的電容器，要設為正確的電容會較困難的情形。 However, there are very small capacitance capacitors such as 2fF, and it is difficult to set the correct capacitance.
此外，也有面積越小的電容器越容易受到上述之寄生電容Cs的影響之情形。 In addition, there are cases where a capacitor with a smaller area is more susceptible to the above-mentioned parasitic capacitance Cs.
亦即，在電容部CM0~CM7的每一個中會在與開關SW0~SW7的配線間產生寄生電容Cs，即使假設每一個寄生電容Cs的電容值為幾乎相同的程度，在例如2fF之類的較小的電容部CM0中，由寄生電容Cs所造成的電容變化仍然會變得比256fF的電容部CM7更顯著。 That is, in each of the capacitor portions CM0 to CM7, a parasitic capacitance Cs is generated between the wiring of the switches SW0 to SW7, even if the capacitance value of each parasitic capacitance Cs is almost the same level, for example, 2fF or the like In the smaller capacitor portion CM0, the capacitance change caused by the parasitic capacitance Cs will still become more significant than that of the 256fF capacitor portion CM7.
從這些情形來看，有下述情形：例如電容部CM0~CM5之6個電容器的並聯連接所形成的電容因寄生電容的影響並不是成為126fF，而是成為比128fF更大。如此一來，會導致電容設定值=64的電容變得比電容設定值=63時的電容更小。 Judging from these situations, there are cases where, for example, the capacitance formed by the parallel connection of the six capacitors of the capacitor portions CM0 to CM5 is not 126fF but larger than 128fF due to the influence of parasitic capacitance. As a result, the capacitance of the capacitance setting value=64 will become smaller than the capacitance setting value=63.
如此，在應以電容設定值來控制的256個階段的電容值中，有發生大小關係的逆轉現象之情形。將發生大量這樣的逆轉現象的狀態稱為線性度變差的狀態。並且，如考慮上述之圖5的處理而可理解地，當線性度變差時，會變得無法正確地生成RAW值。 In this way, in the 256-stage capacitance value that should be controlled by the capacitance setting value, there may be a reversal phenomenon of the magnitude relationship. A state where a large number of such reversal phenomena occur is called a state where linearity is degraded. And, as understood from the processing of FIG. 5 described above, when the linearity deteriorates, it becomes impossible to generate the RAW value correctly.
於是，在本實施形態中，是對感測器IC4中的電容部CM0~CM7與開關SW0~SW7的配置下工夫。 Therefore, in the present embodiment, attention is paid to the arrangement of the capacitance portions CM0 to CM7 and the switches SW0 to SW7 in the sensor IC4.
圖7A是示意地顯示配置構成感測器IC4內的測量用電容部424之元件的區域。構成測量用電容部424的元件，是指作為電容部CM0~CM7而發揮功能的電容器、及成為開關SW0~SW7的電晶體。
FIG. 7A schematically shows the area where the elements constituting the measuring
並且，如圖示地將配置測量用電容部424的元件之區域分成第1區域AR1、第2區域AR2及第3區域AR3。
In addition, as shown in the figure, the area where the elements of the measuring
在第1區域AR1中配置有成為電容部CM0~CM7的電容器。 In the first area AR1, capacitors serving as capacitance portions CM0 to CM7 are arranged.
在第2區域AR2中配置有成為開關(例如開關SW0~SW4)的電晶體，前述開關是對應於被分在電容值較小之側的電容部(例如電容部CM0~CM4)之開關。 Transistors serving as switches (for example, switches SW0 to SW4) are arranged in the second area AR2, and the aforementioned switches are switches corresponding to capacitor parts (for example, capacitor parts CM0 to CM4) classified on the side with a smaller capacitance value.
在第3區域AR3中配置有成為開關(例如開關SW5~SW7)的電晶體，前述開關是對應於被分在電容值較大之側的電容部(例如電容部CM5~CM7)之開關。 Transistors serving as switches (for example, switches SW5 to SW7) are arranged in the third area AR3, and the aforementioned switches are switches corresponding to the capacitor portions (for example, capacitor portions CM5 to CM7) classified on the larger capacitance side.
如此，藉由設成將第2區域AR2形成於比第3區域AR3更接近於第1區域AR1的位置之配置，以改善測量用電容部424的線性度。
In this way, the linearity of the
將線性度改善效果顯示於圖8。圖8A是圖7A的配置時的特性，圖8B是成為比較例之圖7B的配置時的特性。再者，圖7B的配置是指下述之例子：相鄰於第1區域AR1來配置第3區域AR3，且配置有對應於較小電容的電容部CM的開關SW之第2區域AR2變得比第3區域AR3離第1區域 AR1更遠。 The linearity improvement effect is shown in Figure 8. Fig. 8A shows the characteristics of the arrangement of Fig. 7A, and Fig. 8B shows the characteristics of the arrangement of Fig. 7B as a comparative example. Furthermore, the arrangement of FIG. 7B refers to the following example: the third area AR3 is arranged adjacent to the first area AR1, and the second area AR2 where the switch SW of the capacitor portion CM corresponding to the smaller capacitance is arranged becomes AR3 away from the first area than the third area AR1 is farther.
在圖8A、圖8B中，橫軸是顯示作為電容設定值的0~255。縱軸是設為輸出電壓Vc。此輸出電壓Vc是指在不將測量用電容部424連接於接收訊號線22的狀態下，施加驅動電壓AVCC2時的上升波形的電壓值(輸出至比較器421側的電壓值)。
In Fig. 8A and Fig. 8B, the horizontal axis shows 0~255 as the capacitance setting value. The vertical axis is the output voltage Vc. The output voltage Vc refers to the voltage value of the rising waveform (the voltage value output to the
所觀測的輸出電壓Vc是成為間接地表示測量用電容部424的各階段的電容值之電壓。
The observed output voltage Vc is a voltage that indirectly represents the capacitance value of each stage of the measuring
在圖8B的情況下，可看到測量用電容部424的電容值的線性度較差之情形。亦即，所觀測的輸出電壓Vc(電容值)的上下變動較大，線性度擾動得較大。
In the case of FIG. 8B, it can be seen that the linearity of the capacitance value of the
另一方面，在圖8A中所觀測的輸出電壓Vc(電容值)的上下變動已相當地受到抑制，可知線性度已相當地得到改善。 On the other hand, the fluctuation of the output voltage Vc (capacitance value) observed in FIG. 8A has been considerably suppressed, and it can be seen that the linearity has been considerably improved.
可如此改善線性度的原因是源自於可以讓小電容側的電容部CM(例如電容部CM0~CM4)的電容器、與開關SW(電晶體)之間的配線長度變得比較短。藉由將配線長縮短，即可減低這些小電容側中的作為寄生電容Cs的電容值。如此一來，寄生電容Cs對小電容側的電容部CM中的電容值之影響相對變得較小。另一方面，大電容側的電容部CM是原本寄生電容Cs的影響就較小。因為相對於電容器的電容值而為寄生電容Cs的電容值足夠小的緣故。如此一來，藉由在小電容側將配線長度縮短以縮小寄生電容Cs之作法，若作為測量用電容部424中的電容部
CM0~CM7的整體來觀看，是將由寄生電容Cs所造成的電容誤差朝均一化的方向來使電容誤差的程度之差變小。亦即，可以將設計上之本來的誤差相對於電容的比率朝均一化的方向來進行調整。
The reason why the linearity can be improved in this way is that the wiring length between the capacitor of the capacitor portion CM (for example, the capacitor portions CM0 to CM4) and the switch SW (transistor) on the small-capacitance side can be made shorter. By shortening the wiring length, the capacitance value of the parasitic capacitance Cs on the side of these small capacitances can be reduced. In this way, the influence of the parasitic capacitance Cs on the capacitance value in the capacitance portion CM on the small capacitance side becomes relatively small. On the other hand, the capacitance portion CM on the large capacitance side originally has a small influence of the parasitic capacitance Cs. This is because the capacitance value of the parasitic capacitance Cs is sufficiently small relative to the capacitance value of the capacitor. In this way, by shortening the wiring length on the small capacitance side to reduce the parasitic capacitance Cs, if it is used as the capacitance part of the measuring
藉此，變得難以產生上述之逆轉現象，而可以考慮為可改善線性度。 As a result, it becomes difficult to generate the above-mentioned reversal phenomenon, and it can be considered that the linearity can be improved.
再者，作為本實施形態，作為使由寄生電容Cs所造成的誤差之影響更加均一化的構成，也可考慮圖7C的配置例。 Furthermore, as the present embodiment, as a configuration to make the influence of the error caused by the parasitic capacitance Cs more uniform, the arrangement example of FIG. 7C can also be considered.
圖7C的配置例是在第1區域AR1中對各電容部CM0~CM7的電容器配置下工夫之例。顯示有下述情形：設成越小的電容部CM0的電容器變得越接近於第2區域AR2。 The arrangement example of FIG. 7C is an example in which the arrangement of the capacitors of the respective capacitance portions CM0 to CM7 is made in the first area AR1. It is shown that the capacitor set to the smaller capacitance portion CM0 becomes closer to the second area AR2.
當然，並非受限為將全部的電容器嚴密地設成依電容順序而從第2區域AR2按照順序地將距離拉長之作法，只要因應於各電容值的電容器的尺寸等來配置即可。此時，針對較小電容的電容器(或構成較小電容的電容部CM之電容器)，可以藉由縮短與開關SW的距離，而減少小電容側中的寄生電容Cs，並減低各電容部CM0~CM7中的由寄生電容Cs所造成的電容誤差的比率之差。 Of course, it is not limited to the method of strictly setting all capacitors in order of capacitance and sequentially extending the distance from the second area AR2, as long as they are arranged in accordance with the size of the capacitor of each capacitance value. At this time, for a capacitor with a smaller capacitance (or a capacitor constituting the capacitor portion CM with a smaller capacitance), the parasitic capacitance Cs on the small capacitance side can be reduced by shortening the distance from the switch SW, and the capacitance portions CM can be reduced. ~ The difference in the ratio of the capacitance error caused by the parasitic capacitance Cs in CM7.
[3-2：第2例] [3-2: The second example]
說明作為第2例而將測量用電容部424如圖9地構成的例子。
As a second example, an example in which the
這是測量用電容部424具有電容部CM0~CM10、及與
此電容部CM0~CM10的每一個相對應的開關SW0~SW10之例子。在此情況下，也是為了感測動作，而將測量用電容部424的電容值以和圖4、圖5所說明的例子同樣的想法來變更。
This is that the measuring
在此情況下，為了進行11個電容部CM0~CM10的連接的開啟/關閉，而使用位元“0”~位元“10”之11位元的電容設定值來控制開關SW0~SW10。 In this case, in order to turn on/off the connection of the 11 capacitor parts CM0 to CM10, the 11-bit capacitance setting value of bit "0" to bit "10" is used to control the switches SW0 to SW10.
藉由11位元的電容設定值，即可將電容值以2048個階段的方式來切換。各電容部CM0~CM10的電容值是設為2fF、4fF、8fF、16fF、32fF、64fF、128fF、256fF、512fF、1024fF、2048fF。從而，可將測量用電容部424的電容值從0fF變更至4094fF。
With the 11-bit capacitance setting value, the capacitance value can be switched in 2048 stages. The capacitance value of each capacitor portion CM0 to CM10 is set to 2fF, 4fF, 8fF, 16fF, 32fF, 64fF, 128fF, 256fF, 512fF, 1024fF, 2048fF. Therefore, the capacitance value of the
在此例中電容部CM0~CM10是設成各自藉由1個電容器來構成。又，開關SW0~SW10是各自以電晶體來構成。 In this example, the capacitors CM0 to CM10 are each configured by one capacitor. In addition, the switches SW0 to SW10 are each composed of a transistor.
並且，在感測器IC4中是將電容部CM0~CM7與開關SW0~SW7配置成如圖7A。 In addition, in the sensor IC4, the capacitor parts CM0~CM7 and the switches SW0~SW7 are arranged as shown in Fig. 7A.
例如在第2區域AR2中，配置有成為開關SW0~SW4的電晶體，且前述開關SW0~SW4是對應於比較小的電容值的電容部CM0~CM4，在第3區域AR3中配置有成為開關SW5~SW10的電晶體，且前述開關SW5~SW10是對應於比較大的電容值的電容部CM5~CM10。 For example, in the second area AR2, transistors that become switches SW0 to SW4 are arranged, and the aforementioned switches SW0 to SW4 are capacitor parts CM0 to CM4 corresponding to relatively small capacitance values, and in the third area AR3, there are arranged switches that become switches. Transistors of SW5 to SW10, and the aforementioned switches SW5 to SW10 are capacitor parts CM5 to CM10 corresponding to relatively large capacitance values.
藉由如此進行，可以得到和上述之第1例同樣的效果。亦即，在將測量用電容部424的電容可變階段數設得
較多的情況下，圖7A的配置也是有效的。
By doing this, the same effect as the above-mentioned first example can be obtained. That is, when the number of capacitance variable stages of the
再者，此情況也如圖7C所示，針對第1區域AR1之構成各電容部CM0~CM10的電容器，藉由將構成越小電容值的電容部CM之電容器配置在越接近於第2區域的位置之作法，因為可以縮小由較小的電容部CM所造成的電容誤差，且將電容誤差的比率均一化，因而變得較理想。 Furthermore, in this case, as shown in FIG. 7C, for the capacitors constituting the respective capacitor portions CM0 to CM10 in the first area AR1, the capacitors constituting the capacitor portion CM with a smaller capacitance value are arranged closer to the second area The position of the method can reduce the capacitance error caused by the smaller capacitance portion CM, and the ratio of the capacitance error can be made uniform, so it becomes more ideal.
[3-3：第3例] [3-3: Example 3]
將第3例之測量用電容部424的構成顯示於圖10。這雖然是和圖9相同地具有電容部CM0~CM10與開關SW0~SW10之構成，但是是以複數個電容器來構成大電容側(例如電容部CM7~CM10)的例子。
The configuration of the
電容部CM0~CM6是各自利用1個2fF、4fF、8fF、16fF、32fF、64fF、128fF的電容器來構成。 The capacitors CM0 to CM6 are each composed of one 2fF, 4fF, 8fF, 16fF, 32fF, 64fF, 128fF capacitor.
電容部CM7是以2個128fF的電容器的並聯連接來構成256fF的電容。電容部CM8是以4個128fF的電容器的並聯連接來構成512fF的電容。電容部CM9是以8個128fF的電容器的並聯連接來構成1024fF的電容。電容部CM10是以16個128fF的電容器的並聯連接來構成2048fF的電容。 The capacitor CM7 is a parallel connection of two 128fF capacitors to form a 256fF capacitor. The capacitor CM8 is a parallel connection of four 128fF capacitors to form a 512fF capacitor. The capacitor CM9 is a parallel connection of eight 128fF capacitors to form a 1024fF capacitor. The capacitance portion CM10 is a parallel connection of 16 capacitors of 128 fF to form a capacitance of 2048 fF.
如此，藉由將大電容側全部都藉由128fF的電容器來構成，測量用電容部424是配置2fF至128fF的電容器。
In this way, by configuring all the large-capacitance sides with 128fF capacitors, the measuring
如圖9所示，在利用2fF至2048fF的電容器之情況下，會使最小面積的電容器至最大面積的電容器的面積比變得相當大。相對於此，在圖10的情況下，由於最大面積的電 容器為128fF，因此可以將最小面積的電容器至最大面積的電容器的面積比縮小。藉此，對於將由寄生電容Cs的影響所造成的電容誤差的比率均一化之情形變得較有利。 As shown in FIG. 9, in the case of using capacitors of 2fF to 2048fF, the area ratio of the capacitor with the smallest area to the capacitor with the largest area becomes quite large. In contrast, in the case of Figure 10, due to the largest area of electricity The container is 128fF, so the area ratio of the capacitor with the smallest area to the capacitor with the largest area can be reduced. Thereby, it becomes more advantageous to make the ratio of the capacitance error caused by the influence of the parasitic capacitance Cs uniform.
又，在圖10的例子中，是藉由不利用比128fF的電容器更大的面積的電容器，以讓電容器配置的自由度增加，在IC設計上也變得較有利。 In addition, in the example of FIG. 10, a capacitor with a larger area than a 128fF capacitor is not used, so that the degree of freedom of capacitor placement is increased, which is also advantageous in IC design.
當然在此圖10的構成之情況下，也是採用圖7A或圖7C的配置，但是可考慮到例如下述例子：將電容部CM0~CM6及開關SW0~SW6設成小電容側，並將電容部CM7~CM10及開關SW7~SW10設成大電容側。當然，大電容側與小電容側的區分並不限定於此，亦可配合實際的配置設計的方便來變更。無論如何，只要使小電容的電容部CM與開關SW的配線儘量變短即可。 Of course, in the case of the configuration of Fig. 10, the configuration of Fig. 7A or Fig. 7C is also adopted, but for example, the following example can be considered: the capacitor parts CM0~CM6 and the switches SW0~SW6 are set to the small capacitor side, and the capacitor Parts CM7~CM10 and switches SW7~SW10 are set to the large capacitance side. Of course, the distinction between the large-capacitance side and the small-capacitance side is not limited to this, and it can also be changed according to the convenience of the actual layout design. In any case, it is only necessary to make the wiring between the capacitor portion CM of the small capacitance and the switch SW as short as possible.
[3-4：第4例] [3-4: Example 4]
藉由圖11、圖12、圖13來說明測量用電容部424的第4例之構成。這是只以特定的電容的電容器來構成全部的電容部CM0~CM10的例子。
The configuration of the fourth example of the
此外，雖然和圖7A同樣地採用第1區域AR1、第2區域AR2及第3區域AR3的配置構造，但是在配置電容部CM0~CM10的電容器之第1區域AR1中，是設成將構成各電容部CM的電容器配置成點對稱之構成。 In addition, although the arrangement structure of the first area AR1, the second area AR2, and the third area AR3 is adopted as in FIG. 7A, in the first area AR1 where the capacitors of the capacitor portions CM0 to CM10 are arranged, the structures are The capacitors of the capacitor portion CM are arranged in a point-symmetrical configuration.
藉由只以特定的電容的電容器來構成全部的電容部CM0~CM10之作法，可以減低因電容器的面積的不同所產生的電容誤差，且可以有助於線性度改善。 By forming all the capacitor parts CM0 to CM10 with only capacitors of specific capacitance, the capacitance error caused by the difference in the area of the capacitor can be reduced, and the linearity can be improved.
又，藉由如圖7A的配置，如上所述，可以將由寄生電容Cs的影響所造成的電容誤差的比率之差均一化，這也可以有助於線性度改善。 Furthermore, with the configuration shown in FIG. 7A, as described above, the difference in the ratio of capacitance errors caused by the influence of the parasitic capacitance Cs can be uniformized, which can also contribute to the improvement of linearity.
此外，藉由在第1區域AR1中將電容器設為點對稱配置，可減低在光蝕刻步驟等中所產生的x方向或y方向的傾斜誤差(後述)之影響，這也使電容精度提升，且與線性度的改善有關。 In addition, by arranging the capacitors in the first area AR1 in point symmetry, the influence of the inclination error in the x-direction or the y-direction (described later) generated in the photoetching step etc. can be reduced, which also improves the accuracy of the capacitors. And it is related to the improvement of linearity.
如此，第4例是成為可綜合地實現線性度的改善之例子。 In this way, the fourth example is an example that can comprehensively achieve linearity improvement.
首先，藉由圖11來說明只以特定的電容的電容器來構成全部的電容部CM0~CM10的情況之構成例。 First, with reference to FIG. 11, a configuration example in the case where all the capacitor portions CM0 to CM10 are configured by only capacitors of a specific capacitance will be described.
測量用電容部424的電容部CM0~CM10全部都是以16fF的電容器所構成。
All the capacitance portions CM0 to CM10 of the
電容部CM0是以8個16fF的電容器的串聯連接來構成2fF的電容。 The capacitor CM0 is a series connection of eight 16fF capacitors to form a 2fF capacitor.
電容部CM1是以4個16fF的電容器的串聯連接來構成4fF的電容。 The capacitor CM1 is a series connection of four 16fF capacitors to form a 4fF capacitor.
電容部CM2是以2個16fF的電容器的串聯連接來構成8fF的電容。 The capacitance portion CM2 is a series connection of two 16fF capacitors to form an 8fF capacitance.
電容部CM3是以1個16fF的電容器來構成。 The capacitor CM3 is composed of one 16fF capacitor.
電容部CM4是以2個16fF的電容器的並聯連接來構成32fF的電容。 The capacitor CM4 is a parallel connection of two 16fF capacitors to form a 32fF capacitor.
電容部CM5是以4個16fF的電容器的並聯連接來構成64fF的電容。 The capacitor CM5 is a parallel connection of four 16fF capacitors to form a 64fF capacitor.
電容部CM6是以8個16fF的電容器的並聯連接來構成128fF的電容。 The capacitor CM6 is a parallel connection of eight 16fF capacitors to form a 128fF capacitor.
電容部CM7是以16個16fF的電容器的並聯連接來構成256fF的電容。 The capacitor portion CM7 is a parallel connection of 16 capacitors of 16 fF to form a capacitance of 256 fF.
關於電容部CM8~CM10，是為了方便圖示而以方塊來顯示。 The capacitors CM8~CM10 are shown in squares for the convenience of illustration.
電容部CM8是以32個16fF的電容器的並聯連接來構成512fF的電容。 The capacitor CM8 is a parallel connection of 32 capacitors of 16fF to form a capacitor of 512fF.
電容部CM9是以64個16fF的電容器的並聯連接來構成1024fF的電容。 The capacitance portion CM9 is a parallel connection of 64 16fF capacitors to form a 1024fF capacitance.
電容部CM8是以128個16fF的電容器的並聯連接來構成2048fF的電容。 The capacitor CM8 is a parallel connection of 128 16fF capacitors to form a 2048fF capacitor.
如此，全部以相同的電容值的電容器來形成各電容部CM0~CM10之作法有助於線性度改善的理由可以考慮如下。 In this way, the reason why the capacitors CM0 to CM10 are all formed with capacitors of the same capacitance value contributes to the improvement of linearity can be considered as follows.
電容器的電容是依賴於面積或周邊長度。並且，可將IC內的電容器的佈置之成品尺寸的誤差表現為電容誤差。此時，佈置面積越大越難以受到尺寸誤差的影響，面積越小變得越容易受到影響。 The capacitance of a capacitor is dependent on the area or peripheral length. Moreover, the error of the finished product size of the arrangement of the capacitor in the IC can be expressed as a capacitance error. At this time, the larger the layout area, the harder it is to be affected by dimensional errors, and the smaller the area, the more susceptible it is.
再者，基本上(理論上)電容器電容是與面積成比例。 Furthermore, basically (theoretically) the capacitance of a capacitor is proportional to the area.
舉一個例子來說明受到由面積所造成的尺寸誤差的影響的容易度之不同。例如圖12A所示，設為16fF的電容器的設計尺寸為5μm×5μm的正方形，64fF的電容器的設計尺寸為10μm×10μm的正方形。 Give an example to illustrate the difference in ease of being affected by dimensional errors caused by area. For example, as shown in FIG. 12A, the design size of a 16fF capacitor is a square of 5 μm×5 μm, and the design size of a 64fF capacitor is a square of 10 μm×10 μm.
在此，設想在IC上的成品尺寸已成為在縱方向及橫方向上+0.1μm的情況。16fF的電容器是成為成品尺寸為5.1μm×5.1μm的正方形，64fF的電容器是成為成品尺寸成為10.1μm×10.1μm的正方形之情況。 Here, it is assumed that the size of the finished product on the IC has become +0.1 μm in the vertical and horizontal directions. The 16fF capacitor is a square with a finished size of 5.1μm×5.1μm, and the 64fF capacitor is a square with a finished size of 10.1μm×10.1μm.
16fF的電容的變化量是成為(5.1μm×5.1μm)÷(5μm×5μm)=1.04，而形成為產生有4%的電容誤差之情形。 The amount of change in the capacitance of 16fF is (5.1μm×5.1μm)÷(5μm×5μm)=1.04, and a capacitance error of 4% occurs.
64fF的電容的變化量是成為(10.1μm×10.1μm)÷(10μm×10μm)=1.01，而形成為產生有2%的電容誤差之情形。 The amount of change in the capacitance of 64fF is (10.1μm×10.1μm)÷(10μm×10μm)=1.01, and a 2% capacitance error occurs.
將成品尺寸設為+0.1μm並同樣地計算時，實際的電容即成為如下所述。 When the product size is set to +0.1μm and calculated in the same way, the actual capacitance becomes as follows.
‧16fF：4%的誤差=16.64 ‧16fF: 4% error = 16.64
‧32fF：2.8%的誤差=32.9fF ‧32fF: 2.8% error = 32.9fF
‧64fF：2%的誤差=65.28fF ‧64fF: 2% error=65.28fF
‧128fF：1.4%的誤差=129.79fF ‧128fF: 1.4% error=129.79fF
‧256fF：1%的誤差=258.56fF ‧256fF: 1% error=258.56fF
在此，將測量用電容部424的電容值設為254fF的情況下，是取電容部CM0~CM6的各電容值的總和。
Here, when the capacitance value of the
該電容部CM0~CM6的各電容值的總和，即使將2fF至8fF的誤差設為與16fF相同的4%，仍然會成為2.08+4.16+8.32+16.64+32.9+65.28+129.79=259.17[fF]。亦即，欲將電容設為「254fF」時的電容值 會成為「259.17fF」。 The sum of the capacitance values of the capacitors CM0~CM6, even if the error from 2fF to 8fF is set to 4% which is the same as 16fF, it will still be 2.08+4.16+8.32+16.64+32.9+65.28+129.79=259.17[fF] . That is, the capacitance value when you want to set the capacitance to "254fF" Will become "259.17fF".
另一方面，由於實際的「256fF」的電容器是因上述的誤差而為258.56fF，因此會成為「254fF」≧「256fF」而導致發生逆轉現象。 On the other hand, since the actual "256fF" capacitor is 258.56fF due to the above-mentioned error, it will become "254fF"≧"256fF" and a reverse phenomenon will occur.
亦即，成品尺寸的誤差所帶來的電容誤差按每個電容而偏差，因而使這樣的逆轉現象在例如256階段之類的可變電容的各階段中大量發生，而使線性度惡化。 That is, the capacitance error caused by the error of the finished product size varies for each capacitor, so that such reversal phenomenon occurs in a large amount in each stage of the variable capacitor such as 256 stages, and the linearity is deteriorated.
相對於此，由於在本實施形態的情況下僅使用「16fF」的電容器，因此成品尺寸的誤差對各電容器所帶來的電容誤差成為幾乎均一。如此一來，於各電容部CM所產生的電容誤差，無論該電容的大小如何，都會成為幾乎相同的誤差。 On the other hand, since only the "16fF" capacitor is used in the case of this embodiment, the error of the finished product size becomes almost uniform for the capacitance error caused by each capacitor. In this way, the capacitance error generated in each capacitance portion CM will become almost the same error regardless of the size of the capacitance.
亦即，如圖12B所示，當假設為成品尺寸為+0.1μm而和上述同樣地計算時，實際的電容會成為如下所述。亦即，為全部的電容器均成為5.1μm×5.1μm的正方形之情況。 That is, as shown in FIG. 12B, when the product size is assumed to be +0.1 μm and calculated in the same manner as described above, the actual capacitance will be as follows. That is, it is the case where all capacitors are 5.1 μm×5.1 μm square.
‧16fF的電容部CM3：4%誤差=16.64fF ‧16fF capacitor part CM3: 4% error=16.64fF
‧32fF的電容部CM4：16.64fF×2=33.28fF ‧32fF capacitor part CM4: 16.64fF×2=33.28fF
‧64fF的電容部CM5：16.64fF×4=66.56fF ‧64fF capacitor part CM5: 16.64fF×4=66.56fF
‧128fF的電容部CM6：16.64fF×8=133.12fF ‧128fF capacitor part CM6: 16.64fF×8=133.12fF
‧256fF的電容部CM7：16.64fF×16=266.24fF ‧ 256fF capacitor part CM7: 16.64fF×16=266.24fF
‧512fF的電容部CM8：16.64fF×32=532.48fF ‧512fF capacitor part CM8: 16.64fF×32=532.48fF
‧1024fF的電容部CM9：16.64fF×64=1064.96fF ‧1024fF capacitor part CM9: 16.64fF×64=1064.96fF
‧2048fF的電容部CM10：16.64fF×128=2129.92fF 在此情況下，由於電容誤差全部都是4%，因此不會發生如上述之「254fF」≧「256fF」的逆轉現象。因此，變得可大幅地改善線性度。 ‧2048fF capacitor part CM10: 16.64fF×128=2129.92fF In this case, since the capacitance error is all 4%, the above-mentioned "254fF" ≧ "256fF" reversal phenomenon will not occur. Therefore, it becomes possible to greatly improve linearity.
並且，如圖13A所示，採用第1區域AR1、第2區域AR2、及第3區域AR3的配置構造。 In addition, as shown in FIG. 13A, an arrangement structure of the first area AR1, the second area AR2, and the third area AR3 is adopted.
如圖示地在第1區域AR1中配置構成電容部CM0~CM10的全部16fF的電容器。再者，在第1區域AR1中1個格子是表示1個16fF的電容器。在各個格子中附有「0」~「10」，意義為：「0」是構成CM0的電容器，「1」是構成CM1的電容器，...「10」是構成CM10的電容器。 As shown in the figure, all 16 fF capacitors constituting the capacitance portions CM0 to CM10 are arranged in the first area AR1. In addition, one grid in the first area AR1 represents one 16fF capacitor. "0" ~ "10" are attached to each grid, meaning: "0" is the capacitor that constitutes CM0, "1" is the capacitor that constitutes CM1, ... "10" is the capacitor that constitutes CM10.
在第2區域AR2中配置有成為開關(例如開關SW0~SW5)的電晶體，前述開關是對應於被分在電容值較小之側的電容部(例如電容部CM0~CM5)之開關。 Transistors serving as switches (for example, switches SW0 to SW5) are arranged in the second area AR2, and the switches are switches corresponding to the capacitor parts (for example, capacitor parts CM0 to CM5) classified on the side with a smaller capacitance value.
在第3區域AR3中配置有成為開關(例如開關SW6~SW10)的電晶體，前述開關是對應於被分在電容值較大之側的電容部(例如電容部CM6~CM10)之開關。 Transistors serving as switches (for example, switches SW6 to SW10) are arranged in the third area AR3, and the aforementioned switches are switches corresponding to the capacitor portions (for example, capacitor portions CM6 to CM10) that are classified on the side with a larger capacitance value.
大電容側與小電容側的區分並不受限於此，只要配合實際的配置設計的方便來變更即可。 The distinction between the large-capacitance side and the small-capacitance side is not limited to this, as long as the actual configuration design is convenient to change.
藉由像這樣的第2區域AR2、第3區域AR3中的開關配置，可以在小電容側的電容部CM中縮短配線長度，並且可以縮小由寄生電容Cs的影響所造成的電容誤差。藉此，和第1例同樣地，可以將設計上的本來的誤差相對於電容的比率朝均一化的方向來進行調整，藉此，變得難以產生上述之逆轉現象，而可改善線性度。 With the switch arrangement in the second area AR2 and the third area AR3 as described above, the wiring length in the capacitor portion CM on the small-capacitance side can be shortened, and the capacitance error caused by the influence of the parasitic capacitance Cs can be reduced. As a result, as in the first example, the ratio of the original design error to the capacitance can be adjusted in a uniform direction, thereby making it difficult to generate the above-mentioned reversal phenomenon, and the linearity can be improved.
此外，在第1區域AR1中，是構成各電容部CM的電容器相對於第1區域AR1的中心點CT而配置成點對稱。 In addition, in the first area AR1, the capacitors constituting each capacitance portion CM are arranged point-symmetrically with respect to the center point CT of the first area AR1.
電容部CM0是將附上『0』的8個電容器以對中心點CT成為點對稱的關係來配置。電容部CM1是將附上『1』的4個電容器以對中心點CT成為點對稱的關係來配置。電容部CM1是將附上『2』的2個電容器以對中心點CT成為點對稱的關係來配置。 In the capacitor portion CM0, eight capacitors with "0" are arranged in a point-symmetric relationship with the center point CT. In the capacitor portion CM1, four capacitors with "1" are arranged in a point-symmetric relationship with respect to the center point CT. In the capacitor portion CM1, two capacitors attached with "2" are arranged in a point-symmetrical relationship with the center point CT.
針對電容部CM3是將附上『3』的4個電容器以對中心點CT成為點對稱的關係來配置。但是，電容部CM3亦可是1個電容器。配置有4個電容器之構成是用於對CM0~CM10全部都進行點對稱配置的調整之含義，實際上只使用附上『3』的4個電容器的其中任1個，其他是作為虛擬(dummy)。同樣地在配置調整的意義上也構成有附上『dum』的8個虛擬電容器。 For the capacitor CM3, the four capacitors with "3" are arranged in a point-symmetric relationship with the center point CT. However, the capacitor part CM3 may be one capacitor. The configuration with 4 capacitors is used to adjust all CM0~CM10 points symmetrically. In fact, only one of the 4 capacitors with "3" is used, and the others are used as dummy (dummy). ). Similarly, in the sense of configuration adjustment, 8 virtual capacitors with "dum" are also constructed.
電容部CM4是將附上『4』的2個電容器以對中心點CT成為點對稱的關係來配置。電容部CM5是將附上『5』的4個電容器以對中心點CT成為點對稱的關係來配置。針對電容部CM6~CM10的每一個也是將附上『6』的8個電容器、附上『7』的16個電容器、附上『8』的32個電容器、附上『9』的64個電容器、附上『10』的128個電容器，以對中心點CT成為點對稱的關係來配置。 In the capacitor portion CM4, two capacitors with "4" are arranged in a point-symmetrical relationship with respect to the center point CT. In the capacitor portion CM5, four capacitors attached with "5" are arranged in a point-symmetric relationship with the center point CT. For each of the capacitors CM6~CM10, there are 8 capacitors with "6", 16 capacitors with "7", 32 capacitors with "8", and 64 capacitors with "9". , The 128 capacitors with "10" attached are arranged in a point-symmetric relationship with the center point CT.
針對較大電容值的電容部CM，因為會成為配置大量特定的電容值的電容器(在此例中為16fF)之情 形，所以將構成小電容側的電容部CM的電容器配置成集中於第1區域AR1的中央側。 For the capacitor part CM with a larger capacitance value, it will be a situation where a large number of capacitors with a specific capacitance value (in this example, 16fF) are arranged Therefore, the capacitors constituting the capacitor portion CM on the small-capacitance side are arranged to be concentrated on the center side of the first area AR1.
並且，藉由如圖示地設為點對稱配置，即使在特性上產生傾斜時也可以形成為不受到配置的影響。 Furthermore, by setting it as a point symmetrical arrangement as shown in the figure, it can be formed so as not to be affected by the arrangement even when the characteristic is inclined.
在此所謂的「傾斜」是指取決於佈置之特性的變化之情形，基本上是相對於x方向或y方向來設想暫時的變化。產生特性的傾斜的因素可列舉光蝕刻步驟的處理、基板濃度、膜厚等，可以說是因綜合上的製程偏差所產生。 The so-called "tilt" here refers to a situation that depends on changes in the characteristics of the layout, and basically assumes a temporary change with respect to the x direction or the y direction. Factors that cause the inclination of characteristics include processing in the photoetching step, substrate concentration, film thickness, etc., which can be said to be caused by overall process variations.
考慮例如在x方向上具有傾斜的情況。在圖13B中是將第1區域AR1的中央部(粗線CAR)放大而顯示。如圖示，電容值在x方向上具有傾斜，並設為x方向的4個電容器的電容值為15.8fF、15.9fF、16fF、16.1fF。 Consider, for example, a case where there is a tilt in the x direction. In FIG. 13B, the center part (thick line CAR) of the first area AR1 is enlarged and displayed. As shown in the figure, the capacitance value has a slope in the x direction, and the capacitance values of the four capacitors in the x direction are 15.8fF, 15.9fF, 16fF, and 16.1fF.
在此情況下，附上『5』的電容部CM5的電容值是成為15.8+15.9+16+16.1=63.8fF。 In this case, the capacitance value of the capacitor section CM5 with "5" is 15.8+15.9+16+16.1=63.8fF.
亦即，藉由在第1區域AR1中以對中心點CT成為點對稱的關係來配置電容器，因為可以抵消由傾斜所造成的誤差，並且可以減低特性傾斜的影響，所以可以縮小在各電容部CM所產生的誤差。據此，可以有助於線性度的改善。 That is, by arranging the capacitors in the first area AR1 in a point-symmetrical relationship with the center point CT, the error caused by the tilt can be canceled, and the effect of the characteristic tilt can be reduced, so it is possible to reduce the size of each capacitor portion Error caused by CM. Accordingly, it can contribute to the improvement of linearity.
[3-5：第5例] [3-5: Example 5]
藉由圖14來說明測量用電容部424的第5例之構成。這雖然是和圖11同樣地只以特定的電容(例如16fF)的電容器來構成全部的電容部CM0~CM10的例子，但是開關SW4~SW10的構成不同。如上述之第4例所說明，雖然可以藉由全部以相同的電容值的電容器來形成各電容部
CM0~CM10，以改善線性度，但是圖14是可以進一步提升電容精度的例子。
The configuration of the fifth example of the
在圖14的測量用電容部424中，電容部CM0~CM3及開關SW0~SW3的構成是和圖11相同。亦即，電容部CM0~CM3是全部使用16fF的電容器，又，相對於該電容部CM0~CM3(1個或複數個串聯連接的電容器)，而設置由1個開關元件所形成的開關SW0~SW3。
In the
在此圖14的構成中，是針對開關SW4~SW10而將開關元件設置成各自以1：1的方式來對應於電容元件，其中前述開關SW4~SW10是對應於藉由複數個電容器的並聯連接所構成的電容部CM4~CM10之開關。 In the configuration of FIG. 14, the switch elements are set to correspond to the capacitive element in a 1:1 manner for the switches SW4 to SW10, and the aforementioned switches SW4 to SW10 correspond to the parallel connection of a plurality of capacitors. Switches of capacitors CM4~CM10 formed.
例如電容部CM4是設成藉由2個16fF的電容器的並聯連接而得到32fF，作為開關SW4則是設成設置與此2個電容器的每一個相對應的2個開關元件。 For example, the capacitor portion CM4 is set to obtain 32fF by connecting two 16fF capacitors in parallel, and the switch SW4 is set to provide two switching elements corresponding to each of the two capacitors.
開關SW5、SW6、SW7、SW8、SW9、SW10也是同樣的。 The same applies to switches SW5, SW6, SW7, SW8, SW9, and SW10.
例如電容部CM7是設成藉由16個16fF的電容器的並聯連接而得到256fF，作為對應於此的開關SW7則是設成設置與此16個電容器相對應的16個開關元件。 For example, the capacitor portion CM7 is set to obtain 256fF by connecting 16 16fF capacitors in parallel, and as the switch SW7 corresponding to this, 16 switching elements corresponding to the 16 capacitors are provided.
為了方便圖示，將電容部CM8~CM10、開關SW8~SW10方塊化，開關SW8~SW10也是按各自對應的電容部CM8~CM10的每個電容器而設置有開關元件。 For the convenience of illustration, the capacitors CM8 to CM10 and the switches SW8 to SW10 are block-shaped, and the switches SW8 to SW10 are also provided with switching elements for each capacitor of the corresponding capacitors CM8 to CM10.
如此，針對作為測量用電容部424內的電容部CM而並聯連接的電容器，是對應於1個1個的16fF的電容器來設置
開關元件。
In this way, the capacitors connected in parallel as the capacitor portion CM in the measuring
與1個電容部CM相對應的開關SW內之複數個開關元件，是同時受到開啟/關閉控制。 A plurality of switching elements in the switch SW corresponding to one capacitor part CM are simultaneously controlled on/off.
例如開關SW4的2個開關元件，是在選擇電容部CM4時同時設為開啟，又，將電容部CM4從整體的電容排除時是同時設為關閉。 For example, the two switching elements of the switch SW4 are simultaneously turned on when the capacitor portion CM4 is selected, and when the capacitor portion CM4 is excluded from the overall capacitance, they are simultaneously turned off.
如此，藉由將開關元件也並聯地形成，即可以促進線性度的改善。 In this way, by forming the switching elements in parallel, the linearity can be improved.
如上述，雖然在電容部CM的電容器與開關SW的開關元件的配線間會產生寄生電容Cs，但是在電容部CM4~CM10中，藉由對並聯的各電容器各自連接開關元件，即可以謀求寄生電容的均一化，並可以藉此減少起因於寄生電容的電容誤差，並形成精度較高的電容值。從而，可以有助於線性度的改善。 As mentioned above, although the parasitic capacitance Cs is generated between the capacitor of the capacitor portion CM and the switching element of the switch SW, in the capacitor portions CM4 to CM10, by connecting the switching element to each capacitor in parallel, the parasitic capacitance can be achieved. The uniformity of the capacitance can reduce the capacitance error caused by the parasitic capacitance and form a capacitance value with higher accuracy. Thus, it can contribute to the improvement of linearity.
[3-6：第6例] [3-6: The sixth example]
以圖15來說明測量用電容部424的第6例之構成。
The configuration of the sixth example of the
如上述第5例所示，藉由對應於並聯連接的電容器的每1個來設置開關元件之作法，對於寄生電容Cs的均一化而言是較佳的，但是會使開關元件數量和電容器數量一起大幅地增加。如此一來，也可能發生配置面積的擴大或佈置的困難性之類被視為在製造上的不期望的情況。 As shown in the fifth example above, the arrangement of switching elements corresponding to each of the capacitors connected in parallel is better for the uniformization of the parasitic capacitance Cs, but it will increase the number of switching elements and the number of capacitors. Increased significantly together. In this way, the expansion of the arrangement area or the difficulty of the arrangement may be regarded as undesirable in manufacturing.
於是，作為將寄生電容Cs的均一化與配置面積等一起考量之構成，可考慮圖15的構成。 Therefore, as a configuration in which the uniformization of the parasitic capacitance Cs and the arrangement area are considered together, the configuration of FIG. 15 can be considered.
在圖15中，是在測量用電容部424中提取並
顯示電容部CM4~CM10及開關SW4~SW10的部分。圖示外的部分是和圖14同樣。
In FIG. 15, it is extracted and combined in the
此圖15是設成例如將到128fF為止的電容作為單位來設置1個開關元件。 In FIG. 15, it is assumed that, for example, one switching element is provided with a capacitance up to 128 fF as a unit.
亦即，針對電容值為128fF以下的電容部CM4、CM5、CM6，是對應於各個電容部CM4、CM5、CM6來設置由1個開關元件所形成的開關SW4、SW5、SW6。 That is, for the capacitor portions CM4, CM5, and CM6 having a capacitance value of 128 fF or less, the switches SW4, SW5, and SW6 formed by one switching element are provided corresponding to the respective capacitor portions CM4, CM5, and CM6.
由於電容部CM7是藉由16個16fF的電容器而使電容值為256fF，因此按每8個電容器(128fF)來設置1個開關元件。亦即，以2個開關元件來形成開關SW7。 Since the capacitance portion CM7 uses 16 16 fF capacitors to have a capacitance value of 256 fF, one switching element is provided for every 8 capacitors (128 fF). That is, the switch SW7 is formed by two switching elements.
電容部CM8是藉由32個16fF的電容器來讓電容值成為512fF。圖中的一點鏈線的4個框是各自顯示8個電容器的並聯連接。按每此8個電容器(128fF)來設置1個開關元件。亦即，以4個開關元件來形成開關SW8。 The capacitor CM8 uses 32 16fF capacitors to make the capacitance value 512fF. The 4 boxes of the one-dot chain line in the figure each show the parallel connection of 8 capacitors. One switching element is provided for every 8 capacitors (128fF). That is, the switch SW8 is formed by four switching elements.
電容部CM9與開關SW9是為了圖式的方便而方塊化來顯示，電容部CM9是藉由64個16fF的電容器來讓電容值成為1024fF。在此情況下也是按每8個電容器的並聯連接(128fF)來設置1個開關元件，並且以8個開關元件來形成開關SW9。 The capacitor part CM9 and the switch SW9 are shown in blocks for the convenience of the drawing. The capacitor part CM9 uses 64 16fF capacitors to make the capacitance value 1024fF. Also in this case, one switching element is provided for every 8 capacitors connected in parallel (128fF), and 8 switching elements form the switch SW9.
電容部CM10與開關SW10也是以方塊化來顯示，電容部CM10是藉由128個16fF的電容器來讓電容值成為2048fF。在此情況下也是按每8個電容器的並聯連接(128fF)來設置1個開關元件，並且以16個開關元件來形成 開關SW10。 The capacitor part CM10 and the switch SW10 are also displayed in squares, and the capacitor part CM10 uses 128 16fF capacitors to make the capacitance value 2048fF. In this case, one switching element is provided for every 8 capacitors connected in parallel (128fF), and 16 switching elements are used. Switch SW10.
藉由設為像這樣的構成，以相較於圖14的構成來減少開關元件數量。雖然相對於並聯連接的各電容器之寄生電容Cs的均一化的效果會變得較小一些，但是可降低佈置上的困難性。換言之，既可得到寄生電容Cs的均一化的效果，且成為適合於設計或製造上的情形之構成。 By adopting such a configuration, the number of switching elements can be reduced compared to the configuration of FIG. 14. Although the effect of uniformizing the parasitic capacitance Cs of the capacitors connected in parallel will be smaller, the difficulty in arrangement can be reduced. In other words, it is possible to obtain the effect of uniformity of the parasitic capacitance Cs, and it becomes a configuration suitable for the design or manufacturing situation.
再者，雖然是設為以128fF作為單位來設置開關，但是當然並不限定於以128fF作為單位。 In addition, although it is assumed that the switch is provided in units of 128fF, it is of course not limited to the units of 128fF.
<4.實施形態的效果及變形例> <4. Effects of the embodiment and modification examples>
根據以上之實施形態的觸控面板裝置1或觸控面板驅動裝置3可得到如以下的效果。
According to the
實施形態的觸控面板驅動裝置3是對觸控面板2進行掃描，前述掃描是依序選擇相鄰的一對發送訊號線21與相鄰的一對接收訊號線22之掃描。並且具備有接收電路42，前述接收電路42是接收來自觸控面板2的一對接收訊號線22之藉由伴隨於使用者的操作的電容變化而使波形變化的各接收訊號R+、R-，並且生成用於觸控面板操作監視的檢測值(RAW值)。在此接收電路42中設置有測量用電容部424，前述測量用電容部424具有複數個電容部CM及複數個開關SW，前述電容部CM是電容值不同的第1電容部至第X電容部，且可各自並聯地連接於一邊的接收訊號線，前述開關SW是第1開關至第X開關，且對應於各電容部CM的每一個，接收電路42是進行下述動作來生成RAW值：一面藉由各開關SW來選擇連接於一邊的接收訊號線的電
容部，藉此依序切換測量用電容部424的電容值，一面比較來自一邊的接收訊號線與另一邊的接收訊號線的各接收訊號R-、R+之位準。在包含接收電路42的積體電路即感測器IC4D中設置有：第1區域AR1，配置構成第1~第X的各電容部CM的電容元件(電容器)；第2區域AR2，配置與被分在電容值較小之側的電容部CM相對應的開關SW；及第3區域AR3，配置與被分在電容值較大之側的電容部CM相對應的開關SW，第2區域AR2是形成在比第3區域AR3更接近於第1區域AR1的位置。
The touch
藉由將第2區域AR2設為比第3區域AR3更接近於第1區域AR1的位置，可以使較小的電容的電容部CM與開關SW之間的配線長度變得較短。藉此，可以在較小的電容的電容部CM中讓電容誤差變小，且可以作為整體來將各電容部CM的誤差的比率朝均一化的方向調整。藉由如此進行，在如例如圖4的例子所示地以8位元的電容設定值來控制的256個階段的電容、或如圖9、圖10、圖11的例子所示地以11位元的電容設定值來控制的2048個階段的電容中，就變得不會或不容易產生電容值的逆轉之類的情形。 By setting the second area AR2 to a position closer to the first area AR1 than the third area AR3, the wiring length between the capacitor portion CM of a smaller capacitance and the switch SW can be shortened. Thereby, the capacitance error can be reduced in the capacitor portion CM of a smaller capacitance, and the error ratio of each capacitor portion CM can be adjusted to be uniform as a whole. By doing this, for example, as shown in the example of FIG. 4, the capacitance of 256 stages controlled by the 8-bit capacitance setting value, or the 11-bit capacitance as shown in the example of FIG. 9, FIG. 10, and FIG. Among the 2048-stage capacitors controlled by the basic capacitance setting value, it becomes impossible or difficult to cause the reversal of the capacitance value.
作為結果，變得可改善測量用電容部424的線性度，並可藉此確保RAW值的正確性。從而，變得也將MCU5所求出的操作位置座標的資訊之精度提升，而能夠對製品側MCU90提供高精度的操作檢測資訊。
As a result, it becomes possible to improve the linearity of the
在實施形態中已描述了下述的例子：如圖7C所示，在第1區域AR1內，在第1電容部至第X電容部之電 容部CM當中的形成電容值較小的電容部CM之電容元件是配置在比形成電容值較大的電容部CM之電容元件更接近於第2區域AR2的位置。 In the embodiment, the following example has been described: as shown in FIG. 7C, in the first area AR1, the electric power between the first capacitor portion to the Xth capacitor portion Among the capacitors CM, the capacitor element forming the capacitor portion CM having a smaller capacitance value is arranged at a position closer to the second area AR2 than the capacitor element forming the capacitor portion CM having a larger capacitance value.
藉此，可以在較小的電容的電容部CM中，讓電容元件與開關SW之間的配線長度變得較短，並且可以讓較小的電容的電容部CM的電容誤差變小。這也可以作為整體而有助於各電容部CM的電容誤差的均一化、線性度的改善。 Thereby, in the capacitor portion CM of a smaller capacitance, the wiring length between the capacitance element and the switch SW can be shortened, and the capacitance error of the capacitor portion CM of the smaller capacitance can be reduced. This can also contribute to the uniformization of the capacitance error of each capacitance portion CM and the improvement of linearity as a whole.
又，在圖10的第3例的情況下設成：在第1電容部至第X電容部之各電容部CM當中，預定值以上的電容值的電容部CM是藉由複數個電容元件的並聯連接所形成。 In addition, in the case of the third example of FIG. 10, it is assumed that among the capacitor portions CM of the first capacitor portion to the X-th capacitor portion, the capacitor portion CM having a capacitance value greater than a predetermined value is formed by a plurality of capacitor elements Connected in parallel.
藉由針對預定值以上的電容部，是以電容元件的並聯連接來形成必要的電容，可以將在整體上的面積比變小。藉此，可以將由電容器面積之差所造成的寄生電容產生的誤差的影響程度之差變小，並作為整體來將電容部CM的電容誤差變小。這也對測量用電容部424的線性度改善變得有效。
By connecting the capacitor elements in parallel to form the necessary capacitance for the capacitor portion having a predetermined value or more, the overall area ratio can be reduced. Thereby, the difference in the degree of influence of the error caused by the parasitic capacitance caused by the difference in capacitor area can be reduced, and the capacitance error of the capacitor portion CM as a whole can be reduced. This also becomes effective for improving the linearity of the measuring
在圖11、圖12、圖13中所說明的第4例中，是說明了下述構成：形成各電容部CM的複數個電容元件，全部都是藉由特定的電容值(例如16fF)的電容元件所形成，且在第1區域AR1中，構成每一個電容部CM的電容元件(1個電容部CM中的複數個電容器)是配置成點對稱。 In the fourth example illustrated in FIG. 11, FIG. 12, and FIG. 13, the following structure is explained: the plurality of capacitor elements forming each capacitor portion CM are all made of a specific capacitance value (for example, 16fF) Capacitive elements are formed, and in the first area AR1, the capacitive elements (a plurality of capacitors in one capacitor CM) constituting each capacitor CM are arranged in point symmetry.
藉由將各電容部CM的全部的電容器設為例如16fF的
電容器，並將面積設為均一，可以將起因於面積的電容誤差的比率之差均一化。又，藉由點對稱的配置，即使在感測器IC4中於x方向或y方向上發生特性傾斜之情形，仍然可以藉由配置位置來防止導致電容誤差之差變大的情形。從而，可以讓各電容部CM的電容誤差變小，而對測量用電容部424的線性度改善變得有效。
By setting all the capacitors of each capacitor section CM to, for example, 16fF
The area of the capacitor is made uniform, and the difference in the ratio of the capacitance error caused by the area can be made uniform. In addition, with the point-symmetrical arrangement, even if the sensor IC4 has a characteristic tilt in the x-direction or the y-direction, the arrangement position can still prevent the capacitance error from becoming larger. Therefore, the capacitance error of each capacitance portion CM can be reduced, and the linearity improvement of the
再者，在第4例中，雖然設成在以特定的電容值的電容器來構成全部的電容部CM的情況下如圖13所示地配置為點對稱，但是電容器配置並不受限於此。 In addition, in the fourth example, although all capacitor portions CM are configured with capacitors of a specific capacitance value, the arrangement is point-symmetrical as shown in FIG. 13, but the capacitor arrangement is not limited to this. .
例如雖然在第1區域AR1中以16fF的電容器來構成全部，但是也可以設成將越小的電容值的電容部CM配置於越接近於第2區域AR2的位置。亦即，也可以採用圖7C的構成。 For example, although the first area AR1 is composed of 16 fF capacitors, the capacitor portion CM with a smaller capacitance value may be arranged closer to the second area AR2. That is, the configuration of FIG. 7C may also be adopted.
藉此，可以減少在小電容側的寄生電容Cs，並且減低各電容部CM中的由寄生電容Cs所造成的電容誤差的比率之差。 Thereby, the parasitic capacitance Cs on the small capacitance side can be reduced, and the difference in the ratio of capacitance errors caused by the parasitic capacitance Cs in each capacitance portion CM can be reduced.
在圖14、圖15所說明的第5例、第6例的情況下，藉由設成相對於在電容部CM中並聯連接的電容器的每1個(或以128fF等的預定電容單位)來設置開關元件，可以促進在電容器與開關元件間的配線所產生的寄生電容Cs的均一化，且可以有助於線性度的改善。 In the case of the fifth and sixth examples illustrated in FIGS. 14 and 15, it is set for each of the capacitors connected in parallel in the capacitor CM (or in a predetermined capacitance unit such as 128fF). The provision of the switching element can promote the uniformity of the parasitic capacitance Cs generated in the wiring between the capacitor and the switching element, and can contribute to the improvement of linearity.
實施形態的測量用電容部424是將第1電容部至第X電容部之各電容值設為2的乘冪的關係之電容值。
The measuring
具體而言，在圖4的第1例的構成之情況下，電容部 CM0~CM7的各電容值是設為具有21、22、23...28之比例的關係之2的1次方至2的X次方的電容值。 Specifically, in the case of a first example configuration of FIG. 4, each of the capacitance of the capacitor portion CM0 ~ CM7 is set to have a relation of 2 21, 22, 23 ... 28 of the ratio of The capacitance value from 1 to 2 to the X power.
又，在圖9的第2例、圖10的第3例、圖11的第4例、圖14的第5例、圖15的第6例的構成之情況下，電容部CM0~CM10的各電容值是設為具有21、22、23...211的比例的關係之2的1次方至2的X次方的電容值。 Also, in the case of the second example of FIG. 9, the third example of FIG. 10, the fourth example of FIG. 11, the fifth example of FIG. 14, and the sixth example of FIG. 15, each of the capacitor portions CM0 to CM10 The capacitance value is a capacitance value set to have a ratio of 2 1 , 2 2 , 2 3 ... 2 11 from the 1st power of 2 to the X power of 2.
藉此，測量用電容部424可以藉由電容部的選擇以2X個階段的方式來改變合成電容值。並且，藉由如圖7A、圖7C、圖13A的配置，以成為在2X個階段當中不產生逆轉現象，前述逆轉現象是導致較小的電容值這方相較於較大的電容值，實際的電容變得較大之類的現象。
Accordingly, the
此外，在此情況下，較理想的是以X位元的電容設定值來進行電容可變控制。以例如8位元(或11位元)的電容設定值，將各位元分配於電容部CM0~CM7(或CM10)的開關SW0~SW7(或SW10)之開啟/關閉控制。 In addition, in this case, it is ideal to perform capacitance variable control with a capacitance setting value of X bits. Using, for example, an 8-bit (or 11-bit) capacitor setting value, each bit is allocated to the on/off control of the switches SW0 to SW7 (or SW10) of the capacitor portions CM0 to CM7 (or CM10).
藉此，電容設定值本身成為顯示合成電容值之值，且如上所述，可以利用電容設定值來得到RAW值，其中前述合成電容值是藉由第1電容部至第X電容部的選擇而實現的複數個階段的合成電容值。這在運算處理上會成為非常有效率的處理。 Thereby, the capacitance setting value itself becomes the value showing the composite capacitance value, and as described above, the RAW value can be obtained by using the capacitance setting value, wherein the aforementioned composite capacitance value is determined by the selection of the first to the Xth capacitor The combined capacitance value of multiple stages realized. This will become a very efficient process in arithmetic processing.
在圖11中所說明的第4例(或圖14的第5例、圖15的第6例)中，是藉由利用16fF的電容器來形成2fF~2048fF之11個電容部CM0~CM10，而可以將必要的電容器數量變得比較少。 In the fourth example illustrated in FIG. 11 (or the fifth example in FIG. 14 and the sixth example in FIG. 15), 11 capacitor portions CM0 to CM10 of 2fF to 2048fF are formed by using 16fF capacitors, and The number of necessary capacitors can be reduced.
例如當全部都設為2fF的電容器時，會為了2048fF而變得要將1024個電容器並聯連接，與全部為16fF的情況之128個相較之下顯著變多。當然，雖然若使用32fF、64fF等之電容器，就可以更加減少必要的電容器數量，但是另一方面，電容變得越大則電容器的面積會變得越大。考量到這些，藉由在電容部CM當中使用中央附近的電容值的電容器，在IC設計上即變得有利。 For example, when all capacitors are 2fF, 1024 capacitors will be connected in parallel for 2048fF, which is significantly more than the 128 capacitors in the case of 16fF. Of course, while using 32fF, 64fF, etc. capacitors, the number of necessary capacitors can be further reduced, but on the other hand, the larger the capacitance, the larger the area of the capacitor. In consideration of these, by using a capacitor with a capacitance near the center in the capacitor portion CM, it becomes advantageous in IC design.
再者，如第4例所示地僅利用1個電容值的電容器的情況下，也可以考慮下述情形：在基準電容部422側也利用和測量用電容部424的電容器相同的電容值之電容器。
Furthermore, in the case of using only one capacitance value capacitor as shown in the fourth example, the following situation can also be considered: the
例如基準電容部422側，雖然以1個256fF的電容器來構成即可，但是若考慮作為比較基準的精度提升，也可考慮在基準電容部422也以16個16fF的電容器的並聯連接來構成256fF的電容。
For example, the
又，在實施形態的觸控面板裝置1中，雖然是以進行觸控操作之構成來說明，但是也可以作為與所謂的懸停感測(hover sensing)(非接觸式接近操作)相對應的觸控面板裝置來實現。
In addition, in the
又，實施形態的構成或動作僅是一例。本發明可考慮到其他各種的構成例、動作例。 In addition, the configuration or operation of the embodiment is only an example. In the present invention, various other configuration examples and operation examples can be considered.
接收電路42或測量用電容部424並不限定於以上揭示之構成。特別是將用於第2區域AR2、第3區域AR3的配置的小電容側/大電容側的區分，只要能因應於所使用的電容
器電容、數量、元件尺寸、開關元件的類別、構造等來決定即可。
The receiving
又，雖然顯示了在電容部CM0~CM7中以256個階段的方式來改變電容的構成、及在電容部CM0~CM10中以2048個階段的方式來改變電容的構成，但是也可考慮下述情形：設為設置更多數量的電容部CM，而能夠以更多階段的方式來改變電容。當然也可以考慮減少可變電容階段數量的例子。 In addition, although it is shown that the configuration of the capacitor is changed in 256 steps in the capacitor parts CM0 to CM7, and the configuration of the capacitor is changed in 2048 steps in the capacitor parts CM0 to CM10, the following can also be considered Situation: It is assumed that a larger number of capacitor parts CM are provided, and the capacitance can be changed in more stages. Of course, an example of reducing the number of variable capacitor stages can also be considered.
AR1‧‧‧第1區域
AR1‧‧‧
AR2‧‧‧第2區域
AR2‧‧‧
AR3‧‧‧第3區域
AR3‧‧‧
CM0~CM7‧‧‧電容部 CM0~CM7‧‧‧Capacitor
Claims (5)
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| CN103135840A (en) * | 2011-12-05 | 2013-06-05 | 乐金显示有限公司 | Touch screen sensing device and method for sensing touch screen |
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| CN103135840A (en) * | 2011-12-05 | 2013-06-05 | 乐金显示有限公司 | Touch screen sensing device and method for sensing touch screen |
| US20150054777A1 (en) * | 2012-02-29 | 2015-02-26 | Lg Innotek Co., Ltd. | Position sensing method of touch panel and integrated circuit |
| TW201443754A (en) * | 2013-05-08 | 2014-11-16 | Touchplus Information Corp | Method and device for sensing control point on capacitive-type panel |
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