TWI697882B - Display apparatus - Google Patents

Display apparatus Download PDF

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TWI697882B
TWI697882B TW108110490A TW108110490A TWI697882B TW I697882 B TWI697882 B TW I697882B TW 108110490 A TW108110490 A TW 108110490A TW 108110490 A TW108110490 A TW 108110490A TW I697882 B TWI697882 B TW I697882B
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transistor
partitions
display
coupled
display device
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TW108110490A
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TW202009903A (en
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李明賢
張哲嘉
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友達光電股份有限公司
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Abstract

The present invention provides a display apparatus. The display apparatus includes a plurality of display areas, each of the display areas includes a plurality of display pixels, a control line, and a switch. The switch is coupled between the plurality of display pixels and the control line of corresponding display area, and is controlled by a data update control signal of a gate line in the display area to be turned on or cut off.

Description

顯示裝置Display device

本發明是有關於一種顯示裝置，且特別是有關於一種分區更新顯示畫面的顯示裝置。 The present invention relates to a display device, and more particularly to a display device for updating a display screen by partition.

由於顯示裝置的大型化、高頻化及高解析化的發展，使得顯示器的消耗電力快速增加。因此，發展出分區更新顯示畫面的技術，僅針對局部的分區進行正常頻率的影像資料刷新，而在其它的大部分分區則進行降低頻率的影像資料刷新，來有效地降低顯示裝置的消耗電力。 Due to the development of large-scale, high-frequency, and high-resolution display devices, the power consumption of the display is rapidly increasing. Therefore, a technology for updating the display screen by partition has been developed. Only partial partitions are refreshed with normal frequency of image data, while in most other partitions, image data is refreshed at a reduced frequency to effectively reduce the power consumption of the display device.

然而，先前技術的分區更新顯示畫面的顯示裝置，同行分區共用分區控制線，當分區更新顯示畫面時，產生分區間的交互影響。當進行分區更新顯示畫面時，基於不同分區的各顯示畫素內薄膜電晶體(Thin-Film-Transistor,TFT)導通(ON)或斷開(OFF)的狀態不同，而產生分區間不同的漏電現象。上述的漏電現象，會使在不同分區間，顯示畫素產生不同的光學表現，並導致顯示器整體的顯示畫面發生畫面串擾(cross-talk)，而造成顯示品質的降低。 However, in the prior art display device that updates the display screen by partition, the same partitions share the partition control line, and when the partition updates the display screen, an interactive influence between the partitions occurs. When the display screen is updated by partition, the ON or OFF state of the thin film transistor (Thin-Film-Transistor, TFT) in each display pixel based on different partitions is different, resulting in different leakage between partitions. phenomenon. The above-mentioned leakage phenomenon will cause different optical performances of display pixels between different partitions, and cause cross-talk to occur in the overall display screen of the display, which will reduce the display quality.

本發明提供一種分區更新顯示畫面的顯示裝置，可有效地降低顯示裝置的消耗電力，並且提升顯示品質。 The present invention provides a display device for updating display images in partitions, which can effectively reduce the power consumption of the display device and improve the display quality.

本發明的顯示裝置包括多個分區。各分區包含多個顯示畫素、控制線及開關。控制線用以傳輸分區控制信號。開關耦接在多個顯示畫素與控制線間，且受控於分區內閘極線的分區致能信號以被導通或斷開。 The display device of the present invention includes a plurality of partitions. Each zone contains multiple display pixels, control lines and switches. The control line is used to transmit the zone control signal. The switch is coupled between a plurality of display pixels and the control line, and is controlled by the partition enable signal of the gate line in the partition to be turned on or off.

基於上述，本發明提出了一種分區更新顯示畫面的顯示裝置，透過在分區中提供開關，並透過開關的導通或斷開決定分區的資料刷新頻率。由於開關的導通或斷開是由分區的閘極線所控制，因此可避免其它分區於資料刷新時的影響，可改善上述在不同分區間的畫面串擾問題，確保顯示裝置在分區更新顯示畫面時也能夠維持良好的顯示品質。 Based on the above, the present invention proposes a display device for updating display screens in partitions. Switches are provided in the partitions, and the data refresh frequency of the partitions is determined by the on or off of the switches. Since the on or off of the switch is controlled by the gate line of the partition, it can avoid the influence of other partitions when the data is refreshed, which can improve the above-mentioned crosstalk problem between different partitions, and ensure that the display device updates the display screen when the partition is updated. It can also maintain good display quality.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式詳細說明如下。 In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

20:多工器電路 20: Multiplexer circuit

30:閘極驅動器 30: Gate driver

40:源極驅動器 40: source driver

100:顯示裝置 100: display device

CL1~CL3:控制線 CL1~CL3: control line

CLC:畫素電容 CLC: pixel capacitance

CLP:走線 CLP: routing

GL1~GLM:閘極線 GL1~GLM: gate line

PX11~PXMN:顯示畫素 PX11~PXMN: display pixels

SL1~SLN:資料傳輸線 SL1~SLN: data transmission line

SW1、SW2:開關 SW1, SW2: switch

T1、T2、TSW:電晶體 T1, T2, TSW: Transistor

Z11~Z33:分區 Z11~Z33: Partition

圖1是本發明的第一實施例的顯示裝置中包含多個分區的示意圖。 FIG. 1 is a schematic diagram of a display device including multiple partitions in a first embodiment of the present invention.

圖2是本發明的第一實施例的多個分區的其中一個分區的示意圖。 Fig. 2 is a schematic diagram of one of the multiple partitions in the first embodiment of the present invention.

圖3是本發明與傳統的分區更新顯示畫面的顯示裝置在不同分區的漏電差異的示意圖。 FIG. 3 is a schematic diagram of the leakage difference between the present invention and the traditional display device for updating the display screen in different partitions.

圖4是本發明的第一實施例的電路架構的示意圖。 FIG. 4 is a schematic diagram of the circuit structure of the first embodiment of the present invention.

圖5是本發明的第二實施例的多個分區的其中一個分區的示意圖。 FIG. 5 is a schematic diagram of one of the multiple partitions in the second embodiment of the present invention.

請參照圖1，圖1是本發明的第一實施例的顯示裝置的示意圖。顯示裝置100中具有排列為陣列的多個分區Z11~Z33，其中，分區Z11~Z31形成第一顯示行；分區Z12~Z32形成第二顯示行；分區Z13~Z33形成第三顯示行。在本實施例中，顯示裝置100的各分區Z11~Z33，分別耦接多條閘極線GL1~GLM以及多條資料傳輸線SL1~SLN，顯示裝置100並耦接多條控制線CL1~CL3。其中，控制線CL1~CL3分別與各分區的資料傳輸線SL1~SLN相鄰設置，控制線CL1~CL3分別對應不同的顯示行。在本實施例中，僅示意地以9個分區Z11~Z33為範例，在本發明其他實施例中，分區的數量並不以此為限，可任意調整。 Please refer to FIG. 1, which is a schematic diagram of a display device according to a first embodiment of the present invention. The display device 100 has a plurality of partitions Z11 to Z33 arranged in an array, wherein the partitions Z11 to Z31 form a first display line; the partitions Z12 to Z32 form a second display line; and the partitions Z13 to Z33 form a third display line. In this embodiment, each zone Z11~Z33 of the display device 100 is respectively coupled to a plurality of gate lines GL1~GLM and a plurality of data transmission lines SL1~SLN, and the display device 100 is also coupled to a plurality of control lines CL1~CL3. Among them, the control lines CL1 to CL3 are respectively arranged adjacent to the data transmission lines SL1 to SLN of each partition, and the control lines CL1 to CL3 respectively correspond to different display lines. In this embodiment, only nine partitions Z11 to Z33 are taken as an example. In other embodiments of the present invention, the number of partitions is not limited to this, and can be adjusted arbitrarily.

以下請同步參照圖1以及圖2，其中，圖2是本發明的第一實施例的多個分區的其中一個分區的示意圖。在本實施例中，以分區Z11為範例，分區Z11包括多個顯示畫素PX11~PXMN以及開關SW1。在細節上，顯示畫素PX11~PX1N透過閘極線GL1接至開關SW1的控制端，顯示畫素PX1N~PXMN透過走線CLP 耦接至開關SW1的第一端，開關SW1的第二端則耦接至控制線CL1。 Please refer to FIG. 1 and FIG. 2 simultaneously. FIG. 2 is a schematic diagram of one of the multiple partitions in the first embodiment of the present invention. In this embodiment, the zone Z11 is taken as an example. The zone Z11 includes a plurality of display pixels PX11~PXMN and a switch SW1. In detail, the display pixels PX11~PX1N are connected to the control terminal of the switch SW1 through the gate line GL1, and the display pixels PX1N~PXMN are routed through the CLP It is coupled to the first end of the switch SW1, and the second end of the switch SW1 is coupled to the control line CL1.

值得注意的，開關SW1的控制端耦接分區Z11的閘極線GL1，並依據閘極線GL1上的分區致能信號來控制開關SW1的導通或斷開，來將控制線CL1的分區控制信號導入分區Z11。 It is worth noting that the control terminal of the switch SW1 is coupled to the gate line GL1 of the zone Z11, and controls the switch SW1 to be turned on or off according to the zone enable signal on the gate line GL1 to control the zone control signal of the control line CL1 Import partition Z11.

在顯示畫素PX11~PXMN的架構方面，以顯示畫素PX1N為範利，顯示畫素PX1N包括電晶體T1、T2以及畫素電容CLC。電晶體T1的控制端耦接至開關SW1的第一端，電晶體T1的第一端耦接至電晶體T2的第二端，電晶體T2的控制端耦接至對應的閘極線GL1，電晶體T2的第一端耦接至對應的資料傳輸線SLN，畫素電容CLC串接在電晶體T1的第二端及參考接地端間。 In terms of the structure of the display pixels PX11~PXMN, the display pixel PX1N is used as a model, and the display pixel PX1N includes transistors T1, T2, and pixel capacitors CLC. The control terminal of the transistor T1 is coupled to the first terminal of the switch SW1, the first terminal of the transistor T1 is coupled to the second terminal of the transistor T2, and the control terminal of the transistor T2 is coupled to the corresponding gate line GL1, The first terminal of the transistor T2 is coupled to the corresponding data transmission line SLN, and the pixel capacitor CLC is connected in series between the second terminal of the transistor T1 and the reference ground terminal.

在動作細節上，當分區更新顯示畫面的動作進行時，以僅針對分區Z11進行顯示畫面更新為範例。分區Z11在資料更新模式下，對應分區Z11的閘極線GL1~GLM依據第一刷新頻率來執行閘極掃描動作，且對應分區Z11的資料料SL1~SLN同樣依據第一刷新頻率來執行資料傳輸動作，控制線CL1依據第一刷新頻率提供分區控制信號，並藉以第一刷新頻率執行分區Z11的顯示畫面刷新。在另一方面，分區Z11外的其他分區Z12~Z33工作在資料保持模式，並以相對低的第二刷新頻率執行其他分區Z12~Z33的顯示畫面刷新。在本發明實施例中，第一刷新頻率可以為60赫茲(Hz)，第二刷新頻率則可以為1Hz。 In terms of operation details, when the partition update display screen is performed, the display screen update only for the partition Z11 is taken as an example. In the data update mode of zone Z11, the gate lines GL1~GLM corresponding to zone Z11 perform gate scanning according to the first refresh frequency, and the data materials SL1~SLN corresponding to zone Z11 also perform data transmission according to the first refresh frequency In action, the control line CL1 provides a partition control signal according to the first refresh frequency, and performs the display screen refresh of the partition Z11 by the first refresh frequency. On the other hand, the other partitions Z12~Z33 outside the partition Z11 work in the data retention mode, and refresh the display screens of the other partitions Z12~Z33 at a relatively low second refresh frequency. In the embodiment of the present invention, the first refresh frequency may be 60 Hertz (Hz), and the second refresh frequency may be 1 Hz.

細節上來說明，當分區Z11在資料更新模式下時，開關 SW1可依據閘極線GL1上的分區致能信號以被導通或斷開。在當開關SW1依據閘極線GL1上的分區致能信號被導通時，控制線CL1上的分區控制信號可透過被導通的開關SW1傳送至顯示畫素PX11~PX1N，例如透過走線CLP傳送至顯示畫素PX1N中的電晶體T1的控制端，並透過控制電晶體T1的導通動作，以使顯示畫素PX11~PX1N執行資料刷新動作。在資料更新模式下，控制線CL1上的分區控制信號可依據相對高的第一刷新頻率進行顯示畫素PX11~PX1N的資料刷新動作。 In detail, when the partition Z11 is in the data update mode, switch SW1 can be turned on or off according to the partition enable signal on the gate line GL1. When the switch SW1 is turned on according to the partition enable signal on the gate line GL1, the partition control signal on the control line CL1 can be transmitted to the display pixels PX11~PX1N through the turned-on switch SW1, such as through the trace CLP. The control terminal of the transistor T1 in the display pixel PX1N controls the conduction of the transistor T1 so that the display pixels PX11~PX1N perform data refreshing actions. In the data update mode, the partition control signal on the control line CL1 can perform the data refresh action of the display pixels PX11~PX1N according to the relatively high first refresh frequency.

相對的，當分區Z11在資料保持模式下時，控制線CL1上的分區控制信號則依據相對低的第二刷新頻率進行動作，並在當開關SW1依據閘極線GL1上的分區致能信號被導通時，控制線CL1上的分區控制信號可透過被導通的開關SW1傳送至顯示畫素PX11~PX1N，例如透過走線CLP傳送至顯示畫素PX1N中的電晶體T1的控制端，並透過控制電晶體T1的導通動作，以使顯示畫素PX11~PX1N執行資料刷新動作。在資料保持模式下，控制線CL1上的分區控制信號可依據相對低的第二刷新頻率進行顯示畫素PX11~PX1N的資料刷新動作。 In contrast, when the zone Z11 is in the data retention mode, the zone control signal on the control line CL1 operates according to the relatively low second refresh frequency, and when the switch SW1 is activated according to the zone enable signal on the gate line GL1 When turned on, the partition control signal on the control line CL1 can be transmitted to the display pixels PX11~PX1N through the turned-on switch SW1, for example, through the wiring CLP to the control terminal of the transistor T1 in the display pixel PX1N, and through the control The turn-on action of the transistor T1 enables the display pixels PX11~PX1N to perform data refresh action. In the data retention mode, the partition control signal on the control line CL1 can perform the data refresh action of the display pixels PX11 to PX1N according to the relatively low second refresh frequency.

由上述的說明可以得知，藉由在各分區Z11~Z33內設置開關SW1，可使分區更新顯示畫面只針對其中的一個或多個分區，例如Z11，以第一刷新頻率進行顯示畫面刷新動作，針對其他的多個分區，例如Z12~Z33，以低於第一刷新頻率的第二刷新頻率進行顯示畫面刷新動作，以降低顯示裝置的消耗電力。 From the above description, it can be known that by setting the switch SW1 in each zone Z11~Z33, the zone update display screen can only be used for one or more zones, such as Z11, to perform the display screen refresh action at the first refresh frequency. For other multiple partitions, such as Z12~Z33, the display screen is refreshed at a second refresh frequency lower than the first refresh frequency to reduce the power consumption of the display device.

藉由分區Z11的開關SW1的設置，即使同行上的多個分區Z11、Z21、Z31共用一條控制線CL1，當分區Z11工作在資料維持模式時，藉由開關SW1受到對應於第二刷新頻率的閘極線GL1的控制，使分區Z11不受其他分區Z21或Z31以第一刷新頻率進行顯示畫面刷新動作的影響，仍是以第二刷新頻率進行各顯示畫素PX11~PXMN的資料刷新動作。即，藉由開關SW1的設置，可避免分區Z11與共用一條控制線CL1的其他分區Z21、Z31之間因刷新頻率不同所造成的交互影響。 With the setting of the switch SW1 of the zone Z11, even if multiple zones Z11, Z21, Z31 on the same line share a control line CL1, when the zone Z11 is working in the data maintenance mode, the switch SW1 receives the corresponding control line CL1. The gate line GL1 is controlled so that the partition Z11 is not affected by other partitions Z21 or Z31 performing the display screen refreshing operation at the first refresh frequency, and the data refreshing operation of each display pixel PX11~PXMN is still performed at the second refresh frequency. That is, by setting the switch SW1, the interaction between the partition Z11 and the other partitions Z21 and Z31 sharing the same control line CL1 due to the different refresh frequencies can be avoided.

本發明的顯示裝置100的開關SW1可以由電晶體TSW所建構，電晶體TSW的控制端耦接至閘極線GL1，並用以接收分區致能信號。電晶體TSW的第一端耦接至控制線CL1，電晶體TSW的第二端耦接至分區Z11內多個顯示畫素PX11~PXMN中的電晶體(例如電晶體T1)的控制端。電晶體TSW與電晶體T1、T2可以是相同型態的電晶體。因此，本發明的顯示裝置100的開關SW1，可以在顯示裝置的矩陣(Array)基板製造過程中，與矩陣基板同時製作完成，不需額外的製程成本或材料消耗。 The switch SW1 of the display device 100 of the present invention may be constructed by a transistor TSW, and the control terminal of the transistor TSW is coupled to the gate line GL1 and used to receive the partition enable signal. The first end of the transistor TSW is coupled to the control line CL1, and the second end of the transistor TSW is coupled to the control end of the transistors (such as the transistor T1) in the plurality of display pixels PX11 to PXMN in the zone Z11. The transistor TSW and the transistors T1 and T2 can be the same type of transistors. Therefore, the switch SW1 of the display device 100 of the present invention can be manufactured at the same time as the matrix substrate during the manufacturing process of the array substrate of the display device, without additional process cost or material consumption.

本發明的顯示裝置100，當各分區Z11~Z33中的一個分區Z11工作在資料更新模式時，分區Z11工作在第一刷新頻率(例如60Hz)，且對應於第一刷新頻率的開關SW1被導通或斷開。當各分區Z11~Z33中的其它分區Z12~Z33工作在資料保持模式時，各分區Z12~Z33工作在第二刷新頻率(例如1Hz)。因為第一刷新頻率大於第二刷新頻率，所以只有部分的分區(例如分區 Z11)，使用第一刷新頻率進行顯示畫面刷新動作。而其他的分區Z12~Z33，以較低第二刷新頻率進行顯示畫面刷新動作而進入節能的耗電狀態，因此能夠降低耗電。 In the display device 100 of the present invention, when one of the zones Z11 to Z33 is operating in the data update mode, the zone Z11 operates at the first refresh frequency (for example, 60 Hz), and the switch SW1 corresponding to the first refresh frequency is turned on Or disconnect. When the other partitions Z12 to Z33 among the partitions Z11 to Z33 work in the data retention mode, the partitions Z12 to Z33 work at the second refresh frequency (for example, 1 Hz). Because the first refresh frequency is greater than the second refresh frequency, only some partitions (such as partitions Z11), use the first refresh frequency to refresh the display screen. The other partitions Z12 to Z33 perform display screen refreshing operations at a lower second refresh frequency and enter an energy-saving power consumption state, so power consumption can be reduced.

圖2中，開關SW1的控制端耦接分區Z11的閘極線GL1，即分區致能信號由分區Z11的閘極線GL1提供，但是本發明並不以此為限。開關SW1的控制端可以耦接分區Z11的任何一條閘極線，也就是說，分區致能信號可由各分區Z11中的閘極線GL1~GLM之中的任何一條閘極線所提供。 In FIG. 2, the control terminal of the switch SW1 is coupled to the gate line GL1 of the zone Z11, that is, the zone enable signal is provided by the gate line GL1 of the zone Z11, but the present invention is not limited to this. The control terminal of the switch SW1 can be coupled to any gate line of the zone Z11, that is, the zone enable signal can be provided by any one of the gate lines GL1~GLM in each zone Z11.

圖3是用來說明本發明與先前技術的分區更新顯示畫面的顯示裝置在不同分區的漏電差異的示意圖。以下請同步參照圖2以及圖3，其中，顯示裝置100的各分區Z11~Z33中，只有分區Z22是以第一刷新頻率(例如60Hz)工作在資料更新模式，顯示區Z22以外的其他各分區(例如Z12、Z33)則是以第二刷新頻率(例如1Hz)工作在資料保持模式。在圖3中，分區Z22是在資料更新模式，分區Z22以第一刷新頻率(例如60Hz)進行顯示畫面刷新時，分區Z22中所連接的控制線CL2、各閘極線GL1~GLM與各資料傳輸線SL1~SLN，都是對應第一刷新頻率進行工作，即對分區Z22內各顯示畫素PX11~PXMN的各畫素電容CLC，以第一刷新頻率進行資料刷新。 FIG. 3 is a schematic diagram for explaining the difference in leakage between the present invention and the prior art display device for updating the display screen by partition in different partitions. Please refer to Fig. 2 and Fig. 3 simultaneously. Among the zones Z11 to Z33 of the display device 100, only zone Z22 operates in the data update mode at the first refresh frequency (for example, 60 Hz), and all zones other than the display zone Z22 (E.g. Z12, Z33) work in the data retention mode at the second refresh frequency (e.g. 1 Hz). In Figure 3, the zone Z22 is in the data update mode. When the zone Z22 refreshes the display screen at the first refresh frequency (for example, 60 Hz), the control line CL2, the gate lines GL1~GLM and the data connected in the zone Z22 The transmission lines SL1~SLN all work corresponding to the first refresh frequency, that is, the pixel capacitance CLC of each display pixel PX11~PXMN in the zone Z22 is refreshed at the first refresh frequency.

在圖3中，分區Z12是在資料保持模式，分區Z12以第二刷新頻率(例如1Hz)進行顯示畫面刷新時，分區Z12中所連接各閘極線GL1~GLM與各資料傳輸線SL1~SLN是對應第二刷 新頻率進行工作，但是控制線CL2因為與處於資料更新模式的分區Z22共用，所以控制線CL2是對應第一刷新頻率(例如60Hz)。雖然，分區Z12與分區Z22使用相同的控制線CL2，但是開關SW1的控制端是耦接在分區Z12的閘極線GL1，因此分區Z12的開關SW1亦是對應第二刷新頻率而被導通或斷開。所以，分區Z12藉由開關SW1隔開了分區Z22依據第一刷新頻率所執行的資料更新動作的影響。 In Figure 3, the zone Z12 is in the data retention mode. When the zone Z12 refreshes the display screen at the second refresh frequency (for example, 1Hz), the gate lines GL1~GLM and the data transmission lines SL1~SLN connected in the zone Z12 are Corresponding to the second brush The new frequency works, but because the control line CL2 is shared with the zone Z22 in the data update mode, the control line CL2 corresponds to the first refresh frequency (for example, 60 Hz). Although zone Z12 and zone Z22 use the same control line CL2, the control terminal of switch SW1 is coupled to the gate line GL1 of zone Z12, so switch SW1 of zone Z12 is also turned on or off corresponding to the second refresh frequency. open. Therefore, the partition Z12 is separated from the influence of the data update operation performed by the partition Z22 according to the first refresh frequency by the switch SW1.

如此一來，分區Z12與分區Z22及分區Z33上的顯示影像之間的光學表現上的差異可以被降低，也不會有畫面串擾等現象發生。因此，本發明的顯示裝置在進行分區更新顯示畫面時，仍可維持良好的顯示品質。 In this way, the difference in optical performance between the displayed images on the zone Z12, the zone Z22 and the zone Z33 can be reduced, and there will be no picture crosstalk and other phenomena. Therefore, the display device of the present invention can still maintain good display quality when the display screen is updated by partition.

另外，本實施例是例示各顯示畫素PX11~PXMN中包含2個電體體T1、T2，但是本發明不以此為限。即本發明也可適用於各顯示畫素PX11~PXMN中包含2個以上的電晶體。 In addition, this embodiment illustrates that each display pixel PX11 to PXMN includes two electrical bodies T1 and T2, but the present invention is not limited to this. That is, the present invention can also be applied to each display pixel PX11 to PXMN including two or more transistors.

圖4是本發明的第一實施例的電路架構的示意圖。如圖4所示，本發明的分區更新顯示畫面的顯示裝置400具有多工器電路20、閘極驅動器30及源極驅動器40。多工器電路20的輸出端耦接各控制線CL1~CL3及各資料傳輸線SL1~SLN。當各分區Z11~Z33中的一個分區，例如分區Z11工作在資料更新模式時，對應的多工器電路20的輸出端的控制線CL1依據第一刷新頻率進行工作。當其他分區，例如Z12、Z13工作在資料保持模式時，對應的多工器電路20的輸出端的控制線CL2、CL3依據第二刷新頻 率進行工作。 FIG. 4 is a schematic diagram of the circuit structure of the first embodiment of the present invention. As shown in FIG. 4, the display device 400 for updating the display screen by partition of the present invention has a multiplexer circuit 20, a gate driver 30 and a source driver 40. The output end of the multiplexer circuit 20 is coupled to the control lines CL1 to CL3 and the data transmission lines SL1 to SLN. When one of the zones Z11 to Z33, for example, zone Z11 works in the data update mode, the control line CL1 of the output terminal of the corresponding multiplexer circuit 20 works according to the first refresh frequency. When other partitions, such as Z12 and Z13 work in data retention mode, the control lines CL2 and CL3 of the output terminal of the corresponding multiplexer circuit 20 are based on the second refresh frequency. Rate to work.

另外，上述的實施例是以一個多工器電路20為範例，不過，多工器電路20可對應分區的數量任意調整，或是將多工器電路20併入多個源極驅動器40中而不獨立設置。 In addition, the above-mentioned embodiment takes one multiplexer circuit 20 as an example. However, the multiplexer circuit 20 can be adjusted arbitrarily corresponding to the number of partitions, or the multiplexer circuit 20 can be incorporated into a plurality of source drivers 40. Not set independently.

在另一方面，閘極驅動器30的輸出端分別耦接各閘極線GL1~GLM，且當分區Z11工作在資料更新模式時，對應分區Z11的閘極驅動器30的輸出端工作在第一刷新頻率，當其他分區，例如分區Z21、分區Z31工作在資料保持模式時，對應分區Z21、分區Z31的閘極驅動器30的輸出端工作在第二刷新頻率。 On the other hand, the output terminal of the gate driver 30 is respectively coupled to the gate lines GL1~GLM, and when the zone Z11 works in the data update mode, the output terminal of the gate driver 30 corresponding to the zone Z11 works in the first refresh mode. Frequency. When other zones, such as zone Z21 and zone Z31 work in the data retention mode, the output terminal of the gate driver 30 corresponding to zone Z21 and zone Z31 works at the second refresh frequency.

此外，源極驅動器40的輸出端分別耦接至各資料傳輸線SL1~SLN，且當各分區Z11工作在資料更新模式時，對應分區Z11的源極驅動器40的輸出端工作在第一刷新頻率，當其他分區，例如分區Z12、分區Z13分區工作在資料保持模式時，對應分區Z12、分區Z13的源極驅動器40的輸出端工作在第二刷新頻率。 In addition, the output terminal of the source driver 40 is respectively coupled to each data transmission line SL1~SLN, and when each zone Z11 works in the data update mode, the output terminal of the source driver 40 corresponding to the zone Z11 works at the first refresh frequency, When other zones, such as zone Z12 and zone Z13, work in the data retention mode, the output terminals of the source driver 40 corresponding to zone Z12 and zone Z13 work at the second refresh frequency.

上述的第二刷新頻率是資料保持模式中所使用的頻率，實施例是以使用1Hz進行資料保持為範例。不過，只要是第二刷新頻率小於第一刷新頻率即可。例如，若各顯示畫素PX11~PXMN的電晶體T1或電晶體T2的斷開特性不佳而漏電較大，可考慮將資料保持模式中使用的頻率從1Hz提高至5Hz或更高，以確保分區更新顯示畫面的顯示品質。 The above-mentioned second refresh frequency is the frequency used in the data retention mode, and the embodiment uses 1 Hz for data retention as an example. However, as long as the second refresh frequency is lower than the first refresh frequency. For example, if the transistor T1 or transistor T2 of each display pixel PX11~PXMN has poor disconnection characteristics and large leakage, consider increasing the frequency used in the data retention mode from 1Hz to 5Hz or higher to ensure Update the display quality of the display screen by partition.

圖5是本發明的第二實施例的多個分區Z11~Z33的其中 一個分區Z11的示意圖。與圖2的實施例不相同的是各分區Z11~Z33多設置了開關SW2。第二實施例中，對於與第一實施例相同的部分標註相同的參照編號並省略說明，對與第一實施例的不同點進行說明。 FIG. 5 is a diagram of a plurality of zones Z11 to Z33 in the second embodiment of the present invention Schematic diagram of a zone Z11. The difference from the embodiment in FIG. 2 is that each zone Z11 to Z33 is provided with a switch SW2. In the second embodiment, the same parts as those in the first embodiment are denoted by the same reference numerals and descriptions are omitted, and differences from the first embodiment will be described.

如圖5所示，本發明的第二實施例在各分區Z11~Z33中，分別設置二個開關，即開關SW1與開關SW2。開關SW1與開關SW2的第一端分別耦接分區Z11的控制線CL1，開關SW1與開關SW2的第二端分別耦接分區Z11內各顯示畫素PX11~PXMN的電晶體T1的控制端，開關SW1的控制端耦接分區Z11的閘極線GL1，開關SW2的控制端耦接分區Z11的閘極線GL2。 As shown in FIG. 5, in the second embodiment of the present invention, two switches are respectively provided in each zone Z11 to Z33, namely a switch SW1 and a switch SW2. The first ends of the switch SW1 and the switch SW2 are respectively coupled to the control line CL1 of the zone Z11, and the second ends of the switch SW1 and the switch SW2 are respectively coupled to the control end of the transistor T1 of the display pixels PX11~PXMN in the zone Z11. The switch The control terminal of SW1 is coupled to the gate line GL1 of zone Z11, and the control terminal of switch SW2 is coupled to the gate line GL2 of zone Z11.

因此，本發明的第二實施例中，藉由開關SW1與開關SW2的二個開關共同驅動分區Z11中的各顯示畫素PX11~PXMN的各電晶體T1的控制端。在分區Z11的閘極線GL1及閘極線GL2接續使開關SW1及開關SW2導通的情況下，分區Z11中的走線CLP及各顯示畫素PX11~PXMN的各電晶體T1的控制端，將可以有更長的時間可以充電或放電至控制線CL1的電壓準位。當各電晶體T1的控制端的電壓準位與控制線CL1的電壓準位相符時，可以確保各電晶體T1正常動作，能更有效完整更新畫素電容CLC的影像資料。 Therefore, in the second embodiment of the present invention, the two switches of the switch SW1 and the switch SW2 jointly drive the control terminals of the transistors T1 of the display pixels PX11 to PXMN in the partition Z11. When the gate line GL1 and gate line GL2 of zone Z11 are connected to make switch SW1 and switch SW2 conductive, the trace CLP in zone Z11 and the control terminal of each transistor T1 of each display pixel PX11~PXMN will There can be a longer time for charging or discharging to the voltage level of the control line CL1. When the voltage level of the control terminal of each transistor T1 matches the voltage level of the control line CL1, the normal operation of each transistor T1 can be ensured, and the image data of the pixel capacitor CLC can be updated more effectively and completely.

圖5中，開關SW1的控制端耦接分區Z11的第一閘極線GL1，開關SW2的控制端耦接分區Z11的第二閘極線GL2，但是本發明並不以此為限。開關SW1與開關SW2的控制端可分別耦 接分區Z11中的任何二條閘極線。 In FIG. 5, the control terminal of the switch SW1 is coupled to the first gate line GL1 of the zone Z11, and the control terminal of the switch SW2 is coupled to the second gate line GL2 of the zone Z11, but the invention is not limited to this. The control terminals of switch SW1 and switch SW2 can be coupled separately Connect to any two gate lines in zone Z11.

本發明的第二實施例中，藉由二個開關SW1、SW2來確保走線CLP及各電晶體T1的控制端的電壓準位，確保各電晶體T1正常動作，能更有效完整更新各畫素電容CLC的影像資料。但是本發明並不以此為限。即可藉由二個以上的開關來使分區Z11中的各顯示畫素PX11~PXMN的各電晶體T1的控制端的電壓準位，更接近控制線CL1的電壓準位。 In the second embodiment of the present invention, two switches SW1 and SW2 are used to ensure the voltage level of the wiring CLP and the control terminal of each transistor T1, to ensure the normal operation of each transistor T1, and to update each pixel more effectively and completely Image data of capacitor CLC. However, the present invention is not limited to this. That is, more than two switches can be used to make the voltage level of the control terminal of each transistor T1 of each display pixel PX11~PXMN in the zone Z11 closer to the voltage level of the control line CL1.

綜上所述，本發明的分區更新顯示畫面的顯示裝置藉由在各分區內增加設置一個開關，確保了各分區間不會有交互的影響。只要是在資料保持模式中的各分區，其內部各電晶體都是對應第二刷新頻率的狀態，各顯示畫素的畫素電容的漏電小。所以在資料保持模式中的各分區間，不會有光學表現上的差異，即不會有畫面串擾等現象發生。因此，本發明實施例的顯示裝置在進行分區更新顯示畫面時，仍可維持良好的顯示品質。 In summary, the display device for updating the display screen of the partitions of the present invention, by adding a switch in each partition, ensures that there will be no interactive influence between the partitions. As long as it is in each partition in the data retention mode, the internal transistors are in a state corresponding to the second refresh frequency, and the pixel capacitance of each display pixel has a small leakage current. Therefore, there will be no difference in optical performance between the partitions in the data retention mode, that is, no picture crosstalk will occur. Therefore, the display device of the embodiment of the present invention can still maintain a good display quality when the display screen is updated by partition.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

CL1‧‧‧控制線 CL1‧‧‧Control line

CLC‧‧‧畫素電容 CLC‧‧‧Pixel capacitor

CLP‧‧‧走線 CLP‧‧‧routing

GL1~GLM‧‧‧閘極線 GL1~GLM‧‧‧Gate line

PX11~PXMN‧‧‧顯示畫素 PX11~PXMN‧‧‧Display pixels

SL1~SLN‧‧‧資料傳輸線 SL1~SLN‧‧‧Data transmission line

SW1‧‧‧開關 SW1‧‧‧Switch

T1、T2、TSW‧‧‧電晶體 T1, T2, TSW‧‧‧Transistor

Z11‧‧‧分區 Z11‧‧‧Zone

Claims (10)

一種顯示裝置，包括：多個分區，對應多條閘極線，各該分區包括：多個顯示畫素；一控制線，用以傳輸一分區控制信號；以及一開關，耦接在多個顯示畫素與該控制線間，受控於該分區內閘極線的分區致能信號以被導通或斷開。 A display device includes: a plurality of partitions corresponding to a plurality of gate lines, each of the partitions includes: a plurality of display pixels; a control line for transmitting a partition control signal; and a switch coupled to the plurality of displays The pixel and the control line are controlled by the zone enable signal of the gate line in the zone to be turned on or off. 如申請專利範圍第1項所述的顯示裝置，其中各該分區中的該些顯示畫素排列成多個顯示行以及多個顯示列，該些顯示列分別耦接至多條閘極線，該些顯示行分別耦接多條資料傳輸線。 As for the display device described in claim 1, wherein the display pixels in each of the partitions are arranged into a plurality of display rows and a plurality of display columns, and the display columns are respectively coupled to a plurality of gate lines, the The display lines are respectively coupled to a plurality of data transmission lines. 如申請專利範圍第2項所述的顯示裝置，其中各該顯示畫素包括：一第一電晶體，其控制端耦接至該開關的第一端；一第二電晶體，具有第一端耦接至該資料傳輸線，該第一電晶體的第一端耦接至該第二電晶體的第二端，該第二電晶體的控制端耦接至對應的各該閘極線；以及一畫素電容，串接在該第一電晶體的第二端及參考接地端間。 The display device according to claim 2, wherein each of the display pixels includes: a first transistor whose control terminal is coupled to the first terminal of the switch; and a second transistor with a first terminal Coupled to the data transmission line, the first end of the first transistor is coupled to the second end of the second transistor, and the control end of the second transistor is coupled to each of the corresponding gate lines; and a The pixel capacitor is connected in series between the second terminal of the first transistor and the reference ground terminal. 如申請專利範圍第2項所述的顯示裝置，其中該分區致能信號由各該分區中的該些閘極線的其中之一所提供。 As for the display device described in item 2 of the scope of patent application, the partition enabling signal is provided by one of the gate lines in each partition. 如申請專利範圍第1項所述的顯示裝置，其中該開關為一電晶體，該電晶體的第二端耦接至該控制線，該電晶體的第一 端耦接至該第一電晶體的控制端，該電晶體的控制端接收該分區致能信號。 The display device according to claim 1, wherein the switch is a transistor, the second end of the transistor is coupled to the control line, and the first end of the transistor is The terminal is coupled to the control terminal of the first transistor, and the control terminal of the transistor receives the partition enabling signal. 如申請專利範圍第1項所述的顯示裝置，其中當各該分區工作在一資料更新模式時，對應的該開關被導通，且各該分區工作在一第一刷新頻率，當各該分區工作在一資料保持模式時，對應的該開關被斷開，且各該分區工作在一第二刷新頻率，其中該第一刷新頻率大於該第二刷新頻率。 For the display device described in item 1 of the scope of patent application, when each of the partitions works in a data update mode, the corresponding switch is turned on, and each of the partitions works at a first refresh frequency, and when each of the partitions works In a data retention mode, the corresponding switch is turned off, and each of the partitions operates at a second refresh frequency, wherein the first refresh frequency is greater than the second refresh frequency. 如申請專利範圍第6項所述的顯示裝置，更包括：多工器電路，該多工器電路耦接該控制線。 The display device described in item 6 of the scope of patent application further includes a multiplexer circuit, and the multiplexer circuit is coupled to the control line. 如申請專利範圍第7項所述的顯示裝置，其中當各該分區工作在該資料更新模式時，對應的該多工器電路的控制線依據該第一刷新頻率進行工作，其中當各該區工作在該資料保持模式時，對應的該的控制線依據該第二刷新頻率進行工作。 For the display device described in item 7 of the scope of patent application, when each of the partitions is operating in the data update mode, the corresponding control line of the multiplexer circuit operates according to the first refresh frequency, wherein when each of the partitions When working in the data retention mode, the corresponding control line works according to the second refresh frequency. 如申請專利範圍第6項所述的顯示裝置，其中該第一刷新頻率為60赫茲，該第二刷新頻率為1赫茲。 According to the display device described in item 6 of the scope of patent application, the first refresh rate is 60 Hz, and the second refresh rate is 1 Hz. 如申請專利範圍第1項所述的顯示裝置，更包括：多個閘極驅動器，分別耦接該些閘極線，用以分別提供多個閘極驅動信號；以及多個源極驅動器，分別耦接至該些資料傳輸線，用以分別提供多個源極驅動信號。 For example, the display device described in claim 1 further includes: a plurality of gate drivers respectively coupled to the gate lines to provide a plurality of gate driving signals; and a plurality of source drivers, respectively It is coupled to the data transmission lines to provide a plurality of source driving signals respectively.
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