TWI440004B - Liquid crystal display device and method for driving the same - Google Patents
Liquid crystal display device and method for driving the same Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
- G09G3/342—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
- G09G2340/0435—Change or adaptation of the frame rate of the video stream
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Description
本發明係關於一種液晶顯示裝置，特別是有關一種能避免圖框率切換造成畫面閃爍之液晶顯示裝置及其驅動方法。The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device capable of avoiding frame flicker caused by frame rate switching and a driving method thereof.
無縫式動態刷新切換(Seamless Dynamic Refresh Rate Switching,SDRRS)技術為Intel公司所提出用於筆記型電腦之液晶顯示裝置之省電技術，當筆記型電腦之液晶顯示裝置處於待機狀態時，其圖框率(frame rate)可以從60赫茲(Hertz,Hz)切換至40 Hz，以達省電之目的。然而液晶顯示裝置切換至不同圖框率時，會造成液晶電容的充電時間不同，因此會造成畫面閃爍的問題。Seamless Dynamic Refresh Rate Switching (SDRRS) technology is a power saving technology proposed by Intel Corporation for a liquid crystal display device of a notebook computer. When the liquid crystal display device of the notebook computer is in a standby state, the figure is The frame rate can be switched from 60 Hz (Hertz, Hz) to 40 Hz for power saving purposes. However, when the liquid crystal display device is switched to a different frame rate, the charging time of the liquid crystal capacitor is different, which may cause a problem of flickering of the screen.
請參閱第1A圖，其係繪示習知液晶顯示裝置實施SDRRS技術時，60Hz之圖框率之控制訊號時序圖。液晶顯示裝置係由一時序控制器(Timing Controller,T-Con)來控制閘極驅動積體電路(gate driver integrated circuits)及源極驅動積體電路(source driver integrated circuits)，再由閘極驅動積體電路控制閘極線的導通，由源極驅動積體電路將資料寫入源極線。圖中N、N+1、N+2分別表示與第N條閘極線、第N+1條閘極線、第N+2條閘極線有關之控制訊號。準備訊號STH及寫入訊號LP係由時序控制器傳送至源極驅動積體電路，閘極控制訊號OE係由時序控制器傳送至閘極驅動積體電路。準備訊號STH為高準位時表示時序控制器準備傳送資料至源極驅動積體電路。寫入訊號LP為高準位時表示時序控制器將資料傳送至源極驅動積體電路，寫入訊號LP為低準位時表示源極驅動積體電路將資料寫入源極線。閘極控制訊號OE為高準位時不導通閘極線，防止相鄰兩條閘極線重疊導通時造成再寫入的問題，閘極控制訊號OE為低準位時導通閘極線。Please refer to FIG. 1A , which is a timing diagram of a control signal of a frame rate of 60 Hz when the conventional liquid crystal display device implements the SDRRS technology. The liquid crystal display device controls a gate driver integrated circuit and a source driver integrated circuit by a Timing Controller (T-Con), and is driven by a gate. The integrated circuit controls the conduction of the gate line, and the source drives the integrated circuit to write the data to the source line. In the figure, N, N+1, and N+2 respectively represent control signals related to the Nth gate line, the N+1th gate line, and the N+2th gate line. The preparation signal STH and the write signal LP are transmitted from the timing controller to the source drive integrated circuit, and the gate control signal OE is transmitted from the timing controller to the gate drive integrated circuit. When the preparation signal STH is at the high level, it indicates that the timing controller is ready to transmit data to the source drive integrated circuit. When the write signal LP is at the high level, the timing controller transmits the data to the source drive integrated circuit, and when the write signal LP is at the low level, the source drive integrated circuit writes the data to the source line. When the gate control signal OE is at a high level, the gate line is not turned on, and the problem of rewriting is prevented when the adjacent two gate lines are overlapped and turned on. When the gate control signal OE is at a low level, the gate line is turned on.
首先，當時序控制器傳送高凖位之準備訊號STH至源極驅動積體電路時，表示通知源極驅動積體電路準備將與第N條閘極線電性耦接之源極線之資料傳送至源極驅動積體電路，接著當寫入訊號LP為高準位時，時序控制器將與第N條閘極線電性耦接之源極線之資料傳送至源極驅動積體電路，而時序控制器同時傳送高準位之閘極控制訊號OE至閘極驅動積體電路，防止再寫入的問題。資料傳送完畢後，時序控制器傳送低準位之閘極控制訊號OE至閘極驅動積體電路以導通第N條閘極線，同時傳送低準位之寫入訊號LP至源極驅動積體電路，源極驅動積體電路將資料寫入與第N條閘極線電性耦接之源極線並開始充電以保持資料，也就是說，第N條閘極線之充電時間為閘極控制訊號OE為低準位之期間，以T1表示。First, when the timing controller transmits the high-level preparation signal STH to the source driving integrated circuit, it indicates that the source driving integrated circuit prepares to prepare the source line electrically coupled to the Nth gate line. The data is transmitted to the source driving integrated circuit, and then when the write signal LP is at the high level, the timing controller transmits the data of the source line electrically coupled to the Nth gate line to the source driving integrated circuit. The timing controller simultaneously transmits the high level gate control signal OE to the gate drive integrated circuit to prevent rewriting. After the data transfer is completed, the timing controller transmits the low level gate control signal OE to the gate drive integrated circuit to turn on the Nth gate line, and simultaneously transmits the low level write signal LP to the source drive integrated body. The circuit, the source driving integrated circuit writes the data into the source line electrically coupled to the Nth gate line and starts charging to maintain the data, that is, the charging time of the Nth gate line is the gate The period during which the control signal OE is at a low level is represented by T1.
當時序控制器再次傳送高準位之準備訊號STH至源極驅動積體電路時，表示通知源極驅動積體電路準備將與第N+1條閘極線電性耦接之源極線之資料傳送至源極驅動積體電路，接著當寫入訊號LP為高準位時，時序控制器將與第N+1條閘極線電性耦接之源極線之資料傳送至源極驅動積體電路，而時序控制器同時傳送高準位之閘極控制訊號OE至閘極驅動積體電路，防止再寫入的問題。資料傳送完畢後，時序控制器傳送低準位之閘極控制訊號OE至閘極驅動積體電路以導通第N+1條閘極線，同時傳送低準位之寫入訊號LP至源極驅動積體電路，源極驅動積體電路將資料寫入與第N+1條閘極線電性耦接之源極線並開始充電以保持資料，也就是說，第N+1條閘極線之充電時間為閘極控制訊號OE變成低準位之期間，同樣為T1。至於後續之控制時序依此類推，此不再贅述。When the timing controller transmits the high-level preparation signal STH to the source driving integrated circuit again, it indicates that the source driving integrated circuit is ready to electrically connect the source line with the (N+1)th gate line. The data is transmitted to the source driving integrated circuit, and then when the write signal LP is at the high level, the timing controller transmits the data of the source line electrically coupled to the (N+1)th gate line to the source driver. The integrated circuit simultaneously transmits the high-level gate control signal OE to the gate drive integrated circuit to prevent re-writing. After the data transfer is completed, the timing controller transmits the low level gate control signal OE to the gate drive integrated circuit to turn on the N+1th gate line, and simultaneously transmits the low level write signal LP to the source drive. In the integrated circuit, the source driving integrated circuit writes the data into the source line electrically coupled to the N+1th gate line and starts charging to maintain the data, that is, the N+1th gate line The charging time is the period during which the gate control signal OE becomes a low level, which is also T1. As for the subsequent control timing and so on, this will not be described again.
請參閱第1B圖，其係繪示習知液晶顯示裝置實施SDRRS技術時，40Hz之圖框率之控制訊號時序圖。準備訊號STH、寫入訊號LP及閘極控制訊號OE之控制時序與第1A圖相同。第1B圖與第1A圖之差異在於第1B圖之圖框率降低為40Hz，因此閘極控制訊號OE之週期增加，由於閘極控制訊號OE為高準位的期間不變，代表閘極控制訊號OE為低準位的期間增加，即代表40Hz之圖框率之充電時間增加，該40Hz之圖框率之充電時間以T2表示。由於40Hz圖框率之充電時間T2與60Hz圖框率之充電時間T1不同，圖框率切換時會造成畫面閃爍的問題。Please refer to FIG. 1B , which is a timing diagram of a control signal of a frame rate of 40 Hz when the conventional liquid crystal display device implements the SDRRS technology. The control timing of the preparation signal STH, the write signal LP, and the gate control signal OE is the same as that of FIG. 1A. The difference between FIG. 1B and FIG. 1A is that the frame rate of FIG. 1B is reduced to 40 Hz, so the period of the gate control signal OE is increased, and the gate control signal OE is high during the period of the high level, which represents the gate control. The signal OE is increased during the low level period, that is, the charging time representing the frame rate of 40 Hz is increased, and the charging time of the frame rate of 40 Hz is represented by T2. Since the charging time T2 of the 40 Hz frame rate is different from the charging time T1 of the 60 Hz frame rate, the frame rate may cause a flickering phenomenon.
現有解決方法是以60Hz圖框率之充電時間T1為基礎，藉由增加第1B圖中閘極控制訊號OE為高準位的期間來減少閘極控制訊號OE為低準位的期間，使得40Hz圖框率之充電時間T2縮短至T1，因此無論圖框率為60Hz或40Hz時，皆保持相同之充電時間(即T1)，避免圖框率切換時畫面閃爍的問題。The existing solution is based on the charging time T1 of the frame rate of 60 Hz, and reduces the period during which the gate control signal OE is at a low level by increasing the period of the gate control signal OE in the first FIG. The charging time T2 of the frame rate is shortened to T1, so the same charging time (ie, T1) is maintained regardless of the frame rate of 60 Hz or 40 Hz, and the problem of flickering of the screen when the frame rate is switched is avoided.
近來發展GIP(gate in panel)架構之液晶顯示裝置，其不採用上述外加的閘極驅動積體電路，而是將與閘極驅動積體電路中移位暫存功能等效之電路直接製作於一液晶面板上，因此可省下使用閘極驅動積體電路的成本，且該電路可於製作閘極線、源極線以及畫素的製程中完成，無需額外製程。然而在使用GIP架構之液晶顯示裝置中，若採用上述閘極控制訊號OE來作時序控制，該電路將會非常複雜以致於該液晶面板上空間不足以配置。Recently, a liquid crystal display device of a GIP (gate in panel) structure is developed. Instead of using the above-described external gate driving integrated circuit, a circuit equivalent to the shift temporary storage function in the gate driving integrated circuit is directly fabricated. On a liquid crystal panel, the cost of using the gate driving integrated circuit can be saved, and the circuit can be completed in the process of fabricating the gate line, the source line, and the pixel without an additional process. However, in the liquid crystal display device using the GIP architecture, if the gate control signal OE is used for timing control, the circuit will be so complicated that the space on the liquid crystal panel is insufficient for configuration.
本發明之一目的在於提供一種能避免圖框率切換造成畫面閃爍之液晶顯示裝置及其驅動方法。An object of the present invention is to provide a liquid crystal display device capable of avoiding flickering of a frame caused by frame rate switching and a driving method thereof.
為達到上述目的，根據本發明之一特點係提供一種液晶顯示裝置，其包括一液晶面板以及一驅動電路。該液晶面板包括複數條閘極線及複數條源極線彼此交錯排列。該驅動電路用以驅動該液晶面板顯示影像。該驅動電路包括一時序控制器、一偵測單元、一層級移位電路、一閘極驅動單元以及至少一源極驅動單元。該時序控制器接受一輸入圖框率並提供不同輸入圖框率之至少一閘極導通訊號以及一源極資料寫入訊號。該偵測單元偵測該輸入圖框率並選擇符合該輸入圖框率之該閘極導通訊號以及該源極資料寫入訊號。該層級移位電路接收符合該輸入圖框率之該閘極導通訊號。該閘極驅動單元設置於該液晶面板上，根據該閘極導通訊號來導通該液晶面板之該等閘極線。該源極驅動單元根據該源極資料寫入訊號將資料寫入各源極線。各閘線之充電時間為該閘極驅動單元根據該閘極導通訊號導通各閘極線且該源極驅動單元根據該源極資料寫入訊號將該資料寫入各源極線之期間，該時序控制器係調整該源極資料寫入訊號之工作週期(duty cycle)以使該充電時間於該輸入圖框率切換前及切換後相同。In order to achieve the above object, according to a feature of the present invention, a liquid crystal display device including a liquid crystal panel and a driving circuit is provided. The liquid crystal panel includes a plurality of gate lines and a plurality of source lines staggered with each other. The driving circuit is configured to drive the liquid crystal panel to display an image. The driving circuit comprises a timing controller, a detecting unit, a level shifting circuit, a gate driving unit and at least one source driving unit. The timing controller accepts an input frame rate and provides at least one gate conduction number and a source data write signal for different input frame rates. The detecting unit detects the input frame rate and selects the gate conduction communication number and the source data writing signal that meet the input frame rate. The level shifting circuit receives the gate conduction number corresponding to the input frame rate. The gate driving unit is disposed on the liquid crystal panel, and turns on the gate lines of the liquid crystal panel according to the gate conduction communication number. The source driving unit writes data to each source line according to the source data write signal. The charging time of each gate line is a period during which the gate driving unit turns on the gate lines according to the gate conduction communication number and the source driving unit writes the data to each source line according to the source data writing signal, The timing controller adjusts a duty cycle of the source data write signal to make the charging time the same before and after the input frame rate switching.
根據本發明之另一特點係提供一種液晶顯示裝置之驅動方法，該液晶顯示裝置包括一液晶面板以及一驅動電路，該液晶面板包括複數條閘極線及複數條源極線彼此交錯排列，該驅動電路包括一時序控制器、一偵測單元、一層級移位電路、一閘極驅動單元設置於該液晶面板上以及至少一源極驅動單元，該驅動方法包括：該時序控制器接受一輸入圖框率並提供不同圖框率之至少一閘極導通訊號以及一源極資料寫入訊號；該偵測單元偵測該輸入圖框率並選擇符合該輸入圖框率之該閘極導通訊號以及該源極資料寫入訊號；該層級移位電路接收符合該輸入圖框率之該閘極導通訊號；該閘極驅動單元根據該閘極導通訊號來導通該液晶面板之該等閘極線；以及該源極驅動單元根據該源極資料寫入訊號將資料寫入各源極線，其中各閘線之充電時間為該閘極導通訊號導通各閘極線且根據該源極資料寫入訊號將該資料寫入各源極線之期間，該時序控制器係調整該源極資料寫入訊號之工作週期(duty cycle)以使該充電時間於該輸入圖框率切換前及切換後相同。According to another feature of the present invention, a liquid crystal display device includes a liquid crystal panel and a driving circuit, and the liquid crystal panel includes a plurality of gate lines and a plurality of source lines staggered with each other. The driving circuit includes a timing controller, a detecting unit, a level shifting circuit, a gate driving unit disposed on the liquid crystal panel and at least one source driving unit, the driving method comprising: the timing controller accepting an input The frame rate provides at least one gate conduction number and a source data write signal at different frame rates; the detecting unit detects the input frame rate and selects the gate conduction number corresponding to the input frame rate And the source data writing signal; the level shifting circuit receives the gate conduction communication number corresponding to the input frame rate; the gate driving unit turns on the gate lines of the liquid crystal panel according to the gate conduction communication number And the source driving unit writes the data to each source line according to the source data writing signal, wherein the charging time of each gate line is the gate conduction number The timing controller adjusts a duty cycle of the source data write signal to enable the charging by the gate line and writing the data to each source line according to the source data write signal. The time is the same before and after the switching of the input frame rate.
本發明之液晶顯示裝置及其驅動方法藉由該偵測單元偵測輸入圖框率並選擇對應輸入圖框率之控制訊號，使得閘極線在不同輸入圖框率具有相同之充電時間，因此可避免圖畫面閃爍的問題。The liquid crystal display device and the driving method thereof of the present invention detect the input frame rate and select the control signal corresponding to the input frame rate, so that the gate lines have the same charging time at different input frame rates, It can avoid the problem of flickering of the picture.
以下結合附圖對本發明的技術方案進行詳細說明。The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.
請參閱第2圖，其係繪示根據本發明之液晶顯示裝置。該液晶顯示裝置包括一液晶面板10以及一驅動電路。該液晶面板10包括複數條閘極線G1-G2M以及複數條源極線S1-SN彼此交錯排列。該驅動電路包括一時序控制器200、一偵測單元202、一層級移位電路204、一閘極驅動單元206以及至少一源極驅動單元(以源極驅動單元208、210、212表示)。該驅動電路用以驅動該液晶面板10顯示影像。Please refer to FIG. 2, which shows a liquid crystal display device according to the present invention. The liquid crystal display device includes a liquid crystal panel 10 and a driving circuit. The liquid crystal panel 10 includes a plurality of gate lines G1-G2M and a plurality of source lines S1-SN staggered with each other. The driving circuit includes a timing controller 200, a detecting unit 202, a level shifting circuit 204, a gate driving unit 206, and at least one source driving unit (represented by the source driving units 208, 210, 212). The driving circuit is configured to drive the liquid crystal panel 10 to display an image.
本發明之液晶顯示裝置係採用GIP架構，故使用製作於該液晶面板10上之該閘極驅動單元206來代替習知外加之閘極驅動積體電路。於本實施例中，該閘極驅動單元206包括一第一移位暫存電路2060以及一第二移位暫存電路2062製作於該液晶面板10之兩側。該第一移位暫存電路2060控制奇數條閘極線G1、G3...G2M-1，該第二移位暫存電路2062控制偶數條閘極線G2、G4...G2M。由於採用GIP架構且分成兩側控制，因此所需之控制訊號至少包括閘極起始訊號STV1、STV2、閘極導通訊號CLK1、CLK2、CLK3、CLK4，稍後將解釋各訊號之功能。該層級移位電路204將對應之控制訊號傳送至該等移位暫存電路2060、2062，即該層級移位電路204將控制奇數條閘極線之閘極起始訊號STV1、閘極導通訊號CLK1、CLK3傳送至該移位暫存電路2060，該層級移位電路204將控制偶數條閘極線之閘極起始訊號STV2訊號、閘極導通訊號CLK2、CLK4傳送至該移位暫存電路2062。此外，該時序控制器200傳送源極資料寫入訊號TP至該等源極驅動單元206、208、210以控制資料的寫入。Since the liquid crystal display device of the present invention adopts the GIP architecture, the gate driving unit 206 fabricated on the liquid crystal panel 10 is used instead of the conventionally applied gate driving integrated circuit. In this embodiment, the gate driving unit 206 includes a first shift temporary storage circuit 2060 and a second shift temporary storage circuit 2062 formed on both sides of the liquid crystal panel 10. The first shift register circuit 2060 controls the odd-numbered gate lines G1, G3, ..., G2M-1, and the second shift register circuit 2062 controls the even-numbered gate lines G2, G4, ..., G2M. Since the GIP architecture is adopted and divided into two sides, the required control signals include at least the gate start signals STV1, STV2, the gate conduction signals CLK1, CLK2, CLK3, and CLK4, and the functions of the signals will be explained later. The level shifting circuit 204 transmits the corresponding control signal to the shift register circuits 2060, 2062, that is, the level shift circuit 204 controls the gate start signal STV1 of the odd gate lines and the gate conduction number. CLK1, CLK3 are transferred to the shift register circuit 2060, and the level shift circuit 204 transmits the gate start signal STV2 signal and the gate conduction signal number CLK2, CLK4 of the even gate line to the shift register circuit. 2062. In addition, the timing controller 200 transmits a source data write signal TP to the source drive units 206, 208, 210 to control the writing of data.
本發明之液晶顯示裝置未使用閘極驅動積體電路，因此其控制訊號與習知技術不同，請參閱第3A圖，其係繪示該液晶顯示裝置實施SDRRS技術時，60赫茲之圖框率之控制訊號時序圖。源極資料寫入訊號TP為高準位時表示時序控制器200將資料傳送至源極驅動積體電路208、210、212，TP訊號為低準位時表示源極驅動積體電路208、210、212將資料寫入源極線S1-SN。閘極起始訊號STV1、STV2係為致能(enable)訊號，當閘極起始訊號STV1從高準位變成低準位時，致能閘極導通訊號CLK1，當閘極起始訊號STV2從高準位變成低準位時，致能閘極導通訊號CLK2。閘極導通訊號CLK1-CLK4為高準位時分別表示導通閘極線G1-G4。The liquid crystal display device of the present invention does not use a gate driving integrated circuit, so the control signal is different from the prior art. Please refer to FIG. 3A, which shows the frame rate of the 60 Hz when the liquid crystal display device implements the SDRRS technology. Control signal timing diagram. When the source data write signal TP is at a high level, the timing controller 200 transmits the data to the source drive integrated circuits 208, 210, and 212. When the TP signal is at a low level, the source drive integrated circuits 208 and 210 are indicated. 212 writes the data to the source line S1-SN. The gate start signals STV1 and STV2 are enable signals. When the gate start signal STV1 changes from the high level to the low level, the gate conduction signal CLK1 is enabled, and when the gate start signal STV2 is from When the high level becomes low, the gate is connected to the communication number CLK2. When the gate conduction communication numbers CLK1-CLK4 are at a high level, the conduction gate lines G1-G4 are respectively indicated.
控制訊號之時序說明如下。閘極起始訊號STV1為高準位時，表示準備導通閘極線G1，閘極起始訊號STV1訊號從高準位變成低準位時致能閘極導通訊號CLK1為高準位，導通閘極線G1，閘極導通訊號CLK1為高準位時，源極資料寫入訊號TP經過液晶極性轉換(即閘極導通訊號CLK1為高準位後源極資料寫入訊號TP第一次高準位)以防止液晶於一固定電壓驅動過久後再次高準位時，即閘極導通訊號CLK1為高準位後源極資料寫入訊號TP第二次高準位時，該時序控制器200將源極線S1-SN之資料傳送至該等源極驅動單元206、208、210，當閘極導通訊號CLK1導通閘極線G1(即閘極導通訊號CLK1為高準位)且源極資料寫入訊號TP為低準位時，該等源極驅動單元206、208、210將源極線S1-SN之資料寫入源極線S1-SN。最後閘極導通訊號CLK1變成低準位後不導通閘極線G1。綜上可知，閘極導通訊號CLK1導通閘極線G1(即閘極導通訊號CLK1為高凖位)且根據源極資料寫入訊號TP將源極線S1-SN之資料寫入源極線S1-SN(即源極資料寫入訊號TP為低準位)之期間為閘極線G1之充電時間，以T3表示。The timing of the control signal is described below. When the gate start signal STV1 is at the high level, it indicates that the gate line G1 is ready to be turned on, and when the gate start signal STV1 is changed from the high level to the low level, the gate signal CLK1 is turned to the high level, and the gate is turned on. When the gate line G1 and the gate conduction signal number CLK1 are at the high level, the source data write signal TP is converted by the liquid crystal polarity (ie, the gate conduction signal number CLK1 is at the high level, and the source data is written to the signal TP for the first time. The timing controller 200 is configured to prevent the liquid crystal from being driven high again after a fixed voltage is applied for a long time, that is, when the gate conduction signal number CLK1 is at a high level and the source data is written to the second high level of the signal TP. The data of the source line S1-SN is transmitted to the source driving units 206, 208, 210, and the gate conduction signal CLK1 is turned on the gate line G1 (ie, the gate conduction communication number CLK1 is at a high level) and the source data is When the write signal TP is at a low level, the source driving units 206, 208, 210 write the data of the source line S1-SN to the source line S1-SN. After the gate conduction signal number CLK1 becomes the low level, the gate line G1 is not turned on. In summary, the gate conduction signal number CLK1 turns on the gate line G1 (ie, the gate conduction signal number CLK1 is a high clamp) and writes the source line S1-SN data to the source line S1 according to the source data write signal TP. The period of -SN (ie, the source data write signal TP is low level) is the charging time of the gate line G1, which is represented by T3.
上述閘極起始訊號STV1為高準位時，表示準備導通閘極線G1，閘極起始訊號STV1為高準位後延遲一段時間閘極起始訊號STV2為高準位，表示準備導通閘極線G2，後續之時序控制與上述相同，即閘極起始訊號STV2從高準位變成低準位時致能閘極導通訊號CLK2為高準位，導通閘極線G2，閘極導通訊號CLK2為高準位時，源極資料寫入訊號TP經過液晶極性轉換(即閘極導通訊號CLK2為高準位後源極資料寫入訊號TP第一次高準位)以防止液晶於固定電壓驅動過久後再次高準位時，即閘極導通訊號CLK2為高準位後源極資料寫入訊號TP第二次為高準位時，該時序控制器200將源極線S1-SN之資料傳送至該等源極驅動單元206、208、210，當閘極導通訊號CLK2導通閘極線G2(即閘極導通訊號CLK2為高凖位)且源極資料寫入訊號TP為低準位時，該等源極驅動單元206、208、210將源極線S1-SN之資料寫入源極線S1-SN。最後閘極導通訊號CLK2變成低準位後不導通閘極線G2。綜上可知，閘極導通訊號CLK2導通閘極線G2(即閘極導通訊號CLK2為高凖位)且根據源極資料寫入訊號TP將源極線S1-SN之資料寫入源極線S1-SN(即源極資料寫入訊號TP為低準位)之期間為閘極線G2之充電時間，同樣為T3。When the gate start signal STV1 is at a high level, it indicates that the gate line G1 is ready to be turned on, and the gate start signal STV1 is at a high level, and the gate start signal STV2 is delayed for a period of time, indicating that the gate is ready to be turned on. The pulse line G2, the subsequent timing control is the same as above, that is, when the gate start signal STV2 changes from the high level to the low level, the enable gate conduction signal number CLK2 is at a high level, the gate line G2 is turned on, and the gate conduction number is When CLK2 is at a high level, the source data write signal TP is converted by the liquid crystal polarity (ie, the gate conduction signal CLK2 is at a high level and the source data is written to the first high level of the signal TP) to prevent the liquid crystal from being fixed at a fixed voltage. When the driving is too high and then the high level is reached, that is, when the gate conduction signal CLK2 is at the high level and the source data writing signal TP is at the high level for the second time, the timing controller 200 sets the source line S1-SN. The data is transmitted to the source driving units 206, 208, 210. When the gate conduction signal number CLK2 is turned on the gate line G2 (ie, the gate conduction signal number CLK2 is a high clamp) and the source data write signal TP is at a low level. The source driving units 206, 208, 210 write the data of the source lines S1-SN to the source lines. S1-SN. After the gate conduction signal number CLK2 becomes the low level, the gate line G2 is not turned on. In summary, the gate conduction signal number CLK2 turns on the gate line G2 (ie, the gate conduction signal number CLK2 is a high clamp) and writes the source line S1-SN data to the source line S1 according to the source data write signal TP. The period of -SN (ie, the source data write signal TP is low level) is the charging time of the gate line G2, which is also T3.
接著導通閘極線G3之時序如下，閘極導通訊號CLK1訊號為高準位結束後換閘極導通訊號CLK3為高準位，導通閘極線G3，閘極導通訊號CLK3為高準位時，源極資料寫入訊號TP經過液晶極性轉換(即閘極導通訊號CLK3為高準位後源極資料寫入訊號TP第一次高準位)以防止液晶於固定電壓驅動過久後再次高準位時，即閘極導通訊號CLK3為高準位後源極資料寫入訊號TP第二次高準位時，該時序控制器200將源極線S1-SN之資料傳送至該等源極驅動單元206、208、210，當閘極導通訊號CLK3導通閘極線G3(即閘極導通訊號CLK3為高凖位)且源極資料寫入訊號TP為低準位時，該等源極驅動單元206、208、210將源極線S1-SN之資料寫入源極線S1-SN。最後閘極導通訊號CLK3變成低準位後不導通閘極線G3。綜上可知，閘極導通訊號CLK3導通閘極線G3(即閘極導通訊號CLK3為高凖位)且根據源極資料寫入訊號TP將源極線S1-SN之資料寫入源極線S1-SN(即源極資料寫入訊號TP為低準位)之期間為閘極線G3之充電時間，同樣為T3。Then, the timing of the gate line G3 is as follows: when the gate conduction signal CLK1 signal is at the high level, the gate conduction signal CLK3 is at a high level, the gate line G3 is turned on, and the gate conduction signal number CLK3 is at a high level. The source data write signal TP is subjected to liquid crystal polarity conversion (ie, the gate conduction signal CLK3 is at a high level, and the source data is written to the first high level of the signal TP) to prevent the liquid crystal from being driven again at a fixed voltage for a long time. When the bit is connected to the second high level of the source data write signal TP after the gate conduction signal number CLK3 is high level, the timing controller 200 transmits the data of the source line S1-SN to the source drivers. The cells 206, 208, 210, when the gate conduction signal number CLK3 is turned on the gate line G3 (ie, the gate conduction signal number CLK3 is a high clamp) and the source data write signal TP is at a low level, the source driving units 206, 208, 210 write the data of the source line S1-SN to the source line S1-SN. After the gate conduction signal number CLK3 becomes the low level, the gate line G3 is not turned on. In summary, the gate conduction signal number CLK3 turns on the gate line G3 (ie, the gate conduction signal number CLK3 is a high clamp) and writes the source line S1-SN data to the source line S1 according to the source data write signal TP. The period of -SN (ie, the source data write signal TP is low level) is the charging time of the gate line G3, which is also T3.
接著導通閘極線G4之時序如下，閘極導通訊號CLK2為高準位結束後換閘極導通訊號CLK4為高準位，導通閘極線G4，閘極導通訊號CLK4為高準位時，源極資料寫入訊號TP經過液晶極性轉換(即閘極導通訊號CLK4為高準位後源極資料寫入訊號TP第一次高準位)以防止液晶於固定電壓驅動過久後再次高準位時，即閘極導通訊號CLK4為高準位後源極資料寫入訊號TP第二次高準位時，該時序控制器200將源極線S1-SN之資料傳送至該等源極驅動單元206、208、210，當閘極導通訊號CLK4導通閘極線G4(即閘極導通訊號CLK4為高凖位)且源極資料寫入訊號TP為低準位時，該等源極驅動單元206、208、210將源極線S1-SN之資料寫入源極線S1-SN。最後閘極導通訊號CLK4變成低準位後不導通閘極線G4。綜上可知，閘極導通訊號CLK4導通閘極線G4(即閘極導通訊號CLK4為高凖位)且根據源極資料寫入訊號TP將源極線S1-SN之資料寫入源極線S1-SN(即源極資料寫入訊號TP為低準位)之期間為閘極線G4之充電時間，同樣為T3。Then, the timing of the gate line G4 is as follows. After the gate conduction signal number CLK2 is at the high level, the gate conduction signal number CLK4 is at a high level, the gate line G4 is turned on, and the gate conduction signal number CLK4 is at a high level. The polarity data write signal TP passes through the liquid crystal polarity conversion (ie, the gate conduction signal number CLK4 is at a high level and the source data write signal TP is first high level) to prevent the liquid crystal from being driven high again after a fixed voltage is applied for a long time. When the gate conduction signal number CLK4 is at a high level and the source data is written to the second high level of the signal TP, the timing controller 200 transmits the data of the source line S1-SN to the source driving units. 206, 208, 210, when the gate conduction communication number CLK4 turns on the gate line G4 (ie, the gate conduction communication number CLK4 is a high clamp) and the source data write signal TP is at a low level, the source driving unit 206 208, 210 write the data of the source line S1-SN to the source line S1-SN. After the gate conduction signal number CLK4 becomes the low level, the gate line G4 is not turned on. In summary, the gate conduction signal number CLK4 turns on the gate line G4 (ie, the gate conduction signal number CLK4 is a high clamp) and writes the source line S1-SN data to the source line S1 according to the source data write signal TP. The period of -SN (ie, the source data write signal TP is low level) is the charging time of the gate line G4, which is also T3.
第五至八條閘極線再依序由閘極導通訊號CLK1-CLK4依序導通，第九至十二條閘極線再依序由閘極導通訊號CLK1-CLK4依序導通，依此類推，此不再贅述。The fifth to eighth gate lines are sequentially turned on sequentially by the gate conduction communication number CLK1-CLK4, and the ninth to the twelveth gate lines are sequentially turned on sequentially by the gate conduction communication number CLK1-CLK4, and so on. This will not be repeated here.
請參閱第3B圖，其係繪示該液晶顯示裝置實施SDRRS技術時，40赫茲之圖框率之控制訊號時序圖。第3B圖之控制時序與第3A圖相同，兩者之差異在於第3B圖之圖框率降低為40Hz，因此源極資料寫入訊號TP之週期增加，由於源極資料寫入訊號TP為高準位的期間不變，代表源極資料寫入訊號TP為低準位的期間增加，而源極資料寫入訊號TP為低準位至閘極導通訊號CLK1變成低準位之期間為40Hz之圖框率之充電時間，如圖中T4之期間，因此充電時間T4與充電時間T3不同，圖框率切換時會造成畫面閃爍的問題。本發明之解決方法係將60Hz圖框率之充電時間T3為基礎，藉由增加第3B圖中源極資料寫入訊號TP之工作週期(duty cycle)，即增加源極資料寫入訊號TP為高準位的期間來減少源極資料寫入訊號TP為低準位的期間，圖中所示斜線區域即為增加高凖位的期間，並將源極資料寫入訊號TP為高準位及低準位的期間存入該時序控制器200，使得40Hz圖框率之充電時間T4縮短至T3，因此無論圖框率為60Hz或40 Hz時，皆保持相同之充電時間(即T3)，避免圖框率切換時畫面閃爍的問題。Please refer to FIG. 3B , which is a timing diagram of the control signal of the frame rate of 40 Hz when the liquid crystal display device implements the SDRRS technology. The control timing of FIG. 3B is the same as that of FIG. 3A. The difference between the two is that the frame rate of FIG. 3B is reduced to 40 Hz, so the period of the source data write signal TP is increased, because the source data write signal TP is high. The period of the level is unchanged, and the period during which the source data write signal TP is at the low level is increased, and the period during which the source data write signal TP is at the low level until the gate conduction signal CLK1 becomes the low level is 40 Hz. The charging time of the frame rate is as shown in the period of T4 in the figure. Therefore, the charging time T4 is different from the charging time T3, and the frame flickering may cause a problem of flickering of the screen. The solution of the present invention is based on the charging time T3 of the frame rate of 60 Hz. By increasing the duty cycle of the source data writing signal TP in FIG. 3B, the source data writing signal TP is increased. During the high-level period, the source data write signal TP is reduced to a low level. The hatched area shown in the figure is the period in which the high clamp is increased, and the source data is written to the signal TP at a high level. The low-level period is stored in the timing controller 200, so that the charging time T4 of the 40Hz frame rate is shortened to T3, so the same charging time (ie, T3) is maintained regardless of the frame rate of 60 Hz or 40 Hz. The problem of flickering when the frame rate is switched.
請再參閱第2圖，由於本發明採用GIP架構，因此該液晶顯示裝置必須包括該偵測單元202來偵測圖框率是否切換。於本實施例中，該偵測單元202係設置於該時序控制器200內。於另一實施例中，該偵測單元202可以獨立於該時序控制器200而設置。當一輸入圖框率A(60Hz或40Hz)被輸入至該時序控制器200時，該偵測單元202根據該輸入圖框率A選擇該時序控制器200所輸出符合該輸入圖框率A之閘極起始訊號STV1、STV2、閘極導通訊號CLK1、CLK2、CLK3、CLK4及源極資料寫入訊號TP，再將閘極起始訊號STV1、STV2、閘極導通訊號CLK1、CLK2、CLK3、CLK4及源極資料寫入訊號TP傳送至該層級移位電路204及該等源極驅動單元208、210、212，再由該層級移位電路204及該等源極驅動單元206、208、210根據上述第3A圖及第3B圖之時序圖控制液晶面板以顯示影像。Please refer to FIG. 2 again. Since the present invention adopts the GIP architecture, the liquid crystal display device must include the detecting unit 202 to detect whether the frame rate is switched. In this embodiment, the detecting unit 202 is disposed in the timing controller 200. In another embodiment, the detecting unit 202 can be set independently of the timing controller 200. When an input frame rate A (60 Hz or 40 Hz) is input to the timing controller 200, the detecting unit 202 selects, according to the input frame rate A, that the output of the timing controller 200 conforms to the input frame rate A. Gate start signals STV1, STV2, gate conduction communication numbers CLK1, CLK2, CLK3, CLK4 and source data write signals TP, and then gate start signals STV1, STV2, gate conduction signals CLK1, CLK2, CLK3, The CLK4 and source data write signals TP are transmitted to the level shifting circuit 204 and the source driving units 208, 210, 212, and the level shifting circuit 204 and the source driving units 206, 208, 210 The liquid crystal panel is controlled to display an image according to the timing charts of FIGS. 3A and 3B.
請參閱第4圖，其係繪示第2圖之該偵測單元202之一實施例及其偵測該輸入圖框率A之原理。該偵測單元202包括一比較器2020以及一多工器2022。該比較器2020比較該輸入圖框率A以及一參考圖框率B。該參考圖框率B係作為參考基準，其可以為60Hz或40Hz，本實施例以60Hz為例。該輸入圖框率A輸入至該時序控制器200後，該時序控制器200產生該輸入圖框率A以及該參考圖框率B(60Hz)至該比較器2020，若該輸入圖框率A為60Hz，則該比較器2020之一比較結果C為1，該多工器2022選擇符合60Hz圖框率之控制訊號至該層級移位電路204。若該輸入圖框率A切換為40Hz，則該比較器2020之一比較結果C為0，該多工器2022選擇符合40Hz圖框率之控制訊號至該層級移位電路204。Please refer to FIG. 4 , which illustrates an embodiment of the detecting unit 202 of FIG. 2 and the principle of detecting the input frame rate A. The detecting unit 202 includes a comparator 2020 and a multiplexer 2022. The comparator 2020 compares the input frame rate A with a reference frame rate B. The reference frame rate B is used as a reference reference, which may be 60 Hz or 40 Hz. In this embodiment, 60 Hz is taken as an example. After the input frame rate A is input to the timing controller 200, the timing controller 200 generates the input frame rate A and the reference frame rate B (60 Hz) to the comparator 2020, if the input frame rate A At 60 Hz, one of the comparators 2020 compares the result C to 1, and the multiplexer 2022 selects a control signal that conforms to the frame rate of 60 Hz to the level shifting circuit 204. If the input frame rate A is switched to 40 Hz, the comparison result C of the comparator 2020 is 0, and the multiplexer 2022 selects a control signal conforming to the 40 Hz frame rate to the level shifting circuit 204.
請參閱第5圖，其係繪示根據本發明之液晶顯示裝置之驅動方法流程圖。該液晶顯示裝置包括一液晶面板以及一驅動電路，該液晶面板包括複數條閘極線及複數條源極線彼此交錯排列，該驅動電路包括一時序控制器、一偵測單元、一層級移位電路、一閘極驅動單元設置於該液晶面板上以及至少一源極驅動單元，該驅動方法包括下列步驟。Please refer to FIG. 5, which is a flow chart showing a driving method of a liquid crystal display device according to the present invention. The liquid crystal display device includes a liquid crystal panel and a driving circuit. The liquid crystal panel includes a plurality of gate lines and a plurality of source lines staggered with each other. The driving circuit includes a timing controller, a detecting unit, and a level shifting The circuit and a gate driving unit are disposed on the liquid crystal panel and the at least one source driving unit, and the driving method comprises the following steps.
步驟S500中，該時序控制器接受一輸入圖框率並提供不同輸入圖框率之至少一閘極導通訊號以及一源極資料寫入訊號。又，該時序控制器進一步提供至少一閘極起始訊號，當該閘極起始訊號從高準位變成低準位時，致能該閘極導通訊號。In step S500, the timing controller accepts an input frame rate and provides at least one gate conduction communication number and a source data writing signal of different input frame rates. Moreover, the timing controller further provides at least one gate start signal, and when the gate start signal changes from a high level to a low level, the gate conduction number is enabled.
步驟S510中，該偵測單元偵測該輸入圖框率並選擇符合該輸入圖框率之該閘極導通訊號以及該源極資料寫入訊號。In step S510, the detecting unit detects the input frame rate and selects the gate conduction communication number and the source data writing signal that meet the input frame rate.
步驟S520中，該層級移位電路接收符合該輸入圖框率之該閘極導通訊號。In step S520, the hierarchical shift circuit receives the gate conduction communication number that meets the input frame rate.
步驟S530中，該移位暫存單元根據該閘極導通訊號來導通該液晶面板之該等閘極線。In step S530, the shift temporary storage unit turns on the gate lines of the liquid crystal panel according to the gate conduction communication number.
步驟S540中，該源極驅動單元根據該源極資料寫入訊號將資料寫入各源極線，其中各閘線之充電時間為該閘極導通訊號導通各閘極線且根據該源極資料寫入訊號將該資料寫入各源極線之期間，該時序控制器係調整該源極資料寫入訊號之工作週期(duty cycle)以使該充電時間於該輸入圖框率切換前及切換後相同。In step S540, the source driving unit writes data to each source line according to the source data writing signal, wherein the charging time of each gate line is that the gate conducting communication number turns on each gate line and according to the source data. When the write signal writes the data to each source line, the timing controller adjusts the duty cycle of the source data write signal to make the charging time before the switching of the input frame rate and switch After the same.
於一實施例中，該移位暫存單元包括一第一移位暫存電路以及第二移位暫存電路分別控制奇數條閘極線以及偶數條閘極線以使該等奇數條閘極線以及該等偶數條閘極線交替導通。該層級移位電路將對應該第一移位暫存電路之該等控制訊號傳送至該第一移位暫存電路，將對應該第二移位暫存電路之該等控制訊號傳送至該第二移位暫存電路。In one embodiment, the shift register unit includes a first shift register circuit and a second shift register circuit respectively controlling the odd gate lines and the even gate lines to make the odd gates The lines and the even number of gate lines are alternately turned on. The level shifting circuit transmits the control signals corresponding to the first shift register circuit to the first shift register circuit, and transmits the control signals corresponding to the second shift register circuit to the first Two shift temporary storage circuits.
該偵測單元包括一比較器以及一多工器，於步驟S510中包括：該比較器比較該輸入圖框率以及一參考圖框率；以及該多工器根據該比較器之一比較結果選擇對應該輸入圖框率之該等控制訊號。The detecting unit includes a comparator and a multiplexer. The step S510 includes: comparing, by the comparator, the input frame rate and a reference frame rate; and selecting, by the multiplexer, the comparison result according to one of the comparators These control signals should be entered for the frame rate.
綜上所述，雖然本發明已用較佳實施例揭露如上，然其並非用以限定本發明，本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。In view of the above, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the invention, and the present invention may be made without departing from the spirit and scope of the invention. Various modifications and refinements are made, and the scope of the present invention is defined by the scope of the appended claims.
10．．．液晶面板10. . . LCD panel
200．．．時序控制器200. . . Timing controller
202．．．偵測單元202. . . Detection unit
204．．．層級移位電路204. . . Hierarchical shift circuit
206．．．閘極驅動單元206. . . Gate drive unit
208、210、212．．．源極驅動單元208, 210, 212. . . Source drive unit
2020．．．比較器2020. . . Comparators
2022．．．多工器2022. . . Multiplexer
2060．．．第一移位暫存電路2060. . . First shift register circuit
2062．．．第二移位暫存電路2062. . . Second shift temporary storage circuit
A．．．輸入圖框率A. . . Input frame rate
B．．．參考圖框率B. . . Reference frame rate
C．．．比較結果C. . . Comparing results
CLK1、CLK2、CLK3、CLK4．．．閘極導通訊號CLK1, CLK2, CLK3, CLK4. . . Gate conduction number
G1-G2M．．．閘極線G1-G2M. . . Gate line
LP．．．寫入訊號LP. . . Write signal
OE．．．閘極控制訊號OE. . . Gate control signal
S1-SN．．．源極線S1-SN. . . Source line
S500-S540．．．步驟S500-S540. . . step
STH．．．準備訊號STH. . . Prepare the signal
STV1、STV2．．．閘極起始訊號STV1, STV2. . . Gate start signal
TP．．．源極資料寫入訊號TP. . . Source data write signal
第1A圖係繪示習知液晶顯示裝置實施SDRRS技術時，60Hz之圖框率之控制訊號時序圖；FIG. 1A is a timing diagram of a control signal of a frame rate of 60 Hz when the conventional liquid crystal display device implements the SDRRS technology;
第1B圖係繪示習知液晶顯示裝置實施SDRRS技術時，40Hz之圖框率之控制訊號時序圖；FIG. 1B is a timing diagram of a control signal of a frame rate of 40 Hz when the conventional liquid crystal display device implements the SDRRS technology;
第2圖係繪示根據本發明之液晶顯示裝置；Figure 2 is a view showing a liquid crystal display device according to the present invention;
第3A圖係繪示該液晶顯示裝置實施SDRRS技術時，60赫茲之圖框率之控制訊號時序圖；FIG. 3A is a timing chart showing the control signal of the frame rate of 60 Hz when the liquid crystal display device implements the SDRRS technology;
第3B圖係繪示該液晶顯示裝置實施SDRRS技術時，40赫茲之圖框率之控制訊號時序圖；FIG. 3B is a timing chart showing the control signal of the frame rate of 40 Hz when the liquid crystal display device implements the SDRRS technology;
第4圖係繪示第2圖之該偵測單元之一實施例及其偵測輸入圖框率之原理；以及Figure 4 is a diagram showing an embodiment of the detecting unit of Figure 2 and the principle of detecting the input frame rate;
第5圖係繪示根據本發明之液晶顯示裝置之驅動方法流程圖。Fig. 5 is a flow chart showing a driving method of a liquid crystal display device according to the present invention.
10．．．液晶面板10. . . LCD panel
200．．．時序控制器200. . . Timing controller
202．．．偵測單元202. . . Detection unit
204．．．層級移位電路204. . . Hierarchical shift circuit
206．．．閘極驅動單元206. . . Gate drive unit
208、210、212．．．源極驅動單元208, 210, 212. . . Source drive unit
2060．．．第一移位暫存電路2060. . . First shift register circuit
2062．．．第二移位暫存電路2062. . . Second shift temporary storage circuit
A．．．輸入圖框率A. . . Input frame rate
CLK1、CLK2、CLK3、CLK4．．．閘極導通訊號CLK1, CLK2, CLK3, CLK4. . . Gate conduction number
G1-G2M．．．閘極線G1-G2M. . . Gate line
S1-SN．．．源極線S1-SN. . . Source line
STV1、STV2．．．閘極起始訊號STV1, STV2. . . Gate start signal
TP．．．源極資料寫入訊號TP. . . Source data write signal
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| KR102533341B1 (en) * | 2016-11-11 | 2023-05-17 | 삼성디스플레이 주식회사 | Display device and method for driving the same |
| US11250752B2 (en) * | 2017-10-03 | 2022-02-15 | Intel Corporation | Display circuits |
| TWI695205B (en) * | 2018-08-10 | 2020-06-01 | 友達光電股份有限公司 | Image-sensing display device and image processing method |
| CN109188804B (en) * | 2018-09-03 | 2021-06-22 | Tcl华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display |
| US11087708B2 (en) * | 2019-06-05 | 2021-08-10 | Himax Technologies Limited | Method for transmitting data from timing controller to source driver and associated timing controller and display system |
| TWI709950B (en) * | 2019-08-23 | 2020-11-11 | 大陸商北京集創北方科技股份有限公司 | Display control signal processing circuit, source drive circuit and display device |
| CN112255595A (en) * | 2020-10-17 | 2021-01-22 | 中国电波传播研究所（中国电子科技集团公司第二十二研究所） | Sea clutter data preprocessing method based on simulated airborne measurement |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW491959B (en) * | 1998-05-07 | 2002-06-21 | Fron Tec Kk | Active matrix type liquid crystal display devices, and substrate for the same |
| US7002564B1 (en) * | 2001-03-06 | 2006-02-21 | Pixelworks, Inc. | Failsafe display of frame locked graphics |
| WO2008139656A1 (en) * | 2007-05-11 | 2008-11-20 | Sharp Kabushiki Kaisha | Liquid crystal display device |
| TW201035956A (en) * | 2009-03-27 | 2010-10-01 | Hannstar Display Corp | Liquid crystal display device having low power consumption and method thereof |
-
2011
- 2011-03-04 TW TW100107436A patent/TWI440004B/en not_active IP Right Cessation
- 2011-05-12 US US13/106,843 patent/US20120223927A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| TW201237839A (en) | 2012-09-16 |
| US20120223927A1 (en) | 2012-09-06 |
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