TWI697865B

TWI697865B - Electronic device with graphics processing computing resource configuration function and control method thereof

Info

Publication number: TWI697865B
Application number: TW108102796A
Authority: TW
Inventors: 林明凱
Original assignee: 神雲科技股份有限公司
Priority date: 2019-01-24
Filing date: 2019-01-24
Publication date: 2020-07-01
Also published as: TW202029120A

Abstract

An electronic device with graphics processing computing resource configuration function and a control method of an electronic device are provided. The electronic device includes a processor, a switching circuit, and an image processing circuit. The processor includes a first processing unit and a second processing unit. The switching circuit is coupled to the first processing unit and the second processing unit. The image processing circuit includes a first graphics processing circuit and a second graphics processing circuit which are respectively connected to the switching circuits. The processor and the image processing circuit are used to run the test program to generate test data. The processor controls the switching circuit according to the test data, which makes the first processing unit be electrically connected to the first graphics processing circuit and the second processing unit be electrically connected to the second graphics processing circuit or makes the first processing unit be electrically connected to the first graphics processing circuit and the second graphics processing circuit.

Description

具圖形處理運算資源配置功能之電子裝置與其控制方法Electronic device with graphics processing operation resource allocation function and its control method

本發明是有關於一種電子裝置與電子裝置的控制方法，且特別是具有圖形處理運算資源配置功能之電子裝置與其控制方法。 The present invention relates to an electronic device and a control method of the electronic device, and in particular to an electronic device with a graphics processing operation resource allocation function and a control method thereof.

電子裝置具有處理器與影像處理電路。一般而言，當處理器與影像處理電路之複數個圖形處理電路共同運作時，處理器分配給各個圖形處理電路的資源會決定整體影像處理的效能。因此，需要一種電子裝置與電子裝置的控制方法，改善處理器與複數圖形處理電路的運算資源配置方式，提升整體電子裝置的影像處理效能。 The electronic device has a processor and an image processing circuit. Generally speaking, when a processor and a plurality of graphics processing circuits of an image processing circuit work together, the resources allocated by the processor to each graphics processing circuit will determine the overall image processing performance. Therefore, there is a need for an electronic device and a control method of the electronic device, which can improve the computing resource allocation method of the processor and the complex graphics processing circuit, and enhance the image processing performance of the overall electronic device.

本發明實施例提供一種具有圖形處理運算資源配置功能之電子裝置，包含處理器、切換電路以及影像處理電路。處理器包含第一處理單元與第二處理單元。切換電路連接第一處理單元與第二處理單元。影像處理電路包含個別連接切換電路的第一圖形處理電路與第二圖形處理電路。處理器與影像處理電路用以運行測試程式以產生測試資料，且處理器用以依據測試資料控制切換電路，致使第一處理單元電性連接第一圖形處理電路且第二處理單元電性連接第二圖形處理電路，或致使第一處理單元電性連接第一圖形處理電路與第二圖形處理電路。 The embodiment of the present invention provides an electronic device with a graphics processing operation resource allocation function, including a processor, a switching circuit, and an image processing circuit. The processor includes a first processing unit and a second processing unit. The switching circuit connects the first processing unit and the second processing unit. The image processing circuit includes a first graphics processing circuit and a second graphics processing circuit separately connected to the switching circuit. The processor and the image processing circuit are used to run the test program to generate test data, and the processor is used to control the switching circuit according to the test data, so that the first processing unit is electrically connected to the first graphics processing circuit and the second processing unit is electrically connected to the second Graphics processing circuit, or cause the first processing order The element is electrically connected to the first graphics processing circuit and the second graphics processing circuit.

本發明實施例提供一種具有圖形處理運算資源配置功能之電子裝置的控制方法，包含：透過處理器以及影像處理電路運行測試程式以產生測試資料；以及依據測試資料，將處理器之第一處理單元電性連接影像處理電路之第一圖形處理電路且將處理器之第二處理單元電性連接影像處理電路之第二圖形處理電路，或將第一處理單元電性連接第一圖形處理電路與第二圖形處理電路。 An embodiment of the present invention provides a control method of an electronic device with a graphics processing operation resource allocation function, including: running a test program through a processor and an image processing circuit to generate test data; and according to the test data, the first processing unit of the processor The first graphics processing circuit of the image processing circuit is electrically connected, and the second processing unit of the processor is electrically connected to the second graphics processing circuit of the image processing circuit, or the first processing unit is electrically connected to the first graphics processing circuit and the first graphics processing circuit. 2. Graphics processing circuit.

綜上所述，本發明實施例所提供之具有圖形處理運算資源配置功能之電子裝置與電子裝置的控制方法可改善處理器與影像處理電路之複數圖形處理電路的運算資源配置方式，進而提升整體電子裝置的實際影像處理效能。再者，電子裝置之使用者可更彈性地搭配任意之擴充卡且不論擴充卡為何，電子裝置都能達到最佳之實際影像處理效能。 In summary, the electronic device and the control method of the electronic device with the graphics processing computing resource allocation function provided by the embodiments of the present invention can improve the computing resource allocation method of the complex graphics processing circuit of the processor and the image processing circuit, thereby improving the overall The actual image processing performance of the electronic device. Furthermore, the user of the electronic device can more flexibly match any expansion card and the electronic device can achieve the best actual image processing performance regardless of the expansion card.

100:電子裝置 100: electronic device

110:處理器 110: processor

111:第一處理單元 111: first processing unit

111A:連接埠 111A: Port

111B:連接埠 111B: Port

112:第二處理單元 112: second processing unit

112A:連接埠 112A: Port

112B:連接埠 112B: Port

120:切換電路 120: switching circuit

130:影像處理電路 130: image processing circuit

131:第一圖形處理電路 131: The first graphics processing circuit

132:第二圖形處理電路 132: The second graphics processing circuit

133:第三圖形處理電路 133: The third graphics processing circuit

140:擴充卡 140: Expansion card

301:步驟 301: Step

302:步驟 302: Step

[圖1A-1C]是依據本發明之一些實施例之具有圖形處理運算資源配置功能之電子裝置的示意圖。 [FIGS. 1A-1C] are schematic diagrams of electronic devices with graphics processing and computing resource allocation functions according to some embodiments of the present invention.

[圖2A-2C]是圖1A-1C之電子裝置之一實施態樣的示意圖。 [Fig. 2A-2C] is a schematic diagram of an implementation aspect of the electronic device of Fig. 1A-1C.

[圖3A-3C]是圖1A-1C之電子裝置之另一實施態樣的示意圖。 [FIGS. 3A-3C] are schematic diagrams of another embodiment of the electronic device of FIGS. 1A-1C.

[圖4]是依據本發明之一些實施例之具有圖形處理運算資源配置功能之電子裝置的控制方法的流程圖。 [FIG. 4] is a flowchart of a control method of an electronic device with graphics processing operation resource allocation function according to some embodiments of the present invention.

圖1A是依據本發明實施例之具有圖形處理運算資源配置功能之電子裝置100的示意圖。電子裝置100包含處理器110、切換電路120以及影像處理電路130。切換電路120連接在處理器110與影像處理電路130之間。其中，圖1A係以處理器110包含兩處理單元為例，處理器110包含第一處理單元111與第二處理單元112。並且，圖1A係以影像處理電路130包含兩圖形處理電路(例如Graphics Processing Unit，GPU)為例，影像處理電路130包含第一圖形處理電路131與第二圖形處理電路132。如圖1A所示，處理單元111、112連接切換電路120，且切換電路120連接圖形處理電路131、132。電子裝置100需要使用圖形處理電路131、132。在此情況下，由於處理器110包含處理單元111、112，因此處理器110需要判定如何配置處理單元111、112與圖形處理電路131、132。 Figure 1A is a graph processing computing resource allocation function according to an embodiment of the present invention Schematic diagram of the electronic device 100. The electronic device 100 includes a processor 110, a switching circuit 120 and an image processing circuit 130. The switching circuit 120 is connected between the processor 110 and the image processing circuit 130. In FIG. 1A, the processor 110 includes two processing units as an example, and the processor 110 includes a first processing unit 111 and a second processing unit 112. In addition, in FIG. 1A, the image processing circuit 130 includes two graphics processing circuits (such as Graphics Processing Unit, GPU) as an example. The image processing circuit 130 includes a first graphics processing circuit 131 and a second graphics processing circuit 132. As shown in FIG. 1A, the processing units 111 and 112 are connected to the switching circuit 120, and the switching circuit 120 is connected to the graphics processing circuits 131 and 132. The electronic device 100 needs to use graphics processing circuits 131 and 132. In this case, because the processor 110 includes processing units 111 and 112, the processor 110 needs to determine how to configure the processing units 111 and 112 and the graphics processing circuits 131 and 132.

在運作上，請合併參照圖4，在步驟301中，處理器110控制切換電路120操作於第一模式，以使處理單元111、112與圖形處理電路131、132進入如圖1B所示之第一連接模式，即第一處理單元111及第二處理單元112經由切換電路120分別連接第一圖形處理電路131及第二圖形處理電路132。在此情況下，處理器110與影像處理電路130在步驟301中共同運行測試程式，並且基於所述測試程式的運行產生第一測試資料。繼之，在步驟301中，處理器110控制切換電路120操作於第二模式，以使處理單元111、112與圖形處理電路131、132進入如圖1C所示之第二連接模式，即第一處理單元111經由切換電路120連接第一圖形處理電路131及第二圖形處理電路132，而第二處理單元112並未連接於任一圖形處理電路131、132。同樣地，基於第二連接模式，處理器110與影像處理電路130在步驟301中共同運行所述測試程式，並且基於所述測試程式的運行產生第二測試資料。 In operation, please refer to FIG. 4 together. In step 301, the processor 110 controls the switching circuit 120 to operate in the first mode, so that the processing units 111, 112 and the graphics processing circuits 131, 132 enter the first mode shown in FIG. 1B. A connection mode is that the first processing unit 111 and the second processing unit 112 are respectively connected to the first graphics processing circuit 131 and the second graphics processing circuit 132 via the switching circuit 120. In this case, the processor 110 and the image processing circuit 130 jointly run the test program in step 301, and generate first test data based on the running of the test program. Subsequently, in step 301, the processor 110 controls the switching circuit 120 to operate in the second mode, so that the processing units 111, 112 and the graphics processing circuits 131, 132 enter the second connection mode as shown in FIG. 1C, that is, the first connection mode. The processing unit 111 is connected to the first graphics processing circuit 131 and the second graphics processing circuit 132 via the switching circuit 120, and the second processing unit 112 is not connected to any graphics processing circuit 131, 132. Similarly, based on the second connection mode, the processor 110 and the image processing circuit 130 jointly run the test program in step 301, and generate based on the running of the test program The second test data.

進一步地，在步驟302中，處理器110先比較第一測試資料與第二測試資料。若處理器110判定第一測試資料相應於處理器110與影像處理電路130的實際影像處理效能優於第二測試資料相應於處理器110與影像處理電路130的實際影像處理效能，則處理器110在步驟302中控制切換電路120使處理單元111、112與圖形處理電路131、132進入對應第一測試資料的第一連接模式(如圖1B所示)；反之，若處理器110判定第二測試資料相應的實際影像處理效能優於第一測試資料相應的實際影像處理效能，則處理器110在步驟302中控制切換電路120使處理單元111、112與圖形處理電路131、132進入對應第二測試資料的第二連接模式(如圖1C所示)。 Further, in step 302, the processor 110 first compares the first test data with the second test data. If the processor 110 determines that the actual image processing performance of the first test data corresponding to the processor 110 and the image processing circuit 130 is better than the actual image processing performance of the second test data corresponding to the processor 110 and the image processing circuit 130, the processor 110 In step 302, the switching circuit 120 is controlled to make the processing units 111, 112 and the graphics processing circuits 131, 132 enter the first connection mode corresponding to the first test data (as shown in FIG. 1B); on the contrary, if the processor 110 determines the second test The actual image processing performance corresponding to the data is better than the actual image processing performance corresponding to the first test data. Then the processor 110 controls the switching circuit 120 in step 302 to make the processing units 111, 112 and the graphics processing circuits 131, 132 enter the corresponding second test The second connection mode of the data (as shown in Figure 1C).

基於上述實施例之內容，電子裝置100可自動地判斷處理器110之處理單元111、112與影像處理電路130之圖形處理電路131、132之間的最佳配置模式。具體而言，電子裝置100可依據需求運行各種測試程式，並且可透過處理器110依據各種測試程式所產生的測試資料控制切換電路120，自動地使處理器110之處理單元111、112與影像處理電路130之圖形處理電路131、132具有最佳的配置，藉以產生較佳的實際影像處理效能。 Based on the content of the above-mentioned embodiments, the electronic device 100 can automatically determine the optimal configuration mode between the processing units 111 and 112 of the processor 110 and the graphics processing circuits 131 and 132 of the image processing circuit 130. Specifically, the electronic device 100 can run various test programs according to requirements, and can control the switching circuit 120 through the processor 110 according to the test data generated by the various test programs, and automatically enable the processing units 111 and 112 of the processor 110 to perform image processing. The graphics processing circuits 131 and 132 of the circuit 130 have the best configuration to produce better actual image processing performance.

在一些實施例中，處理器110與影像處理電路130共同運行測試程式時，處理器110可控制切換電路120以使處理單元111、112與圖形處理電路131、132先進入如圖1C所示之第二連接模式，並且在第二連接模式的狀況下產生測試資料。繼之，處理器110再控制切換電路120以使處理單元111、112與圖形處理電路131、132先進入如圖1B所示之第一連接模式，並且在第一連接模式的狀況下產生測試資料。 In some embodiments, when the processor 110 and the image processing circuit 130 jointly run the test program, the processor 110 may control the switching circuit 120 so that the processing units 111, 112 and the graphics processing circuits 131, 132 enter the data shown in FIG. 1C first. The second connection mode, and the test data is generated in the second connection mode. Subsequently, the processor 110 controls the switching circuit 120 to The processing units 111, 112 and the graphics processing circuits 131, 132 first enter the first connection mode as shown in FIG. 1B, and generate test data in the first connection mode.

在一些實施例中，前述之測試程式包含第一連接模式與第二連接模式的切換順序，例如，第一連接模式係優先於第二連接模式。處理器110基於測試程式所包含的切換順序先控制切換電路120操作於第一模式，使處理單元111、112與圖形處理電路131、132進入如圖1B所示例的第一連接模式，處理器110與影像處理電路130再基於第一連接模式協同運行測試程式，並產生第一測試資料；在產生第一測試資料之後，處理器110再控制切換電路120切換至第二模式，使處理單元111、112與圖形處理電路131、132進入如圖1C所示例的第二連接模式，處理器110與影像處理電路130再基於第二連接模式協同運行測試程式，並產生第二測試資料。處理器110比較第一測試資料及第二測試資料，並基於比較結果判定如何配置處理單元111、112與圖形處理電路131-132。 In some embodiments, the aforementioned test program includes a sequence of switching between the first connection mode and the second connection mode. For example, the first connection mode has priority over the second connection mode. The processor 110 first controls the switching circuit 120 to operate in the first mode based on the switching sequence included in the test program, so that the processing units 111, 112 and the graphics processing circuits 131, 132 enter the first connection mode as shown in FIG. 1B. The processor 110 Cooperating with the image processing circuit 130 to run the test program based on the first connection mode and generate the first test data; after the first test data is generated, the processor 110 controls the switching circuit 120 to switch to the second mode, so that the processing units 111, 112 and the graphics processing circuits 131 and 132 enter the second connection mode as illustrated in FIG. 1C, and the processor 110 and the image processing circuit 130 cooperate to run the test program based on the second connection mode, and generate second test data. The processor 110 compares the first test data and the second test data, and determines how to configure the processing units 111 and 112 and the graphics processing circuits 131-132 based on the comparison result.

在一些實施例中，電子裝置100更可包含一記憶體單元，記憶體單元儲存有不同連接模式的切換順序之列表，處理器110與影像處理電路130在協同運行測試程式時，處理器110讀取記憶體單元，以取得儲存在記憶體單元中不同連接模式的切換順序，處理器110基於儲存在記憶體單元中不同連接模式的切換順序控制切換電路120，以該記憶體單元儲存有第一及第二連接模式兩種連接模式的切換順序為例，使處理單元111、112與圖形處理電路131、132依據儲存在記憶體單元中不同連接模式的切換順序分別進入第一連接模式及第二連接模式。例如，記憶體單元係儲存第二連接模式優先於第一連接模式，則處理器110先控制切換電路 120操作於第二模式，使處理單元111、112與圖形處理電路131、132進入如圖1C所示例的第二連接模式，藉以產生第二測試資料。同理，在產生第二測試資料之後，處理器110再控制切換電路120切換至第一模式，使處理單元111、112與圖形處理電路131、132進入如圖1B所示例的第一連接模式，藉以產生第一測試資料。處理器110再基於第一測試資料及第二測試資料判定如何配置處理單元111、112與圖形處理電路131-132。 In some embodiments, the electronic device 100 may further include a memory unit. The memory unit stores a list of switching sequences of different connection modes. When the processor 110 and the image processing circuit 130 cooperate to run the test program, the processor 110 reads The memory unit is taken to obtain the switching sequence of different connection modes stored in the memory unit, and the processor 110 controls the switching circuit 120 based on the switching sequence of the different connection modes stored in the memory unit, and the memory unit stores the first The switching sequence of the two connection modes and the second connection mode is taken as an example. The processing units 111, 112 and the graphics processing circuits 131, 132 enter the first connection mode and the second connection mode according to the switching sequence of the different connection modes stored in the memory unit. Connection mode. For example, if the memory unit stores the second connection mode in preference to the first connection mode, the processor 110 first controls the switching circuit 120 operates in the second mode, so that the processing units 111 and 112 and the graphics processing circuits 131 and 132 enter the second connection mode as illustrated in FIG. 1C, thereby generating second test data. In the same way, after generating the second test data, the processor 110 controls the switching circuit 120 to switch to the first mode, so that the processing units 111, 112 and the graphics processing circuits 131, 132 enter the first connection mode as illustrated in FIG. 1B. In order to generate the first test data. The processor 110 then determines how to configure the processing units 111 and 112 and the graphics processing circuits 131-132 based on the first test data and the second test data.

在另一些實施例中，各圖形處理電路131-132具有不同的預設影像處理效能，而前述之記憶體單元中預先儲存有多個預設之不同圖形處理電路的代碼及/或型號以及對應之預設影像處理效能。處理器110與影像處理電路130在協同運行測試程式時，處理器110可根據圖形處理電路131-132之代碼及/或型號讀取記憶體單元，並比對圖形處理電路131-132之代碼及/或型號以及預設之代碼及/或型號，以取得各圖形處理電路131-132的預設影像處理效能，處理器110再依據圖形處理電路131-132的預設影像處理效能判定應先控制切換電路120進入第一模式或第二模式，於此不再贅述。 In other embodiments, each graphics processing circuit 131-132 has different preset image processing performance, and the aforementioned memory unit prestores a plurality of preset codes and/or models of different graphics processing circuits and corresponding The default image processing performance. When the processor 110 and the image processing circuit 130 are running the test program in cooperation, the processor 110 can read the memory unit according to the code and/or model of the graphics processing circuit 131-132, and compare the code and the code of the graphics processing circuit 131-132. / Or the model and the preset code and/or model to obtain the preset image processing performance of each graphics processing circuit 131-132, and the processor 110 should control first according to the preset image processing performance of the graphics processing circuit 131-132 The switching circuit 120 enters the first mode or the second mode, which will not be repeated here.

在一些實施例中，切換電路120包含多個開關元件，藉此受控於處理器110以切換連接各處理單元111、112與影像處理電路130之各圖形處理電路131-132來呈現分別對應各種連接模式之各種連結關係，例如前述之第一連接模式及第二連接模式。在一些實施例中，切換電路120包含重定時器(re-timer)。在此狀況下，處理器110可控制重定時器以補償不同路徑所造成的資料延遲，進而取得更精確的實際影像處理效能。 In some embodiments, the switching circuit 120 includes a plurality of switching elements, thereby being controlled by the processor 110 to switch the graphics processing circuits 131-132 connecting the processing units 111, 112 and the image processing circuit 130 to display corresponding various Various connection relationships of connection modes, such as the aforementioned first connection mode and second connection mode. In some embodiments, the switching circuit 120 includes a re-timer. In this situation, the processor 110 can control the retimer to compensate for the data delay caused by different paths, so as to obtain more accurate actual image processing performance.

圖2A-2C及圖3A-3C是依據本發明之另一實施例之電子裝置100的示意圖。請合併參照圖2A-2C及圖3A-3C，圖2A-2C及圖3A-3C與圖1A-1C之差異在於，電子裝置100更包含擴充卡140，擴充卡140可為主機匯流排介面(Host Bus Adapter；HBA)卡或獨立磁碟冗餘陣列(Redundant Array of Independent Disks；RAID)卡。並且，影像處理電路130包含三個圖形處理電路131-133。其中，擴充卡140連接切換電路120，且切換電路120連接圖形處理電路131-133。基此，處理器110需要判定如何配置處理單元111、112與圖形處理電路131-133之間之連接，以根據不同之擴充卡140而連動調整處理單元111、112與圖形處理電路131-133之間之連接。並且，根據不同之擴充卡140，處理器110能配置處理單元111、112為滿載或未滿載之不同連接組合。 2A-2C and 3A-3C are electronic devices according to another embodiment of the present invention Schematic diagram of set 100. Please refer to FIGS. 2A-2C and 3A-3C together. The difference between FIGS. 2A-2C and 3A-3C and FIGS. 1A-1C is that the electronic device 100 further includes an expansion card 140, which can be a host bus interface ( Host Bus Adapter; HBA) card or Redundant Array of Independent Disks (RAID) card. In addition, the image processing circuit 130 includes three graphics processing circuits 131-133. The expansion card 140 is connected to the switching circuit 120, and the switching circuit 120 is connected to the graphics processing circuits 131-133. Based on this, the processor 110 needs to determine how to configure the connection between the processing units 111, 112 and the graphics processing circuits 131-133, so as to adjust the processing units 111, 112 and the graphics processing circuits 131-133 according to different expansion cards 140. Between the connection. Furthermore, according to different expansion cards 140, the processor 110 can configure the processing units 111 and 112 to be fully loaded or under-loaded with different connection combinations.

詳細而言，如圖2A-2C及圖3A-3C所示，處理器110的第一處理單元111具有兩連接埠111A、111B，處理器110的第二處理單元112具有兩連接埠112A、112B，擴充卡140與影像處理電路130係共用處理器110的連接埠111A、111B、112A、112B，也就是處理器110的連接埠111A、111B、112A、112B可連接於圖形處理電路131-133及擴充卡140中之任一者。其中，處理器110配置滿載之連接係表示處理器110的全部連接埠111A、111B、112A、112B均分別連接於圖形處理電路131-133及擴充卡140中之任一者；再者，處理器110配置為非滿載之連接係表示處理器110之四個連接埠111A、111B、112A、112B中之至少一者未連接於圖形處理電路131-133及擴充卡140中之任一者。處理器110能控制切換電路120之組態來配置各處理單元111、112與圖形處理電路131-133之間形成滿載之連接或未滿載之連接。並且，處理器110能基於滿載或未滿載之連接改變切換電路120之組態而形成處理單元111、112與圖形處理電路131-133之間分別對應各種連接模式之滿載或未滿載之多種連接組合。 In detail, as shown in FIGS. 2A-2C and 3A-3C, the first processing unit 111 of the processor 110 has two ports 111A, 111B, and the second processing unit 112 of the processor 110 has two ports 112A, 112B The expansion card 140 and the image processing circuit 130 share the ports 111A, 111B, 112A, and 112B of the processor 110. That is, the ports 111A, 111B, 112A, and 112B of the processor 110 can be connected to the graphics processing circuits 131-133 and Any one of expansion cards 140. Wherein, the fully loaded connection of the processor 110 means that all the ports 111A, 111B, 112A, and 112B of the processor 110 are respectively connected to any one of the graphics processing circuits 131-133 and the expansion card 140; further, the processor The configuration of 110 as a non-full connection means that at least one of the four ports 111A, 111B, 112A, and 112B of the processor 110 is not connected to any one of the graphics processing circuits 131-133 and the expansion card 140. The processor 110 can control the configuration of the switching circuit 120 to configure each processing unit 111, 112 and the graphics processing circuits 131-133 to form a fully loaded connection or an underloaded connection. Furthermore, the processor 110 can be based on the The connection changes the configuration of the switching circuit 120 to form multiple connection combinations between the processing units 111, 112 and the graphics processing circuits 131-133 corresponding to various connection modes, which are fully loaded or not fully loaded.

舉例來說，以處理器110之其中一第一處理單元111係經由切換電路120固定連接於擴充卡140為例，如圖2A所示，第一處理單元111之其中一連接埠111A係經由切換電路120固定連接於擴充卡140，且第一處理單元111之另一連接埠111B係經由切換電路120連接於第一圖形處理電路131，第二處理單元112之兩連接埠112A、112B則經由切換電路120分別連接於圖形處理電路132、133，也就是處理器110之全部連接埠111A、111B、112A、112B均分別連接於圖形處理電路131-133及擴充卡140中之任一者，前述之連接形成滿載之第一連接模式；接著，以前述之第一處理單元111之其中一連接埠111A經由切換電路120固定連接於擴充卡140為例，處理器110基於滿載之連接改變切換電路120之組態，如圖2B所示，致使第一處理單元111之連接埠111B變更為經由切換電路120連接於第二圖形處理電路132，第二處理單元112之連接埠112A、112B則變更為經由切換電路120連接於圖形處理電路131、133；於是，處理器110之全部連接埠111A、111B、112A、112B均分別連接於圖形處理電路131-133及擴充卡140中之任一者，前述之連接形成滿載之第二連接模式；同理，以前述之第一處理單元111之其中一連接埠111A經由切換電路120固定連接於擴充卡140為例，處理器110再基於滿載之連接改變切換電路120之組態，如圖2C所示，致使第一處理單元111之連接埠111B變更為經由切換電路120連接於第三圖形處理電路133，第二處理單元112之連接埠112A、112B則變更為經由切換電路120連接於圖形處理電路131、132；於是，處理器110的全部連接埠111A、111B、112A、112B均分別連接於圖形處理電路131-133及擴充卡140中之任一者，前述之連接形成滿載之第三連接模式。 For example, taking one of the first processing units 111 of the processor 110 fixedly connected to the expansion card 140 via the switching circuit 120 as an example, as shown in FIG. 2A, one of the ports 111A of the first processing unit 111 is switched through The circuit 120 is fixedly connected to the expansion card 140, the other port 111B of the first processing unit 111 is connected to the first graphics processing circuit 131 through the switching circuit 120, and the two ports 112A and 112B of the second processing unit 112 are switched through The circuit 120 is respectively connected to the graphics processing circuits 132 and 133, that is, all the ports 111A, 111B, 112A, and 112B of the processor 110 are respectively connected to any one of the graphics processing circuits 131-133 and the expansion card 140. The aforementioned The connection forms a fully loaded first connection mode; then, taking one of the ports 111A of the aforementioned first processing unit 111 fixedly connected to the expansion card 140 via the switching circuit 120 as an example, the processor 110 changes the switching circuit 120 based on the fully loaded connection The configuration, as shown in FIG. 2B, causes the port 111B of the first processing unit 111 to be changed to be connected to the second graphics processing circuit 132 via the switching circuit 120, and the ports 112A and 112B of the second processing unit 112 are changed to be connected to the second graphics processing circuit 132 via the switching circuit. The circuit 120 is connected to the graphics processing circuits 131 and 133; therefore, all the ports 111A, 111B, 112A, and 112B of the processor 110 are respectively connected to any one of the graphics processing circuits 131-133 and the expansion card 140. The aforementioned connection A fully loaded second connection mode is formed; in the same way, one of the ports 111A of the aforementioned first processing unit 111 is fixedly connected to the expansion card 140 via the switching circuit 120 as an example, the processor 110 then changes the switching circuit 120 based on the fully loaded connection The configuration, as shown in Figure 2C, causes the port 111B of the first processing unit 111 to be changed to be connected to the third graphics processing circuit 133 via the switching circuit 120, and the ports 112A and 112B of the second processing unit 112 to be changed to via The switching circuit 120 is connected to the graphics processing circuits 131 and 132; All the ports 111A, 111B, 112A, and 112B of the processor 110 are respectively connected to any one of the graphics processing circuits 131-133 and the expansion card 140, and the aforementioned connection forms a fully loaded third connection mode.

進一步，在未滿載之情形中，以前述之第一處理單元111之連接埠111A係經由切換電路120固定連接於擴充卡140為例，如圖3A所示，第一處理單元111之連接埠111B並未經由切換電路120連接於影像處理電路130中之任一圖形處理電路131-133，而第二處理單元112之連接埠112A、112B經由切換電路120連接於圖形處理電路131、132；於是，處理器110之四個連接埠111A、111B、112A、112B之其中至少一者並未連接於圖形處理電路131、132及擴充卡140中之任一者，前述之連接形成未滿載之第一連接模式。接著，以前述之第一處理單元111之連接埠111A係經由切換電路120固定連接於擴充卡140為例，處理器110基於未滿載之連接改變切換電路120之組態，如圖3B所示，致使第一處理單元111之連接埠111B由未連接於影像處理電路130變更為經由切換電路120連接於第一圖形處理電路131，第二處理單元112之連接埠112A則變更為經由切換電路120連接於第二圖形處理電路132，第二處理單元112之連接埠112B則變更為未經由切換電路120連接於影像處理電路130；於是，處理器110之四個連接埠111A、111B、112A、112B之其中至少一者並未連接於圖形處理電路131、132及擴充卡140中之任一者，前述之連接形成未滿載之第二連接模式；同理，以前述之第一處理單元111之連接埠111A經由切換電路120固定連接於擴充卡140為例，處理器110再基於未滿載之連接改變切換電路120之組態，如圖3C所示，致使第一處理單元111之連接埠111B變更為經由切換電路120連接於第二圖形處理電路132，第二處理單元112之連接埠112A則變更為經由切換電路120連接於第一圖形處理電路131，第二處理單元112之連接埠112B則亦未經由切換電路120連接於影像處理電路130；於是，處理器110之四個連接埠111A、111B、112A、112B之其中至少一者並未連接於圖形處理電路131、132及擴充卡140中之任一者，前述之連接形成未滿載之第三連接模式。 Further, in the case of not being fully loaded, take the aforementioned connection port 111A of the first processing unit 111 fixedly connected to the expansion card 140 via the switching circuit 120 as an example, as shown in FIG. 3A, the connection port 111B of the first processing unit 111 It is not connected to any of the graphics processing circuits 131-133 in the image processing circuit 130 through the switching circuit 120, and the ports 112A and 112B of the second processing unit 112 are connected to the graphics processing circuits 131 and 132 through the switching circuit 120; therefore, At least one of the four connection ports 111A, 111B, 112A, 112B of the processor 110 is not connected to any of the graphics processing circuits 131, 132 and the expansion card 140, and the aforementioned connection forms the first connection that is not fully loaded mode. Next, taking the aforementioned connection port 111A of the first processing unit 111 fixedly connected to the expansion card 140 via the switching circuit 120 as an example, the processor 110 changes the configuration of the switching circuit 120 based on the under-loaded connection, as shown in FIG. 3B. As a result, the port 111B of the first processing unit 111 is changed from not being connected to the image processing circuit 130 to being connected to the first graphics processing circuit 131 via the switching circuit 120, and the port 112A of the second processing unit 112 is changed to being connected via the switching circuit 120 In the second graphics processing circuit 132, the port 112B of the second processing unit 112 is changed to not be connected to the image processing circuit 130 by the switch circuit 120; therefore, the four ports 111A, 111B, 112A, 112B of the processor 110 At least one of them is not connected to any of the graphics processing circuits 131, 132 and the expansion card 140, and the aforementioned connection forms a second connection mode that is not fully loaded; for the same reason, the aforementioned connection port of the first processing unit 111 111A is fixedly connected to the expansion card 140 via the switching circuit 120 as an example. The processor 110 then changes the configuration of the switching circuit 120 based on the under-loaded connection, as shown in FIG. 3C, causing the connection port 111B of the first processing unit 111 to change To connect to the second graphics processing circuit 132 via the switching circuit 120, the port 112A of the second processing unit 112 is changed to connect to the first graphics processing circuit 131 via the switching circuit 120, and the port 112B of the second processing unit 112 is also changed The switching circuit 120 is not connected to the image processing circuit 130; therefore, at least one of the four ports 111A, 111B, 112A, and 112B of the processor 110 is not connected to the graphics processing circuits 131, 132 and the expansion card 140 In either case, the aforementioned connection forms a third connection mode that is not fully loaded.

基此，處理器110依據滿載之第一連接模式、滿載之第二連接模式、滿載之第三連接模式、未滿載之第一連接模式、未滿載之第二連接模式及未滿載之第三連接模式與影像處理電路130協同運行測試程式而分別產生六筆測試資料。處理器110分別比較六筆測試資料並判定相應於最佳之實際影像處理效能之測試資料，以控制切換電路120切換至對應之組態。舉例來說，以滿載之第一連接模式、滿載之第二連接模式、滿載之第三連接模式、未滿載之第一連接模式、未滿載之第二連接模式及未滿載之第三連接模式分別對應於第一測試資料、第二測試資料、第三測試資料、第四測試資料、第五測試資料及第六測試資料為例，若處理器110判斷出第一測試資料相應的實際影像處理效能優於其他測試資料相應的實際影像處理效能，處理器110則控制切換電路120使處理單元111、112與圖形處理電路131-133進入對應第一測試資料的滿載之第一連接模式，如圖2A所示。其餘情況則依此類推，不再贅述。 Based on this, the processor 110 is based on the fully loaded first connection mode, the fully loaded second connection mode, the fully loaded third connection mode, the under-loaded first connection mode, the under-loaded second connection mode, and the under-loaded third connection The mode and the image processing circuit 130 cooperate to run the test program to generate six test data respectively. The processor 110 respectively compares the six test data and determines the test data corresponding to the best actual image processing performance to control the switching circuit 120 to switch to the corresponding configuration. For example, the first connection mode is fully loaded, the second connection mode is fully loaded, the third connection mode is fully loaded, the first connection mode is not fully loaded, the second connection mode is not fully loaded, and the third connection mode is not fully loaded. Corresponding to the first test data, the second test data, the third test data, the fourth test data, the fifth test data, and the sixth test data as examples, if the processor 110 determines the actual image processing performance corresponding to the first test data Better than the actual image processing performance corresponding to other test data, the processor 110 controls the switching circuit 120 to make the processing units 111, 112 and the graphics processing circuits 131-133 enter the first connection mode corresponding to the full load of the first test data, as shown in FIG. 2A Shown. The rest of the situation can be deduced by analogy and will not be repeated.

於是，由於擴充卡140係依電子裝置100的不同客戶的要求而有不同的客製化規格，也就是擴充卡140的運作效能會隨著客戶要求不同的客製化規格而不同，且也會因為客戶臨時改變要求而搭配具有不同運作效能的擴充卡140，電子裝置100之設計者並無法預知客戶是否會改變擴充卡140之運作效能而預先以較佳的連接模式配置連接處理器110與影像處理電路130，也無法確保以相同的連接模式來使電子裝置100搭配不同的擴充卡140後，仍能以原本的連接模式使所搭配的影像處理電路130具有較佳的實際影像處理效能，而根據本發明之電子裝置100之一些實施例，處理器110能依據實際的狀況(例如：電子裝置100實際搭配使用的擴充卡140與影像處理電路130)自動地配置處理器110與影像處理電路130之連接模式，電子裝置100之使用者可更彈性地搭配任意之擴充卡140且都能達到電子裝置100之最佳之實際影像處理效能，而無需修改或重新設計電子裝置100。 Therefore, since the expansion card 140 has different customized specifications according to the requirements of different customers of the electronic device 100, that is, the operating performance of the expansion card 140 will vary according to the different customized specifications required by the customers, and will also Because the customer temporarily changes the requirements, the collocation has a different operation As a high-performance expansion card 140, the designer of the electronic device 100 cannot predict whether the customer will change the operating performance of the expansion card 140 and configure the processor 110 and the image processing circuit 130 in a better connection mode in advance. After the electronic device 100 is matched with different expansion cards 140, the original connection mode can still make the matched image processing circuit 130 have better actual image processing performance, and some of the electronic device 100 according to the present invention In an embodiment, the processor 110 can automatically configure the connection mode of the processor 110 and the image processing circuit 130 according to actual conditions (for example, the expansion card 140 and the image processing circuit 130 actually used by the electronic device 100), and the use of the electronic device 100 It can be more flexibly matched with any expansion card 140 and can achieve the best actual image processing performance of the electronic device 100 without modifying or redesigning the electronic device 100.

在一些實施例中，處理器110與影像處理電路130共同運行測試程式時，處理器110可依據上述操作以任意次序產生第一、第二、第三、第四、第五、第六測試資料。 In some embodiments, when the processor 110 and the image processing circuit 130 run the test program together, the processor 110 can generate the first, second, third, fourth, fifth, and sixth test data in any order according to the above operations .

在一些實施例中，處理器110尚未判定執行特定影像處理工作需要使用的圖形處理電路131-133。在此狀況下，處理器110可控制切換電路120，使得處理單元111、112與圖形處理電路131-133之間的所有可能的連結方式皆可被建構以執行測試程式並產生測試資料。處理器110可依據所述測試資料選擇需要使用的圖形處理電路131-133的數量以及連結方式。舉例而言，處理器110在比較對應處理單元111、112與圖形處理電路131-133之間的各種連結方式所產生的測試資料後，判斷僅需要使用圖形處理電路131、132。在此狀況下，處理器110關閉第三圖形處理電路133，並且依據各測試資料的比較結果連結處理單元111、112與圖形處理電路131、132。例如，在圖3A至圖3C中，處理器110已關閉第三圖形處理電路133，處理器110僅連接於圖形處理電路131、132。 In some embodiments, the processor 110 has not yet determined the graphics processing circuits 131-133 that need to be used to perform specific image processing tasks. In this situation, the processor 110 can control the switching circuit 120 so that all possible connection modes between the processing units 111 and 112 and the graphics processing circuits 131-133 can be constructed to execute the test program and generate test data. The processor 110 can select the number of graphics processing circuits 131-133 to be used and the connection method according to the test data. For example, the processor 110 compares the test data generated by the various connection modes between the corresponding processing units 111 and 112 and the graphics processing circuits 131-133 and determines that only the graphics processing circuits 131 and 132 are required. In this situation, the processor 110 turns off the third graphics processing circuit 133, and connects the processing units 111 and 112 to the graphics processing circuit based on the comparison results of the test data. Circuits 131, 132. For example, in FIGS. 3A to 3C, the processor 110 has turned off the third graphics processing circuit 133, and the processor 110 is only connected to the graphics processing circuits 131 and 132.

綜上所述，本發明實施例所提供之電子裝置與電子裝置的控制方法可改善處理器與影像處理電路之複數圖形處理電路的運算資源配置方式，進而提升整體電子裝置的實際影像處理效能。再者，電子裝置之使用者可更彈性地搭配任意之擴充卡且不論擴充卡為何，電子裝置都能達到最佳之實際影像處理效能。 In summary, the electronic device and the control method of the electronic device provided by the embodiments of the present invention can improve the computing resource allocation method of the multiple graphics processing circuits of the processor and the image processing circuit, thereby enhancing the actual image processing performance of the overall electronic device. Furthermore, the user of the electronic device can more flexibly match any expansion card and the electronic device can achieve the best actual image processing performance regardless of the expansion card.

100:電子裝置 100: electronic device

110:處理器 110: processor

111:第一處理單元 111: first processing unit

112:第二處理單元 112: second processing unit

120:切換電路 120: switching circuit

130:影像處理電路 130: image processing circuit

131:第一圖形處理電路 131: The first graphics processing circuit

132:第二圖形處理電路 132: The second graphics processing circuit

Claims

一種具圖形處理運算資源配置功能之電子裝置，包含：一處理器，包含一第一處理單元與一第二處理單元；一切換電路，連接該第一處理單元與該第二處理單元；以及一影像處理電路，包含個別連接該切換電路的一第一圖形處理電路與一第二圖形處理電路；其中，該處理器與該影像處理電路用以運行一測試程式以產生一測試資料，且該處理器用以依據該測試資料控制該切換電路，致使該第一處理單元電性連接該第一圖形處理電路且該第二處理單元電性連接該第二圖形處理電路，或致使該第一處理單元電性連接該第一圖形處理電路與該第二圖形處理電路。 An electronic device with graphics processing and computing resource allocation function, including: A processor including a first processing unit and a second processing unit; A switching circuit connecting the first processing unit and the second processing unit; and An image processing circuit, including a first graphics processing circuit and a second graphics processing circuit connected to the switching circuit; Wherein, the processor and the image processing circuit are used to run a test program to generate a test data, and the processor is used to control the switching circuit according to the test data, so that the first processing unit is electrically connected to the first graphics processing The circuit and the second processing unit are electrically connected to the second graphics processing circuit, or the first processing unit is electrically connected to the first graphics processing circuit and the second graphics processing circuit.

如請求項1所述之電子裝置，其中該切換電路係操作於一第一模式或一第二模式，當該切換電路操作於該第一模式時，該第一處理單元經由該切換電路電性連接該第一圖形處理電路且該第二處理單元經由該切換電路電性連接該第二圖形處理電路而形成一第一連接模式，當該切換電路操作於該第二模式時，該第一處理單元經由該切換電路電性連接該第一圖形處理電路與該第二圖形處理電路而形成一第二連接模式；其中，該處理器與該影像處理電路係根據該第一連接模式及該第二連接模式運行該測試程式以產生包含一第一測試資料及一第二測試資料之該測試資料，該處理器比較該第一測試資料及該第二測試資料而產生一比較結果以判斷該電子裝置之一影像處理效能，且該處理器根據該比較結果選擇性地控制該切換電路操作於該第一模式或該第二模式。 The electronic device according to claim 1, wherein the switching circuit is operated in a first mode or a second mode, and when the switching circuit is operated in the first mode, the first processing unit is electrically connected through the switching circuit The first graphics processing circuit is connected and the second processing unit is electrically connected to the second graphics processing circuit via the switching circuit to form a first connection mode. When the switching circuit operates in the second mode, the first processing The unit is electrically connected to the first graphics processing circuit and the second graphics processing circuit via the switching circuit to form a second connection mode; Wherein, the processor and the image processing circuit run the test program according to the first connection mode and the second connection mode to generate the test data including a first test data and a second test data, and the processor compares The first test data and the second test data generate a comparison result to determine an image processing performance of the electronic device, and the processor selectively controls the switching circuit to operate in the first mode or the The second mode.

如請求項2所述之電子裝置，更包含一擴充卡連接於該切換電路，其中，該切換電路固定連接該擴充卡與該處理器之任一該第一處理單元或該第二處理單元。The electronic device according to claim 2, further comprising an expansion card connected to the switching circuit, wherein the switching circuit is fixedly connected to either the first processing unit or the second processing unit of the expansion card and the processor.

如請求項1所述之電子裝置，其中，該影像處理電路更包含連接該切換電路的一第三圖形處理電路；其中，該處理器更用以依據該測試資料控制該切換電路，致使該第二處理單元電性連接該第三圖形處理電路。 The electronic device according to claim 1, wherein the image processing circuit further includes a third graphics processing circuit connected to the switching circuit; Wherein, the processor is further used for controlling the switching circuit according to the test data, so that the second processing unit is electrically connected to the third graphics processing circuit.

如請求項1所述之電子裝置，其中，該影像處理電路更包含連接該切換電路的一第三圖形處理電路；其中，該處理器更用以依據該測試資料關閉該第三圖形處理電路。 The electronic device according to claim 1, wherein the image processing circuit further includes a third graphics processing circuit connected to the switching circuit; Wherein, the processor is further used to turn off the third graphics processing circuit according to the test data.

如請求項1所述之電子裝置，其中，該切換電路包含複數開關元件與一重定時器。The electronic device according to claim 1, wherein the switching circuit includes a plurality of switching elements and a retimer.

一種具圖形處理運算資源配置功能之電子裝置的控制方法，包含：透過一處理器以及一影像處理電路運行一測試程式以產生一測試資料；以及依據該測試資料，將該處理器之一第一處理單元電性連接該影像處理電路之一第一圖形處理電路且將該處理器之一第二處理單元電性連接該影像處理電路之一第二圖形處理電路，或將該第一處理單元電性連接該第一圖形處理電路與該第二圖形處理電路。 A control method of an electronic device with graphics processing and computing resource allocation function, including: Run a test program through a processor and an image processing circuit to generate test data; and According to the test data, a first processing unit of the processor is electrically connected to a first graphics processing circuit of the image processing circuit and a second processing unit of the processor is electrically connected to a first graphics processing circuit of the image processing circuit Two graphics processing circuits, or the first processing unit is electrically connected to the first graphics processing circuit and the second graphics processing circuit.

如請求項7所述之電子裝置的控制方法，其中透過該處理器以及該影像處理電路運行該測試程式以產生該測試資料之步驟包含：透過該處理器控制一切換電路操作於一第一模式，操作於該第一模式之該切換電路連接該第一處理單元與該第一圖形處理電路，且連接該第二處理單元與該第二圖形處理電路；在該切換電路操作於該第一模式時，透過該處理器與該影像處理電路運行該測試程式以產生一第一測試資料；透過該處理器控制該切換電路操作於一第二模式，操作於該第二模式之該切換電路連接該第一處理單元與該第一圖形處理電路及該第二圖形處理電路；及在該切換電路操作於該第二模式時，透過該處理器與該影像處理電路運行該測試程式以產生一第二測試資料；其中，依據該測試資料，將該第一處理單元電性連接該第一圖形處理電路且將該第二處理單元電性連接該第二圖形處理電路，或將該第一處理單元電性連接該第一圖形處理電路與該第二圖形處理電路之步驟包含：透過該處理器比較該第一測試資料及該第二測試資料而產生一比較結果以判斷該電子裝置之一影像處理效能；及透過該處理器根據該比較結果選擇性地控制該切換電路操作於該第一模式或該第二模式，使該第一處理單元電性連接該第一圖形處理電路且該第二處理單元電性連接該第二圖形處理電路，或使該第一處理單元電性連接該第一圖形處理電路與該第二圖形處理電路。 The control method for an electronic device according to claim 7, wherein the step of running the test program through the processor and the image processing circuit to generate the test data includes: A switching circuit is controlled to operate in a first mode through the processor, and the switching circuit operating in the first mode connects the first processing unit and the first graphics processing circuit, and connects the second processing unit and the second Graphics processing circuit; When the switching circuit is operating in the first mode, run the test program through the processor and the image processing circuit to generate a first test data; Controlling the switching circuit to operate in a second mode through the processor, and the switching circuit operating in the second mode connects the first processing unit with the first graphics processing circuit and the second graphics processing circuit; and When the switching circuit is operating in the second mode, run the test program through the processor and the image processing circuit to generate a second test data; Wherein, according to the test data, the first processing unit is electrically connected to the first graphics processing circuit and the second processing unit is electrically connected to the second graphics processing circuit, or the first processing unit is electrically connected to the The steps of the first graphics processing circuit and the second graphics processing circuit include: Comparing the first test data and the second test data through the processor to generate a comparison result to determine an image processing performance of the electronic device; and The processor selectively controls the switching circuit to operate in the first mode or the second mode according to the comparison result, so that the first processing unit is electrically connected to the first graphics processing circuit and the second processing unit is electrically connected The second graphics processing circuit is connected, or the first processing unit is electrically connected to the first graphics processing circuit and the second graphics processing circuit.

如請求項8所述之電子裝置的控制方法，更包含：透過該切換電路固定連接該擴充卡及該處理器中之任一該第一處理單元或該第二處理單元。The control method of the electronic device according to claim 8, further comprising: permanently connecting the expansion card and the processor through the switching circuit to any one of the first processing unit or the second processing unit.

如請求項7所述之電子裝置的控制方法，更包含：依據該測試資料將該第二處理單元電性連接該影像處理電路之一第三圖形處理電路。 The control method of an electronic device as described in claim 7, further comprising: According to the test data, the second processing unit is electrically connected to a third graphics processing circuit of the image processing circuit.

如請求項7所述之電子裝置的控制方法，更包含：透過該處理器依據該測試資料關閉該影像處理電路之一第三圖形處理電路。 The control method of an electronic device as described in claim 7, further comprising: A third graphics processing circuit of the image processing circuit is turned off by the processor according to the test data.