TWI697210B - Phase-locked loop with automatic band selector and multi-band voltage control oscillator thereof - Google Patents

Phase-locked loop with automatic band selector and multi-band voltage control oscillator thereof Download PDF

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TWI697210B
TWI697210B TW108116251A TW108116251A TWI697210B TW I697210 B TWI697210 B TW I697210B TW 108116251 A TW108116251 A TW 108116251A TW 108116251 A TW108116251 A TW 108116251A TW I697210 B TWI697210 B TW I697210B
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band
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electrically connected
control signal
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TW202042508A (en
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王朝欽
蔡宗毅
王鼎勝
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國立中山大學
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Abstract

A phase-locked loop with automatic band selector includes a frequency phase detector, a charge pump, a low pass filter, an automatic band selector, a multi-band voltage control oscillator and a frequency divider. The charge pump receives the rising signal and the falling signal of the frequency phase detector and outputs the analog voltage. The analog voltage is filtered by the low pass filter into a control signal and transmitted to the multi-band voltage controlled oscillator for frequency control. Wherein the automatic band selector can be controlled the frequency band of the multi-band voltage controlled oscillator according to the control signal, thus when the process variation is too large and the frequency offset is not at the expected operating frequency, the frequency band can still operate normally by the frequency band changing.

Description

具自動頻帶選擇器之鎖相迴路及其多頻帶壓控振盪器Phase-locked loop with automatic frequency band selector and its multi-band voltage-controlled oscillator

本發明是關於一種鎖相迴路，特別是關於一種具自動頻帶選擇之鎖相迴路及其多頻帶壓控振盪器。The invention relates to a phase locked loop, in particular to a phase locked loop with automatic frequency band selection and its multi-band voltage controlled oscillator.

鎖相迴路(Phase-locked loops)為一種回授系統，其藉由回授訊號與參考訊號之間頻率相位的比對進行壓控振盪器的控制，使得鎖相迴路輸出之訊號的頻率相位能與參考訊號同步，以提供一穩定的操作時脈而常使用於通訊系統中。一般鎖相迴路具有一頻率相位偵測器、一低通濾波器、一壓控振盪器及一除頻器，該頻率相位偵測器用以比對一參考訊號與該分頻器輸出之一回授訊號的頻率及相位而輸出一偵測訊號，該頻率相位偵測器輸出之該偵測訊號經由該低通濾波器濾除高頻訊號後傳送至該壓控振盪器進行控制，該壓控振盪器輸出之一輸出訊號經由該除頻器除頻為該回授訊號再回授至該頻率相位偵測器，經由數次之回授及鎖相後即可讓壓控振盪器輸出之頻率相位與參考訊號同步，而可提供頻率穩定的輸出訊號。隨著半導體製程的演進，半導體元件的尺寸越來越小，使得製程變異已成為不可忽視的問題之一，而若壓控振盪器製程偏移量過大時，可能會導致其輸出頻率不在預期操作頻率範圍內，讓鎖相迴路更甚是整體電路無法正常動作。Phase-locked loops (Phase-locked loops) are a feedback system that controls the voltage-controlled oscillator by comparing the frequency and phase between the feedback signal and the reference signal, so that the frequency and phase of the signal output by the phase-locked loop can be It is synchronized with the reference signal to provide a stable operating clock and is often used in communication systems. The general phase-locked loop has a frequency-phase detector, a low-pass filter, a voltage-controlled oscillator and a frequency divider. The frequency-phase detector is used to compare a reference signal with the output of the frequency divider. The frequency and phase of the given signal output a detection signal. The detection signal output by the frequency and phase detector is filtered by the low-pass filter and then transmitted to the voltage-controlled oscillator for control. The voltage control One output signal of the oscillator output is divided by the frequency divider to the feedback signal and then fed back to the frequency and phase detector. After several times of feedback and phase lock, the frequency of the voltage controlled oscillator can be output The phase is synchronized with the reference signal, and can provide an output signal with stable frequency. With the evolution of semiconductor processes, the size of semiconductor devices is getting smaller and smaller, making process variation one of the issues that cannot be ignored. If the offset of the voltage-controlled oscillator process is too large, it may cause its output frequency to not operate as expected Within the frequency range, the phase-locked loop and even the entire circuit cannot operate normally.

本發明的主要目的在於提供具自動頻帶選擇器之鎖相迴路，可藉由自動頻帶選擇器改變多頻帶壓控振盪器的操作頻帶，使多頻帶壓控振盪器在製程變異大時仍可正常動作。The main purpose of the present invention is to provide a phase-locked loop with an automatic frequency band selector, which can change the operating frequency band of the multi-band voltage controlled oscillator by the automatic frequency band selector, so that the multi-band voltage controlled oscillator can still be normal when the process variation is large action.

本發明之一種具自動頻帶選擇器之鎖相迴路包含一頻率相位偵測器、一電荷泵、一低通濾波器、一自動頻帶選擇器、一多頻帶壓控振盪器及一除頻器，該頻率相位偵測器接收一參考訊號及一回授訊號，該頻率相位偵測器用以比對該參考訊號及該回授訊號的頻率相位並輸出一上升訊號及一下降訊號，該電荷泵電性連接該頻率相位偵測器，該電荷泵接收該上升訊號及該下降訊號，且該電荷泵輸出一類比電壓，該低通濾波器電性連接該電荷泵，該低通濾波器接收該類比電壓，且該低通濾波器輸出一控制訊號，該自動頻帶選擇器電性連接該低通濾波器，該自動頻帶選擇器接收該控制訊號，該自動頻帶選擇器將該控制訊號與一高電位訊號及一低電位訊號比對而輸出一P型頻帶控制訊號及一N型頻帶控制訊號，該多頻帶壓控振盪器電性連接該低通濾波器及該自動頻帶選擇器以接收該控制訊號、該P型頻帶控制訊號及該N型頻帶控制訊號，其中該P型頻帶控制訊號及該N型頻帶控制訊號用以改變該多頻帶壓控振盪器的一頻帶，該控制訊號用以控制該多頻帶壓控振盪器於該頻帶的一振盪頻率，該除頻器電性連接該多頻帶壓控振盪器及該頻率相位偵測器，該除頻器用以將該多頻帶壓控振盪器之一輸出訊號除頻為該回授訊號，並傳送至該頻率相位偵測器。A phase-locked loop with an automatic frequency band selector of the present invention includes a frequency phase detector, a charge pump, a low-pass filter, an automatic frequency band selector, a multi-band voltage controlled oscillator and a frequency divider, The frequency phase detector receives a reference signal and a feedback signal. The frequency phase detector is used to compare the frequency phase of the reference signal and the feedback signal and output an up signal and a down signal. The charge pump Is connected to the frequency phase detector, the charge pump receives the rising signal and the falling signal, and the charge pump outputs an analog voltage, the low-pass filter is electrically connected to the charge pump, and the low-pass filter receives the analog Voltage, and the low-pass filter outputs a control signal, the automatic band selector is electrically connected to the low-pass filter, the automatic band selector receives the control signal, and the automatic band selector connects the control signal and a high potential The signal is compared with a low potential signal to output a P-band control signal and an N-band control signal. The multi-band voltage-controlled oscillator is electrically connected to the low-pass filter and the automatic band selector to receive the control signal , The P-type band control signal and the N-type band control signal, wherein the P-type band control signal and the N-type band control signal are used to change a frequency band of the multi-band voltage-controlled oscillator, and the control signal is used to control the The multi-band voltage controlled oscillator is at an oscillation frequency of the frequency band. The frequency divider is electrically connected to the multi-band voltage controlled oscillator and the frequency phase detector. The frequency divider is used for the multi-band voltage controlled oscillator. An output signal divided by the frequency is the feedback signal and sent to the frequency phase detector.

本發明藉由該自動頻帶選擇器根據該控制訊號的大小輸出頻帶控制訊號至該多頻帶壓控制振盪器，而改變該多頻帶壓控振盪器的頻帶，使得該多頻帶壓控制振盪器能夠有效地抵抗製程變異。The present invention changes the frequency band of the multi-band voltage controlled oscillator by the automatic frequency band selector outputting the frequency band control signal to the multi-band voltage controlled oscillator according to the size of the control signal, so that the multi-band voltage controlled oscillator can be effectively Resistance to process variations.

請參閱第1圖，其為本發明之一實施例，一種鎖相迴路100之功能方塊圖，該鎖相迴路100具有一頻率相位偵測器110、一電荷泵120、一低通濾波器130、一自動頻帶選擇器140、一多頻帶壓控振盪器150及一除頻器160。其中，該電荷泵120電性連接該頻率相位偵測器110，該低通濾波器130電性連接該電荷泵120，該自動頻帶選擇器140電性連接該低通濾波器130，該多頻帶壓控振盪器150電性連接該自動頻帶選擇器140及該低通濾波器130，該除頻器160電性連接該多頻帶壓控振盪器150及該頻率相位偵測器110。Please refer to FIG. 1, which is a functional block diagram of a phase-locked loop 100 according to an embodiment of the present invention. The phase-locked loop 100 has a frequency phase detector 110, a charge pump 120, and a low-pass filter 130. , An automatic frequency band selector 140, a multi-band voltage controlled oscillator 150 and a frequency divider 160. Wherein, the charge pump 120 is electrically connected to the frequency and phase detector 110, the low-pass filter 130 is electrically connected to the charge pump 120, and the automatic band selector 140 is electrically connected to the low-pass filter 130, the multi-band The voltage controlled oscillator 150 is electrically connected to the automatic band selector 140 and the low-pass filter 130, and the frequency divider 160 is electrically connected to the multi-band voltage controlled oscillator 150 and the frequency phase detector 110.

請參閱第1及2圖，其中第2圖為本實施之該頻率相位偵測器110的電路圖，該頻率相位偵測器110用以比對一參考訊號S ref及一回授訊號S fed的頻率與相位，在本實施例中，該頻率相位偵測器110具有一第一動態偵測單元111、一第二動態偵測單元112、一NOR閘113、一第一反相器114、一第二反相器115及一突波消除電路116。該第一動態偵測單元111接收該參考訊號S ref，該第二動態偵測單元112接收該除頻器160輸出之該回授訊號S fed，該NOR閘113電性連接該第一動態偵測單元111及該第二動態偵測單元112，且該NOR閘113輸出之一邏輯訊號S L回傳至該第一動態偵測單元111及該第二動態偵測單元112，該第一反相器114電性連接該第一動態偵測單元111，該第二反相器115電性連接該第二動態偵測單元112，該突波消除電路116電性連接該第一反相器114及該第二反相器115，且該突波消除電路116輸出該上升訊號UP及該下降訊號DN。 Please refer to FIGS. 1 and 2, wherein FIG. 2 is a circuit diagram of the frequency and phase detector 110 of the present embodiment. The frequency and phase detector 110 is used to compare a reference signal S ref and a feedback signal S fed Frequency and phase. In this embodiment, the frequency and phase detector 110 has a first motion detection unit 111, a second motion detection unit 112, a NOR gate 113, a first inverter 114, a The second inverter 115 and a surge cancellation circuit 116. The first motion detection unit 111 receives the reference signal S ref , the second motion detection unit 112 receives the feedback signal S fed output from the frequency divider 160, and the NOR gate 113 is electrically connected to the first motion detection Detection unit 111 and the second motion detection unit 112, and a logic signal SL output by the NOR gate 113 is returned to the first motion detection unit 111 and the second motion detection unit 112, The phase inverter 114 is electrically connected to the first motion detection unit 111, the second inverter 115 is electrically connected to the second motion detection unit 112, and the surge cancellation circuit 116 is electrically connected to the first inverter 114 And the second inverter 115, and the surge cancellation circuit 116 outputs the up signal UP and the down signal DN.

請參閱第2圖，本實施例之該突波消除電路116具有一第三反相器116a、一第四反相器116b、一第一AND閘116c及一第二AND閘116d，該第三反相器116a電性連接該第一反相器114，該第四反相器116b電性連接該第二反相器115，該第一AND閘116c電性連接該第一反相器114及該第四反相器116b，且該第一AND閘116c根據該第一反相器114及該第四反相器116b輸出之電位產生該上升訊號UP，該第二AND閘116d電性連接該第二反相器115及該第三反相器116a，且該第二AND閘116d根據該第二反相器115及該第三反相器116a輸出之電位產生該下降訊號DN。Please refer to FIG. 2, the surge cancellation circuit 116 of this embodiment has a third inverter 116a, a fourth inverter 116b, a first AND gate 116c and a second AND gate 116d. The third The inverter 116a is electrically connected to the first inverter 114, the fourth inverter 116b is electrically connected to the second inverter 115, and the first AND gate 116c is electrically connected to the first inverter 114 and The fourth inverter 116b, and the first AND gate 116c generates the rising signal UP according to the potentials output by the first inverter 114 and the fourth inverter 116b, and the second AND gate 116d is electrically connected to the The second inverter 115 and the third inverter 116a, and the second AND gate 116d generate the falling signal DN according to the potentials output by the second inverter 115 and the third inverter 116a.

請參閱第2圖，該第一動態偵測單元111及該第二動態偵測訊號112輸出訊號之初始值為高電位，當該參考訊號S ref領先該回授訊號S fed時，該第一動態偵測單元111之輸出為低電位，該第二動態偵測單元112之輸出為高電位，使得該突波消除電路116輸出之該上升訊號UP為高電位，輸出之該下降訊號DN為低電位。當該參考訊號S ref落後該回授訊號S fed時，該第一動態偵測單元111之輸出為高電位，該第二動態偵測單元112之輸出為低電位，使得該突波消除電路116輸出之該上升訊號UP為低電位，輸出之該下降訊號DN為高電位，藉此讓後端電路能夠得知該參考訊號S ref及該回授訊號S fed之間的頻率相位差。而當該上升訊號UP及該下降訊號DN皆為高電位時，該NOR閘113輸出高電位，重置該第一動態偵測單元111及該第二動態偵測單元112，可減少該頻率相位偵測器110的死區。 Referring to FIG. 2, the initial value of the output signals of the first motion detection unit 111 and the second motion detection signal 112 is high. When the reference signal S ref leads the feedback signal S fed , the first The output of the motion detection unit 111 is a low potential, and the output of the second motion detection unit 112 is a high potential, so that the up signal UP output by the surge cancellation circuit 116 is a high potential, and the down signal DN output is a low Potential. When the reference signal S ref lags the feedback signal S fed , the output of the first motion detection unit 111 is high and the output of the second motion detection unit 112 is low, so that the surge cancellation circuit 116 The output up signal UP is low, and the output down signal DN is high, so that the back-end circuit can learn the frequency phase difference between the reference signal S ref and the feedback signal S fed . When both the up signal UP and the down signal DN are high, the NOR gate 113 outputs a high potential to reset the first motion detection unit 111 and the second motion detection unit 112, which can reduce the frequency phase The dead zone of the detector 110.

請參閱第1及3圖，其中第3圖為本實施例之該電荷泵120的電路圖，該電荷泵120接收該頻率相位偵測器110輸出之該下降訊號DN，並經由一反相器接收該上升訊號UP，且該電荷泵120根據該下降訊號DN及反相之該上升訊號UP輸出一類比電壓V A，其中，當該上升訊號UP為高電位時反相之該上升訊號UP導通P型電晶體121，使該電荷泵120輸出之該類比電壓V A上升，而當該下降訊號DN為高電位時導通N型電晶體122，使該電荷泵120輸出之該類比電壓V A下降，藉此將數位之該上升訊號UP及該下降訊號DN轉換成類比之該類比電壓V A。 Please refer to FIGS. 1 and 3, wherein FIG. 3 is a circuit diagram of the charge pump 120 of this embodiment. The charge pump 120 receives the down signal DN output by the frequency phase detector 110 and receives it through an inverter. The rising signal UP, and the charge pump 120 outputs an analog voltage V A according to the falling signal DN and the inverted rising signal UP, wherein the rising signal UP inverted when the rising signal UP is at a high potential turns on P type transistor 121, the charge pump 120 so that the output of such voltage rise ratio V A, and when the decrease signal DN to a high voltage N-type transistor is turned on 122, 120 so that the charge pump output voltage lower than the class V A, In this way, the digital up signal UP and the down signal DN are converted into an analog voltage V A.

請參閱第1圖，該低通濾波器130接收該電荷泵120之該類比電壓V A，該低通濾波器130濾除該類比電壓V A中的高頻成份，且該低通濾波器130輸出一控制訊號V ctrl。 Referring to FIG. 1, the low-pass filter 130 receives the analog voltage V A of the charge pump 120, the low-pass filter 130 filters out high-frequency components in the analog voltage V A , and the low-pass filter 130 A control signal V ctrl is output.

請參閱第1圖，該自動頻帶選擇器140接收該低通濾波器130輸出之該控制訊號V ctrl，在本實施例中，該自動頻帶選擇器140具有一第一比較器141、一第二比較器142、一溫度編碼計數器143及一數位類比轉換器144。其中，該第一比較器141接收該控制訊號V ctrl及一低電位訊號VL，該第一比較器141比對該控制訊號V ctrl及該低電位訊號VL的電位大小並輸出一第一比較訊號S c1，該第二比較器142接收該控制訊號V ctrl及一高電位訊號VH，該第二比較器142比對該控制訊號V ctrl及該高電位訊號VH的的電位大小並輸出一第二比較訊號S c2，該溫度編碼計數器143接收該第一比較訊號S c1及該第二比較訊號S c2，且該溫度編碼計數器143根據該第一比較訊號S c1及該第二比較訊號S c2輸出一溫度編碼訊號S TC，該數位類比轉換器144電性連接該溫度編碼計數器143，該數位類比轉換器144根據該溫度編碼訊號S TC輸出一P型頻帶控制訊號S cp及一N型頻帶控制訊號S cn至該多頻帶壓控振盪器150，以控制該多頻帶壓控振盪器150的頻帶。 Please refer to FIG. 1, the automatic frequency band selector 140 receives the control signal V ctrl output by the low-pass filter 130. In this embodiment, the automatic frequency band selector 140 has a first comparator 141 and a second A comparator 142, a temperature code counter 143 and a digital analog converter 144. The first comparator 141 receives the control signal V ctrl and a low potential signal VL. The first comparator 141 compares the potential of the control signal V ctrl and the low potential signal VL and outputs a first comparison signal S c1 , the second comparator 142 receives the control signal V ctrl and a high-potential signal VH, the second comparator 142 compares the potential of the control signal V ctrl and the high-potential signal VH and outputs a second The comparison signal S c2 , the temperature code counter 143 receives the first comparison signal S c1 and the second comparison signal S c2 , and the temperature code counter 143 outputs according to the first comparison signal S c1 and the second comparison signal S c2 A temperature coding signal S TC , the digital analog converter 144 is electrically connected to the temperature coding counter 143, the digital analog converter 144 outputs a P-band control signal S cp and an N-band control according to the temperature coding signal S TC The signal S cn is sent to the multi-band voltage controlled oscillator 150 to control the frequency band of the multi-band voltage controlled oscillator 150.

請參閱第4圖，為本實施例之該溫度編碼計數器143的電路圖，該溫度編碼計數器143是由複數個邏輯電路及複數個D型正反器組成，由右至左的該D型正反器輸出之S 0~S 9訊號則分別為該溫度編碼訊號S TC之第0至9位元。其中，當該控制訊號V ctrl小於該低電位訊號VL及該高電位訊號VH時，該第一比較訊號S c1為高電位，該第二比較訊號S c2為低電位，這將使得該溫度編碼計數器143上數，例如，由0000000111上數至0000001111。而當該控制訊號V ctrl大於該高電位訊號VH及該低電位訊號VL時，該第一比較訊號S c1為低電位，該第二比較訊號S c2為高電位，這將使得該溫度編碼計數器143下數，例如，由0001111111下數至0000111111。 Please refer to FIG. 4, which is a circuit diagram of the temperature encoding counter 143 of this embodiment. The temperature encoding counter 143 is composed of a plurality of logic circuits and a plurality of D-type flip-flops, and the D-type positive and negative from right to left The S 0 ~S 9 signals output by the device are the 0th to 9th bits of the temperature coding signal S TC respectively. Wherein, when the control signal V ctrl is less than the low potential signal VL and the high potential signal VH, the first comparison signal S c1 is high potential, and the second comparison signal S c2 is low potential, which will make the temperature coding The counter 143 counts up, for example, from 0000000111 to 0000001111. When the control signal V ctrl is greater than the high potential signal VH and the low potential signal VL, the first comparison signal S c1 is low potential, and the second comparison signal S c2 is high potential, which will make the temperature coding counter 143 countdown, for example, from 0001111111 countdown to 0000111111.

請參閱第5圖，為本實施例之該數位類比轉換器144的電路圖，該溫度編碼訊號S TC之各個位元S 0~S 9分別控制多個N型電晶體，而各該N型電晶體的導通或截止將改變電流I S的分流大小，進而改變該P型頻帶控制訊號S cp及該N型頻帶控制訊號S cn的電位。其中，若該溫度編碼訊號S TC之各個位元S 0~S 9為邏輯1較多而導通較多個N型電晶體時，電流I S的分流大小會提高，使得該P型頻帶控制訊號S cp上升並使N型頻帶控制訊號S cn下降。反之，該溫度編碼訊號S TC之各個位元S 0~S 9為邏輯1較少而導通較少個N型電晶體時，電流I S的分流大小會減少，使得該P型頻帶控制訊號S cp下降並使N型頻帶控制訊號S cn上升。 Please refer to FIG. 5, which is a circuit diagram of the digital-to-analog converter 144 of this embodiment. Each bit S 0 ~S 9 of the temperature-coded signal S TC controls a plurality of N-type transistors, and each N-type transistor the crystals turned on or off to change the magnitude of the current I S of the shunt, thereby changing the potential of the P-type band control signal S cp, and the N-type band of the control signal S cn. Among them, if each bit S 0 ~S 9 of the temperature-coded signal S TC is more logic 1 and more N-type transistors are turned on, the shunt size of the current I S will increase, making the P-type band control signal S cp rises and causes the N-band control signal S cn to fall. Conversely, when each bit S 0 ~ S 9 of the temperature-coded signal S TC is less logic 1 and fewer N-type transistors are turned on, the shunt size of the current I S will be reduced, making the P-type band control signal S cp falls and causes the N-band control signal S cn to rise.

請參閱第1圖，該多頻帶壓控振盪器150接收該低通濾波器130輸出之該控制訊號V ctrl及該數位類比轉換器144輸出之該P型頻帶控制訊號S cp及該N型頻帶控制訊號S cn。其中該控制訊號V ctrl用以控制該多頻帶壓控振盪器150於該頻帶的一振盪頻率，該P型頻帶控制訊號S cp及該N型頻帶控制訊號S cn則用以改變該多頻帶壓控振盪器150的一頻帶。 Referring to FIG. 1, the multi-band voltage controlled oscillator 150 receives the control signal V ctrl output from the low-pass filter 130 and the P-band control signal S cp and the N-band output from the digital-to-analog converter 144 Control signal S cn . The control signal V ctrl is used to control an oscillation frequency of the multi-band voltage-controlled oscillator 150 in the frequency band, and the P-type band control signal S cp and the N-type band control signal S cn are used to change the multi-band voltage A frequency band of the controlled oscillator 150.

請參閱第6圖，為本實施例之該多頻帶壓控振盪器150的電路圖，該多頻帶壓控振盪器150具有一控制電晶體151、一第一電流鏡152、一第一開關串153、一延遲元件串154、一第二開關串155及一第二電流鏡156。其中，該第一電流鏡152具有一P型參考電晶體152a及複數個P型電流鏡電晶體152b，該第一開關串153具有複數個P型電晶體153a，該第二電流鏡156具有一N型參考電晶體156a及複數個N型電流鏡電晶體156b，該第二開關串155具有複數個N型電晶體155a，該延遲元件串154具有複數個延遲元件154a。Please refer to FIG. 6, which is a circuit diagram of the multi-band voltage controlled oscillator 150 of this embodiment. The multi-band voltage controlled oscillator 150 has a control transistor 151, a first current mirror 152, and a first switch string 153 , A delay element string 154, a second switch string 155 and a second current mirror 156. Wherein, the first current mirror 152 has a P-type reference transistor 152a and a plurality of P-type current mirror transistors 152b, the first switch string 153 has a plurality of P-type transistors 153a, and the second current mirror 156 has a An N-type reference transistor 156a and a plurality of N-type current mirror transistors 156b, the second switch string 155 has a plurality of N-type transistors 155a, and the delay element string 154 has a plurality of delay elements 154a.

其中，該控制電晶體151為一N型電晶體，該控制電晶體151之閘極接收該控制訊號V ctrl，該控制電晶體151之汲極電性連接該第一電流鏡152之該P型參考電晶體152a，該控制電晶體151之源極經由一電阻157接地，該第一電流鏡152之該P型參考電晶體152a之閘極及汲極電性連接該控制電晶體151之汲極，該P型參考電晶體152a之源極接收一電源電壓V DD，使該控制電晶體151之汲極經由該第一電流鏡152之該P型參考電晶體152a接收該電源電壓V DD，該些P型電流鏡電晶體152b之閘極電性連接該P型參考電晶體152a之閘極，該些P型電流鏡電晶體152b之源極接收電源電壓V DD。該第一開關串153之各該P型電晶體153a之源極電性連接各該P型電流鏡電晶體152b之汲極，各該P型電晶體153a之汲極電性連接各該延遲元件154a，各該P型電晶體153a之閘極接收該P型頻帶控制訊號S cp。該第二電流鏡156之該N型參考電晶體156a之汲極及閘極電性連接其中之一該P型電流鏡電晶體152b之汲極，該N型參考電晶體156a之源極接地，各該N型電流鏡電晶體156b之閘極電性連接該N型參考電晶體156a之閘極，各該N型電流鏡電晶體156b之源極接地。該第二開關串155之各該N型電晶體155a之源極電性連接各該N型電流靜電晶體156b之汲極，各該N型電晶體155a之汲極電性連接各該延遲元件154a，各該N型電晶體155a之閘極接收該N型頻帶控制訊號S cn。各該延遲元件154a為雙端延遲元件，各該延遲元件154a相互串聯，該延遲元件154a輸出一正振盪訊號V o+及一負振盪訊號V o-，在本實施例中，是以該延遲元件154a之該正振盪訊號V o+作為該多頻帶壓控振盪器150之一輸出訊號S O。其中，由於該控制訊號V ctrl的電位大小可改變流經該控制電晶體151的電流大小，進而改變流經該第一電流鏡152、該第二電流鏡156及該延遲元件串154的電流，而能控制該多頻帶壓控振盪器150的振盪頻率。 The control transistor 151 is an N-type transistor, the gate of the control transistor 151 receives the control signal V ctrl , and the drain of the control transistor 151 is electrically connected to the P-type of the first current mirror 152 With reference to the transistor 152a, the source of the control transistor 151 is grounded via a resistor 157, and the gate and the drain of the P-type reference transistor 152a of the first current mirror 152 are electrically connected to the drain of the control transistor 151 , The source of the P-type reference transistor 152a receives a power supply voltage V DD , so that the drain of the control transistor 151 receives the power supply voltage V DD through the P-type reference transistor 152a of the first current mirror 152, the The gates of the P-type current mirror transistors 152b are electrically connected to the gates of the P-type current mirror transistors 152a, and the sources of the P-type current mirror transistors 152b receive the power supply voltage V DD . The source of each P-type transistor 153a of the first switch string 153 is electrically connected to the drain of each P-type current mirror transistor 152b, and the drain of each P-type transistor 153a is electrically connected to each delay element At 154a, the gate of each P-type transistor 153a receives the P-type band control signal S cp . The drain and gate of the N-type reference transistor 156a of the second current mirror 156 are electrically connected to one of the drains of the P-type current mirror transistor 152b, and the source of the N-type reference transistor 156a is grounded. The gate of each N-type current mirror transistor 156b is electrically connected to the gate of the N-type reference transistor 156a, and the source of each N-type current mirror transistor 156b is grounded. The source of each N-type transistor 155a of the second switch string 155 is electrically connected to the drain of each N-type current electrostatic transistor 156b, and the drain of each N-type transistor 155a is electrically connected to each delay element 154a The gate of each N-type transistor 155a receives the N-type band control signal S cn . Each of the delay elements 154a is a double-ended delay element, and each of the delay elements 154a is connected in series with each other. The delay element 154a outputs a positive oscillation signal V o+ and a negative oscillation signal V o- . In this embodiment, the delay element The positive oscillation signal V o+ of 154a is used as one of the output signals S O of the multi-band voltage controlled oscillator 150. Wherein, since the potential of the control signal V ctrl can change the current flowing through the control transistor 151, and thus the current flowing through the first current mirror 152, the second current mirror 156 and the delay element string 154, The oscillation frequency of the multi-band voltage controlled oscillator 150 can be controlled.

請參閱第1及6圖，當該控制訊號V ctrl大於該高電位訊號VH及該低電位訊號VL時，會讓該溫度編碼計數器143上數，令該P型頻帶控制訊號S cp上升及該N型頻帶控制訊號S cn下降，使得通過各該延遲元件154a的電流減少，反之，當該控制訊號V ctrl小於該高電位訊號VH及該低電位訊號VL時，會讓該溫度編碼計數器143下數，令該P型頻帶控制訊號S cp下降及該N型頻帶控制訊號S cn上升，使得通過各該延遲元件154a的電流增加。藉此，該自動頻帶選擇器140可在該控制電壓V ctrl大於該高電位訊號VH或小於該低電位訊號VL時以該P型頻帶控制訊號S cp及該N型頻帶控制訊號S cn改變該多頻帶壓控振盪器150之操作頻帶，而達成自動頻帶選擇之功效。 Please refer to Figs. 1 and 6, when the control signal V ctrl is greater than the high potential signal VH and the low potential signal VL, the temperature encoding counter 143 will be counted up, causing the P-band control signal S cp to rise and the The N-band control signal S cn decreases, so that the current through each of the delay elements 154a decreases. On the contrary, when the control signal V ctrl is less than the high potential signal VH and the low potential signal VL, the temperature code counter 143 will be lowered As a result, the P-band control signal S cp decreases and the N-band control signal S cn increases, so that the current through each of the delay elements 154a increases. Thereby, the automatic frequency band selector 140 can change the P-band control signal S cp and the N-type band control signal S cn when the control voltage V ctrl is greater than the high potential signal VH or less than the low potential signal VL The operating frequency band of the multi-band voltage controlled oscillator 150 achieves the effect of automatic frequency band selection.

請參閱第1圖，該除頻器160接收該多頻帶壓控振盪器150之該輸出訊號S O，並將其除頻為該回授訊號S fed，最後再將該回授訊號S fed傳送至該頻率相位偵測器110進行頻率相位比對，而可在在數次回授後達成該鎖相迴路100之鎖相。 Please refer to FIG. 1, the frequency divider 160 receives the output signal S O of the multi-band voltage controlled oscillator 150 and divides it into the feedback signal S fed , and finally transmits the feedback signal S fed The frequency-phase detector 110 performs frequency-phase comparison, and the phase-locking of the phase-locked loop 100 can be achieved after several feedbacks.

本發明藉由該自動頻帶選擇器140根據該控制訊號V ctrl輸出頻帶控制訊號至多頻帶壓控振盪器150，改變多頻帶壓控振盪器150的頻帶，使得多頻帶壓控振盪器150能夠有效地抵抗製程變異。 In the present invention, the automatic frequency band selector 140 outputs a frequency band control signal to the multi-band voltage controlled oscillator 150 according to the control signal V ctrl to change the frequency band of the multi-band voltage controlled oscillator 150 so that the multi-band voltage controlled oscillator 150 can effectively Resist process variation.

本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。The scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application. Any changes and modifications made by those who are familiar with this skill without departing from the spirit and scope of the present invention shall fall within the scope of protection of the present invention. .

100:鎖相迴路 110:頻率相位偵測器 111:第一動態偵測單元 112:第二動態偵測單元 113:NOR閘 114:第一反相器 115:第二反相器 116:突波消除電路 116a:第三反相器 116b:第四反相器 116c:第一AND閘 116d:第二AND閘 120:電荷泵 130:低通濾波器 140:自動頻帶選擇器 141:第一比較器 142:第二比較器 143:溫度編碼計數器 144:數位類比轉換器 150:多頻帶壓控振盪器 151:控制電晶體 152:第一電流鏡 152a:P型參考電晶體 152b:P型電流鏡電晶體 153:第一開關串 153a:P型電晶體 154:延遲元件串 154a:延遲元件 155:第二開關串 155a:N型電晶體 156:第二電流鏡 156a:N型參考電晶體 156b:N型電流鏡電晶體 157:電阻 Sref:參考訊號 Sfed:回授訊號 UP:上升訊號 DN:下降訊號 VA:類比電壓 Vctrl:控制訊號 VH:高電位訊號 VL:低電位訊號 SO:輸出訊號 SL:邏輯訊號 Sc1:第一比較訊號 Sc2:第二比較訊號 Scp:P型頻帶控制訊號 Scn:N型頻帶控制訊號 VDD:電源電壓 STC:溫度編碼訊號100: phase locked loop 110: frequency phase detector 111: first motion detection unit 112: second motion detection unit 113: NOR gate 114: first inverter 115: second inverter 116: surge Elimination circuit 116a: third inverter 116b: fourth inverter 116c: first AND gate 116d: second AND gate 120: charge pump 130: low-pass filter 140: automatic band selector 141: first comparator 142: Second comparator 143: Temperature code counter 144: Digital analog converter 150: Multi-band voltage controlled oscillator 151: Control transistor 152: First current mirror 152a: P-type reference transistor 152b: P-type current mirror Crystal 153: First switch string 153a: P-type transistor 154: Delay element string 154a: Delay element 155: Second switch string 155a: N-type transistor 156: Second current mirror 156a: N-type reference transistor 156b: N Current mirror transistor 157: Resistance S ref : Reference signal S fed : Feedback signal UP: Up signal DN: Down signal V A : Analog voltage V ctrl : Control signal VH: High potential signal VL: Low potential signal S O : Output signal S L : Logic signal S c1 : First comparison signal S c2 : Second comparison signal S cp : P-type band control signal S cn : N-type band control signal V DD : Power supply voltage S TC : Temperature-coded signal

第1圖：依據本發明之一實施例，一種具自動頻帶選擇器之鎖相迴路的功能方塊圖。 第2圖：依據本發明之一實施例，一頻率相位偵測器的電路圖。 第3圖：依據本發明之一實施例，一電荷泵的電路圖。 第4圖： 依據本發明之一實施例，一自動頻帶選擇器之溫度編碼計數器的電路圖。 第5圖：依據本發明之一實施例，該自動頻帶選擇器之數位類比轉換器的電路圖。 第6圖：依據本發明之一實施例，一多頻帶壓控振盪器的電路圖。 Figure 1: A functional block diagram of a phase-locked loop with an automatic frequency band selector according to an embodiment of the invention. Figure 2: A circuit diagram of a frequency phase detector according to an embodiment of the invention. Figure 3: A circuit diagram of a charge pump according to an embodiment of the invention. Fig. 4: According to one embodiment of the present invention, a circuit diagram of a temperature encoding counter of an automatic band selector. Fig. 5: According to an embodiment of the present invention, a circuit diagram of a digital-to-analog converter of the automatic band selector. Fig. 6: A circuit diagram of a multi-band voltage controlled oscillator according to an embodiment of the present invention.

100:鎖相迴路 100: phase locked loop

110:頻率相位偵測器 110: Frequency and phase detector

120:電荷泵 120: charge pump

130:低通濾波器 130: Low-pass filter

140:自動頻帶選擇器 140: Automatic band selector

141:第一比較器 141: First comparator

142:第二比較器 142: Second comparator

143:溫度編碼計數器 143: temperature code counter

144:數位類比轉換器 144: digital to analog converter

150:多頻帶壓控振盪器 150: Multi-band voltage controlled oscillator

160:除頻器 160: frequency divider

Sref:參考訊號 S ref : reference signal

Sfed:回授訊號 S fed : Feedback signal

UP:上升訊號 UP: rising signal

DN:下降訊號 DN: Down signal

VA:類比電壓 V A : analog voltage

Vctrl:控制訊號 V ctrl : control signal

VL:低電位訊號 VL: low potential signal

VH:高電位訊號 VH: high potential signal

Sc1:第一比較訊號 S c1 : the first comparison signal

Sc2:第二比較訊號 S c2 : Second comparison signal

STC:溫度編碼訊號 S TC : temperature coding signal

Scn:N型頻帶控制訊號 S cn : N-band control signal

Scp:P型頻帶控制訊號 S cp : P-type band control signal

SO:輸出訊號 S O : output signal

Claims (7)

一種具自動頻帶選擇器之鎖相迴路，其包含：一頻率相位偵測器，接收一參考訊號及一回授訊號，該頻率相位偵測器用以比對該參考訊號及該回授訊號的頻率相位並輸出一上升訊號及一下降訊號；一電荷泵，電性連接該頻率相位偵測器，該電荷泵接收該上升訊號及該下降訊號，且該電荷泵輸出一類比電壓；一低通濾波器，電性連接該電荷泵，該低通濾波器接收該類比電壓，且該低通濾波器輸出一控制訊號；一自動頻帶選擇器，電性連接該低通濾波器，該自動頻帶選擇器接收該控制訊號，該自動頻帶選擇器將該控制訊號與一高電位訊號及一低電位訊號比對而輸出一P型頻帶控制訊號及一N型頻帶控制訊號；一多頻帶壓控振盪器，電性連接該低通濾波器及該自動頻帶選擇器以接收該控制訊號、該P型頻帶控制訊號及該N型頻帶控制訊號，其中該P型頻帶控制訊號及該N型頻帶控制訊號用以改變該多頻帶壓控振盪器的一頻帶，該控制訊號用以控制該多頻帶壓控振盪器於該頻帶的一振盪頻率；以及一除頻器，電性連接該多頻帶壓控振盪器及該頻率相位偵測器，該除頻器用以將該多頻帶壓控振盪器之一輸出訊號除頻為該回授訊號，並傳送至該頻率相位偵測器；其中該多頻帶壓控振盪器具有一控制電晶體、一第一電流鏡、一第一開關串、一延遲元件串、一第二開關串及一第二電流鏡，該控制電晶體接收該控制訊號，該第一電流鏡電性連接該控制電晶體，該第一開關串電性連接該第一電流鏡，該第一開關串經由該第一電流鏡耦接一電源電壓，該延遲元件串電性連接該 第一開關串，該第二開關串電性連接該延遲元件串，該第二電流鏡電性連接該第二開關串及該第一電晶體串，該第二開關串經由該第二電流鏡接地，其中該第一開關串受該P型頻帶控制訊號控制，該第二開關串受該N型頻帶控制訊號控制而改變該延遲元件串接收之電流大小，其中該第一電流鏡具有一P型參考電晶體及複數個P型電流鏡電晶體，該第一開關串具有複數個P型電晶體，該P型參考電晶體電性連接該控制電晶體，各該P型電晶體電性連接各該P型電流鏡電晶體，該第二電流鏡具有一N型參考電晶體及複數個N型電流鏡電晶體，該第二開關串具有複數個N型電晶體，該N型參考電晶體電性連接其中之一該P型電晶體，各該N型電晶體電性連接各該N型電流鏡電晶體，該延遲元件串具有複數個延遲元件，各該延遲元件電性連接各該P型電晶體及各該N型電晶體，且各該延遲元件相互串聯，其中之一該延遲元件輸出一正振盪訊號及一負振盪訊號。 A phase-locked loop with an automatic frequency band selector, including: a frequency and phase detector that receives a reference signal and a feedback signal, the frequency and phase detector is used to compare the frequency of the reference signal and the feedback signal Phase and output a rising signal and a falling signal; a charge pump, electrically connected to the frequency phase detector, the charge pump receives the rising signal and the falling signal, and the charge pump outputs an analog voltage; a low-pass filter Device, electrically connected to the charge pump, the low-pass filter receives the analog voltage, and the low-pass filter outputs a control signal; an automatic frequency band selector, electrically connected to the low-pass filter, the automatic frequency band selector Receiving the control signal, the automatic band selector compares the control signal with a high potential signal and a low potential signal to output a P-band control signal and an N-band control signal; a multi-band voltage controlled oscillator, The low-pass filter and the automatic frequency band selector are electrically connected to receive the control signal, the P-type band control signal and the N-type band control signal, wherein the P-type band control signal and the N-type band control signal are used to Changing a frequency band of the multi-band voltage controlled oscillator, the control signal is used to control an oscillation frequency of the multi-band voltage controlled oscillator in the frequency band; and a frequency divider electrically connected to the multi-band voltage controlled oscillator and The frequency and phase detector, the frequency divider is used to divide the output signal of the multi-band voltage controlled oscillator into the feedback signal, and transmitted to the frequency and phase detector; wherein the multi-band voltage controlled oscillator It has a control transistor, a first current mirror, a first switch string, a delay element string, a second switch string and a second current mirror. The control transistor receives the control signal and the first current mirror Is electrically connected to the control transistor, the first switch string is electrically connected to the first current mirror, the first switch string is coupled to a power supply voltage via the first current mirror, and the delay element string is electrically connected to the A first switch string, the second switch string is electrically connected to the delay element string, the second current mirror is electrically connected to the second switch string and the first transistor string, and the second switch string passes through the second current mirror Grounded, wherein the first switch string is controlled by the P-type band control signal, the second switch string is controlled by the N-type band control signal to change the amount of current received by the delay element string, and wherein the first current mirror has a P Type reference transistor and a plurality of P-type current mirror transistors, the first switch string has a plurality of P-type transistors, the P-type reference transistor is electrically connected to the control transistor, and each of the P-type transistors is electrically connected Each of the P-type current mirror transistors, the second current mirror has an N-type reference transistor and a plurality of N-type current mirror transistors, the second switch string has a plurality of N-type transistors, and the N-type reference transistor One of the P-type transistors is electrically connected, each of the N-type transistors is electrically connected to each of the N-type current mirror transistors, the delay element string has a plurality of delay elements, and each of the delay elements is electrically connected to each of the P And each of the N-type transistors, and each of the delay elements is connected in series with each other, and one of the delay elements outputs a positive oscillation signal and a negative oscillation signal. 如申請專利範圍第1項所述之具自動頻帶選擇器之鎖相迴路，其中該頻率相位偵測器具有一第一動態偵測單元、一第二動態偵測單元、一NOR閘、一第一反相器、一第二反相器及一突波消除電路，該第一動態偵測單元接收該參考訊號，該第二動態偵測單元接收該回授訊號，該NOR閘電性連接該第一動態偵測單元及該第二動態偵測單元，且該NOR閘輸出之一邏輯訊號回傳至該第一動態偵測單元及該第二動態偵測單元，該第一反相器電性連接該第一動態偵測單元，該第二反相器電性連接該第二動態偵測單元，該突波消除電路電性連接該第一反相器及該第二反相器，且該突波消除電路輸出該上升訊號及該下降訊號。 A phase-locked loop with an automatic frequency band selector as described in item 1 of the patent scope, wherein the frequency phase detector has a first motion detection unit, a second motion detection unit, a NOR gate, a first An inverter, a second inverter, and a surge cancellation circuit, the first motion detection unit receives the reference signal, the second motion detection unit receives the feedback signal, and the NOR gate is electrically connected to the first A motion detection unit and the second motion detection unit, and a logic signal output by the NOR gate is returned to the first motion detection unit and the second motion detection unit, the first inverter is electrically Connected to the first motion detection unit, the second inverter is electrically connected to the second motion detection unit, the surge cancellation circuit is electrically connected to the first inverter and the second inverter, and the The surge cancellation circuit outputs the rising signal and the falling signal. 如申請專利範圍第2項所述之具自動頻帶選擇器之鎖相迴路，其中該突波消除電路具有一第三反相器、一第四反相器、一第一AND閘及一第二AND閘，該第三反相器電性連接該第一反相器，該第四反相器電性連接該第二反相 器，該第一AND閘電性連接該第一反相器及該第四反相器，且該第一AND閘輸出該上升訊號，該第二AND閘電性連接該第二反相器及該第三反相器，且該第二AND閘輸出該下降訊號。 A phase-locked loop with an automatic frequency band selector as described in item 2 of the patent scope, wherein the surge cancellation circuit has a third inverter, a fourth inverter, a first AND gate and a second AND gate, the third inverter is electrically connected to the first inverter, and the fourth inverter is electrically connected to the second inverter The first AND gate is electrically connected to the first inverter and the fourth inverter, and the first AND gate outputs the rising signal, and the second AND gate is electrically connected to the second inverter and The third inverter, and the second AND gate outputs the falling signal. 如申請專利範圍第1項所述之具自動頻帶選擇器之鎖相迴路，其中該自動頻帶選擇器具有一第一比較器、一第二比較器、一溫度編碼計數器及一數位類比轉換器，該第一比較器及該第二比較器電性連接該低通濾波器，該第一比較器用以比對該控制訊號及該低電位訊號的大小並輸出一第一比較訊號，該第二比較器用以比對該控制訊號及該高電位訊號的大小並輸出一第二比較訊號，該溫度編碼計數器接收該第一比較訊號及該第二比較訊號，且該溫度編碼計數器輸出一溫度編碼訊號，該數位類比轉換器電性連接該溫度編碼計數器，該數位類比轉換器根據該溫度編碼訊號輸出該P型頻帶控制訊號及該N型頻帶控制訊號至該多頻帶壓控振盪器。 A phase-locked loop with an automatic frequency band selector as described in item 1 of the patent application scope, wherein the automatic frequency band selector has a first comparator, a second comparator, a temperature encoding counter and a digital analog converter, the The first comparator and the second comparator are electrically connected to the low-pass filter, the first comparator is used to compare the size of the control signal and the low potential signal and output a first comparison signal, and the second comparator is used Output a second comparison signal at a size that is greater than that of the control signal and the high potential signal, the temperature code counter receives the first comparison signal and the second comparison signal, and the temperature code counter outputs a temperature code signal, the The digital-to-analog converter is electrically connected to the temperature coding counter, and the digital-to-analog converter outputs the P-band control signal and the N-band control signal to the multi-band voltage controlled oscillator according to the temperature coding signal. 一種多頻帶壓控振盪器，其包含：一控制電晶體，接收一控制訊號並受該控制訊號控制；一第一電流鏡，電性連接該控制電晶體，該第一電流鏡接收一電源電壓，其中該第一電流鏡具有一P型參考電晶體及複數個P型電流鏡電晶體，該第一開關串具有複數個P型電晶體，該P型參考電晶體電性連接該控制電晶體，各該P型電晶體電性連接各該P型電流鏡電晶體；一第一開關串，電性連接該第一電流鏡，該第一開關串接收一P型頻帶控制訊號並受該P型頻帶控制訊號控制；一第二電流鏡，電性連接該第一電流鏡，且該第二電流鏡接地，其中該第二電流鏡具有一N型參考電晶體及複數個N型電流鏡電晶體，該第二開關串具有複 數個N型電晶體，該N型參考電晶體電性連接其中之一該P型電晶體，各該N型電晶體電性連接各該N型電流鏡電晶體；一第二開關串，電性連接該第二電流鏡，該第二開關串接收一N型頻帶控制訊號並受該N型頻帶控制訊號控制；以及一延遲元件串，電性連接該第一開關串及該第二開關串，其中該P型頻帶控制訊號及該N型頻帶控制訊號用以改變該延遲元件串之一頻帶，該控制訊號則用以改變該延遲元件串於該頻帶中的振盪頻率，其中該延遲元件串具有複數個延遲元件，各該延遲元件電性連接各該P型電晶體及各該N型電晶體，且各該延遲元件相互串聯，其中之一該延遲元件輸出一正振盪訊號及一負振盪訊號。 A multi-band voltage controlled oscillator, comprising: a control transistor, receiving a control signal and controlled by the control signal; a first current mirror, electrically connected to the control transistor, the first current mirror receiving a power supply voltage , Wherein the first current mirror has a P-type reference transistor and a plurality of P-type current mirror transistors, the first switch string has a plurality of P-type transistors, and the P-type reference transistor is electrically connected to the control transistor , Each of the P-type transistors is electrically connected to each of the P-type current mirror transistors; a first switch string is electrically connected to the first current mirror, the first switch string receives a P-type band control signal and is controlled by the P Type band control signal control; a second current mirror, electrically connected to the first current mirror, and the second current mirror is grounded, wherein the second current mirror has an N-type reference transistor and a plurality of N-type current mirror Crystal, the second switch string has a complex Several N-type transistors, the N-type reference transistor is electrically connected to one of the P-type transistors, each N-type transistor is electrically connected to each of the N-type current mirror transistors; a second switch string, electrically Is connected to the second current mirror, the second switch string receives an N-band control signal and is controlled by the N-band control signal; and a delay element string is electrically connected to the first switch string and the second switch string , Wherein the P-type band control signal and the N-type band control signal are used to change a frequency band of the delay element string, and the control signal is used to change the oscillation frequency of the delay element string in the frequency band, wherein the delay element string There are a plurality of delay elements, each of which is electrically connected to each of the P-type transistor and each of the N-type transistors, and each of the delay elements is connected in series with each other, and one of the delay elements outputs a positive oscillation signal and a negative oscillation Signal. 如申請專利範圍第5項所述之多頻帶壓控振盪器，其中該控制電晶體為一N型電晶體，該控制電晶體之一汲極經由該第一電流鏡之該P型參考電晶體接收該電源電壓，該控制電晶體之一源極經由一電阻接地，該控制電晶體之一閘極接收該控制訊號。 The multi-band voltage-controlled oscillator as described in item 5 of the patent application range, wherein the control transistor is an N-type transistor, and a drain of the control transistor passes through the P-type reference transistor of the first current mirror Receiving the power supply voltage, a source of the control transistor is grounded via a resistor, and a gate of the control transistor receives the control signal. 如申請專利範圍第5項所述之多頻帶壓控振盪器，其中各該延遲元件為雙端延遲元件。 The multi-band voltage controlled oscillator as described in item 5 of the patent application scope, wherein each of the delay elements is a double-ended delay element.
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